Control Method of Memory Device

Abstract

The present invention discloses a control method for a memory device. The control method for the memory device uses an inverted data to mark the data stored in a memory block as an inverted state or a non-inverted state, so that when data is written to the memory block, the number of bits whose data states are changed in the memory block is not greater than half of the total number of bits of the memory block, thereby reducing power consumption. The control method of the present invention can also use the inverted data to mark a memory block with defective bits and select a spare block to repair the memory block with defective bits.

Description

Technical Field

[0001] The present invention relates to the field of memory device control, and more particularly to a control method for a memory device that can achieve power saving, repair of defective bits, and extension of the memory life. Background Art

[0002] Conventional random access memories, such as magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM), require a large current to change the data state of a bit to achieve a write operation. The change in the data state includes changing from "0" to "1" or from "1" to "0". Therefore, the more bits whose data states are changed, the greater the energy consumed by the write operation. In addition, when a bit changes its data state too frequently, the durability and reliability of the bit will decrease, thus shortening the service life of the random access memory.

[0003] Conventional methods for repairing defective bits in random access memories are all completed during the manufacturing process. When a user encounters a defective bit during use, generally, error-correcting code (ECC) technology is used for repair. However, the ECC technology requires the support of other components to perform the repair. For example, it requires the support of a motherboard or a CPU, and conventional random access memories cannot repair defective bits by themselves. Summary of the Invention

[0004] The object of the present invention is to provide a control method for a memory device that can achieve power saving, repair of defective bits, and extension of the life of the memory device.

[0005] To achieve the above object, the present invention provides a control method for a memory device, the control method of the memory device comprising: providing an inverted data to mark the first data of a memory block as an inverted state or a non-inverted state, the inverted data having at least two bits; when writing a second data, determining whether to write the second data or a third data into the memory block according to the first data and the inverted data, the third data being the inversion of the second data; when detecting a defective bit in the memory block, changing at least one of the at least two bits to a data state that is neither 0 nor 1; and selecting one of a plurality of spare blocks to replace the memory block, the inverted data marking the selected spare block.

[0006] According to the specific embodiments provided by the present invention, the following technical effects are disclosed by the present invention:

[0007] The control method of the memory device of the present invention uses inverted data to mark the data stored in the memory block as an inverted state or a non-inverted state, so that when writing data to the memory block, the number of bits whose data states are changed in the memory block does not exceed half of the total number of bits of the memory block, thereby reducing energy consumption. In addition, the present invention can also use the inverted data to mark the memory block with bad bits and select a spare block to repair the memory block with bad bits. Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0009] Figure 1 is the memory device of the present invention.

[0010] Figure 2 is Figure 1 an embodiment of the memory array 12 in

[0011] Figure 3 is the read / write operation flowchart of the memory device 10 of the present invention.

[0012] Figure 4 illustrates the way to repair bad bits of the memory device 10 of the present invention.

[0013] Figure 5 is the first arrangement of the memory block and the spare block.

[0014] Figure 6 is the second arrangement of the memory block and the spare block.

[0015] Symbol Description:

[0016] 10, memory device; 12, memory array; 122, bit; 124, bit; 126, bit; 14, inverter circuit; 16, inverter circuit; 18, first buffer; 20, second buffer. Detailed Embodiments

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0018] Figure 1 is the memory device 10 of the present invention. Figure 2 is Figure 1 an embodiment of the memory array 12 in Figure 1 and Figure 2 Referring to, the memory device 10 includes a memory array 12, an inverter circuit 14 and an inverter circuit 16, and a first buffer 18 and a second buffer 20. The memory array 12 can be divided into two parts. The first part includes a plurality of memory blocks N1 to Nn and a plurality of marker blocks K1 to Kn, and the second part includes a plurality of spare blocks R1 to R5 and a plurality of marker blocks KR1 to KR5. Each memory block has m bits 122, where m is a positive integer, so the first data stored in a memory block has a first quantity m of bits. Each spare block has m bits 124. Each marker block has 2 bits 126. The marker blocks K1 to Kn and KR1 to KR5 are used to store the inverted data WIB. The inverted data WIB stored in the marker blocks K1 to Kn are respectively used to mark the memory blocks N1 to Nn as the inverted state or the non-inverted state, and the inverted data WIB stored in the marker blocks KR1 to KR5 are respectively used to mark the spare blocks R1 to R5 as the inverted state or the non-inverted state. In Figure 2 the embodiment of, the memory blocks N1 to Nn, the marker blocks K1 to Kn, the spare blocks R1 to R5, and the marker blocks KR1 to KR5 are in the same memory array 12, but the memory blocks N1 to Nn, the marker blocks K1 to Kn, the spare blocks R1 to R5, and the marker blocks KR1 to KR5 can also be respectively arranged in different memory arrays.

[0019] Figure 3It is a flowchart of the read / write operation of the memory device 10 of the present invention. When the memory device 10 receives a read / write command, the first data of one of the memory blocks N1 to Nn is read out and stored in the first buffer 18 and the second buffer 20, as shown in step S10. Here, the first data of the memory block N1 is read out as an example for illustration. Then, step S12 is performed, and the memory device 10 determines whether a write operation is to be performed. When the memory device 10 is to perform a read operation, the inverter circuit 14 monitors the inverted data WIB of the marker block K1 to determine whether the first data is in an inverted state or a non-inverted state, as shown in step S14. In this embodiment, when the inverted data WIB is "00" or "11", it represents that the first data is in a non-inverted state, and when the inverted data WIB is "01" or "10", it represents that the first data is in an inverted state. The present invention is not limited thereto. For example, when the inverted data WIB is "00" or "11", it represents that the first data is in an inverted state, and when the inverted data WIB is "01" or "10", it represents that the first data is in a non-inverted state. When the inverter circuit 14 determines that it is in a non-inverted state, the inverter circuit 14 directly outputs the first data in the first buffer 18 as the read data DR to the circuit outside the memory device 10, as shown in step S16. In step S14, when the inverter circuit 14 determines that it is in an inverted state, the inverter circuit 14 generates a fourth data by inverting the first data as the read data DR and outputs the fourth data to the circuit outside the memory device 10, as shown in step S18. Assuming the first data is "1001", then the fourth data is "0110".

[0020] In step S12, when the memory device 10 is to perform a write operation, the memory device 10 will proceed to step S20. In step S20, the inverter circuit 16 monitors the inverted data WIB of the marked block K1 to determine whether the first data is in an inverted state or a non-inverted state. When the first data is in a non-inverted state, the inverter circuit 16 stores the second data to be written into the second buffer 20. Then, the memory device 10 compares the first data in the first buffer 18 with the second data in the second buffer 20, as shown in step S22. The comparison process includes finding the bits with the same position but different data states in the first data and the second data, and calculating the number of these bits to generate a second quantity WB. After obtaining the second quantity WB, it is determined whether the second quantity WB is greater than half of the first quantity m, as shown in step S24. If the second quantity WB is less than m / 2, the memory device 10 directly writes the second data into the memory block N1, as shown in step S26. After writing the second data, the inverted data WIB corresponding to the memory block N1 remains in a non-inverted state. If the second quantity WB is greater than m / 2, the inverter circuit 16 inverts the second data to generate a third data, as shown in step S28. After that, the memory device 10 writes the third data into the memory block N1, and at the same time, the inverted data WIB corresponding to the memory block N1 will be changed to an inverted state, as shown in step S30.

[0021] Here, specific embodiments are used to illustrate steps S22 to S30. Assume that the first data is "10010001". Since the first data has 8 bits, the first quantity m is 8. In step S22, if the second data is "10010010", after comparison, it can be known that only the data states of the last two bits of the first data "10010001" and the second data "10010010" are different. Therefore, in step S24, the memory device 10 determines that the second quantity WB is 2 and less than half of the first quantity m. Then, step S26 is performed to write the second data "10010010" into the memory block N1. Since only the data states of the last two bits of the first data "10010001" and the second data "10010010" are different, when writing, only the data states of the last two bits 122 in the memory block N1 need to be changed. In step S22, if the second data is "10001110", after comparison, it can be known that the data states of the last five bits of the first data "10010001" and the second data "10001110" are different. Therefore, in step S24, the memory device 10 determines that the second quantity WB is 5 and greater than half of the first quantity m. That is to say, at this time, if the second data is written into the memory block N1, the data states of five bits 122 need to be changed, which requires a large amount of energy consumption. To save energy consumption, the memory device 10 will perform step S28 to invert the second data to generate the third data "01110001". Finally, the memory device 10 writes the third data "01110001" into the memory block N1, and at the same time changes the inverted state of the inverted data WIB of the flag block K1, as shown in step S30. Since only the data states of the first three bits of the third data "01110001" and the first data "10010001" in the memory block N1 are different, when writing, only the data states of the first three bits 122 in the memory block N1 need to be changed, so the purpose of saving energy can be achieved.

[0022] In step S20, when the first data is in the inverted state, the memory device 10 performs step S32. At this time, the inverter circuit 16 inverts the second data to generate a third data, and stores the third data in the second buffer 20. Then, the memory device 10 compares the first data in the first buffer 18 with the third data in the second buffer 20, as shown in step S34. After the comparison, the memory device 10 can identify the bits with the same positions but different data states in the first data and the third data, and calculates the number of these bits to obtain a second quantity WB. After obtaining the second quantity WB, it is determined whether the second quantity WB is greater than half of the first quantity m, as shown in step S36. If the second quantity WB is less than m / 2, the memory device 10 writes the third data into the memory block N1, as shown in step S38. After writing the third data, the inverted data WIB corresponding to the memory block N1 remains in the inverted state. If the second quantity WB is greater than m / 2, the memory device 10 writes the second data into the memory block N1, and at the same time, the inverted data WIB will be changed to the non-inverted state, as shown in step S40.

[0023] Steps S32 to S40 will be described below with a specific example. Assume that the first data is "01101110". Since the first data has 8 bits, the first quantity m is 8. In step S32, since the first data is marked as the inverted state, the inverter circuit 16 will invert the second data "01110001" to the third data "10001110", and store the third data in the second buffer 20. After the memory device 10 compares the first data "01101110" with the third data "10001110", it can be known that the data states of the first three bits are different. Therefore, the memory device 10 determines that the second quantity WB is 3 and less than half of the first quantity m. The memory device 10 thus performs step S38 to write the third data "10001110" into the memory block N1, and keeps the inverted data WIB in the flag block K1 unchanged. Since only the data states of the first three bits of the first data "01101110" and the third data "10001110" are different, only the data states of the first three bits 122 in the memory block N1 need to be changed during writing. In another embodiment, if the second data is "01101001", the third data "10010110" will be generated in step S32. Then, in steps S34 and S36, the memory device 10 can know that the data states of the first five bits of the first data "01101110" and the third data "1001010" are different. Therefore, it is determined that the second quantity WB is 5 and greater than half of the first quantity m. To save power consumption, the memory device 10 will perform step S40 to write the second data into the memory block N1, and change the inverted data WIB in the flag block K1 to the non-inverted state, as shown in step S40. Since only the data states of the last three bits of the second data "01101001" and the first data "01101110" in the memory block N1 are different, only the data states of the last three bits 122 in the memory block N1 need to be changed during writing, thus achieving the purpose of saving power.

[0024] In Figure 2In this case, taking the marked block K1 as an example, the inverted data WIB has two bits, which can use "00" and "11" to represent the non-inverted state, and "01" and "10" to represent the inverted state. In addition, when bit 126 changes the data state too frequently, the durability and reliability of bit 126 will decrease, which will shorten the service life of the marked block K1. To reduce the change frequency of bit 126, the inverted data WIB can be changed in a sequence. For example, it changes from "00" to "01", then from "01" to "11", then from "11" to "10", and finally "10" back to "00", that is, it repeatedly changes in the order of "00", "01", "11", and "10". In this way, only one bit 126 in the marked block K1 changes the data state each time, and the same bit 126 does not change the data state twice in a row, reducing the change frequency of bit 126, and thus increasing the service life of the marked block K1. The present invention does not limit the number of bits of the inverted data WIB or the marked block. For example, when the inverted data WIB has three bits, it can use "000", "011", and "110" to represent the non-inverted state, use "001", "111", and "100" to represent the inverted state, and can change in the order of "000", "001", "011", "111", "110", and "100". In another embodiment, when the inverted data WIB is "000", "011", or "110", it can also be used to represent the inverted state, while when the inverted data WIB is "001", "111", and "100", it represents the non-inverted state.

[0025] Figure 2 The bit 126 of the marked blocks K1 to K12 can write a third data state X that is neither 0 nor 1. Using this feature, the memory device 10 of the present invention can repair defective bits in real time. When one of the bits 122 in the memory block N1 becomes a defective bit due to overuse or other reasons, at least one of the bits 126 in the marked block K1 can be changed to the data state X to indicate that the memory block N1 has a defective bit. The memory device 10 of the present invention can also select one of the multiple spare blocks R1 to R5 through the inverted data WIB to replace the memory block N1. Figure 4Displays the correspondence between the inverted data WIB and the spare blocks R1 to R5. When the memory device 10 detects that the inverted data WIB corresponding to the memory block N1 is "X0", the memory device 10 will select the spare block R1 to replace the memory block N1. When the memory device 10 detects that the inverted data WIB corresponding to the memory block N1 is "X1", the memory device 10 will select the spare block R2 to replace the memory block N1. When the memory device 10 detects that the inverted data WIB corresponding to the memory block N1 is "0X", the memory device 10 will select the spare block R3 to replace the memory block N1. When the memory device 10 detects that the inverted data WIB corresponding to the memory block N1 is "1X", the memory device 10 will select the spare block R4 to replace the memory block N1. When the memory device 10 detects that the inverted data WIB corresponding to the memory block N1 is "XX", the memory device 10 will select the spare block R5 to replace the memory block N1. Figure 2 Although 5 spare blocks R1 to R5 are taken as examples herein, the present invention is not limited thereto. It is possible to increase or decrease the spare blocks R1 to R5 according to requirements, and as the spare blocks R1 to R5 increase or decrease, the number of bits of the inverted data WIB may also change accordingly.

[0026] In Figure 2 's embodiment, multiple bits 122 form an n×m array, and the arrangement direction of the spare blocks R1 to R5 can be determined according to the relationship between n and m to achieve better repair efficiency. As Figure 5 shown, when n>m (for example, n = 16, m = 8), the spare blocks R1 to R5 can be arranged along the Y direction to achieve better repair efficiency, as shown by the solid line. Specifically, when Figure 5 an inferior bit appears in the n×m array in Figure 5 , the spare blocks R1 to R5 arranged along the Y direction only need to use 8 bits 124 to replace the memory block where the inferior bit is located. In this case, it is equivalent to using 8 bits 124 to repair an inferior bit. However, if Figure 6 the spare blocks R1 to R5 in

[0027] The above description of the preferred embodiments of the present invention is to clarify the purpose of the present invention, and is not intended to limit the present invention to the precisely disclosed form. Modifications or variations are possible based on the above teachings or learned from the embodiments of the present invention. The embodiments are selected and described to explain the principles of the present invention and enable those skilled in the art to utilize the present invention in various embodiments in practical applications. The technical concept of the present invention is intended to be determined by the claims and their equivalents.

Claims

1. A control method for a memory device, characterized in that, The control method of the memory device includes the following steps: A. Providing an inverted data to mark the first data of a memory block as an inverted state or a non-inverted state, where the inverted data has at least two bits; B. When writing a second data, determining whether to write the second data or a third data into the memory block according to the first data and the inverted data, where the third data is the inversion of the second data; C. When detecting bad bits in the memory block, changing at least one of the at least two bits to a data state that is neither 0 nor 1; And D. Selecting one of multiple spare blocks to replace the memory block, and the inverted data marks the selected spare block.

2. The control method of the memory device according to claim 1, wherein, When the first data is marked as a non-inverted state, step B includes the following steps: Comparing the first data with the second data, where both the first data and the second data have a first number of bits; Calculating the number of bits with the same position but different data states in the first data and the second data to generate a second number; If the second number is less than half of the first number, writing the second data into the memory block; And If the second number is greater than half of the first number, writing the third data into the memory block, and changing the inverted data to mark the third data written into the memory block as an inverted state.

3. The control method of the memory device according to claim 2, wherein, The step of comparing the first data with the second data includes: Storing the first data in a first buffer; Storing the second data in a second buffer; and Comparing the first data in the first buffer with the second data in the second buffer.

4. The control method of the memory device according to claim 2, characterized in that, When changing the inverted data, changing one of the at least two bits of the inverted data in a preset order.

5. The control method of the memory device according to claim 1, wherein, When the first data is marked as an inverted state, step B includes the following steps: Inverting the second data to generate the third data; Comparing the first data with the third data, where the first data, the second data, and the third data all have a first number of bits; Calculating the number of bits with the same position but different data states in the first data and the third data to generate a second number; If the second number is less than half of the first number, writing the third data into the memory block; And If the second number is greater than half of the first number, writing the second data into the memory block, and changing the inverted data to mark the second data written into the memory block as a non-inverted state.

6. The control method of the memory device according to claim 5, characterized in that, The step of comparing the first data and the third data includes: Storing the first data in a first buffer; Storing the third data in a second buffer; and Comparing the first data in the first buffer with the third data in the second buffer.

7. The control method of the memory device according to claim 5, wherein, When changing the inverted data, changing one of the at least two bits of the inverted data in a preset order.

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