Packaging method and packaging structure of a multilayer stacked high bandwidth memory

Abstract

The application provides a packaging method and structure of a multilayer stacked high-width-band memory, which comprises the following steps: providing a buffer chip and a plurality of groups of memory chips, each group of memory chips comprising a first memory chip and a second memory chip; wherein the buffer chip is provided with a plurality of first conductive vias, and the first memory chip and the second memory chip are each provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias; mixing bonding the first memory chip and the second memory chip in each group of memory chips to form a plurality of memory micro-modules; sequentially stacking the plurality of memory micro-modules on the buffer chip; and forming a plastic encapsulation layer to wrap the plurality of memory micro-modules and the buffer chip. The double-chip mixed bonding forms a memory micro-module, which can realize super-multilayer chip stacking, improve production efficiency, realize bonding height reduction, greatly increase the number of chip layers, and increase the capacity.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a packaging method and packaging structure of a multi-layer stacked high bandwidth memory. BACKGROUND

[0002] For enterprise-level applications such as data centers, high-capacity high-speed storage is necessary. To meet this demand, high bandwidth memory (HBM) has emerged. As shown in the prior art, Figure 1 HBM uses through silicon vias to vertically interconnect several memory chips 11, and interacts with the outside world through a bottom buffer chip 10. Due to the high density and short vertical interconnection distance of the through silicon vias, the data transmission speed is greatly improved.

[0003] Currently, the multi-layer chip stacking of HBM adopts a thermal compression bonding (TCB) process, which connects the micro-bumps 14 to the chip back pads 13 by rapid heating, and the chip back pads are connected to the through silicon vias 12 of the chip. The composition of the micro-bumps is mainly copper-tin structure, and the main component of the chip back pad is nickel-gold structure. The final stacked structure is protected by a plastic encapsulation layer 15.

[0004] In the case of using copper-tin micro-bumps, due to the deformation of tin during reflow, in order to prevent short circuit between micro-bumps, the spacing between micro-bumps and the height of tin need to be strictly controlled. Currently, the spacing is more than 40 microns, when the spacing is reduced to less than 25 um, due to the small amount of tin, it is fully converted to intermetallic compound under thermal load, resulting in reliability failure.

[0005] In order to improve the storage capacity and data throughput speed, it is necessary to increase the number of chip stacks and the number of pins, but in the current micro-bump mechanism, due to the limitation of bump height and spacing, there is limited space for continuous improvement.

[0006] In view of the above problems, it is necessary to provide a packaging method and packaging structure of a multi-layer stacked high bandwidth memory which is reasonable in design and can effectively solve the above problems. SUMMARY

[0007] The application aims to at least solve one of the technical problems existing in the prior art, and provides a packaging method and packaging structure of a multi-layer stacked high bandwidth memory.

[0008] One aspect of the application provides a packaging method of a multi-layer stacked high bandwidth memory, the method comprising:

[0009] A buffer chip and a plurality of groups of memory chips are provided respectively, each group of the memory chips comprising a first memory chip and a second memory chip; wherein the buffer chip is provided with a plurality of first conductive vias, and the first memory chip and the second memory chip are each provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias;

[0010] The first memory chip and the second memory chip in each group of the memory chips are mixedly bonded respectively to form a plurality of memory micro-modules;

[0011] The plurality of memory micro-modules are sequentially and insulatively stacked on the buffer chip;

[0012] A plastic encapsulation layer is formed to wrap the plurality of memory micro-modules and the buffer chip.

[0013] Optionally, a first passivation layer and a first metal pad are arranged on a surface of the first memory chip facing the second memory chip, and a second passivation layer and a second metal pad are arranged on a surface of the second memory chip facing the first memory chip;

[0014] The mixed bonding of the first memory chip and the second memory chip in each group of the memory chips to form a plurality of memory micro-modules comprises:

[0015] The first passivation layer in the first memory chip is bonded to the second passivation layer in the corresponding second memory chip; and

[0016] The first metal pad in the first memory chip is bonded to the second metal pad in the corresponding second memory chip.

[0017] Optionally, before the plurality of memory micro-modules are sequentially and insulatively stacked on the buffer chip, the method further comprises:

[0018] A first insulating layer is formed on a surface of the first memory chip away from the second memory chip after mixed bonding;

[0019] The first insulating layer is patterned to form a plurality of first openings;

[0020] A plurality of first conductive connection structures are formed at the plurality of first openings, the first conductive connection structures being electrically connected to the second conductive vias on the first memory chip.

[0021] Optionally, the first insulating layer comprises a first passivation sub-layer and a dielectric layer formed sequentially;

[0022] The first conductive connection structure includes a first connection metal pad and a plurality of first bumps disposed on the first connection metal pad.

[0023] Optionally, before sequentially disposing the plurality of memory micro-module insulating stacks on the buffer chip, the method further comprises:

[0024] forming a second insulating layer on a surface of the second memory chip away from the first memory chip after hybrid bonding;

[0025] patterning the second insulating layer to form a plurality of second openings;

[0026] forming a plurality of second conductive connection structures at the plurality of second openings, the second conductive connection structures being electrically connected with the second conductive vias on the second memory chip.

[0027] Optionally, the second insulating layer includes a second passivation sub-layer, and the second conductive connection structure includes a second connection metal pad.

[0028] Optionally, the sequentially disposing the plurality of memory micro-module insulating stacks on the buffer chip comprises:

[0029] disposing a non-conductive adhesive film between adjacent two memory micro-modules.

[0030] Optionally, when the first memory chip is provided with first bumps, the disposing the non-conductive adhesive film between adjacent two memory micro-modules comprises:

[0031] disposing the non-conductive adhesive film on a side of the first bumps away from the first memory chip.

[0032] Optionally, in each group of memory chips, the first memory chip is disposed close to the buffer chip, the second memory chip is disposed away from the buffer chip, and a thickness of the first memory chip is less than a thickness of the second memory chip.

[0033] Optionally, the conductive via is a through-silicon via.

[0034] Optionally, the first memory chip and the second memory chip are of the same type.

[0035] Another aspect of the present application provides a multi-layer stacked high-width-band memory package structure, comprising:

[0036] a buffer chip provided with a plurality of first conductive vias;

[0037] A plurality of memory micro-modules are insulatively stacked on the buffer chip; wherein

[0038] Each of the memory micro-modules comprises a first memory chip and a second memory chip, and the first memory chip and the second memory chip are both provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias and electrically connected thereto; and

[0039] Each of the first memory chips is hybridly bonded to the corresponding second memory chip through a hybrid bonding structure;

[0040] A plastic encapsulation layer encapsulates the plurality of memory micro-modules and the buffer chip.

[0041] Optionally, the hybrid bonding structure comprises a first passivation layer and a first metal pad provided on a surface of the first memory chip facing the second memory chip, and a second passivation layer and a second metal pad provided on a surface of the second memory chip facing the first memory chip;

[0042] The first passivation layer in the first memory chip is bonded to the second passivation layer in the corresponding second memory chip, and the first metal pad in the first memory chip is hybridly bonded to the second metal pad in the corresponding second memory chip.

[0043] Optionally, a first insulating layer is provided on a surface of the first memory chip facing away from the second memory chip;

[0044] A plurality of first openings are provided on the first insulating layer;

[0045] A first conductive connection structure is provided at the plurality of first openings, and the first conductive connection structure is electrically connected to the second conductive vias on the first memory chip.

[0046] Optionally, the first insulating layer comprises a first passivation sub-layer and a dielectric layer provided on the first passivation sub-layer;

[0047] The first conductive connection structure comprises a first connection metal pad and a first bump provided on the first connection metal pad.

[0048] Optionally, a second insulating layer is provided on a surface of the second memory chip facing away from the first memory chip;

[0049] The second insulating layer is provided with a plurality of second openings;

[0050] The second conductive connection structure is arranged at the plurality of second openings and is electrically connected with the second conductive via holes on the second memory chip.

[0051] Optionally, the first memory chip is arranged close to the buffer chip, the second memory chip is arranged away from the buffer chip, and the thickness of the first memory chip is smaller than the thickness of the second memory chip.

[0052] The packaging method and packaging structure of the multi-layer stacked high-bandwidth memory can realize super multi-layer chip stacking, improve production efficiency, realize bonding height reduction, greatly increase the number of chip layers, and increase capacity. The number of chip layers of the packaging structure can be greatly increased, capacity is increased, and the packaging height is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 It is a packaging process schematic diagram of a multi-layer chip in the prior art;

[0054] Figure 2 It is a flowchart of a packaging method of a multi-layer stacked high-bandwidth memory according to an embodiment of the present application;

[0055] Figures 3 to 11 It is a packaging process schematic diagram of a packaging method of a multi-layer stacked high-bandwidth memory according to another embodiment of the present application;

[0056] Figure 12 It is a schematic diagram of a defective chip position in a wafer of a multi-layer stacked high-bandwidth memory according to another embodiment of the present application;

[0057] Figure 13 It is a schematic diagram of a defective chip position in another wafer of a multi-layer stacked high-bandwidth memory according to another embodiment of the present application;

[0058] Figure 14 It is a schematic diagram of a defective chip position after stacking of two wafers of a multi-layer stacked high-bandwidth memory according to another embodiment of the present application. DETAILED DESCRIPTION

[0059] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0060] As shown in the drawings, Figure 2 An aspect of the present application provides a packaging method S100 of a multi-layer stacked high-bandwidth memory, which comprises:

[0061] S100. A buffer chip and multiple sets of memory chips are provided respectively. Each set of memory chips includes a first memory chip and a second memory chip. The buffer chip is provided with multiple first conductive vias, and the first memory chip and the second memory chip are provided with multiple second conductive vias corresponding to the multiple first conductive vias.

[0062] Specifically, such as Figure 11 As shown, a buffer chip 110 and multiple sets of memory chips are provided, each set of memory chips including a first memory chip 120 and a second memory chip 130. The buffer chip 110 is provided with multiple first conductive vias 140a, and the first memory chip 120 and the second memory chip 130 are each provided with multiple second conductive vias 140b corresponding to the multiple first conductive vias 140a. That is, the buffer chip 110, the first memory chip 120, and the second memory chip 130 are electrically connected through the corresponding multiple first conductive vias 140a and multiple second conductive vias 140b. More preferably, the multiple conductive vias 140 can be through-silicon vias (TSVs).

[0063] S120. The first memory chip and the second memory chip in each group of memory chips are respectively mixed and bonded to form multiple memory micro-modules.

[0064] Specifically, the first memory chip 120 and the second memory chip 130 in each group of memory chips are mixed and bonded to form multiple memory micro-modules 150.

[0065] For example, such as Figure 3 As shown, the surface of the first memory chip 120 facing the second memory chip 130 is provided with a first passivation layer 121 and a first metal pad 122, and the surface of the second memory chip 130 facing the first memory chip 120 is provided with a second passivation layer 131 and a second metal pad 132. The surface of the first memory chip 120 with the first passivation layer 121 and the first metal pad 122 has undergone chemical mechanical polishing treatment, and similarly, the surface of the second memory chip 130 with the second passivation layer 131 and the second metal pad 132 has also undergone chemical mechanical polishing treatment.

[0066] Specifically, the first memory chip 120 and the second memory chip 130 in each group of memory chips are hybrid bonded together to form a structure as shown in the figure. Figure 9 The multiple memory micromodules 150 shown specifically include:

[0067] First, such as Figure 3As shown, the first passivation layer 121 in the first memory chip 120 is bonded with the second passivation layer 131 in the corresponding second memory chip 130. The first passivation layer 121 and the second passivation layer 131 are both silicon dioxide passivation layers, and the circuit layers of the first memory chip 120 and the second memory chip 130 are stacked with each other, so that the first passivation layer 121 and the second passivation layer 131, i.e. the silicon dioxide passivation layers, on the surfaces form the bonding.

[0068] Secondly, as shown in the figure, the first metal pad 122 in the first memory chip 120 is bonded with the second metal pad 132 in the corresponding second memory chip 130. In this embodiment, the first metal pad 122 and the second metal pad 132 are both copper pads, and after the first passivation layer 121 and the second passivation layer 131 are bonded, high-temperature compression is performed at a temperature of 200°C or higher, so that the first metal pad 122 and the second metal pad 132 are bonded by the expansion of copper under heat. Figure 3

[0069] It should be noted that when the thickness of the first memory chip 120 is very thin and a plurality of second conductive vias 140b can be exposed, the first memory chip 120 does not need to be thinned; similarly, when the thickness of the second memory chip 130 is very thin and a plurality of second conductive vias 140b can be exposed, the second memory chip 130 also does not need to be thinned. However, when the thickness of the first memory chip 120 is very thick and a plurality of second conductive vias 140b cannot be exposed, and the thickness of the second memory chip 130 is also very thick and a plurality of second conductive vias 140b cannot be exposed, the first memory chip 120 and the second memory chip 130 need to be thinned first. In this embodiment, the first memory chip 120 and the second memory chip 130 both need to be thinned.

[0070] For example, before the plurality of memory micro-module insulating stacks are sequentially arranged on the buffer chip, the method further comprises:

[0071] First, the surface of the first memory chip away from the second memory chip is thinned to expose a plurality of second conductive vias. Specifically, as shown in the figure, the back surface of the first memory chip 120 is thinned, and then a plurality of second conductive vias 140b are exposed by etching process, wherein the first memory chip 120 can be thinned to only retain the circuit layer. Figure 4

[0072] Secondly, a first insulating layer is formed on the surface of the first memory chip away from the second memory chip after the mixed bonding. Specifically, the back surface of the first memory chip 120 forms a first insulating layer 123, and the first insulating layer 123 includes a first passivation sub-layer 123a and a dielectric layer 123b formed in sequence. ​​

[0073] Next, the first insulating layer is patterned to form a plurality of first openings. Specifically, the first insulating layer 123 is patterned using a photolithography process to form a plurality of first openings (not shown in the figure).

[0074] Finally, a plurality of first conductive connection structures are formed at the plurality of first openings, and the first conductive connection structures are electrically connected to the second conductive vias on the first memory chip. Specifically, a plurality of first conductive connection structures 124 are formed at the plurality of first openings, and the first conductive connection structure 124 includes a first connecting metal pad 124a and a plurality of first bumps 124b formed sequentially.

[0075] More specifically, a back-side aperture process is performed on the back side of the hybrid-bonded first memory 120 to form a first insulating layer 123. In this embodiment, as... Figure 4 As shown, a first passivation sublayer 123a is first formed on the back side of the first memory 120, wherein the first passivation sublayer 123a can be a silicon dioxide passivation layer; the first passivation sublayer 123a is patterned using a photolithography process, and a structure as shown is formed on the patterned first passivation sublayer 123a. Figure 4 The first connection metal pad 124a shown in the figure can be a nickel-gold pad in this embodiment; as shown Figure 5 As shown, a dielectric layer 123b is formed on the first connecting metal pad 124a. The material of the dielectric layer 123b can be polyimide (PI), polybenzoxazole (PBO), etc. In this embodiment, the material of the dielectric layer 123b is polyimide (PI), and the formation method is usually wafer spin coating. The dielectric layer 123b is patterned using a photolithography process, and a dielectric layer 123b is formed on the patterned dielectric layer 123b as shown in the figure. Figure 5 The first bump 124b shown can be a copper-tin bump in this embodiment. That is, as shown... Figure 5 As shown, a first passivation sublayer 123a, a first connecting metal pad 124a, a dielectric layer 123b, and a first bump 124b are sequentially formed on the back side of the thinned and mixed-bond first memory 120.

[0076] For example, before sequentially insulatingly stacking the plurality of said memory micromodules on the buffer chip, the method further includes:

[0077] First, the surface of the second memory chip facing away from the first memory chip is thinned to expose multiple second conductive vias. Specifically, as shown... Figure 6 As shown, the back side of the second memory 130 is thinned, and then a plurality of second conductive vias 140b are exposed by etching.

[0078] Secondly, a second insulating layer is formed on the surface of the second memory chip away from the first memory chip after the hybrid bonding. Specifically, as shown in Figure 7 a backside opening process is performed on the back surface of the second memory chip 130 to form a second insulating layer 133, which, in this embodiment, includes a second passivation sub-layer, which can be a silicon dioxide passivation layer.

[0079] Thirdly, the second insulating layer is patterned to form a plurality of second openings. Specifically, the second insulating layer 133 is patterned by a photolithography process to form a plurality of second openings (not labeled in the figure).

[0080] Finally, a plurality of second conductive connection structures are formed at the plurality of second openings, which are electrically connected with the second conductive vias on the second memory chip. Specifically, as shown in Figure 7 a plurality of second conductive connection structures 134 are formed at the plurality of second openings, which are electrically connected with the second conductive vias 140b on the second memory chip 130. In this embodiment, the second conductive connection structures 134 include second connection metal pads, which can be nickel-gold pads.

[0081] S130, sequentially arrange a plurality of the memory micro-module insulating stacks on the buffer chip.

[0082] Specifically, as shown in Figure 9 first, a plurality of memory micro-modules 150 are fixed on the back surface of the buffer chip 110, and then cutting is performed to form a plurality of independent memory micro-module combinations, each of which includes the bottom buffer chip 110 and the memory micro-module 150 arranged on the buffer chip 110. As shown in Figure 10 the same process is used to arrange a plurality of memory micro-modules 150 on the independent memory micro-module combinations in an insulating stack, that is, sequentially arrange a plurality of memory micro-modules 150 on the buffer chip 110 in an insulating stack.

[0083] As shown in Figure 9 the back surface of the buffer chip 110 is provided with a passivation layer and a metal pad, and the front surface of the buffer chip 110 is sequentially provided with a passivation layer, a metal pad, a dielectric layer, and a plurality of bumps.

[0084] For example, as shown in Figure 8 a non-conductive adhesive film 160 is arranged between two adjacent memory micro-modules 150.

[0085] For example, as shown in Figure 8As shown, when the first bump is arranged on the first memory chip, the non-conductive adhesive film is arranged between the two adjacent memory micro-modules, and the non-conductive adhesive film is arranged on the side of the first bump away from the first memory chip.

[0086] Specifically, as shown in Figure 8 As shown, when the first bump 124b is arranged on the first memory chip 120, the non-conductive adhesive film 160 is arranged between the two adjacent memory micro-modules 150, and the non-conductive adhesive film 160 is arranged on the side of the first bump 124a away from the first memory chip 120.

[0087] S140, forming a plastic sealing layer, the plastic sealing layer wrapping the plurality of memory micro-modules and the buffer chip.

[0088] Specifically, as shown in Figure 11 As shown, the plurality of memory micro-modules 150 and the buffer chip 110 are plastic sealed by plastic sealing material to form a plastic sealing layer 170. The plastic sealing method can be film layer vacuum pressing or traditional plastic sealing process, which is not limited in the embodiment. After plastic sealing, cutting is performed to form a final independent multi-layer stacked high-width-band memory package structure.

[0089] Exemplarily, as shown in Figure 11 As shown, in each group of memory chips, the first memory chip 120 is arranged close to the buffer chip 110, the second memory chip 130 is arranged away from the buffer chip 110, and the thickness of the first memory chip 120 is smaller than the thickness of the second memory chip 120. Further preferably, the thickness of the first memory chip 120 is 10-20um, and the thickness of the second memory chip 130 is 40-50um, wherein the back of the first memory chip 120 can be thinned to the limit, that is, only the circuit layer can be reserved.

[0090] The wafer-level hybrid bonding of the first memory chip and the second memory chip utilizes the production efficiency of wafer-level hybrid bonding, and also reduces the yield loss problem in multi-layer wafer-level hybrid bonding. As shown in Figure 12 and Figure 13 As shown, the positions of the defective chips of the two wafers are different in the wafer, as shown in Figure 14 When the two wafers are stacked with each other, additional loss will be caused, so the more the number of stacked layers of the wafer level is, the greater the yield loss is. Two-layer stacking can preferably use similar wafers to minimize such yield loss. In the embodiment, in order to minimize the yield loss in the wafer-level stacking process, the first memory chip 120 and the second memory chip 130 are of the same type.

[0091] The first memory chip and the second memory chip are electrically connected by wafer-level hybrid bonding, which can realize a smaller pitch (less than 10 um), and as a memory micro module, the back of the first memory chip can be thinned to the limit, so that the thickness of the double-chip combination is greatly reduced compared with the same through-silicon via chip of the conventional high-bandwidth memory, and the number and height of the bumps are also reduced, and the number of chip layers can be greatly increased, and the capacity is increased.

[0092] The packaging method of the multi-layer stacked high-bandwidth memory of the application forms a double-chip electrical connection by using wafer-level hybrid bonding to form a memory micro module, realizes a reduction in bonding height, greatly increases the number of chip layers, increases the capacity, and realizes super multi-layer chip stacking. At the same time, the production efficiency is improved, and the yield loss of wafer-level stacking is minimized.

[0093] As shown in Figure 11 Another aspect of the application provides a multi-layer stacked high-bandwidth memory packaging structure 100, comprising:

[0094] A buffer chip 110 is provided with a plurality of first conductive vias 140a;

[0095] A plurality of memory micro modules 150 are insulatively stacked on the buffer chip 110; wherein,

[0096] Each memory micro module 150 comprises a first memory chip 120 and a second memory chip 130, and the first memory chip 120 and the second memory chip 130 are each provided with a plurality of second conductive vias 140b corresponding to and electrically connected to the plurality of first conductive vias 140a; and,

[0097] Each first memory chip 120 is hybrid-bonded to the corresponding second memory chip 130 through a hybrid bonding structure; wherein a non-conductive adhesive film 160 is arranged between the adjacent two memory micro modules 150.

[0098] A plastic encapsulation layer 170 encapsulates the plurality of memory micro modules 150 and the buffer chip 110.

[0099] As shown in Figure 11 The hybrid bonding structure comprises a first passivation layer 121 and a first metal pad 122 arranged on the surface of the first memory chip 120 facing the second memory chip 130, and a second passivation layer 131 and a second metal pad 132 arranged on the surface of the second memory chip 130 facing the first memory chip 120; in this embodiment, the first passivation layer 121 and the second passivation layer 131 can each be a silicon dioxide passivation layer, and the first metal pad 122 and the second metal pad 132 can each be a copper pad.

[0100] The first passivation layer 121 in the first memory chip 120 is bonded to the second passivation layer 131 in the corresponding second memory chip 130, and the first metal pad 122 in the first memory chip 120 is bonded to the second metal pad 132 in the corresponding second memory chip 130.

[0101] For example, such as Figure 11 As shown, a first insulating layer 123 is provided on the surface of the first memory chip 120 that is opposite to the surface of the second memory chip 130;

[0102] The first insulating layer 123 has multiple first openings (not shown in the figure);

[0103] A first conductive connection structure 124 is provided at multiple first openings, and the first conductive connection structure 124 is electrically connected to the second conductive through hole 140b on the first memory chip 120.

[0104] For example, such as Figure 11 As shown, the first insulating layer 123 includes a first passivation sub-layer 123a and a dielectric layer 123b disposed on the first passivation sub-layer 123a. The first passivation sub-layer 123a can be a silicon dioxide passivation layer, and the dielectric layer 123b can be made of polyimide (PI), polybenzoxazole (PBO), etc. In this embodiment, the dielectric layer 123b is made of polyimide (PI).

[0105] The first conductive connection structure 124 includes a first connecting metal pad 124a and a plurality of first bumps 124b disposed on the first connecting metal pad 124a. In this embodiment, the first connecting metal pad 124a can be a nickel-gold pad, and the first bumps 124b can be copper-tin bumps.

[0106] Optional, such as Figure 11 As shown, a second insulating layer 133 is disposed on the surface of the second memory chip 130 opposite to the surface of the first memory chip 120. In this embodiment, the second insulating layer 133 includes a second passivation sublayer, which may be a silicon dioxide passivation layer.

[0107] The second insulating layer 133 is provided with multiple second openings (not shown in the figure);

[0108] A second conductive connection structure 134 is provided at multiple second openings, and the second conductive connection structure 134 is electrically connected to the second conductive via 140b on the second memory chip 130. In this embodiment, the second conductive connection structure 134 includes a second connecting metal pad, which can be a nickel-gold pad.

[0109] For example, such as Figure 11As shown, the first memory chip 120 is arranged close to the buffer chip 110, the second memory chip 130 is arranged away from the buffer chip 110, and the thickness of the first memory chip 120 is less than the thickness of the second memory chip 130. Further preferably, the thickness of the first memory chip 120 is 10-20 um, the thickness of the second memory chip 130 is 40-50 um, and the back of the first memory chip 120 can be thinned to the limit, i.e. only the circuit layer is reserved.

[0110] The packaging structure of the multilayer stacked high-width-band memory of the present application, the first memory chip and the second memory chip form a memory micro-module, and a plurality of memory micro-modules are insulatively stacked on the buffer chip. In the packaging structure, the number of chip layers can be greatly increased, the capacity is increased, and the packaging height is reduced to the maximum extent.

[0111] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A method of packaging a multi-tier stacked high bandwidth memory, the method comprising: The method comprises: respectively providing a buffer chip and a plurality of groups of memory chips, each group of memory chips comprising a first memory chip and a second memory chip; wherein the buffer chip is provided with a plurality of first conductive vias, the first memory chip and the second memory chip are each provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias; wherein the first memory chip and the second memory chip are of the same type; respectively wafer-level hybrid bonding the first memory chip and the second memory chip in each group of memory chips to form a plurality of memory micro-modules, in each group of memory chips, the first memory chip is arranged close to the buffer chip, the second memory chip is arranged away from the buffer chip, and the thickness of the first memory chip is less than the thickness of the second memory chip, wherein the back surface of the first memory chip can be thinned to the limit; sequentially stacking a plurality of memory micro-modules on the buffer chip, wherein a non-conductive adhesive film is arranged between adjacent two memory micro-modules; forming a plastic encapsulation layer, which encapsulates the plurality of memory micro-modules and the buffer chip.

2. The method of claim 1, wherein, The surface of the first memory chip facing the second memory chip is provided with a first passivation layer and a first metal pad, and the surface of the second memory chip facing the first memory chip is provided with a second passivation layer and a second metal pad; The respectively wafer-level hybrid bonding the first memory chip and the second memory chip in each group of memory chips to form a plurality of memory micro-modules comprises: bonding the first passivation layer in the first memory chip with the second passivation layer in the corresponding second memory chip; and, bonding the first metal pad in the first memory chip with the second metal pad in the corresponding second memory chip.

3. The method of claim 2, wherein, Before sequentially stacking a plurality of memory micro-modules on the buffer chip, the method further comprises: forming a first insulating layer on the surface of the first memory chip away from the second memory chip after hybrid bonding; patterning the first insulating layer to form a plurality of first openings; forming a plurality of first conductive connection structures at the plurality of first openings, the first conductive connection structures being electrically connected with the second conductive vias on the first memory chip.

4. The method of claim 3, wherein, The first insulating layer comprises a first passivation sub-layer and a dielectric layer formed in sequence; The first conductive connection structure comprises a first connection metal pad and a first bump provided on the first connection metal pad.

5. The method of claim 3, wherein, Before sequentially stacking a plurality of memory micro-modules on the buffer chip, the method further comprises: forming a second insulating layer on the surface of the second memory chip away from the first memory chip after hybrid bonding; patterning the second insulating layer to form a plurality of second openings; forming a plurality of second conductive connection structures at the plurality of second openings, the second conductive connection structures being electrically connected with the second conductive vias on the second memory chip.

6. The method of claim 5, wherein, The second insulating layer comprises a second passivation sub-layer, and the second conductive connection structure comprises a second connection metal pad.

7. The method according to any one of claims 1 to 6, characterized in that, When the first bump is provided on the first memory chip, the non-conductive adhesive film is provided between the two adjacent memory micro-modules. The non-conductive adhesive film is provided on the side of the first bump away from the first memory chip.

8. The method according to any one of claims 1 to 6, characterized in that, The conductive via is a through-silicon via.

9. A multi-tier stacked high-bandwidth memory package structure, comprising: The package method of the multi-layer stacked high-bandwidth memory according to any one of claims 1 to 8 is used to package to form a package structure, wherein the package structure comprises: a buffer chip provided with a plurality of first conductive vias; a plurality of memory micro-modules insulatively stacked on the buffer chip; wherein each of the memory micro-modules comprises a first memory chip and a second memory chip, and the first memory chip and the second memory chip are both provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias and electrically connected to the plurality of first conductive vias; and each of the first memory chips is hybrid-bonded to the corresponding second memory chip through a hybrid-bonding structure; a plastic encapsulation layer wrapping the plurality of memory micro-modules and the buffer chip.

10. The package structure of claim 9, wherein, The hybrid-bonding structure comprises a first passivation layer and a first metal pad provided on the surface of the first memory chip facing the second memory chip, and a second passivation layer and a second metal pad provided on the surface of the second memory chip facing the first memory chip; the first passivation layer in the first memory chip is bonded to the second passivation layer in the corresponding second memory chip, and the first metal pad in the first memory chip is bonded to the second metal pad in the corresponding second memory chip.

11. The package structure of claim 9, wherein, The surface of the first memory chip away from the second memory chip is provided with a first insulating layer; the first insulating layer is provided with a plurality of first openings; the plurality of first openings are provided with a first conductive connection structure electrically connected to the second conductive vias on the first memory chip.

12. The package structure of claim 11, wherein, The first insulating layer comprises a first passivation sub-layer and a dielectric layer provided on the first passivation sub-layer; The first conductive connection structure comprises a first connection metal pad and a plurality of first bumps provided on the first connection metal pad.

13. The package structure of claim 9, wherein, The surface of the second memory chip away from the first memory chip is provided with a second insulating layer; the second insulating layer is provided with a plurality of second openings; the plurality of second openings are provided with a second conductive connection structure electrically connected to the second conductive vias on the second memory chip.

14. The package structure of claim 9, wherein, The first memory chip is provided close to the buffer chip, the second memory chip is provided away from the buffer chip, and the thickness of the first memory chip is less than the thickness of the second memory chip.

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