Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate having a dielectric layer thereon, the dielectric layer having an opening within the dielectric layer that exposes the substrate surface; forming a barrier layer at the bottom and a portion of the sidewall surface of the opening, wherein the top surface of the barrier layer is lower than the top surface of the dielectric layer; and forming a conductive layer within the opening, wherein the conductive layer is located on the surface of the barrier layer. Because the height of the barrier layer located on the portion of the sidewall surface of the opening meets specific process requirements, after forming the conductive layer, the barrier layer does not need to be etched, thereby reducing etching damage to the conductive layer, improving the morphology of the formed conductive layer, and thereby improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Interconnects are essential structures in semiconductor devices, connecting active areas, transistors, and metal lines on different layers, enabling signal transmission and control. Therefore, during semiconductor manufacturing, the formation of interconnects significantly impacts both device performance and manufacturing costs.

[0003] The interconnect structure generally uses a conductive plug made of a metal material. Currently, in order to improve the adhesion between the conductive plug and the dielectric layer, a barrier layer is formed between the conductive plug and the dielectric layer, which can effectively improve the performance of the interconnect structure.

[0004] However, the performance of the semiconductor structure with the barrier layer formed by the prior art is still relatively poor. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has a dielectric layer, and the dielectric layer has an opening exposing the substrate surface; forming a barrier layer on the bottom and part of the sidewall surface of the opening, and the top surface of the barrier layer is lower than the top surface of the dielectric layer; forming a conductive layer in the opening, and the conductive layer is located on the surface of the barrier layer.

[0007] Optionally, the method for forming the barrier layer includes: forming a barrier material film on the bottom and sidewall surfaces of the opening and the surface of the dielectric layer; and etching the barrier material film until a portion of the sidewall surface of the opening is exposed to form the barrier layer.

[0008] Optionally, the method for etching the blocking material film includes: forming a sacrificial layer on the surface of the blocking material film in the opening, and the top surface of the sacrificial layer is lower than the top surface of the dielectric layer; using the sacrificial layer as a mask, etching the blocking material film to form the blocking layer; after forming the blocking layer, removing the sacrificial layer.

[0009] Optionally, the method for forming the sacrificial layer includes: forming a sacrificial material film in the opening and on the surface of the dielectric layer; and etching back the sacrificial material film to form the sacrificial layer.

[0010] Optionally, the material of the sacrificial material film includes: an organic material containing carbon and oxygen; and the process of forming the sacrificial material film includes: a spin coating process.

[0011] Optionally, the barrier material film is formed by a chemical vapor deposition process or an atomic layer deposition process.

[0012] Optionally, the process of etching the barrier material film is a dry etching process.

[0013] Optionally, the material of the barrier layer includes: titanium nitride, tantalum nitride or tungsten nitride.

[0014] Optionally, the top surface of the conductive layer is flush with the top surface of the barrier layer.

[0015] Optionally, the material of the conductive layer includes: one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0016] Optionally, the method for forming the conductive layer includes: forming a conductive material film in the opening and on the surface of the dielectric layer, and the conductive material film is located on the surface of the blocking layer; etching the conductive material film until the top surface of the blocking layer is exposed, thereby forming the conductive layer in the opening.

[0017] Optionally, the process of etching the conductive material film includes: a wet etching process; the process parameters include: the etching solution used includes dilute hydrofluoric acid, and the dilution ratio is 1000:1 to 3000:1.

[0018] Optionally, it also includes: after forming the conductive material film and before etching the conductive material film, planarizing the conductive material film until the top surface of the dielectric layer is exposed; after the planarization process, etching the conductive material film to form the conductive layer.

[0019] Optionally, the process of planarizing the conductive material film includes: a chemical mechanical polishing process.

[0020] Optionally, the conductive material film is formed by a process including electrochemical plating, a selective metal growth process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0021] Optionally, the base includes: a substrate and a fin located on a surface of the substrate; and the opening exposes the fin.

[0022] Optionally, a gate structure is provided on the substrate, and source and drain doped regions are provided in the substrate on both sides of the gate structure; the opening exposes the top surfaces of the source and drain doped regions.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the barrier layer is first formed, and the barrier layer is located at the bottom and part of the side wall surface of the opening; after the barrier layer is formed, a conductive layer is formed in the opening. Since the height of the barrier layer located on the part of the side wall surface of the opening meets the specific process requirements, after the conductive layer is formed, there is no need to perform an etching process on the barrier layer, thereby reducing the etching damage caused to the conductive layer, which is beneficial to improving the morphology of the formed conductive layer, and further improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 4 It is a structural schematic diagram of each step of a conventional method for forming a semiconductor structure;

[0026] Figures 5 to 11 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0028] First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. Figures 1 to 4 The present invention is a structural schematic diagram of each step of a conventional method for forming a semiconductor structure.

[0029] Please refer to Figure 1 , providing a substrate 100, the substrate 100 comprising: a substrate and a fin located on the surface of the substrate, a dielectric layer 110 and a gate structure 120 spanning the fin on the substrate 100, source-drain doped regions 130 in the fins on both sides of the gate structure 120, the dielectric layer 110 being located on the surface of the gate structure 120 and the source-drain doped regions 130, and the dielectric layer 110 having an opening 140 exposing the top surface of the source-drain doped region 130.

[0030] Please refer to Figure 2 , at the opening 140 ( Figure 1 A barrier material film 150 is formed on the bottom and sidewall surfaces of the dielectric layer 110 and the surface of the dielectric layer 110; a conductive material film 160 is formed on the surface of the barrier material film 150, and the conductive material film 160 fills the opening 140.

[0031] Please refer to Figure 3 , planarizing the barrier material film 150 ( Figure 2 ) and the conductive material film 160 ( Figure 2), until the surface of the dielectric layer 110 is exposed, so that the conductive material film 160 forms an initial conductive layer 161, and the barrier material film 150 forms an initial barrier layer 151.

[0032] Please refer to Figure 4 , etching the initial conductive layer 161 and the initial barrier layer 151 until a portion of the sidewall surface of the opening 140 is exposed, so that the initial conductive layer 161 forms a conductive layer 162, and the initial barrier layer 151 forms a barrier layer 152, and the conductive layer 162 is located on the surface of the barrier layer 152.

[0033] In the above method, the blocking material film 150 is formed before the conductive material film 160 is formed. Since the blocking material film 150 can better adhere to the side wall surface of the opening 140, the conductive material film 160 can better adhere to the blocking material film 150. Therefore, the blocking material film 150 is conducive to the conductive material film 160 being better formed on the bottom and side wall surface of the opening 140.

[0034] However, after forming the initial barrier layer 151 and the initial conductive layer 161, the initial barrier layer 151 and the initial conductive layer 161 need to be etched back, and then an insulating material different from the material of the dielectric layer 110 is formed in the opening 140, so that a plug can be formed on the gate structure 120 in a self-aligned manner to meet specific process requirements. Whether forming the barrier layer 152 by first etching back part of the initial barrier layer 151 and then etching back part of the initial conductive layer 161 to form the conductive layer 162, or forming the conductive layer 162 by first etching back part of the initial conductive layer 161 and then etching back part of the initial barrier layer 151 to form the barrier layer 152, since the existing process has poor etching selectivity for the initial barrier layer 151 and the initial conductive layer 161, it is easy to generate a void A at the interface where the conductive layer 162 and the barrier layer 152 contact during the process of removing part of the initial barrier layer 151, resulting in poor electrical connection between the subsequently formed conductive structure and the conductive layer 162, or even a short circuit.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a barrier layer at the bottom and a portion of the sidewall surface of the opening, wherein the top surface of the barrier layer is lower than the top surface of the dielectric layer; forming a conductive layer in the opening, wherein the conductive layer is located on the surface of the barrier layer. Since the height of the barrier layer located on the surface of the portion of the sidewall of the opening meets the specific process requirements, after the conductive layer is formed, there is no need to perform an etching process on the barrier layer, thereby reducing the etching damage caused to the conductive layer, which is conducive to improving the morphology of the formed conductive layer, and further improving the performance of the formed semiconductor structure.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 5 to 11 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0038] Please refer to Figure 5 , providing a substrate 200 , wherein the substrate 200 has a dielectric layer 210 , and the dielectric layer 210 has an opening 220 exposing the surface of the substrate 200 .

[0039] In this embodiment, the base 200 includes: a substrate (not shown in the figure) and a fin portion (not shown in the figure) located on the surface of the substrate; the opening 200 exposes the fin portion.

[0040] The materials of the substrate and the fins may be single crystal silicon, polycrystalline silicon, or amorphous silicon or silicon germanium, or silicon on insulator (SOI), or may include other materials (such as Group III-V compounds such as gallium arsenide).

[0041] The method for forming the base 200 includes: providing an initial substrate; and patterning the initial substrate to form a substrate and a fin located on the substrate.

[0042] In other embodiments, the base is a planar substrate.

[0043] The dielectric layer 210 is made of a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0044] In this embodiment, a gate structure 231 is provided on the substrate 200 . Source and drain doping regions 232 are provided in the substrate 200 on both sides of the gate structure 231 . The opening 220 exposes the top surfaces of the source and drain doping regions 232 .

[0045] The gate structure 231 includes a gate dielectric layer (not shown in the figure) and a gate layer (not shown in the figure) located on the surface of the gate dielectric layer.

[0046] The material of the gate dielectric layer includes: silicon oxide or high-K dielectric material; the material of the gate layer includes: a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0047] The high-K dielectric material refers to a material with a dielectric constant greater than 3.9.

[0048] The source-drain doping region 232 is doped with source-drain ions, and the source-drain ions include: N-type ions or P-type ions, the N-type ions include phosphorus ions or arsenic ions; the P-type ions include: boron ions, indium ions or BF 2+ .

[0049] Specifically, the dielectric layer 210 covers the gate structure 231 , the substrate, and the surface of the fin.

[0050] A barrier layer is formed on the bottom and part of the sidewall surface of the opening 220, and the top surface of the barrier layer is lower than the top surface of the dielectric layer. For the specific process of forming the barrier layer, please refer to Figures 6 to 8 .

[0051] Please refer to Figure 6 A barrier material film 240 is formed on the bottom and sidewall surfaces of the opening 220 and the surface of the dielectric layer 210 .

[0052] The barrier material film 240 provides material for subsequently forming a barrier layer.

[0053] The material of the barrier material film 240 includes titanium nitride, tantalum nitride or tungsten nitride. In this embodiment, the material of the barrier material film 240 is titanium nitride.

[0054] The barrier material film 240 is formed by a process including electrochemical plating, chemical vapor deposition, or atomic layer deposition.

[0055] In this embodiment, the process for forming the barrier material film 240 is an atomic layer deposition process. By using the atomic layer deposition process, the barrier material film 240 formed has good step coverage and good thickness uniformity on the side walls and bottom surface of the opening 220, which is beneficial to improving the morphology of the barrier material film 240.

[0056] Next, the barrier material film 240 is etched until a portion of the sidewall surface of the opening 220 is exposed to form the barrier layer. For details on the process of etching the barrier material film, please refer to Figures 7 and 8 .

[0057] Please refer to Figure 7 A sacrificial layer 250 is formed on the surface of the barrier material film 240 in the opening 220 , and a top surface of the sacrificial layer 250 is lower than a top surface of the dielectric layer 210 .

[0058] The sacrificial layer 250 is used as a mask for subsequent etching of the barrier material film 240 to protect the portion of the barrier material film 240 covered by the sacrificial layer 250 from being etched.

[0059] The method for forming the sacrificial layer 250 includes: forming a sacrificial material film (not shown in the figure) in the opening 220 and on the surface of the dielectric layer 210 ; and etching back the sacrificial material film to form the sacrificial layer 250 .

[0060] The material of the sacrificial material film includes: an organic material containing carbon and oxygen; the formation process of the sacrificial material film includes: a spin coating process.

[0061] The process of etching back the sacrificial material film includes: an ashing process, a dry etching process and a wet etching process, or a combination of multiple processes.

[0062] Please refer to Figure 8 , using the sacrificial layer 250 as a mask, etching the barrier material film 240 to form the barrier layer 241 .

[0063] The function of the barrier layer 241 is, on the one hand, to prevent ions or atoms in the material subsequently formed in the opening 220 from diffusing into the dielectric layer 210 located on the sidewall of the opening 220 or the source / drain doping region 232 located at the bottom of the opening 220; and on the other hand, to increase the adhesion of the conductive material film subsequently formed, thereby improving the performance of the formed conductive material film.

[0064] Specifically, the top surface of the barrier layer 241 is lower than the top surface of the dielectric layer 210 .

[0065] Specifically, the sacrificial layer 250 is used as a mask to etch the barrier material film 240 , and the barrier material film 240 exposed by the sacrificial layer 250 is removed to form the barrier layer 241 . The barrier layer 241 exposes a portion of the sidewall surface of the opening 220 .

[0066] In this embodiment, the top surface of the barrier layer 241 is flush with the top surface of the sacrificial layer 240 .

[0067] In other embodiments, the top surface of the barrier layer is lower than or higher than the top surface of the sacrificial layer.

[0068] The process of etching the barrier material film 240 is a dry etching process.

[0069] By using the dry etching process to etch the barrier material film 240 , the etching amount of the barrier material film 240 can be more accurately controlled, thereby accurately controlling the height of the formed barrier layer 241 .

[0070] It should be noted that the height refers to the dimension in a direction perpendicular to the surface of the substrate 200 .

[0071] Since the barrier layer 241 is formed by etching a barrier material film, the material of the barrier layer 241 includes titanium nitride, tantalum nitride or tungsten nitride. In this embodiment, the material of the barrier layer 241 is titanium nitride.

[0072] In this embodiment, after forming the barrier layer 241 , the process further includes: removing the sacrificial layer 250 .

[0073] The process of removing the sacrificial layer 250 includes: an ashing process, a wet etching process, and a dry etching process, or a combination of multiple processes.

[0074] In this embodiment, the process of removing the sacrificial layer 250 is an ashing process.

[0075] After forming the barrier layer 241, a conductive layer is formed in the opening 220, and the conductive layer is located on the surface of the barrier layer 241. For the specific process of forming the conductive layer, please refer to Figures 9 to 11 .

[0076] Please refer to Figure 9 A conductive material film 260 is formed in the opening 220 and on the surface of the dielectric layer 210 , and the conductive material film 260 is located on the surface of the barrier layer.

[0077] The conductive material film 260 provides material for subsequently forming a conductive layer.

[0078] The conductive material film 260 may be formed by an electrochemical plating process, a selective metal growth process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

[0079] The conductive material film 260 may be made of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum. In this embodiment, the conductive material film 260 is made of cobalt.

[0080] Please refer to Figure 10 , planarizing the conductive material film 260 until the top surface of the dielectric layer 210 is exposed.

[0081] The process of planarizing the conductive material film 260 includes a chemical mechanical polishing process.

[0082] By planarizing the conductive material film 260 , the surface of the conductive material film 260 is made flat, so that the surface of the conductive layer formed after the conductive material film 260 is subsequently etched is flat and has a good morphology, thereby improving the performance of the formed semiconductor structure.

[0083] Please refer to Figure 11After the planarization process, the conductive material film 260 is etched until the top surface of the barrier layer 241 is exposed, thereby forming the conductive layer 270 in the opening 220 .

[0084] The process of etching the conductive material film 260 includes: a dry etching process or a wet etching process, or a combination of the two.

[0085] In this embodiment, the process of etching the conductive material film 260 is a wet etching process; the process parameters include: the etching solution used includes dilute hydrofluoric acid, and the dilution ratio is 1000:1 to 3000:1.

[0086] In another embodiment, the process of etching the conductive material film 260 is a wet etching process; the process parameters include: the etching process used is a mixed solution of hydrogen peroxide and ammonia water, and the ratio of hydrogen peroxide to ammonia water is 3:1 to 1:1.

[0087] The wet etching process is used, so that it is less likely to leave etched material residue on the sidewalls of the opening 220 and the surface of the dielectric layer 210 , thereby removing the residue more cleanly. At the same time, the surface of the formed conductive layer 270 is smoother, which is beneficial to the electrical performance of the conductive layer 270 .

[0088] In this embodiment, the top surface of the conductive layer 270 is flush with the top surface of the barrier layer 241 .

[0089] The barrier layer 241 is first formed, and the barrier layer 241 is located at the bottom and part of the side wall surface of the opening 220; after the barrier layer 241 is formed, the conductive layer 270 is formed in the opening 220. Since the height of the barrier layer 241 located on the side wall surface of part of the opening 220 has met the specific process requirements, after the conductive layer 270 is formed, there is no need to perform an etching process on the barrier layer 241, thereby reducing the etching damage caused to the conductive layer 270, which is beneficial to improving the morphology of the formed conductive layer, and further improving the performance of the formed semiconductor structure.

[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a dielectric layer thereon, and the dielectric layer has an opening exposing the substrate surface; forming a barrier layer on the bottom and a portion of the sidewall surface of the opening, wherein the top surface of the barrier layer is lower than the top surface of the dielectric layer; A conductive layer is formed in the opening, and the conductive layer is located on the surface of the barrier layer; and the top surface of the conductive layer is lower than the top surface of the dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the barrier layer includes: forming a barrier material film on the bottom and sidewall surfaces of the opening and the surface of the dielectric layer; etching the barrier material film until a portion of the sidewall surface of the opening is exposed to form the barrier layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for etching the barrier material film includes: forming a sacrificial layer on the surface of the barrier material film in the opening, and the top surface of the sacrificial layer is lower than the top surface of the dielectric layer; using the sacrificial layer as a mask, etching the barrier material film to form the barrier layer; after forming the barrier layer, removing the sacrificial layer.

4. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the sacrificial layer comprises: forming a sacrificial material film in the opening and on the surface of the dielectric layer; and etching back the sacrificial material film to form the sacrificial layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The material of the sacrificial material film includes: an organic material containing carbon and oxygen; the formation process of the sacrificial material film includes: a spin coating process.

6. The method for forming a semiconductor structure according to claim 2, wherein: The barrier material film is formed by a process including a chemical vapor deposition process or an atomic layer deposition process.

7. The method for forming a semiconductor structure according to claim 4, wherein: The process of etching the barrier material film is a dry etching process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the barrier layer includes titanium nitride, tantalum nitride or tungsten nitride.

9. The method for forming a semiconductor structure according to claim 1, wherein: The top surface of the conductive layer is flush with the top surface of the barrier layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the conductive layer includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

11. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the conductive layer includes: forming a conductive material film in the opening and on the surface of the dielectric layer, and the conductive material film is located on the surface of the barrier layer; etching the conductive material film until the top surface of the barrier layer is exposed, thereby forming the conductive layer in the opening.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of etching the conductive material film includes: a wet etching process; the process parameters include: the etching solution used includes dilute hydrofluoric acid, and the dilution ratio is 1000:1 to 3000:

1.

13. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: After forming the conductive material film and before etching the conductive material film, planarizing the conductive material film until the top surface of the dielectric layer is exposed; After the planarization process, the conductive material film is etched to form the conductive layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process of planarizing the conductive material film includes: a chemical mechanical polishing process.

15. The method for forming a semiconductor structure according to claim 11, wherein: The conductive material film is formed by a process including electrochemical plating, selective metal growth, physical vapor deposition, chemical vapor deposition or atomic layer deposition.

16. The method for forming a semiconductor structure according to claim 1, wherein: The base comprises: a substrate and a fin portion located on a surface of the substrate; the opening exposes the fin portion.

17. The method for forming a semiconductor structure according to claim 1, wherein: A gate structure is provided on the substrate, and source and drain doping regions are provided in the substrate on both sides of the gate structure; the opening exposes the top surfaces of the source and drain doping regions.

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