Display panel manufacturing method and display panel

Abstract

The embodiments of the present application disclose a display panel manufacturing method and a display panel, which include a driving transistor, a storage capacitor, a switching transistor, and a sensing transistor stacked up and down, wherein at least two transistors are stacked up and down on each other, so as to solve the technical problem that the pixels in the display panel of the prior art adopt a pixel circuit design including multiple transistors and capacitors arranged in a direction parallel to the display panel, resulting in a decrease in the pixel density of the display panel and a decrease in the resolution of the display panel product.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a display panel manufacturing method and a display panel. Background Art

[0002] With the development of display technology, active light-emitting display panels such as the thin film transistor (TFT) substrate of the organic light emitting diode (OLED) display panel, the micro light emitting diode (Micro LED) display panel, and the sub-millimeter light emitting diode (Mini LED) display panel have the advantages of high contrast, high color gamut, and light weight.

[0003] The existing large-size OLED, Micro LED, and Mini LED adopt a 3T1C external pixel circuit design. One pixel requires three thin-film transistors and one storage capacitor. In the display panel, the three thin-film transistors are arranged side by side in a direction parallel to the display panel, which makes it impossible to reduce the size of the pixel. If the display panel requires better electronic properties, more than four thin-film transistors are required in one pixel, which further increases the pixel size, reduces the pixel density, and leads to a problem of reduced resolution of the display panel product. Summary of the invention

[0004] The main purpose of the present application is to provide a method for manufacturing a display panel and a display panel, so as to solve the technical problem that the pixels in the display panel of the prior art adopt a pixel circuit design including multiple TFTs and capacitors arranged in a horizontal direction parallel to the display panel, which causes a decrease in the pixel density of the display panel and leads to a decrease in the resolution of the display panel product.

[0005] In one aspect, an embodiment of the present application provides a method for manufacturing a display panel, comprising:

[0006] forming a buffer layer on the substrate, and forming a first semiconductor element on the buffer layer;

[0007] forming a first insulating layer on the first semiconductor element and the buffer layer, forming a first metal wiring layer on the first insulating layer, and patterning the first metal wiring layer to form a second gate and a first plate of a storage capacitor, wherein the second gate is located above the first semiconductor element;

[0008] Forming a first interlayer dielectric layer on the buffer layer, the first semiconductor element, and the first metal wiring layer, forming a second metal wiring layer on the first interlayer dielectric layer, and patterning the second metal wiring layer to form a second source and a second drain, wherein the first semiconductor element, the second gate, the second source, and the second drain constitute a driving transistor;

[0009] forming a second interlayer dielectric layer on the second metal wiring layer, and forming a second semiconductor element and a third semiconductor element on the second interlayer dielectric layer; and

[0010] Forming a second insulating layer on the second interlayer dielectric layer, the second semiconductor element, and the third semiconductor element, forming a third metal wiring layer on the second insulating layer, and patterning the third metal wiring layer to form a first gate, a first source, a first drain, a third gate, a third source, and a third drain, wherein the first gate, the first source, and the first drain constitute a switch transistor, and the third gate, the third source, and the third drain constitute a sensing transistor;

[0011] In some embodiments of the present application, the method further comprises:

[0012] forming a passivation layer covering the third metal wiring layer, and forming a planarization layer on the passivation layer; and

[0013] forming an electrode layer on the planarization layer, and arranging a light emitting diode on the electrode layer;

[0014] Wherein, the orthogonal projection of the switch transistor on the base substrate at least partially overlaps with the orthogonal projection of the drive transistor on the base substrate, or at least partially overlaps with the orthogonal projection of the storage capacitor on the base substrate;

[0015] The orthogonal projection of the sensing transistor on the base substrate at least partially overlaps the orthogonal projection of the driving transistor on the base substrate, or at least partially overlaps the orthogonal projection of the storage capacitor on the base substrate.

[0016] In some embodiments of the present application, the storage capacitor and the driving transistor are arranged along a direction parallel to the substrate and are electrically connected to the driving transistor;

[0017] The switch transistor and the drive transistor are arranged along a direction perpendicular to the base substrate; and

[0018] The sensing transistor and the driving transistor are arranged along the direction parallel to the base substrate, and are arranged with the storage capacitor along the direction perpendicular to the base substrate.

[0019] In another aspect, an embodiment of the present application further provides a display panel, including:

[0020] substrate substrate;

[0021] At least one pixel circuit is disposed on the substrate and includes:

[0022] A driving transistor, disposed on the substrate;

[0023] A storage capacitor, disposed on the base substrate and electrically connected to the driving transistor;

[0024] A switch transistor is arranged on the substrate;

[0025] A sensing transistor is disposed on the substrate; and

[0026] A light emitting diode, disposed on the base substrate and electrically connected to the driving transistor and the sensing transistor;

[0027] The orthogonal projection of the switch transistor on the base substrate at least partially overlaps with the orthogonal projection of the drive transistor on the base substrate, or at least partially overlaps with the orthogonal projection of the storage capacitor on the base substrate.

[0028] In some embodiments of the present application, the orthogonal projection of the sensing transistor on the substrate at least partially overlaps the orthogonal projection of the driving transistor on the substrate, or at least partially overlaps the orthogonal projection of the storage capacitor on the substrate.

[0029] In some embodiments of the present application, the storage capacitor and the driving transistor are arranged along a direction parallel to the substrate;

[0030] The switch transistor and the drive transistor are arranged along a direction perpendicular to the base substrate; and

[0031] The sensing transistor and the driving transistor are arranged along the direction parallel to the base substrate, and are arranged with the storage capacitor along the direction perpendicular to the base substrate.

[0032] In some embodiments of the present application, the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is arranged on the same layer as the second source or second drain of the driving transistor, and the second electrode plate is arranged on the same layer as the electrode layer connected to the light-emitting diode.

[0033] In some embodiments of the present application, the first electrode plate and the second electrode plate of the storage capacitor and the sensing transistor are arranged along a direction perpendicular to the base substrate, and the sensing transistor is located between the first electrode plate and the second electrode plate.

[0034] In some embodiments of the present application, the second source or the second drain of the driving transistor is grounded;

[0035] One end of the storage capacitor is grounded;

[0036] wherein the first source or the first drain of the switch transistor is electrically connected to the second gate of the drive transistor and the other end of the storage capacitor; and

[0037] A sensing source or a sensing drain of the sensing transistor is grounded.

[0038] In some embodiments of the present application, the driving transistor is disposed between the switch transistor and the base substrate, and the storage capacitor is disposed between the sensing transistor and the base substrate.

[0039] This application has at least the following advantages:

[0040] The display panel manufacturing method and display panel provided in the embodiments of the present application configure the driving transistor, storage capacitor, switch transistor, and sensing transistor in the 3T1C pixel circuit to at least partially overlap each other's orthogonal projections on the substrate, thereby achieving a vertical stacking of the driving transistor, storage capacitor, switch transistor, and sensing transistor, reducing the area of ​​the pixel in the horizontal direction, solving the technical problem that the pixels in the display panel of the prior art use a pixel circuit design including multiple TFTs and capacitors arranged in a horizontal direction parallel to the display panel, resulting in a decrease in the pixel density of the display panel and a decrease in the resolution of the display panel product, thereby achieving an improvement in the pixel density and the resolution of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 is a cross-sectional view of a thin film transistor (TFT) substrate of a display panel according to an embodiment of the present application;

[0043] Figure 2is a pixel circuit diagram of a display panel according to an embodiment of the present application;

[0044] Figure 3 is a flowchart of the steps of the display panel manufacturing method according to an embodiment of the present application;

[0045] Figure 4 is a cross-sectional view of a semi-finished display panel corresponding to step S01 of the manufacturing method in an embodiment of the present application;

[0046] Figure 5 is a cross-sectional view of a semi-finished display panel corresponding to step S02 of the manufacturing method provided in an embodiment of the present application;

[0047] Figure 6 is a cross-sectional view of a semi-finished display panel corresponding to step S03 of the manufacturing method provided in an embodiment of the present application;

[0048] Figure 7 is a cross-sectional view of a semi-finished display panel corresponding to step S04 of the manufacturing method provided in an embodiment of the present application;

[0049] Figure 8 is a cross-sectional view of a semi-finished display panel corresponding to step S04 and step S05 of the manufacturing method provided in an embodiment of the present application;

[0050] Fig. 9 is a cross-sectional view of a semi-finished display panel corresponding to step S05 of the manufacturing method provided in an embodiment of the present application;

[0051] Fig.10 is a cross-sectional view of a semi-finished display panel corresponding to step S06 of the manufacturing method provided in an embodiment of the present application;

[0052] Fig.11 is a cross-sectional view of another semi-finished display panel corresponding to step S06 of the manufacturing method provided in an embodiment of the present application;

[0053] Fig.12 is a cross-sectional view of a semi-finished display panel corresponding to step S07 of the manufacturing method provided in an embodiment of the present application;

[0054] Fig.13 is a cross-sectional view of another semi-finished display panel corresponding to step S07 of the manufacturing method provided in an embodiment of the present application;

[0055] Fig.14 is a cross-sectional view of a semi-finished display panel corresponding to step S08 of the manufacturing method provided in an embodiment of the present application;

[0056] Fig.15 It is a cross-sectional view of a finished display panel corresponding to step S08 of the manufacturing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0058] The main purpose of the present application is to provide a method for manufacturing a display panel and a display panel, so as to solve the technical problem that the display panel pixels in the prior art adopt a pixel circuit design including multiple TFTs and capacitors arranged in a direction parallel to the display panel, which causes a decrease in the pixel density of the display panel and leads to a decrease in the resolution of the display panel product.

[0059] Please refer to Figures 1 to 3 The present application embodiment provides a method for manufacturing a display panel, for manufacturing Figure 1 and Figure 2 The display panel shown includes a 3T1C pixel circuit. The manufacturing method can also be used to manufacture a display panel including a 4T1C pixel circuit or a display panel including more TFTs according to the same principle.

[0060] Please refer to Figure 3 , the display panel manufacturing method comprises:

[0061] Step S01, forming a light shielding layer on a base substrate.

[0062] Please refer to Figure 4 In the above steps, a light shielding layer LS is formed on the base substrate 10. The light shielding layer LS is not a necessary structure of the display panel, so the step S01 can be omitted. The light shielding layer LS is used to prevent the display panel from generating unnecessary light leakage, and it can be a metal layer.

[0063] Step S02: forming a buffer layer on the substrate, and forming a first semiconductor element on the buffer layer.

[0064] Please refer to Figure 5 In the above steps, the buffer layer B is formed on the base substrate 10 and the light shielding layer LS, and the first semiconductor element SC1 is formed on the buffer layer B. The first semiconductor element SC1 is used to form a subsequent driving transistor, which will be further described below.

[0065] Step S03, forming a first insulating layer on the first semiconductor element and the buffer layer, forming a first metal wiring layer on the first insulating layer, and patterning the first metal wiring layer to form a second gate and a first plate of a storage capacitor, wherein the second gate is located above the first semiconductor element. The first semiconductor element SC1 can be further used to form a driving transistor, which will be further described below.

[0066] Please refer to Figure 6 In the above steps, the first insulating layer GI1 is formed on the first semiconductor element SC1 and the buffer layer B, the first metal wiring layer 20 is formed on the first insulating layer GI1, and the first metal wiring layer 20 is patterned to form a second gate GE1 and a first electrode C01 of a storage capacitor Cst, wherein the second gate GE1 is located above the first semiconductor element SC1.

[0067] Step S04, forming a first interlayer dielectric layer on the buffer layer, the first semiconductor element, and the first metal wiring layer, forming a second metal wiring layer on the first interlayer dielectric layer, and patterning the second metal wiring layer to form a second source and a second drain, wherein the first semiconductor element, the second gate, the second source, and the second drain constitute a driving transistor.

[0068] Please refer to Figure 7 and Figure 8 In the above steps, the first interlayer dielectric layer ILD1 is formed on the buffer layer B, the first semiconductor element SC1, and the first metal wiring layer 20, the second metal wiring layer 30 is formed on the first interlayer dielectric layer ILD1, and the second metal wiring layer 30 is patterned to form S1 and a second drain D1 corresponding to the second gate GE1, wherein the first semiconductor element SC1, the second gate GE1, the S1 and the second drain D1 constitute a driving transistor T2. The driving transistor T2 can be further used to constitute a 3T1C pixel circuit. Step S05, forming a second interlayer dielectric layer on the second metal wiring layer, forming a second semiconductor element and a third semiconductor element on the second interlayer dielectric layer.

[0069] Please refer to Figure 8 and Fig. 9 In the above steps, the second interlayer dielectric layer ILD2 is formed on the second metal wiring layer 30, and the second semiconductor element SC2 and the third semiconductor element SC3 are formed on the second interlayer dielectric layer ILD2. The second interlayer dielectric layer ILD2 is used for insulation between the metal wiring layer and the semiconductor element.

[0070] Step S06, forming a second insulating layer on the second interlayer dielectric layer, the second semiconductor element, and the third semiconductor element, forming a third metal wiring layer on the second insulating layer, and patterning the third metal wiring layer to form a first gate, a first source, a first drain, a third gate, a third source, and a third drain, the first gate, the first source, and the first drain constitute a switching transistor, and the third gate, the third source, and the third drain constitute a sensing transistor.

[0071] Please refer to Fig.10 and Fig.11 In the above steps, the second insulating layer GI2 is formed on the second interlayer dielectric layer ILD2, the second semiconductor element SC2, and the third semiconductor element SC3, the third metal wiring layer 40 is formed on the second insulating layer GI2, and the third metal wiring layer 40 is patterned to form a first gate GE2, a first source S2, a first drain D2, a third gate GE3, a third source S3, and a third drain D3. The first gate GE2, the first source S2, and the first drain D2 constitute a switch transistor T1, and the third gate GE3, the third source S3, and the third drain D3 constitute a sensing transistor T3. The switch transistor T1, the sensing transistor T3, and the above-mentioned driving transistor T2 can together constitute a 3T1C pixel circuit.

[0072] Step S07, forming a passivation layer covering the third metal circuit layer, and forming a planarization layer on the passivation layer.

[0073] Please refer to Fig.12 and Fig.13 In the above steps, the passivation layer covers the third metal circuit layer 40, and the planarization layer PLN is formed on the passivation layer PV.

[0074] Step S08, forming an electrode layer on the planarization layer, and disposing a light emitting diode on the electrode layer, thereby completing the manufacture of a finished display panel.

[0075] Please refer to Fig.14 and Fig.15 In the above steps, the electrode layer PE is formed on the planarization layer PLN, and the light emitting diode 50 is disposed on the electrode layer PE, thereby completing the manufacture of the finished display panel 1. In addition, the electrode layer PE is disposed on the same layer as the second electrode plate C02 of the storage capacitor Cst.

[0076] The orthogonal projection of the switch transistor T1 on the base substrate 10 at least partially overlaps the orthogonal projection of the drive transistor T2 on the base substrate 10, or at least partially overlaps the orthogonal projection of the storage capacitor Cst on the base substrate 10. Since the orthogonal projection of the switch transistor T1 at least partially overlaps the orthogonal projection of the drive transistor T2 or the orthogonal projection of the storage capacitor Cst, the switch transistor T1 and the drive transistor T2 are stacked in the vertical direction of the base substrate 10, and the area of ​​the pixel circuit composed of the drive transistor T2, the switch transistor T1, and the sensing transistor T3 along the direction parallel to the display panel 1 is reduced, thereby improving the pixel density, thereby improving the resolution of the display panel.

[0077] In some embodiments of the present application, the orthogonal projection of the sensing transistor T3 on the base substrate 10 at least partially overlaps the orthogonal projection of the driving transistor T2 on the base substrate 10, or at least partially overlaps the orthogonal projection of the storage capacitor Cst on the base substrate 10. Since the orthogonal projection of the sensing transistor T3 at least partially overlaps the orthogonal projection of the driving transistor T2 or the orthogonal projection of the storage capacitor Cst, the switch transistor T1 and the driving transistor T2 are stacked in the vertical direction of the base substrate 10, reducing the area of ​​the pixel circuit composed of the driving transistor T2, the switch transistor T1, and the sensing transistor T3 in the direction parallel to the display panel 1, thereby improving the pixel density.

[0078] In some embodiments of the present application, the storage capacitor Cst and the driving transistor T2 are arranged along a direction X parallel to the base substrate 10, and are electrically connected to the driving transistor T2; the switch transistor T1 and the driving transistor T2 are arranged along a direction Y perpendicular to the base substrate 10; and the sensing transistor T3 and the driving transistor T2 are arranged along the direction X parallel to the base substrate 10, and are arranged with the storage capacitor Cst along the direction Y perpendicular to the base substrate 10. In some embodiments of the present application, the light emitting diode 50 is electrically connected to the driving transistor T2, the switch transistor T1, and the sensing transistor T3 through the electrode layer PE.

[0079] In some embodiments of the present application, the first source S2 or the first drain D2 is electrically connected to the second gate GE1 through a first via hole penetrating the second interlayer dielectric layer ILD2, and the electrode layer PE is electrically connected to the switch transistor and the sensing transistor T3 through a second via hole penetrating the passivation layer and the planarization layer PLN.

[0080] Please refer to Figure 1 and Figure 2 On the other hand, an embodiment of the present application provides a display panel 1, comprising: a base substrate 10 and at least one pixel circuit.

[0081] The pixel circuit is disposed on the base substrate 10 and includes a driving transistor T2 , a storage capacitor Cst, a switch transistor T1 , a sensing transistor T3 , and a light emitting diode 50 .

[0082] The driving transistor T2 is disposed above the base substrate 10 .

[0083] The storage capacitor Cst is disposed above the base substrate 10 and is electrically connected to the driving transistor T2. In addition, the storage capacitor Cst includes a first plate C01 and a second plate C02. Figure 1 shown.

[0084] The switch transistor T1 is disposed above the base substrate 10 .

[0085] The sensing transistor T3 is disposed above the base substrate 10 .

[0086] The light emitting diode 50 is disposed above the base substrate 10 and is electrically connected to the driving transistor T2 and the sensing transistor T3 .

[0087] The orthogonal projection of the switch transistor T1 on the base substrate 10 at least partially overlaps with the orthogonal projection of the drive transistor T2 on the base substrate 10, or at least partially overlaps with the orthogonal projection of the storage capacitor Cst on the base substrate 10. Since the orthogonal projection of the switch transistor T1 at least partially overlaps with the orthogonal projection of the drive transistor T2 or the orthogonal projection of the storage capacitor Cst, the switch transistor T1 and the drive transistor T2 are stacked in the vertical direction of the base substrate 10, reducing the area of ​​the pixel circuit composed of the drive transistor T2, the switch transistor T1, and the sensing transistor T3 in the direction parallel to the display panel 1, thereby improving the pixel density.

[0088] The orthogonal projection of the sensing transistor T3 on the base substrate 10 at least partially overlaps the orthogonal projection of the driving transistor T2 on the base substrate 10, or at least partially overlaps the orthogonal projection of the storage capacitor Cst on the base substrate 10. Since the orthogonal projection of the sensing transistor T3 at least partially overlaps the orthogonal projection of the driving transistor T2 or the orthogonal projection of the storage capacitor Cst, the switch transistor T1 and the driving transistor T2 are stacked in the vertical direction of the base substrate 10, reducing the area of ​​the pixel circuit formed by the driving transistor T2, the switch transistor T1, and the sensing transistor T3 in the direction parallel to the display panel 1, thereby improving the pixel density.

[0089] In some embodiments of the present application, the storage capacitor Cst and the driving transistor T2 are arranged along a direction X parallel to the base substrate 10; the switching transistor T1 and the driving transistor T2 are arranged along a direction Y perpendicular to the base substrate 10; and the sensing transistor T3 and the driving transistor T2 are arranged along the direction X parallel to the base substrate 10, and are arranged with the storage capacitor Cst along the direction Y perpendicular to the base substrate 10.

[0090] In some embodiments of the present application, the storage capacitor Cst includes a first plate C01 and a second plate C02, the first plate C01 is arranged on the same layer as the second source S1 or the second drain D1 of the driving transistor T1, and the second plate C02 is arranged on the same layer as the electrode layer PE of the light-emitting diode 50.

[0091] In some embodiments of the present application, the first electrode plate C01 and the second electrode plate C02 of the storage capacitor Cst and the sensing transistor are arranged along a direction perpendicular to the base substrate 10, and the sensing transistor is located between the first electrode plate C01 and the second electrode plate C02.

[0092] In some embodiments of the present application, S1 or the second drain D1 of the driving transistor T2 is grounded;

[0093] One end of the storage capacitor Cst is grounded; the first source S2 or the first drain D2 of the switch transistor T1 is electrically connected to the second gate GE1 of the driving transistor T2 and the other end of the storage capacitor Cst; and the third source S3 or the third drain D3 of the sensing transistor T3 is grounded.

[0094] In some embodiments of the present application, the driving transistor T2 is disposed between the switch transistor T1 and the base substrate 10 , and the storage capacitor Cst is disposed between the sensing transistor T3 and the base substrate 10 .

[0095] In some embodiments of the present application, the display panel 1 further includes a light shielding layer LS, a buffer layer B, a first semiconductor element SC1, a first insulating layer GI1, a first metal wiring layer 20, a first interlayer dielectric layer ILD1, a second metal wiring layer 30, a second interlayer dielectric layer ILD2, a second insulating layer GI2, a third metal wiring layer 40, a passivation layer, a planar layer, and an electrode layer PE, which are sequentially stacked on the base substrate 10; the second gate GE1 of the driving transistor T2 is formed by patterning the first metal wiring layer 20; the S1 and the second drain D1 of the driving transistor T2 are patterned by the second metal wiring layer 30; the first source S2, the first drain D2, and the first gate GE2 of the switching transistor T1 are patterned by the third metal wiring layer 40; the third source S3, the third drain D3, and the third gate GE3 of the sensing transistor T3 are patterned by the third metal wiring layer 40; and the light-emitting diode 50 is arranged on the electrode layer PE. In addition, the second electrode plate C02 of the storage capacitor Cst is formed on the electrode layer PE and is vertically opposite to the first electrode plate C01.

[0096] This application has at least the following advantages:

[0097] The display panel manufacturing method and display panel 1 provided in the embodiment of the present application configure the driving transistor T2, storage capacitor Cst, switch transistor T1, and sensing transistor T3 in the 3T1C pixel circuit to at least partially overlap each other's orthogonal projections on the base substrate 10, so that the driving transistor T2, storage capacitor Cst, switch transistor T1, and sensing transistor T3 are vertically stacked with each other, reducing the area of ​​the pixel in the horizontal direction, solving the technical problem that the pixels in the display panel 1 of the prior art adopt a pixel circuit design including multiple TFTs and capacitors arranged in a horizontal direction parallel to the display panel 1, resulting in a decrease in the pixel density of the display panel 1 and a decrease in the resolution of the display panel product, thereby achieving an improvement in the pixel density and the resolution of the display panel.

[0098] The display panel manufacturing method and the display panel 1 provided in the embodiments of the present application are introduced in detail above.

[0099] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for manufacturing a display panel, characterized in that: include: forming a buffer layer on the substrate, and forming a first semiconductor element on the buffer layer; forming a first insulating layer on the first semiconductor element and the buffer layer, forming a first metal wiring layer on the first insulating layer, and patterning the first metal wiring layer to form a second gate and a first plate of a storage capacitor, wherein the second gate is located above the first semiconductor element; Forming a first interlayer dielectric layer on the buffer layer, the first semiconductor element, and the first metal wiring layer, forming a second metal wiring layer on the first interlayer dielectric layer, and patterning the second metal wiring layer to form a second source and a second drain, wherein the first semiconductor element, the second gate, the second source, and the second drain constitute a driving transistor; Forming a second interlayer dielectric layer on the second metal wiring layer, and forming a second semiconductor element and a third semiconductor element on the second interlayer dielectric layer; Forming a second insulating layer on the second interlayer dielectric layer, the second semiconductor element, and the third semiconductor element, forming a third metal wiring layer on the second insulating layer, and patterning the third metal wiring layer to form a first gate, a first source, a first drain, a third gate, a third source, and a third drain, wherein the first gate, the first source, and the first drain constitute a switch transistor, and the third gate, the third source, and the third drain constitute a sensing transistor; Among them, the first electrode plate and the second electrode plate of the storage capacitor and the sensing transistor are arranged in a direction perpendicular to the substrate, and the sensing transistor is located between the first electrode plate and the second electrode plate, and the third source is connected between the second source and the second electrode plate of the storage capacitor.

2. The method for manufacturing a display panel according to claim 1, wherein: The method further comprises: forming a passivation layer covering the third metal wiring layer, and forming a planarization layer on the passivation layer; and forming an electrode layer on the planarization layer, and arranging a light emitting diode on the electrode layer; wherein the orthogonal projection of the switch transistor on the substrate at least partially overlaps with the orthogonal projection of the drive transistor on the substrate, or at least partially overlaps with the orthogonal projection of the storage capacitor on the substrate; wherein the orthogonal projection of the sensing transistor on the substrate at least partially overlaps with the orthogonal projection of the drive transistor on the substrate, or at least partially overlaps with the orthogonal projection of the storage capacitor on the substrate.

3. The method for manufacturing a display panel according to claim 1, wherein: The storage capacitor and the driving transistor are arranged along a direction parallel to the base substrate and are electrically connected to the driving transistor; The switch transistor and the drive transistor are arranged along a direction perpendicular to the base substrate.

4. A display panel, characterized in that: The display panel comprises: substrate substrate; At least one pixel circuit is disposed on the substrate and includes: A driving transistor, disposed on the substrate; A storage capacitor, disposed on the base substrate and electrically connected to the driving transistor; A switch transistor, disposed on the driving transistor; a sensing transistor disposed on the driving transistor; and A light emitting diode, disposed on the base substrate and electrically connected to the driving transistor and the sensing transistor; Wherein, the orthogonal projection of the switch transistor on the base substrate at least partially overlaps with the orthogonal projection of the drive transistor on the base substrate, or at least partially overlaps with the orthogonal projection of the storage capacitor on the base substrate; The first electrode plate of the storage capacitor is arranged in the same layer as the second gate of the driving transistor, the first electrode plate and the second electrode plate of the storage capacitor are arranged along a direction perpendicular to the substrate, and the sensing transistor is located between the first electrode plate and the second electrode plate, and the third source of the sensing transistor is connected between the second source of the driving transistor and the second electrode plate.

5. The display panel according to claim 4, characterized in that: The orthogonal projection of the sensing transistor on the base substrate at least partially overlaps the orthogonal projection of the driving transistor on the base substrate, or at least partially overlaps the orthogonal projection of the storage capacitor on the base substrate.

6. The display panel according to claim 4, characterized in that: The storage capacitor and the driving transistor are arranged along a direction parallel to the base substrate; The switch transistor and the drive transistor are arranged along a direction perpendicular to the base substrate.

7. The display panel according to claim 4, characterized in that: The second electrode plate is arranged at the same layer as the electrode layer connected to the light emitting diode.

8. The display panel according to claim 4, characterized in that: The second source or the second drain of the driving transistor is grounded; One end of the storage capacitor is grounded; wherein the first source or the first drain of the switch transistor is electrically connected to the second gate of the drive transistor and the other end of the storage capacitor; as well as A sensing source or a sensing drain of the sensing transistor is grounded.

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