A fan-out packaging method and a packaging structure

Abstract

The present invention provides a fan-out packaging method and a packaging structure. The method includes: respectively providing a wafer carrier and a panel carrier; fixing the first surfaces of multiple groups of first chips on the surface of the wafer carrier in the form of a first array, and forming a first encapsulation layer on the second surfaces of the multiple groups of first chips; separating the multiple groups of first chips from the wafer carrier, and forming a high-density interconnect wiring layer on the first surfaces of the multiple groups of first chips; cutting the multiple groups of first chips, and fixing the side with the high-density interconnect wiring layer on the surface of the panel carrier in the form of a second array; forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer; separating the multiple groups of first chips from the panel carrier, and forming a low-density interconnect wiring layer on the high-density interconnect wiring layer. The packaging method of the present invention can not only well meet the requirements of high-density interconnection, but also has low cost and high yield.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out packaging method and a packaging structure. Background Art

[0002] With the development of semiconductor technology, packaging technology has been developing towards high density / high integration. At present, the fan-out technology has become an important development direction for high-density interconnection. By using the redistribution layer to connect single-chip and multi-chip, the flexibility of packaging integration has been greatly improved. The fan-out technology has been applied to fields such as high-performance computing (HPC) and mobile phone processors.

[0003] At present, there are two main development directions for the fan-out technology. One is the fan-out wafer-level packaging (FOWLP) based on wafer technology, and the other is the fan-out panel-level packaging (FOPLP) based on panel technology. The wiring density of the fan-out wafer-level packaging can be higher. At present, mass production with a line width of 2 microns has been achieved, but the yield is low and the cost is high. Due to the high yield and low cost of the fan-out panel-level packaging, but due to the large panel size and the difficulty in achieving fine line widths, the currently mass-producible line widths are all above 5um.

[0004] In view of the above problems, it is necessary to propose a fan-out packaging method and a packaging structure with reasonable design and effective solution to the above problems. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a fan-out packaging method and a packaging structure.

[0006] In one aspect of the present invention, a fan-out packaging method is provided, and the method includes:

[0007] Providing a wafer carrier and a panel carrier respectively;

[0008] Fixing the first surfaces of multiple groups of first chips on the surface of the wafer carrier in the form of a first array, and forming a first encapsulation layer on the second surfaces of the multiple groups of first chips;

[0009] Separating the multiple groups of first chips from the wafer carrier, and forming a high-density interconnect wiring layer on the first surfaces of the multiple groups of first chips;

[0010] Cutting the multiple groups of first chips, and fixing the side with the high-density interconnect wiring layer on the surface of the panel carrier in the form of a second array;

[0011] Forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer;

[0012] Separate the multiple groups of first chips from the panel carrier, and form a low-density interconnect wiring layer on the high-density interconnect wiring layer.

[0013] In some optional embodiments, forming the high-density interconnect wiring layer on the first surface of the multiple groups of first chips includes:

[0014] Form a first dielectric layer on the first molding layer and the first surface of the multiple groups of first chips, pattern the first dielectric layer to form a plurality of first openings;

[0015] Form a first metal interconnect layer on the surface of the patterned first dielectric layer, pattern the first metal interconnect layer to form the high-density interconnect wiring layer.

[0016] In some optional embodiments, forming the low-density interconnect wiring layer on the surface of the high-density interconnect wiring layer includes:

[0017] Form a second dielectric layer on the surface of the high-density interconnect wiring layer, pattern the second dielectric layer to form a plurality of second openings;

[0018] Form a second metal interconnect layer on the surface of the patterned second dielectric layer, pattern the second metal interconnect layer to form the low-density interconnect wiring layer.

[0019] In some optional embodiments, the dielectric materials of the first dielectric layer and the second dielectric layer are different.

[0020] In some optional embodiments, after forming the low-density interconnect wiring layer, the method further includes:

[0021] Form a third dielectric layer on the surface of the patterned second metal interconnect layer, pattern the third dielectric layer to form a plurality of third openings;

[0022] Perform ball planting at the plurality of third openings to form a plurality of solder balls.

[0023] In some optional embodiments, after forming the plurality of solder balls, the method further includes: grinding the side of the second molding layer facing away from the multiple groups of first chips.

[0024] In some optional embodiments, after forming the second molding layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer, the method further includes: grinding the side of the second molding layer facing away from the multiple groups of first chips.

[0025] In some optional embodiments, after forming the plurality of solder balls, the method further includes: dicing the multiple groups of first chips to form a single-chip package structure.

[0026] In some alternative embodiments, after separating the multiple groups of first chips from the wafer carrier and forming a high-density interconnect wiring layer on a first surface of the multiple groups of first chips, the method further includes:

[0027] Flip-chip bonding a second chip onto the high-density interconnect wiring layer;

[0028] Forming an intermediate interconnect wiring layer on the high-density interconnect wiring layer.

[0029] In some alternative embodiments, after separating the multiple groups of first chips from the panel carrier and forming a low-density interconnect wiring layer on the high-density interconnect wiring layer, the method further includes:

[0030] Patterning the high-density interconnect wiring layer and the low-density interconnect wiring layer to form a target opening area;

[0031] Flip-chip bonding the second chip onto the target opening area.

[0032] In some alternative embodiments, each group of first chips includes one or more first chips.

[0033] In some alternative embodiments, the first surface of the multiple groups of first chips is one of the front and back surfaces of the multiple groups of first chips, and the second surface of the multiple groups of first chips is the other of the front and back surfaces of the multiple groups of first chips.

[0034] Another aspect of the present invention provides a fan-out package structure formed by using the packaging method described above.

[0035] For the fan-out packaging method and package structure of the present invention, after completing the high-density interconnect layer by using the fan-out wafer-level packaging technology in the packaging method, the low-density interconnect layer is completed by using the fan-out panel-level packaging technology. Compared with the current traditional fan-out wafer-level packaging, the fan-out packaging method of the present invention can provide lower cost and higher yield under the condition of the same interconnect density. Compared with the current traditional fan-out panel-level packaging, the fan-out packaging method of the present invention can provide higher interconnect density to meet the requirements of high-performance devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic flowchart of a fan-out packaging method according to an embodiment of the present invention;

[0037] Figure 2 is a schematic diagram of the chip layout area in the wafer carrier according to another embodiment of the present invention;

[0038] Figure 3 is a schematic diagram of the second array B on the panel carrier according to another embodiment of the present invention;

[0039] Figure 4 Schematic diagram of the first array A on the wafer carrier of another embodiment of the present invention;

[0040] Figures 5 to 20 Schematic diagram of the packaging process of a fan - out package structure according to another embodiment of the present invention;

[0041] Figures 21 to 22 Schematic diagram of a partial packaging process of a fan - out package structure according to another embodiment of the present invention;

[0042] Figures 23 to 24 Schematic diagram of a partial packaging process of a fan - out package structure according to another embodiment of the present invention. Detailed implementation manners

[0043] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0044] As Figure 1 shown, one aspect of the present invention provides a packaging method S100 for a fan - out package structure, and the packaging method S100 includes:

[0045] S110, respectively provide a wafer carrier and a panel carrier.

[0046] Specifically, as Figure 2 , Figure 3 and Figure 4 shown, the main material of the wafer carrier 110 is glass, silicon wafer or metal. The main material of the panel carrier 120 is glass, metal or glass fiber resin sheet. The materials of the wafer carrier 110 and the panel carrier 120 are not specifically limited in this embodiment and can be selected according to needs.

[0047] S120, fix the first surfaces of multiple groups of first chips in the form of a first array on the surface of the wafer carrier, and form a first encapsulation layer on the second surfaces of the multiple groups of first chips.

[0048] Specifically, as Figure 5 shown, fix the first surfaces of multiple groups of first chips 130 on the surface of the wafer carrier 110 through a first adhesive 111. Using wafer - level packaging technology, the high - density interconnection requirements can be well achieved. As Figure 3 shown, after pasting, the multiple groups of first chips 130 form a first array A, and the first array A is a square array. As Figure 6 shown, use encapsulant to encapsulate on the second surfaces of the multiple groups of first chips 130 to form a first encapsulation layer 140. The encapsulation method can be film - layer vacuum lamination or traditional encapsulation process, which is not specifically limited in this embodiment.

[0049] It should be noted that the first surface of the multiple groups of first chips 130 can be the front side or the back side of the multiple groups of first chips 130. Correspondingly, the second surface of the multiple groups of first chips 130 is the other side of the front side and the back side of the multiple groups of first chips 130. In this embodiment, the front sides of the multiple groups of first chips 130 are fixed to the surface of the wafer carrier 110 through the adhesive 111.

[0050] It should be further noted that each group of first chips 130 includes one or more first chips 130.

[0051] S130. Separate the multiple groups of first chips from the wafer carrier, and form a high-density interconnect wiring layer on the first surface of the multiple groups of first chips.

[0052] Specifically, as Figure 6 and Figure 7 shown, separate the multiple groups of first chips 130 from the wafer carrier 110. The separation method can adopt thermal separation, laser separation, ultraviolet light separation, mechanical separation and other methods. These methods are all currently commonly used temporary bonding separation methods. The separation method is not specifically limited in this embodiment and can be selected according to actual needs.

[0053] Forming a high-density interconnect wiring layer on the first surface of the multiple groups of first chips 130 includes:

[0054] First, form a first dielectric layer on the first encapsulation layer and the first surface of the multiple groups of first chips, and pattern the first dielectric layer to form a plurality of first openings;

[0055] Specifically, as Figure 8 shown, coat the first dielectric layer 150 on the first encapsulation layer 140 and the first surface of the multiple groups of first chips 130. The material of the first dielectric layer 150 is polyimide (PI), polybenzoxazole (PBO), etc. The coating method is usually wafer spin coating, which is not specifically limited in this embodiment. The first dielectric layer 150 plays a protective role for the multiple groups of first chips 130. As Figure 8 shown, pattern the first dielectric layer 150 through a photolithography process to form a plurality of first openings 151.

[0056] Second, form a first metal interconnect layer on the surface of the patterned first dielectric layer, and pattern the first metal interconnect layer to form the high-density interconnect wiring layer.

[0057] Specifically, as Figure 9As shown, a first metal interconnect layer 160 is deposited on the surface of the patterned first dielectric layer 150. The deposition methods include sputtering and electroplating, etc. The metal materials are usually titanium and copper. In this embodiment, the deposition methods and metal materials are not specifically limited. The first metal interconnect layer 160 is patterned through photolithography and etching processes to form a high-density interconnect wiring layer. The etching process can be wet etching or dry etching. In this embodiment, it is not specifically limited.

[0058] Adopting the fan-out wafer-level packaging to form the above high-density interconnect wiring layer can provide a higher interconnect density and meet the requirements of high-performance devices.

[0059] S140: Cut the multiple groups of first chips, and fix the side with the formed high-density interconnect wiring layer on the surface of the panel carrier in the form of a second array.

[0060] Specifically, as Figure 10 and Figure 11 shown, cut the multiple groups of first chips 130 according to the area size of the panel carrier 120 and fix them on the surface of the panel carrier 120 in the form of the second array B shown. Using the panel-level packaging technology can improve the yield and reduce the manufacturing cost. In this embodiment, as Figure 4 shown, fix the side with the formed high-density interconnect wiring layer on the panel carrier 120 through the second adhesive 121. That is to say, the first metal interconnect layer 160 is adhered to the second adhesive 121. Figure 11

[0061] S150: Form a second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer.

[0062] Specifically, as Figure 12 shown, form a second encapsulation layer 170 on the side of the multiple groups of first chips 130 fixed on the panel carrier 120 in the form of the second array B facing away from the high-density interconnect wiring layer. The encapsulation method can be film layer vacuum lamination or traditional encapsulation process. In this embodiment, it is not specifically limited.

[0063] S160: Separate the multiple groups of first chips from the panel carrier, and form a low-density interconnect wiring layer on the high-density interconnect wiring layer.

[0064] Specifically, as Figure 12 and Figure 13 shown, separate the multiple groups of first chips 130 from the panel carrier 120. The separation methods can include thermal separation, laser separation, ultraviolet light separation, mechanical separation, etc. These methods are all currently commonly used temporary bonding separation methods. In this embodiment, the separation methods are not specifically limited and can be selected according to actual needs.

[0065] ​Forming a low - density interconnect wiring layer on the high - density interconnect wiring layer, including:

[0066] First, form a second dielectric layer on the surface of the high - density interconnect wiring layer, pattern the second dielectric layer to form a plurality of second openings;

[0067] Specifically, as Figure 14 shown, on the surface of the high - density interconnect wiring layer, that is, on the surface of the first metal interconnect layer 160, a second dielectric layer 180 is covered. The second dielectric layer 180 plays a protective role for the first metal interconnect layer 160. The material of the second dielectric layer 180 is a photosensitive dielectric layer (PID) or an Ajinomoto build - up film (ABF), etc., which is not specifically limited in this embodiment. The process of covering the second dielectric layer 180 on the surface of the first metal interconnect layer 160 can be a vacuum laminating process or a printing process, which is not specifically limited in this embodiment. Pattern the second dielectric layer 180 through a photolithography process to form a plurality of second openings 181.

[0068] Second, form a second metal interconnect layer on the surface of the patterned second dielectric layer, pattern the second metal interconnect layer to form the low - density interconnect wiring layer.

[0069] Specifically, as Figure 15 shown, deposit a second metal interconnect layer 190 on the surface of the patterned second dielectric layer 180. The deposition method is electroless plating and electroplating, etc., which is not specifically limited in this embodiment. The metal material of the second metal interconnect layer 190 is usually copper, etc. Pattern the second metal interconnect layer 190 through a photolithography and etching process to form a low - density interconnect wiring layer. The etching process can be wet etching or dry etching, which is not specifically limited in this embodiment.

[0070] Exemplarily, as Figure 9 shown, the dielectric materials of the first dielectric layer 150 and the second dielectric layer 180 are different. The material of the first dielectric layer 150 is polyimide (PI), polybenzoxazole (PBO), etc., and the material of the second dielectric layer 180 is a photosensitive dielectric layer (PID) or an Ajinomoto build - up film (ABF), etc. This is because the first dielectric layer 150 is made by a wafer - level process, and the second dielectric layer 180 is made by a panel - level process. Select a preferred dielectric layer according to different processes, and if the materials of the two dielectric layers are close, there will be no problems such as contact difference or process unfeasibility.

[0071] Exemplarily, as Figure 16 shown, after forming the low - density interconnect wiring layer, the method further includes:

[0072] Form a third dielectric layer on the surface of the patterned second metal interconnect layer, pattern the third dielectric layer to form a plurality of third openings;

[0073] Specifically, as Figure 16 shown, a third dielectric layer 200 is covered on the surface of the second metal interconnect layer 190 after being patterned. The material of the third dielectric layer 200 can use photosensitive solder resist (PSR), etc., and this embodiment does not make specific limitations. The process of covering the third dielectric layer 200 on the second metal interconnect layer 190 can be vacuum laminating or printing process, and this embodiment does not make specific limitations. The third dielectric layer 200 is patterned by photolithography process to form a plurality of third openings 201.

[0074] Ball planting is performed at the plurality of third openings to form a plurality of solder balls.

[0075] Specifically, as Figure 16 and Figure 17 shown, ball planting is performed at the plurality of third openings 201 to form a plurality of solder balls 210.

[0076] Exemplarily, as Figure 18 shown, after forming a plurality of solder balls 210, the plurality of groups of first chips 130 are diced to form a single group of chip package structures.

[0077] Exemplarily, as Figure 19 shown, after forming a plurality of solder balls 210, the side of the second encapsulation layer 170 facing away from the plurality of groups of first chips 130 is polished to reduce the encapsulation thickness, and finally the package structure as Figure 20 shown is formed.

[0078] Exemplarily, after forming the second encapsulation layer 170 on the side of the plurality of groups of first chips 130 facing away from the high-density interconnect wiring layer, the side of the second encapsulation layer 170 facing away from the plurality of groups of first chips 130 is polished to reduce the encapsulation thickness, and finally the package structure as shown in the figure is formed.

[0079] Exemplarily, in another embodiment, after separating the plurality of groups of first chips 130 from the wafer carrier 110 and forming a high-density interconnect wiring layer on the first surface of the plurality of groups of first chips 130, it further includes:

[0080] Flip-chip bonding a second chip on the high-density interconnect wiring layer;

[0081] Specifically, as Figure 22 shown, flip-chip bonding the second chip 220 on the high-density interconnect wiring layer, that is, on the first metal interconnect layer 160. In this embodiment, the second chip 200 is a silicon bridge chip. After flip-chip bonding the silicon bridge chip on the first metal interconnect layer 160, underfill is performed, that is, the gap between the silicon bridge chip and the first metal interconnect layer 160 is filled.

[0082] Form an intermediate interconnect wiring layer on the high-density interconnect wiring layer.

[0083] Specifically, as Figure 22 shown, on the high-density interconnect wiring layer, that is, on the first metal interconnect layer 160, re-wiring is performed. Specifically, a dielectric layer and a metal interconnect layer are sequentially formed on the first metal interconnect layer 160, and then the metal interconnect layer is patterned to form an intermediate interconnect wiring layer. After forming the intermediate interconnect layer, the encapsulation steps of S140 and subsequent steps are continued. Among them, the height of the intermediate interconnect wiring layer can be lower than the height of the second chip 220, or can be the same as the height of the second chip 220. Of course, most preferably, the height of the intermediate interconnect wiring layer is the same as the height of the second chip 220, so that no processing is required when performing the encapsulation steps of S140 and subsequent steps. If the height of the intermediate interconnect wiring layer can be lower than the height of the second chip 220, a protective layer needs to be covered on the surface of the intermediate interconnect wiring layer before performing the encapsulation steps of S140 and subsequent steps.

[0084] Exemplarily, in another embodiment, after separating the multiple groups of first chips from the panel carrier and forming a low-density interconnect wiring layer on the high-density interconnect wiring layer, the method further includes:

[0085] Patterning the high-density interconnect wiring layer and the low-density interconnect wiring layer to form a target opening area;

[0086] Specifically, as Figure 23 shown, the high-density interconnect wiring layer and the low-density interconnect wiring layer are patterned by a photolithography process, that is, the first dielectric layer 150, the first metal interconnect layer 160, the second dielectric layer 180, and the second metal interconnect layer 190 are sequentially patterned to form a target opening area 230.

[0087] Flip-chip the second chip onto the target opening area.

[0088] Specifically, as Figure 24 shown, flip-chip the second chip 220 onto the target opening area 230. In this embodiment, the second chip 220 is a silicon bridge chip. After flip-chipping the silicon bridge chip onto the target opening area 230, underfill is performed, that is, the gap between the silicon bridge chip and the target opening area 230 is filled. After flip-chipping the second chip 220 onto the target opening area 230, ball planting can be directly performed, or a dielectric layer can be covered and then ball planting can be performed. After ball planting, cutting is performed to form a single-group chip package structure.

[0089] It should be noted that in the given embodiments, the dielectric layer structure is a 3-layer or 4-layer structure. In fact, the present invention can be applied to various numbers of layers and can be adjusted according to actual design requirements. The number of interconnect layers used in wafer-level and panel-level processes can also be adjusted according to actual design needs. For example, when high-density interconnects are also required for the second interconnect layer (which cannot be achieved in panel-level processes), two interconnect layers can be fabricated using wafer-level processes and then transferred to panel-level processes for subsequent processing.

[0090] It should be further noted that in the present invention, as Figure 2 shown, the middle area of the wafer carrier 110 is the chip layout area 112, and the chip layout area 112 is distributed in the first array A as Figure 3 shown. The chip layout area 112 has a square structure, and the length of its diagonal is equivalent to the diameter of the wafer carrier 110. Through temporary bonding and wafer-level redistribution, a high-density interconnect wiring layer is formed in the middle area. The chip layout area 112 with completed high-density interconnects is diced and then integrally built onto the panel carrier 120 in the form of the second array B as Figure 4 shown.

[0091] As Figure 4 shown, the current common size of the panel carrier 120 is 510×515 mm. In this case, 4 chip layout areas 112 can be placed simultaneously, and subsequent processes can be completed using panel-level packaging interconnect technology. The production efficiency can reach 4 times that of wafer-level packaging technology. In the future, if LCD panel technology is used, the production efficiency can be increased to 6 - 8 times, and the cost will be greatly reduced.

[0092] As Figure 2 shown, since the area of the chip layout area 112 is smaller than the area of the wafer carrier 110, there will be a certain area loss. Considering that the chips are all rectangular or square in size, the main loss area is the blank area 113 in the figure, and the short side dimension of the blank area 113 is 28 mm. For samples with a package size close to or larger than 28 mm, this area is an invalid area. However, for samples with a package size close to or smaller than 28 mm, the blank area 113 can still be used. Therefore, the design of the chip layout area 112 will not increase the cost of wafer-level packaging. Since high-density interconnects are mainly applied in fields such as high-performance computing, and the packaging in this field is moving towards larger sizes, the present invention has a significant effect of reducing costs.

[0093] In the package design, generally, the interconnect layer density is high near the chip and low far from the chip, and the connection line width shows a trend of gradually increasing. Taking advantage of this feature, in the packaging method of the fan-out package structure provided by the present invention, the fan-out wafer-level packaging technology and the fan-out panel-level packaging technology are integrated to complete the fan-out package manufacturing. For the interconnect layer close to the chip, the wafer-level packaging technology can be used to well meet the high-density interconnect requirements, while for the interconnect layer far from the chip, the panel-level packaging technology can be used to improve the yield and reduce the manufacturing cost.

[0094] Another aspect of the present invention provides a fan-out package structure, which is formed by packaging using the packaging method described above. The specific steps of the packaging method can refer to the relevant records above and will not be elaborated here. The package structure formed by packaging using the packaging method described above not only has low cost and high yield, but also can well meet the high-density interconnect requirements.

[0095] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A fan-out packaging method, characterized in that, The method includes: providing a wafer carrier and a panel carrier respectively; fixing the first surfaces of multiple groups of first chips on the surface of the wafer carrier in the form of a first array, and forming a first encapsulation layer on the second surfaces of the multiple groups of first chips; separating the multiple groups of first chips from the wafer carrier, and forming a high-density interconnect wiring layer on the first surfaces of the multiple groups of first chips; dicing the multiple groups of first chips, and fixing the side with the high-density interconnect wiring layer formed thereon on the surface of the panel carrier in the form of a second array; forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer; separating the multiple groups of first chips from the panel carrier, and forming a low-density interconnect wiring layer on the high-density interconnect wiring layer.

2. The method according to claim 1, characterized in that, The forming of the high-density interconnect wiring layer on the first surfaces of the multiple groups of first chips includes: forming a first dielectric layer on the first encapsulation layer and the first surfaces of the multiple groups of first chips, patterning the first dielectric layer to form multiple first openings; forming a first metal interconnect layer on the surface of the patterned first dielectric layer, and patterning the first metal interconnect layer to form the high-density interconnect wiring layer.

3. The method according to claim 2, wherein The forming of the low-density interconnect wiring layer on the surface of the high-density interconnect wiring layer includes: forming a second dielectric layer on the surface of the high-density interconnect wiring layer, patterning the second dielectric layer to form multiple second openings; forming a second metal interconnect layer on the surface of the patterned second dielectric layer, and patterning the second metal interconnect layer to form the low-density interconnect wiring layer.

4. The method according to claim 3, characterized in that, The dielectric materials of the first dielectric layer and the second dielectric layer are different.

5. The method according to claim 3, characterized in that, After forming the low-density interconnect wiring layer, the method further includes: forming a third dielectric layer on the surface of the patterned second metal interconnect layer, patterning the third dielectric layer to form multiple third openings; performing ball implantation at the multiple third openings to form multiple solder balls.

6. The method according to any one of claims 1 to 5, characterized in that, After forming the multiple solder balls, the method further includes: grinding the side of the second encapsulation layer facing away from the multiple groups of first chips.

7. The method according to any one of claims 1 to 5, characterized in that After forming the second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer, the method further includes: grinding the side of the second encapsulation layer facing away from the multiple groups of first chips.

8. The method according to any one of claims 1 to 5, characterized in that After forming the multiple solder balls, the method further includes: dicing the multiple groups of first chips to form a single-chip package structure.

9. The method according to claim 1, wherein After separating the multiple groups of first chips from the wafer carrier and forming the high-density interconnect wiring layer on the first surfaces of the multiple groups of first chips, the method further includes: flip-chip mounting a second chip on the high-density interconnect wiring layer; forming an intermediate interconnect wiring layer on the high-density interconnect wiring layer.

10. The method according to claim 9, wherein After separating the multiple groups of first chips from the panel carrier and forming the low-density interconnect wiring layer on the high-density interconnect wiring layer, the method further includes: patterning the high-density interconnect wiring layer and the low-density interconnect wiring layer to form a target opening area; flip-chip mounting the second chip on the target opening area.

11. The method according to any one of claims 1 to 5, characterized in that, Each group of first chips includes one or more first chips.

12. The method according to any one of claims 1 to 5, characterized in that The first surface of the multiple groups of first chips is one of the front and back surfaces of the multiple groups of first chips, and the second surface of the multiple groups of first chips is the other of the front and back surfaces of the multiple groups of first chips.

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