Semiconductor memory device and manufacturing method thereof

Abstract

An embodiment provides a semiconductor memory device capable of improving reliability and a method for manufacturing the same. According to the embodiment, the semiconductor memory device includes: a plurality of first wiring layers (WL) stacked along a first direction (Z direction); a first memory pillar (MP) including a first semiconductor layer (29) extending along the first direction within the plurality of first wiring layers; a second wiring layer (39) arranged above the first semiconductor layer; a second semiconductor layer (33) including a first portion (33a) arranged between the first semiconductor layer and the second wiring layer, a second portion (33b) extending above the first semiconductor layer, and a third portion (33c) arranged on the second portion; a first insulating layer (37) arranged between the first portion and the second wiring layer and between the second portion and the second wiring layer; and a second insulating layer (40) arranged on the first insulating layer and in contact with a portion of the second portion.

Description

[0001] [Related Applications]

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-156452 (filing date: September 17, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the same. Background Art

[0004] As a semiconductor storage device, a NAND (Not AND) type flash memory is known. Summary of the Invention

[0005] Embodiments provide a semiconductor memory device capable of improving reliability and a method of manufacturing the same.

[0006] A semiconductor storage device in an embodiment includes: a plurality of first wiring layers stacked along a first direction; a first memory column including a first semiconductor layer extending along the first direction inside the plurality of first wiring layers; a second wiring layer arranged above the first semiconductor layer; a second semiconductor layer including a first portion arranged between the first semiconductor layer and the second wiring layer, a second portion extending above the first semiconductor layer, and a third portion arranged on the second portion; a first insulating layer arranged between the first portion and the second wiring layer and between the second portion and the second wiring layer; and a second insulating layer arranged on the first insulating layer and in contact with a portion of the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing a configuration example of a semiconductor memory device according to one embodiment.

[0008] Figure 2 This is a circuit diagram of a memory cell array included in a semiconductor memory device according to one embodiment.

[0009] Figure 3 This is a top view of a memory cell array included in a semiconductor memory device according to one embodiment.

[0010] Figure 4 This is a cross-sectional view of a memory cell array included in a semiconductor memory device according to one embodiment.

[0011] Figure 5 It is a perspective view of a selection transistor ST1 in a memory cell array included in a semiconductor memory device according to an embodiment.

[0012] Figures 6 to 191 is a cross-sectional view of a memory array showing an example of a manufacturing step of a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION

[0013] The following describes the embodiments with reference to the accompanying drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and repeated descriptions are provided only when necessary. The embodiments described below illustrate the apparatus and method used to embody the technical concept of the present embodiment. The technical concept of the embodiments does not specify the material, shape, structure, or configuration of the components as described below. Various modifications may be made to the technical concept of the embodiments within the scope of the claims.

[0014] A semiconductor memory device according to an embodiment will be described below. Hereinafter, a three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked on a semiconductor substrate will be described as an example of a semiconductor memory device.

[0015] 1. Composition

[0016] 1.1 Overall Structure of a Semiconductor Memory Device

[0017] First, use Figure 1 The overall structure of the semiconductor memory device will be described. Figure 1 This is an example of a block diagram showing the basic overall structure of a semiconductor memory device.

[0018] like Figure 1 As shown, semiconductor memory device 1 is controlled by external memory controller 2. Semiconductor memory device 1 includes memory cell array 10, instruction register 11, address register 12, sequencer 13, driver module 14, row decoder module 15, and sense amplifier module 16.

[0019] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than or equal to 1). A block BLK is a collection of a plurality of memory cells capable of storing data in a nonvolatile manner, and is used as a unit of erasing data, for example.

[0020] In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed structure of the memory cell array 10 will be described below.

[0021] The command register 11 stores the command CMD received by the semiconductor storage device 1 from the memory controller 2. The command CMD includes, for example, an instruction for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like.

[0022] The address register 12 stores address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select a block BLK, a word line, and a bit line, respectively.

[0023] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, based on the command CMD stored in the command register 11, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 to execute read, write, and erase operations.

[0024] The driver module 14 generates voltages used in read operations, write operations, and erase operations, etc. The driver module 14 applies the generated voltages to signal lines corresponding to selected word lines based on, for example, the page address PA stored in the address register 12 .

[0025] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA stored in the address register 12. The row decoder module 15 then transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0026] During a write operation, the sense amplifier module 16 applies a voltage to each bit line based on write data DAT received from the memory controller 2. Furthermore, during a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transmits the determination result to the memory controller 2 as read data DAT.

[0027] The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard. For example, the communication between the semiconductor memory device 1 and the memory controller 2 uses a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, and input / output signals I / O.

[0028] The input / output signal I / O is, for example, an 8-bit signal and may include a command CMD, address information ADD, data DAT, and the like.

[0029] The command latch enable signal CLE is a signal indicating that the input / output signal I / O received by the semiconductor memory device 1 is a command CMD.

[0030] The address latch enable signal ALE is a signal indicating that the signal I / O received by the semiconductor memory device 1 is the address information ADD.

[0031] The write enable signal WEn is a signal that instructs the semiconductor memory device 1 to input an input signal I / O.

[0032] The read enable signal REn is a signal that instructs the semiconductor memory device 1 to output the input / output signal I / O.

[0033] The ready / busy signal RBn is a signal that notifies the memory controller 2 whether the semiconductor storage device 1 is in a ready state to accept a command from the memory controller 2 or a busy state to not accept a command.

[0034] The semiconductor memory device 1 and the memory controller 2 described above can also be combined to form a semiconductor device. As such a semiconductor device, for example, SD (Secure Digital) TM Memory cards such as cards or SSDs (Solid State Drives).

[0035] 1.2 Circuit Structure of Memory Cell Array

[0036] Next, use Figure 2 An example of the circuit configuration of the memory cell array 10 will be described. Figure 2 In the example of FIG. 1 , one block BLK among the plurality of blocks BLK included in the memory cell array 10 is extracted and represented.

[0037] like Figure 2 As shown, the block BLK includes, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of NAND strings NS.

[0038] A plurality of NAND strings NS are associated with bit lines BL0 to BLm (m is an integer greater than or equal to 1), respectively. Each NAND string NS includes, for example, memory cell transistors MC0 to MC7 and selection transistors ST1 and ST2.

[0039] The memory cell transistor MC includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0040] Furthermore, the memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type transistor in which the charge storage layer uses an insulating layer, or an FG (Floating Gate) type transistor in which the charge storage layer uses a conductive layer. In this embodiment, the MONOS type transistor is used as an example.

[0041] In each NAND string NS, the drain of select transistor ST1 is connected to the associated bit line BL, and the source of select transistor ST1 is connected to one end of the series-connected memory cell transistors MC0-MC7. In the same block BLK, the gates of select transistors ST1 in string units SU0-SU3 are commonly connected to select gate lines SGD0-SGD3, respectively. Select gate lines SGD0-SGD3 are connected to the row decoder module 15.

[0042] In each NAND string NS, the drain of select transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0-MC7. Within the same block BLK, the sources of select transistors ST2 are commonly connected to source line SL, and the gates of select transistors ST2 are commonly connected to select gate line SGS. Select gate line SGS is connected to row decoder module 15.

[0043] The bit line BL connects one NAND string NS included in each of the string units SU0 to SU3 in each block BLK in common. The source line SL is connected in common among the plurality of blocks BLK, for example.

[0044] A collection of multiple memory cell transistors MC connected to a common word line WL within a string unit SU is called, for example, a unit unit CU. For example, the storage capacity of a unit unit CU, which includes memory cell transistors MC each storing one bit of data, is defined as "one page of data." Depending on the number of bits of data stored by the memory cell transistors MC, a unit unit CU can have a storage capacity of two or more pages of data.

[0045] Furthermore, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment is not limited to the configuration described above. For example, the number of memory cell transistors MC and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number. The number of string units SU included in each block BLK can also be designed to be any number.

[0046] 1.3 Planar structure of memory cell array

[0047] Next, use Figure 3 An example of a planar structure of the memory cell array 10 will be described. Figure 3 This is a plan view showing a partial region of the memory cell array 10 , with a portion of the insulating layer omitted for simplicity of description.

[0048] In the following description, the X direction is approximately parallel to the semiconductor substrate and corresponds to the direction in which the word line WL extends. The Y direction is approximately parallel to the semiconductor substrate and perpendicular to the X direction, corresponding to the direction in which the bit line BL extends. The Z direction corresponds to a direction approximately perpendicular to the semiconductor substrate and intersecting the X and Y directions. Furthermore, for example, the direction connecting the center of the memory column MP2 and the center of the memory column MP4 described below in the XY plane approximately parallel to the semiconductor substrate is referred to as the A direction. Furthermore, the direction approximately parallel to the semiconductor substrate and perpendicular to the A direction is referred to as the B direction. That is, the A direction corresponds to a direction approximately parallel to the semiconductor substrate and different from the X and Y directions. The B direction corresponds to a direction approximately parallel to the semiconductor substrate and perpendicular to the A direction.

[0049] like Figure 3 As shown, slits SLT extending in the X direction are provided on the Y-direction side of word lines WL extending in the X direction. In this embodiment, select gate lines SGS and word lines WL0 to WL7 are sequentially stacked above a semiconductor substrate. Furthermore, slits SLT are provided, for example, to separate select gate lines SGS and word lines WL for each block BLK.

[0050] For example, the string units SU0 to SU3 are arranged along the Y direction, and a plurality of memory pillars MP are provided in each string unit SU.

[0051] Memory pillars MP correspond to NAND strings NS. More specifically, memory pillars MP correspond to memory cell transistors MC0-MC7 and select transistor ST2 in NAND string NS. Memory pillars MP extend along the Z direction, passing through select gate lines SGS and word lines WL0-WL7. The structure of memory pillars MP is described in detail below.

[0052] For example, the plurality of memory columns MP in each string assembly SU are arranged in two rows offset in the X direction. More specifically, for example, in string assembly SU0, memory column MP1 and memory column MP3 are arranged adjacent to each other in the X direction. Furthermore, memory column MP2 is arranged between memory column MP1 and memory column MP3 in the X direction and at a different position from memory columns MP1 and MP3 in the Y direction. In other words, memory column MP2 is arranged adjacent to memory column MP1 in the A direction and adjacent to memory column MP2 in the B direction.

[0053] Furthermore, the arrangement of the memory pillars MP can be arbitrarily set. For example, the memory pillars MP may be arranged in four rows with staggered positions. Alternatively, the memory pillars MP may not be arranged in a staggered position.

[0054] A selection transistor ST1 is provided on each memory column MP. Furthermore, within the string component SU, the gates of the plurality of selection transistors ST1 respectively provided on the plurality of memory columns MP are commonly connected to the selection gate line SGD. More specifically, for example, in the string component SU0, the selection transistor ST1 provided on each memory column MP1 to MP3 is connected to the selection gate line SGD0. The selection gate line SGD0 is provided in the Y direction between the selection transistor ST1 provided on the memory column MP1 (and MP3) and the selection transistor ST1 provided on the memory column MP2, and extends along the X direction. For example, the center position of the selection gate line SGD0 in the Y direction is located between the center position of the memory column MP1 (and MP3) and the center position of the memory column MP2.

[0055] A stopper layer STP extending in the X direction is provided on the upper portion of the side surface of each select gate line SGD facing the Y direction. The stopper layer STP functions as an etching stopper when processing a contact plug CP1 described below.

[0056] In this embodiment, in two adjacent string units SU, the select transistors ST1 of two memory pillars MP adjacent in the A direction or the B direction are commonly connected to a single bit line BL via contact plugs CP1 and CP2. In other words, the two select transistors ST1 disposed between two select gate lines SGD and adjacent in the A direction or the B direction are commonly connected to a single contact plug CP1.

[0057] More specifically, for example, the semiconductor layer 33 of the memory pillar MP2 of the string unit SU0 and the semiconductor layer 33 of the memory pillar MP4 of the string unit SU1 adjacent in the A direction are connected to one contact plug CP1 .

[0058] Contact plug CP2 is provided above contact plug CP1. Contact plug CP2 connects any one of the multiple bit lines BL extending along the Y direction to contact plug CP1. In other words, the multiple memory pillars MP in a string unit SU are connected to different bit lines BL via select transistor ST1 and contact plugs CP1 and CP2. More specifically, for example, memory pillars MP1-MP3 are connected to different bit lines BL. All memory pillars MP in each string unit SU are connected to a common bit line BL.

[0059] 1.4 Cross-sectional structure of memory cell array

[0060] Next, use Figure 4 An example of a cross-sectional structure of the memory cell array 10 will be described. Figure 4 It is along Figure 3 A cross-sectional view of the A1-A2 line.

[0061] like Figure 4 As shown, an insulating layer 21 is provided on a semiconductor substrate 20. For example, silicon oxide (SiO2) can be used for the insulating layer 21. Furthermore, circuits such as a row decoder module 15 and a sense amplifier module 16 may be provided in the region where the insulating layer 21 is provided, that is, between the semiconductor substrate 20 and the wiring layer 22.

[0062] A wiring layer 22 extending in the X direction and functioning as a source line SL is provided on the insulating layer 21. The wiring layer 22 is made of a conductive material, such as an n-type semiconductor, a p-type semiconductor, or a metal material.

[0063] An insulating layer 23 is provided on the wiring layer 22. The insulating layer 23 can be made of SiO2, for example.

[0064] On the insulating layer 23, nine wiring layers 24 and nine insulating layers 25 are alternately stacked from the bottom, functioning as the select gate line SGS and word lines WL0 to WL7. The wiring layer 24 is made of a conductive material, such as an n-type semiconductor, a p-type semiconductor, or a metal material. The following describes the case of using a stacked structure of titanium nitride (TiN) and tungsten (W) as the wiring layer 24. TiN functions as a barrier layer to prevent the reaction between W and SiO2 when forming W by CVD (chemical vapor deposition), or as an adhesion layer to improve the adhesion of W. Furthermore, SiO2 can be used, for example, for the insulating layer 25.

[0065] A memory pillar MP is provided which penetrates nine wiring layers 24 and has its bottom surface reaching the wiring layer 22. The memory pillar MP includes a blocking insulating film 26, a charge storage layer 27, a tunnel insulating film 28, a semiconductor layer 29, a core layer 30, and a cap layer 31.

[0066] More specifically, a hole corresponding to the memory pillar MP is provided so as to penetrate the multiple wiring layers 24 and the multiple insulating layers 25 and reach the wiring layer 22 from the bottom. A blocking insulating film 26, a charge storage layer 27, and a tunnel insulating film 28 are sequentially layered on the sides of the hole. Furthermore, a semiconductor layer 29 is provided so as to be in contact with the tunnel insulating film 28 on the sides and in contact with the wiring layer 22 on the bottom. The semiconductor layer 29 is a region for forming the channel for the select transistor ST2 and the memory cell transistor MC. Therefore, the semiconductor layer 29 functions as a signal line for the current path connecting the select transistor ST2 and the memory cell transistors MC0-MC7. A core layer 30 is provided within the semiconductor layer 29. Furthermore, a capping layer 31 is provided on the semiconductor layer 29 and the core layer 30, with the sides in contact with the tunnel insulating film 28. In other words, the memory pillar MP includes the semiconductor layer 29 that extends in the Z direction through the interior of the multiple wiring layers 24. Alternatively, the capping layer 31 may be omitted.

[0067] For example, SiO 2 may be used for the blocking insulating film 26 , the tunnel insulating film 28 , and the core layer 30 . For example, silicon nitride (SiN) may be used for the charge storage layer 27 . For example, polysilicon may be used for the semiconductor layer 29 and the cap layer 31 .

[0068] Memory cell transistors MC0 to MC7 are formed by memory pillars MP and eight interconnect layers 24 functioning as word lines WL0 to WL7, respectively. Similarly, select transistor ST2 is formed by memory pillars MP and interconnect layers 24 functioning as select gate lines SGS.

[0069] Above the memory pillars MP, an insulating layer 32 extending in the X and Y directions is provided between the insulating layer 25. The insulating layer 32 functions as an etch stop layer when processing the trenches (i.e., the trench pattern) corresponding to the wiring layer 39. Alternatively, the insulating layer 32 may be omitted. The insulating layer 32 may be made of an insulating material that achieves an etching selectivity ratio with the insulating layer 25. The following describes the use of SiN as the insulating layer 32.

[0070] A trench is provided, which penetrates the insulating layers 25 and 32 , reaches the memory pillar MP at its bottom, and extends along the X direction.

[0071] A wiring layer 39 extending in the X direction is provided within the trench. Wiring layer 39 functions as select gate line SGD. The upper surface of wiring layer 39 in the Z direction is positioned lower than the upper surfaces of semiconductor layer 33 and insulating layer 40, described below. For example, wiring layer 39 can be made of a conductive material, such as an n-type semiconductor, a p-type semiconductor, or a metal. The following describes a case where a TiN / W laminated structure is used as wiring layer 39.

[0072] A semiconductor layer 33 and insulating layers 34 to 36 are provided on the side and bottom surfaces of the trench above the memory pillar MP, between the memory pillar MP and the wiring layer 39. The semiconductor layer 33 is a region for forming the channel of the selection transistor ST1. The insulating layers 34 to 36 function as gate insulating films for the selection transistor ST1. The upper surfaces of the insulating layers 34 to 36 are positioned lower than the upper surface of the semiconductor layer 33. In addition, in this embodiment, a case where three insulating layers 34 to 36 are used as the gate insulating film is described, but the gate insulating film only needs to have one or more layers. For example, a MONOS structure (more specifically, a stacked structure of an insulating layer, a charge storage layer, and an insulating layer) that can control the threshold voltage may be used as the gate insulating film. In this embodiment, for example, SiO2 can be used for the insulating layers 34 and 36, and SiN can be used for the insulating layer 35. Hereinafter, the stacked structure of the insulating layers 34 to 36 is also simply described as a stacked body 37.

[0073] The semiconductor layer 33 has a shape that bends approximately in the Z and Y directions along the wiring layer 39 (hereinafter referred to as a crankshaft shape). More specifically, the semiconductor layer 33 includes two semiconductor layers 33a, two semiconductor layers 33b, and a semiconductor layer 33c. The two semiconductor layers 33a are provided on the cover layers 31 of the memory pillars MP adjacent in the A direction (or the B direction). The bottom surfaces of the two semiconductor layers 33b are in contact with the corresponding semiconductor layers 33a. Furthermore, the two semiconductor layers 33b are arranged along the side surfaces of the wiring layer 39 facing the Y direction. The semiconductor layer 33c is arranged so as to be in contact with the top surfaces of the two semiconductor layers 33b provided on the memory pillars MP adjacent in the A direction (or the B direction). With this structure, two select transistors ST1 adjacent in the A direction (or the B direction) are connected via a single semiconductor layer 33. The bottom surface of the semiconductor layer 33c in the Z direction is located at a higher level than the top surface of the wiring layer 39. Semiconductor layer 33 has a curved shape, with semiconductor layer 33a extending in the Y direction, semiconductor layer 33b extending approximately in the Z direction, and semiconductor layer 33c extending in the Y direction sequentially connected. Semiconductor layer 33 can be made of, for example, polycrystalline silicon or amorphous silicon. Alternatively, semiconductor layer 33c can be made of an n-type semiconductor or p-type semiconductor into which impurities have been introduced, so that conductor 41 is connected to the channel region of select transistor ST1 with low resistance.

[0074] An insulating layer 38 is provided on the side surfaces and bottom surface of the trench excluding the region where the semiconductor layer 33 and the laminate 37 are provided. For example, SiO 2 can be used for the insulating layer 38 .

[0075] An insulating layer 40 is provided so as to contact the side surfaces of the upper portion of the semiconductor layer 33 and cover the upper surface of the laminate 37 and the upper surface of the end portion of the wiring layer 39 in the Y direction. A portion of the bottom surface of the insulating layer 40 may contact the upper surface (at the end portion) of the wiring layer 39. In other words, the bottom surface of the insulating layer 40 may be positioned at the same height as the upper surface of the wiring layer 39. The insulating layer 40 functions as a stop layer STP. More specifically, the insulating layer 40 functions as a surface protective layer for the laminate 37 during the processing of the contact plug CP1. Furthermore, by disposing the insulating layer 40 between the contact plug CP1 and the wiring layer 39, the insulating layer 40 prevents short circuits or insulation breakdown between the contact plug CP1 and the wiring layer 39. Therefore, the width of the insulating layer 40 in the Y direction can be set sufficiently wide so that even if the contact plug CP1 is misaligned, short circuits or insulation breakdown between the contact plug CP1 and the wiring layer 39 will not occur. SiN, for example, can be used for the insulating layer 40. The insulating layer 40 may be made of any insulating material as long as a sufficient etching selectivity with respect to the insulating layer 25 can be obtained when processing the contact plug CP1.

[0076] The selection transistor ST1 is formed by the semiconductor layer 33, the laminate 37, and the wiring layer 39. The channel region of the selection transistor ST1 is formed in a crankshaft shape by the crankshaft-shaped semiconductor layer 33 (semiconductor layer 33a and semiconductor layer 33b) provided along the side and bottom surfaces of the wiring layer 39.

[0077] A conductor 41 functioning as a contact plug CP1 is provided on the semiconductor layer 33 (semiconductor layer 33c). Figure 4 The example shows a case where a portion of the conductor 41 is provided on the insulating layer 40 due to positional deviation caused by manufacturing variation, but the conductor 41 may not be provided on the insulating layer 40. In other words, the bottom surface of the conductor 41 may not be in contact with the insulating layer 40.

[0078] A conductor 42 functioning as a contact plug CP2 is provided on the conductor 41 .

[0079] A wiring layer 43 functioning as a bit line BL and extending in the Y direction is provided on the conductor 42 .

[0080] The conductors 41 and 42 and the wiring layer 43 are made of a conductive material, and for example, a metal material can be used.

[0081] 2. Configuration of Select Transistor ST1 and Select Gate Line SGD

[0082] Next, use Figure 5 An example of the arrangement of the selection transistor ST1 and the selection gate line SGD will be described. Figure 5 : is a perspective view showing the arrangement of the upper portion of the memory pillar MP, the selection transistor ST1, the selection gate line SGD, the contact plugs CP1 and CP2, and the bit line BL. Figure 5 In order to simplify the description, the example Figure 3 The memory columns MP2 and MP4 described in the above description are omitted. Figure 5 In the example, a portion of the insulating layer is omitted.

[0083] like Figure 5 As shown, for example, two memory pillars MP2 and MP4 are arranged in a staggered configuration in the X direction. A wiring layer 39 (selection gate line SGD0) extending in the X direction is provided so as to pass over a portion of the memory pillar MP2. Similarly, a wiring layer 39 (selection gate line SGD1) extending in the X direction is provided so as to pass over a portion of the memory pillar MP4. A semiconductor layer 33 is provided between the memory pillars MP2 and MP4. The semiconductor layer 33 is connected to the wiring layer 43 via conductors 41 and 42. In addition, Figure 5The example shows a case where a portion of the conductor 41 (contact plug CP1 ) is provided on the insulating layer 40 provided on the side surface of the wiring layer 39 due to positional deviation caused by manufacturing deviation, but the conductor 41 may not be provided on the insulating layer 40 .

[0084] 3. Manufacturing method of memory cell array

[0085] Next, use Figures 6 to 18 An example of a method for manufacturing the memory cell array 10 will be described. Figures 6 to 18 The plan view and the cross section along the line A1 - A2 (cross section A1 - A2 ) of the memory cell array 10 during the manufacturing steps are shown respectively.

[0086] Hereinafter, a method of forming the wiring layer 24 by forming a structure equivalent to the wiring layer 24 using a sacrificial layer and then removing the sacrificial layer 44 and replacing it with a conductive material (wiring layer 24) will be described.

[0087] like Figure 6 As shown, an insulating layer 21, a wiring layer 22, and an insulating layer 23 are sequentially formed on a semiconductor substrate 20. Next, nine sacrificial layers 44 corresponding to the wiring layers 24 and nine insulating layers 25 are alternately stacked. The sacrificial layers 44 can be made of a material that achieves a wet etching selectivity with the insulating layers 25. The following describes the case where SiN is used for the sacrificial layers 44.

[0088] Next, a memory pillar MP extending in the Z direction is formed. More specifically, first, a hole is formed that penetrates the nine insulating layers 25, the nine sacrificial layers 44, and the insulating layer 23, and whose bottom reaches the wiring layer 22. Next, after the blocking insulating film 26, the charge storage layer 27, and the tunnel insulating film 28 are sequentially stacked, the blocking insulating film 26, the charge storage layer 27, and the tunnel insulating film 28 on the top insulating layer 25 and on the bottom of the hole are removed, exposing the wiring layer 22 at the bottom of the hole. Next, a semiconductor layer 29 and a core layer 30 are formed to fill the hole. Next, the semiconductor layer 29 and the core layer 30 on the top insulating layer 25 are removed. At this time, the semiconductor layer 29 and the core layer 30 above the hole are also removed. Next, a cover layer 31 is formed to fill the top of the hole.

[0089] like Figure 7 As shown, after the insulating layer 25 is formed on the memory pillar MP, the insulating layer 32 is formed so as to cover the upper surface of the memory pillar MP. At this time, the insulating layer 32 in the region where the slit SLT is to be formed later is removed.

[0090] Next, the insulating layer 25 is formed.

[0091] like Figure 8As shown, a trench TR (groove pattern) is formed that extends in the X direction and whose bottom reaches the memory pillars MP. In this case, for example, the insulating layer 32 can be used as an etch stop layer, and the trench TR can be processed in two stages to reduce processing damage to the upper surfaces of the memory pillars MP. At the bottom of the trench TR, a portion of the upper surface of each memory pillar MP, arranged in two rows and staggered, is exposed.

[0092] Next, semiconductor layer 33, laminate 37 (i.e., insulating layers 34-36), and insulating layer 45 are sequentially stacked. At this point, semiconductor layer 33 is connected to the upper surface of memory pillar MP, i.e., cap layer 31. Insulating layer 45 functions, for example, as a protective layer for laminate 37. For example, a material that achieves a wet etching selectivity with laminate 37 can be used for insulating layer 45.

[0093] like Figure 9 As shown, a mask pattern (resist 46 ) covering the upper sides of two adjacent memory pillars MP is formed between the two trenches TR by photolithography.

[0094] like Figure 10 As shown, for example, by CDE (chemical dry etching), the insulating layer 34 and the insulating layer 45 in the region not covered by the resist 46 are removed.

[0095] like Figure 11 As shown, after the resist 46 is removed, a portion of the semiconductor layer 33 where the surface is exposed, that is, where the laminate 37 and the insulating layer 45 are not provided, is oxidized to form the insulating layer 38. At this time, the semiconductor layer 33 in the area covered by the laminate 37 and the insulating layer 45 is not oxidized. Furthermore, the end area of the semiconductor layer 33 where the surface is covered by the laminate 37 and the insulating layer 45 may also be oxidized.

[0096] Next, the insulating layer 45 is removed by, for example, wet etching.

[0097] like Figure 12 As shown, a wiring layer 39 is formed in the trench TR. More specifically, for example, TiN and W are sequentially formed to fill the trench TR. Next, the TiN and W are removed from the surface and the upper portion of the trench TR to form the wiring layer 39. At this time, the wiring layer 39 is formed so that the upper surface of the wiring layer 39 is lower than the upper surface of the semiconductor layer 33 (semiconductor layer 33c). In other words, the wiring layer 39 is formed so that the trench TR is not completely filled. Therefore, the wiring layer 39 has a sunken shape. In other words, the laminate 37 protrudes from the surface of the wiring layer 39.

[0098] like Figure 13As shown, for example, by CDE, the exposed portion of laminate 37, that is, the portion of laminate 37 that is located higher than the upper surface of semiconductor layer 33c and the upper surface of wiring layer 39 and in contact with the upper portion of semiconductor layer 33b, is removed. This exposes the upper portion of the side surface of semiconductor layer 33 (semiconductor layer 33b) and the upper surface of semiconductor layer 33 (semiconductor layer 33c).

[0099] like Figure 14 As shown, the insulating layer 40 is deposited by, for example, CVD.

[0100] like Figure 15 As shown, for example, insulating layer 40 is etched (hereinafter also referred to as "etch back") by RIE (Reactive ion etching). By etching back insulating layer 40, the insulating layer is removed except for the area in contact with the side surfaces of semiconductor layer 33. In other words, the side portions of insulating layer 40 (the portions in contact with the side surfaces of semiconductor layer 33) remain. In other words, insulating layer 40 is formed so as to be provided on the upper surfaces of the end portions of laminated body 37 and wiring layer 39, with the side surfaces in contact with the upper portion of the side surfaces of semiconductor layer 33 (semiconductor layer 33b).

[0101] like Figure 16 As shown, insulating layer 25 is formed. The surface of insulating layer 25 is then flattened, for example, by CMP (chemical mechanical polishing). Next, replacement is performed. More specifically, first, slit SLT is machined so that the bottom surface reaches the insulating layer 23. At this time, for example, insulating layer 32 is prevented from protruding from the sides of slit SLT. Next, sacrificial layer 44 is removed from the sides of slit SLT by wet etching, forming gap AG.

[0102] like Figure 17 As shown, TiN and W are then formed in sequence to fill the gap AG. The TiN and W formed in the slit SLT and on the uppermost insulating layer 25 are then removed to form the wiring layer 24. The slit SLT is then filled with the insulating layer 47. This completes the replacement.

[0103] like Figure 18 As shown, a conductor 41 is formed whose bottom surface is in contact with the semiconductor layer 33 .

[0104] like Figure 19 As shown, after the insulating layer 25 is formed, the conductor 42 and the wiring layer 43 are formed.

[0105] 4 Effects of this embodiment

[0106] According to the configuration of this embodiment, a semiconductor memory device with improved reliability can be provided. This effect will be described in detail.

[0107] According to the configuration of this embodiment, the select gate line SGD can be formed so as to pass over a portion of the memory pillar MP. Furthermore, the select transistor ST1 can be formed on the memory pillar MP, along the side and bottom surfaces of the select gate line SGD. Furthermore, a stopper layer STP can be formed on the gate insulating film (laminate 37) of the select transistor ST1. Thus, even if the contact plug CP1 is shifted toward the select gate line SGD due to manufacturing variations, the stopper layer STP prevents the gate insulating film from being processed.

[0108] Furthermore, in the configuration of this embodiment, the stopper layer STP is provided between the contact plug CP1 and the select gate line SGD, thereby suppressing inter-wiring short circuits or insulation breakdown between the contact plug CP1 and the select gate line SGD. Consequently, the reliability of the semiconductor memory device can be improved.

[0109] Furthermore, according to the configuration of this embodiment, short circuits or insulation breakdown between the contact plug CP1 and the select gate line SGD caused by manufacturing variations can be suppressed, thereby improving manufacturing yield.

[0110] 5. Modifications, etc.

[0111] The semiconductor storage device in the embodiment includes: a plurality of first wiring layers (WL) stacked along a first direction (Z direction); a first memory column (MP2) including a first semiconductor layer (29) extending along the first direction inside the plurality of first wiring layers; a second wiring layer (39, SGD0) arranged above the first semiconductor layer; a second semiconductor layer (33) including a first portion (33a) arranged between the first semiconductor layer and the second wiring layer, a second portion (33b) extending above the first semiconductor layer, and a third portion (33c) arranged on the second portion; a first insulating layer (37) arranged between the first portion and the second wiring layer and between the second portion and the second wiring layer; and a second insulating layer (40) arranged on the first insulating layer and in contact with a portion of the second portion.

[0112] By applying the above-described embodiment, a semiconductor memory device capable of improving reliability can be provided.

[0113] In addition, the embodiment is not limited to the above-described embodiment, and various modifications can be made.

[0114] For example, in the above embodiment, two adjacent memory pillars MP are connected to a common contact plug CP1. However, the arrangement of the memory pillars MP and the contact plugs CP1 is not limited to this. For example, a contact plug CP1 may be provided for each memory pillar MP. In this case, the semiconductor layer 33 is also provided for each memory pillar MP.

[0115] Furthermore, the memory column MP may be arranged so that the center of the memory column MP in the Y direction is aligned with the center of the select gate line SGD. In this case, two select transistors ST1 can be formed on one memory column MP.

[0116] Furthermore, the term “connected” in the above embodiments also includes an indirect connection with some other component such as a transistor or a resistor interposed therebetween.

[0117] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0118] [Explanation of Symbols]

[0119] 1 Semiconductor memory device

[0120] 2 Memory Controller

[0121] 10 memory cell array

[0122] 11 Instruction register

[0123] 12 Address registers

[0124] 13 Sequencer

[0125] 14 Driver Module

[0126] 15-line decoder module

[0127] 16 Sense Amplifier Modules

[0128] 20 semiconductor substrate

[0129] 21, 23, 25, 32, 34-36, 38, 40, 45, 47 Insulation layer

[0130] 22, 24, 39, 43 wiring layers

[0131] 26 Barrier insulating film

[0132] 27 Charge storage layer

[0133] 28 Tunnel insulating film

[0134] 29, 33, 33a to 33c semiconductor layer

[0135] 30 core layers

[0136] 31 Covering

[0137] 37 Layered

[0138] 41, 42 Conductors

[0139] 44 Sacrificial layer

[0140] 46 Resist.

Claims

1. A semiconductor memory device comprising: A plurality of first wiring layers are stacked along a first direction; a first memory pillar including a first semiconductor layer extending along the first direction within the plurality of first wiring layers; a second wiring layer disposed above the first semiconductor layer; a second semiconductor layer including a first portion disposed between the first semiconductor layer and the second wiring layer, a second portion extending above the first semiconductor layer, and a third portion provided on the second portion; a first insulating layer disposed between the first portion and the second wiring layer and between the second portion and the second wiring layer; and The second insulating layer is provided on the first insulating layer and is in contact with a portion of the second portion.

2. The semiconductor memory device according to claim 1, further comprising: a second memory pillar including a third semiconductor layer extending along the first direction within the plurality of first wiring layers; and a third wiring layer disposed above the third semiconductor layer; and The second semiconductor layer further includes a fourth portion disposed between the third semiconductor layer and the third wiring layer, and a fifth portion extending above the third semiconductor layer and connected to the third portion.

3. The semiconductor memory device according to claim 2, further comprising: a third insulating layer disposed between the fourth portion and the third wiring layer and between the fifth portion and the third wiring layer; and The fourth insulating layer is provided on the third insulating layer and is in contact with a portion of the fifth portion.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein A portion of the bottom surface of the second insulating layer is in contact with a portion of the upper surface of the second wiring layer.

5. The semiconductor memory device according to claim 2, The device further includes a first conductor provided on the fifth portion of the second semiconductor layer. The semiconductor memory device according to claim 5 , wherein A portion of the bottom surface of the first conductor is in contact with the upper surface of the second insulating layer.

7. The semiconductor memory device according to claim 1, wherein The first memory column further includes a charge storage layer.

8. A method for manufacturing a semiconductor memory device, comprising the following steps: forming a memory pillar including a first semiconductor layer extending along a first direction; forming a first insulating layer on the memory column; processing the first insulating layer to form a groove pattern extending in a second direction intersecting the first direction and exposing an upper portion of the memory pillar; forming a second semiconductor layer connected to the memory pillar; forming a second insulating layer on the second semiconductor layer; oxidizing a portion of the second semiconductor layer on the upper surface of which the second insulating layer is not provided; forming a wiring layer in the groove pattern; A third insulating layer is formed on the second insulating layer and in contact with a portion of the second semiconductor layer.

9. The method for manufacturing a semiconductor memory device according to claim 8, wherein The step of forming the third insulating layer includes the following steps: removing a portion of the second insulating layer; depositing the third insulating layer; and The third insulating layer is processed.

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