Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a stack body including conductive layers and insulating layers alternately stacked in a first direction, partition structures each extending in the first and second directions in the stack body, and an intermediate structure extending from an upper end and terminating at a position between an upper end and a lower end of the stack body between adjacent partition structures. The partition structures include a first partition structure including first and second portions arranged in the second direction, the first portion extending from the upper end to the lower end, and the second portion located between adjacent first portions, extending from the upper end and terminating at the position between the upper end and the lower end.

Description

[0001] Cross-reference of related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2020-157519, filed on September 18, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to a semiconductor memory device. Background Technology

[0004] In three-dimensional non-volatile memories where multiple memory cells are stacked on a semiconductor substrate, structural stability is crucial. Summary of the Invention

[0005] Generally, according to one embodiment, a semiconductor memory device includes: a stacked body comprising a structure in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked in a first direction; a plurality of columnar structures, each comprising a semiconductor layer extending through the stacked body in the first direction; a plurality of partitioning structures, each extending in the stacked body in the first direction and in a second direction intersecting the first direction, and dividing the plurality of columnar structures into a plurality of groups in a third direction intersecting the first and second directions; and an intermediate structure provided between the partitioning structures adjacent to each other in the third direction, the intermediate structure extending from an upper end of the stacked body in the first direction and terminating at a position between the upper and lower ends of the stacked body, wherein the partitioning structure includes a first partitioning structure comprising at least two first portions and at least one second portion arranged in the second direction, the second portion being located between the first portions adjacent to each other in the second direction, each of the first portions extending from the upper end of the stacked body to the lower end in the first direction, and the second portion extending from the upper end of the stacked body in the first direction and terminating at the position between the upper and lower ends of the stacked body.

[0006] According to the described embodiment, a semiconductor memory device with a stable structure can be obtained. Attached Figure Description

[0007] Figure 1A This is a plan view schematically illustrating the basic configuration of a semiconductor memory device according to an embodiment.

[0008] Figure 1B This is a cross-sectional view schematically illustrating the basic configuration of a semiconductor memory device according to an embodiment.

[0009] Figure 1C This is a cross-sectional view schematically illustrating the basic configuration of a semiconductor memory device according to an embodiment.

[0010] Figure 2 This is a perspective view illustrating a portion of the configuration of a semiconductor memory device according to an embodiment.

[0011] Figure 3A This is a cross-sectional view schematically illustrating the detailed configuration of memory cell units in a semiconductor memory device according to an embodiment.

[0012] Figure 3B This is a cross-sectional view schematically illustrating the detailed configuration of memory cell units in a semiconductor memory device according to an embodiment.

[0013] Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A This is a plan view schematically illustrating a portion of a semiconductor memory device manufacturing method according to an embodiment.

[0014] Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B This is a cross-sectional view that schematically illustrates a part of a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Figure 10 This is a plan view illustrating a portion of the manufacturing method in a semiconductor memory device according to an embodiment, where the wiring pattern used for shunting is changed.

[0016] Figure 11 This is a plan view illustrating a portion of the manufacturing method in a semiconductor memory device according to an embodiment, where the wiring pattern used for shunting is changed.

[0017] Figure 12 This is a schematic plan view illustrating the configuration of wiring for shunting in a semiconductor memory device according to an embodiment.

[0018] Figure 13A This is a schematic view illustrating a planar pattern of a semiconductor memory device according to an embodiment.

[0019] Figure 13B This is a cross-sectional view illustrating the configuration of a semiconductor memory device according to an embodiment.

[0020] Figure 13CThis is a cross-sectional view illustrating the configuration of a semiconductor memory device according to an embodiment.

[0021] Figure 13D This is a cross-sectional view illustrating the configuration of a semiconductor memory device according to an embodiment.

[0022] Figure 14A This is a plan view illustrating a first modified example of a semiconductor memory device according to an embodiment.

[0023] Figure 14B This is a cross-sectional view illustrating a first modified example of a semiconductor memory device according to an embodiment.

[0024] Figure 14C This is a cross-sectional view illustrating a first modified example of a semiconductor memory device according to an embodiment.

[0025] Figure 14D This is a cross-sectional view illustrating a first modified example of a semiconductor memory device according to an embodiment.

[0026] Figure 15A This is a plan view illustrating a second modified example of a semiconductor memory device according to an embodiment.

[0027] Figure 15B This is a cross-sectional view illustrating a second modified example of a semiconductor memory device according to an embodiment.

[0028] Figure 16A This is a plan view illustrating a third modified example of a semiconductor memory device according to an embodiment.

[0029] Figure 16B This is a cross-sectional view illustrating a third modified example of a semiconductor memory device according to an embodiment. Detailed Implementation

[0030] One of the embodiments will be described below with reference to the accompanying drawings.

[0031] First, the basic configuration of a semiconductor memory device (NAND-type non-volatile semiconductor memory device) according to an embodiment will be described.

[0032] Figure 1A A schematic diagram illustrating the basic configuration of a semiconductor memory device according to this embodiment. Figure 1B and Figure 1C It is along Figure 1A The sectional view taken by lines BB and CC. Figure 2 This is a perspective view illustrating a portion of the configuration of a semiconductor memory device according to this embodiment. However, Figure 2The conductive layer 11 is not shown in the diagram for easy viewing. Incidentally, the X direction (third direction), Y direction (second direction), and Z direction (first direction) are orthogonal to each other.

[0033] The semiconductor memory device according to this embodiment includes a stacked layer 10, a plurality of pillar structures 20, a plurality of partition structures 30, and a plurality of intermediate structures 40. The stacked layer 10, pillar structures 20, partition structures 30, and intermediate structures 40 are provided above a semiconductor substrate 100.

[0034] The stacked layer 10 has a structure in which a plurality of conductive layers 11 and a plurality of insulating layers 12 are alternately stacked in the Z direction. Incidentally, a large number of conductive layers 11 and insulating layers 12 are actually stacked, and the number of stacked conductive layers 11 and insulating layers 12 is greater than the number shown in the figures. The conductive layers 11 are formed of a metallic material (e.g., tungsten (W)) and the insulating layers 12 are formed of an insulating material (e.g., silicon oxide). The conductive layers 11 and insulating layers 12 are provided parallel to an XY plane perpendicular to the Z direction. The conductive layers 11 include the function of electrode layers, more specifically, word lines or select gate lines of a NAND string. The insulating layers 12 include the function of insulating adjacent conductive layers 11 from each other.

[0035] Each of the columnar structures 20 extends through the stacked layer 10 in the Z direction, includes a semiconductor layer extending in the Z direction and a charge storage layer surrounding the side surface of the semiconductor layer, forms a memory cell at each intersection with a word line, and forms a selection transistor at each intersection with a selection gate line.

[0036] Figure 3A and Figure 3B Each of these is a cross-sectional view schematically illustrating the detailed configuration of a memory cell unit arranged by the conductive layer 11 and the columnar structure 20. Figure 3A It is a sectional view taken in a direction parallel to the Z direction, and Figure 3B It is a sectional view taken in a direction perpendicular to the Z direction.

[0037] The columnar structure 20 includes a semiconductor layer 21, a tunneling insulating layer 22, a charge storage layer 23, a barrier insulating layer 24, and a core insulating layer 25. Each of the semiconductor layer 21, tunneling insulating layer 22, charge storage layer 23, and barrier insulating layer 24 has a cylindrical shape, and the core insulating layer 25 has a columnar shape. More specifically, the semiconductor layer 21 surrounds the side surface of the core insulating layer 25, the tunneling insulating layer 22 surrounds the side surface of the semiconductor layer 21, the charge storage layer 23 surrounds the side surface of the tunneling insulating layer 22, and the barrier insulating layer 24 surrounds the side surface of the charge storage layer 23. For example, the semiconductor layer 21 is formed of silicon, the tunneling insulating layer 22 is formed of silicon oxide, the charge storage layer 23 is formed of silicon nitride, the barrier insulating layer 24 is formed of silicon oxide, and the core insulating layer 25 is formed of silicon oxide.

[0038] The conductive layer 11 surrounding the columnar structure 20 serves as a gate electrode, and the memory cell is configured with a portion serving as the gate electrode of the conductive layer 11 and a portion surrounded by the conductive layer 11 of the columnar structure 20.

[0039] The upper select transistor portion (drain-side select transistor portion) and the lower select transistor portion (source-side select transistor portion) for selecting the memory cell unit are provided on the upper and lower layers of the memory cell unit, respectively. The basic configuration of these select transistor portions is also similar to... Figure 3A and Figure 3B The configuration of the memory cell unit is described herein. In the selection transistor section, the tunneling insulating layer 22, the charge storage layer 23, and the barrier insulating layer 24 are all used as gate insulating layers.

[0040] Each of the partition structures 30 extends in the Z and Y directions within the stacked layer 10, and the columnar structures 20 are divided into multiple groups in the X direction by the partition structures 30. The partition structures 30 are arranged at approximately regular intervals in the X direction, and the number of columns of columnar structures 20 arranged between adjacent partition structures 30 is constant. In this embodiment, nine rows of columnar structures 20, including the dummy columnar structures (columnar structures arranged at positions corresponding to the intermediate structure 40) described below, are arranged between adjacent partition structures 30.

[0041] The partition structure 30 includes a first partition structure 31 and a second partition structure 32. Except for the second portion 31b of the first partition structure 31, which will be described below, the first partition structure 31 and the second partition structure 32 are formed by embedding predetermined material into slits used in the replacement process described below. The first partition structure 31 and the second partition structure 32 are provided alternately in the X direction.

[0042] The first partition structure 31 includes a first part 31a and a second part 31b, which will be described below.

[0043] By the way, in Figure 1A In the example, a first partition structure 31 is described with two first portions 31a and one second portion 31b, but the first partition structure 31 may alternately provide multiple first portions 31a and multiple second portions 31b in the Y direction. Generally, the first partition structure 31 includes at least two first portions 31a and at least one second portion 31b arranged in the Y direction, and the second portion 31b is located between adjacent first portions 31a in the Y direction. In addition, in the Y direction, the total length of the at least two first portions 31a is greater than the total length of the at least one second portion 31b.

[0044] like Figure 1C As described, the first portion 31a extends from the upper end to the lower end of the stacked layer 10 in the Z direction. Therefore, in the region where the first portion 31a is provided, the stacked layer 10 is divided from the upper end to the lower end in the X direction. The first portion 31a includes a conductive portion 31a1 and an insulating portion 31a2. The conductive portion 31a1 extends from the upper end to the lower end of the stacked layer 10, and the lower end of the conductive portion 31a1 is connected to the common source region of the semiconductor substrate 100. The insulating portion 31a2 is interposed between the conductive portion 31a1 and the stacked layer 10, and the conductive portion 31a1 is electrically isolated from the conductive layer 11 of the stacked layer 10 through the insulating portion 31a2.

[0045] The second part 31b is provided adjacent to the first part 31a. More specifically, the second part 31b is provided between the first parts 31a. Figure 1B As described, the second portion 31b extends in the Z direction from the upper end of the stacked layer 10 to a predetermined position between the upper and lower ends of the stacked layer 10, and is formed by an insulating portion extending to the predetermined position. Therefore, in the region where the second portion 31b is provided, the stacked layer 10 is divided from the upper end to the predetermined position in the X direction. More specifically, the second portion 31b, extending from the upper end of the stacked layer 10 in the Z direction, terminates at the predetermined position and is divided in the X direction by a predetermined number of conductive layers 11 (in the illustrated example, three conductive layers 11). The predetermined number of conductive layers 11 serve as the gate electrodes of the upper select transistor portion of the NAND string.

[0046] like Figure 1B and Figure 1CAs described, the second partition structure 32 has a structure that extends from the upper end to the lower end of the stacked layer 10 in the Z direction. Therefore, in the region where the second partition structure 32 is provided, the stacked layer 10 is divided from the upper end to the lower end in the X direction. The second partition structure 32 includes a conductive portion 32a1 and an insulating portion 32a2. The conductive portion 32a1 extends from the upper end to the lower end of the stacked layer 10, and the lower end of the conductive portion 32a1 is connected to the common source region of the semiconductor substrate 100. The insulating portion 32a2 is interposed between the conductive portion 32a1 and the stacked layer 10, and the conductive portion 32a1 is electrically isolated from the conductive layer 11 of the stacked layer 10 through the insulating portion 32a2.

[0047] An intermediate structure 40 is provided between adjacent partition structures 30 in the X direction. More specifically, the intermediate structure 40 is provided at approximately the center of adjacent partition structures 30 in the X direction and between adjacent first partition structures 31 and second partition structures 32 in the X direction. Additionally, the intermediate structure 40 is provided at the position corresponding to a column of the dummy columnar structure 20d that is not used as a memory cell. That is, the intermediate structure 40 is provided at the position corresponding to the center column of the columnar structure 20.

[0048] The intermediate structure 40 extends in the stacked layer 10 in both the Z and Y directions. More specifically, the intermediate structure 40 has an insulating portion extending from the upper end of the stacked layer 10 in the Z direction and terminating at a predetermined position between the upper and lower ends of the stacked layer 10. Therefore, in the region where the intermediate structure 40 is provided, the stacked layer 10 is divided from the upper end to the predetermined position in the X direction. More specifically, the intermediate structure 40 divides a predetermined number of conductive layers 11 in the X direction (three conductive layers 11 in the illustrated example). The predetermined number of conductive layers 11 serve as the gate electrode of the upper selection transistor portion.

[0049] The intermediate structure 40 is formed using the same process as the second portion 31b of the first partition structure 31. Therefore, the material of the intermediate structure 40 is the same as the material of the second portion 31b of the first partition structure 31. In addition, the positions of the upper and lower ends of the intermediate structure 40 in the height direction (Z direction) correspond to the positions of the second portion 31b of the first partition structure 31 in the height direction (Z direction), and the number of conductive layers 11 divided by the intermediate structure 40 is the same as the number of conductive layers 11 divided by the second portion 31b of the first partition structure 31.

[0050] Furthermore, the linewidth (width in the X direction) of the intermediate structure 40 is substantially the same as the linewidth of the second part 31b of the first partition structure 31 and smaller than the linewidth of the first part 31a of the first partition structure 31 and the linewidth of the second partition structure 32. Therefore, the area occupied by the intermediate structure 40 (area occupied in the X direction) is smaller than the area occupied by the first partition structure 31 and the second partition structure 32 (area occupied in the X direction).

[0051] Incidentally, the upper ends of the first partition structure 31 (first part 31a and second part 31b), the second partition structure 32, and the intermediate structure 40 can be positioned in the height direction (Z direction) as follows: Figure 1B and Figure 1C The positions may be aligned as illustrated in the examples, or they may not be aligned at all. For example, the upper positions of the first portion 31a and the second portion 31b of the first partition structure 31 may or may not be aligned with each other. Similarly, the upper positions of the second portion 31b, the intermediate structure 40, and the second partition structure 32 of the first partition structure 31 may or may not be aligned with each other.

[0052] Next, the functions of the partition structure 30 and the intermediate structure 40 will be described.

[0053] As described above, the partition structure 30 is formed essentially by filling slits with a predetermined material for the replacement process described below. The slits are used to remove the sacrificial layer and form the conductive layer 11 during the replacement process.

[0054] Furthermore, as described above, the first partition structure 31 and the second partition structure 32 are provided alternately in the X direction. A block consists of a second partition structure 32, a first partition structure 31, and a second partition structure 32 that are continuous in the X direction. In the same block, except for the conductive layer 11 divided in the X direction by the second portion 31b of the first partition structure 31 and the intermediate structure 40, each of the conductive layers 11 contained in the stacked layer body 10 is commonly electrically connected. That is, in the same block, each conductive layer 11 serves as a common word line or as a lower selection gate line for the gate electrode of the lower selection transistor portion.

[0055] The intermediate structure 40 is provided at approximately the center position between adjacent partition structures 30 in the X direction. That is, the intermediate structure 40 is provided at approximately the center position between the first partition structure 31 and the second partition structure 32. Therefore, in this embodiment, the number of columns of the columnar structures 20 arranged between the intermediate structure 40 and the first partition structure 31 is the same as the number of columns of the columnar structures 20 arranged between the intermediate structure 40 and the second partition structure 32 (4 columns).

[0056] Additionally, as described above, the intermediate structure 40 is divided into a predetermined number of conductive layers 11 in the X direction (three conductive layers 11 in the illustrated example). As described, the predetermined number of conductive layers 11 (three conductive layers 11) serve as the gate electrodes of the upper selection transistor portion. Therefore, the gate electrodes of the selection transistors located in the same layer are shared between the adjacent intermediate structure 40 and partition structure 30, and the predetermined number of conductive layers 11 serve as a common upper selection gate line.

[0057] As described above, in this embodiment, the first partition structure 31 includes a second portion 31b extending from the upper end of the stacked layer 10 to a predetermined position between the upper and lower ends of the stacked layer 10. This provides a semiconductor memory device with a stable structure. In particular, the stable structure can be maintained during the replacement process described below. Further description follows.

[0058] As described, the partition structure 30 is formed by filling the slits used for the replacement process with a predetermined material. The replacement process is performed during the formation of the stacked layer body 10. More specifically, the stacked layer body 10 is formed by alternately stacking insulating layers and sacrificial layers, then removing the sacrificial layers by etching through the slits to form cavities, and filling the cavities with conductive layers. Therefore, during the cavity formation stage, the insulating layer 12 constituting the stacked layer body 10 is supported only by the columnar structure 20 and is unstable.

[0059] In this embodiment, the first partition structure 31 includes a first portion 31a and a second portion 31b. The first portion 31a extends from the upper end to the lower end of the stacked layer 10, similar to the second partition structure 32. Therefore, in the region corresponding to the first portion 31a, a slit is formed during the replacement process and effectively functions during the replacement process. The second portion 31b extends from the upper end of the stacked layer 10 to a predetermined position between the upper and lower ends of the stacked layer 10. Therefore, the insulating layer 12 can be supported by the second portion 31b during the replacement process, and the stability of the structure can be improved. Thus, according to the structure of this embodiment, structural stability can be achieved without interfering with the replacement process.

[0060] Furthermore, in this embodiment, the linewidth (width in the X direction) of the intermediate structure 40 is smaller than the linewidth of the first portion 31a of the first partition structure 31 and the linewidth of the second partition structure 32, and the occupied area (occupied area in the X direction) of the intermediate structure 40 is smaller than the occupied area (occupied area in the X direction) of the first partition structure 31 and the second partition structure 32. If a portion with a large linewidth (e.g., the first portion 31a of the first partition structure 31) is provided in the intermediate structure 40, then the occupied area of ​​the intermediate structure 40 is substantially defined by the portion with the large linewidth, and the total area of ​​the cell array region increases. In this embodiment, since the linewidth of the entire intermediate structure 40 is small, the total area of ​​the cell array region can be reduced.

[0061] Furthermore, in this embodiment, the total length of the first portion 31a, including the conductive portion 31a1, in the Y direction is longer than the total length of the second portion 31b in the Y direction. As described, the conductive portion 31a1 of the first portion 31a extends from the upper end to the lower end of the stacked layer 10 and is connected to the common source region of the semiconductor substrate 100. Therefore, the resistance in the Y direction can be reduced by making the length of the first portion 31a relatively long, and the source line resistance can be reduced from the perspective of the entire cell array region.

[0062] Next, we will refer to Figures 4A to 9A (Flat pattern diagram) and Figures 4B to 9B (Cross-sectional view) Describes a method for manufacturing a semiconductor memory device according to this embodiment.

[0063] First, such as Figure 4A and Figure 4B As described, a stacked film 10x, in which multiple insulating layers 12 and multiple sacrificial layers 13 are alternately stacked in the Z direction, is formed on a semiconductor substrate 100. For example, the insulating layer 12 is formed of silicon oxide and the sacrificial layer 13 is formed of silicon nitride. Subsequently, in the stacked film 10x, slits are formed from the upper end of the stacked film 10x to a height position corresponding to the lower end of the intermediate structure 40, and the insulating structure portion 51 is formed by filling the slits with an insulator (e.g., silicon oxide). The insulating structure portion 51 is formed at a planar position corresponding to the first partition structure 31, the second partition structure 32, and the intermediate structure 40.

[0064] Next, as Figure 5A and Figure 5B As explained, memory holes are formed in the stacked film 10x, and columnar structures 20 are formed in the memory holes. Columnar structures 20 are also formed as dummy columnar structures 20d at positions corresponding to the portion of the insulating structure portion 51.

[0065] Next, as Figure 6A and Figure 6B As described above, an insulating layer 61 is formed over the entire surface, and then a slit 52 is formed through the insulating layer 61 in the stacked film 10x. More specifically, the slit 52 is formed at a position corresponding to the first portion 31a of the first partition structure 31 and at a position corresponding to the second partition structure 32. At this time, the slit 52 is not formed, but the insulating structure portion 51 remains at the position corresponding to the second portion 31b of the first partition structure 31. Furthermore, the etching solution is introduced through the slit 52, and the sacrificial layer 13 is selectively etched. Therefore, a cavity 53 is formed in the region where the sacrificial layer 13 is removed. As described above, the slit 52 is not formed, but the insulating structure portion 51 remains at the position corresponding to the second portion 31b of the first partition structure 31. This improves the stability of the structure even when the cavity 53 is formed.

[0066] Next, as Figure 7A and Figure 7B As described, cavity 53 is filled with a metallic material (e.g., tungsten (W)) to form conductive layer 11. Furthermore, insulating portions 31a2 and 32a2, and conductive portions 31a1 and 32a1 are formed in slit 52. Conductive portions 31a1 and 32a1 are connected to the common source region of semiconductor substrate 100 to provide a predetermined potential to the common source region of semiconductor substrate 100. Therefore, a first partition structure 31, a second partition structure 32, and an intermediate structure 40 are obtained.

[0067] include Figure 1A , Figure 1B and Figure 1C The semiconductor memory device with the basic configuration described herein can be obtained in the manner described above.

[0068] Next, as Figure 8A and Figure 8B As described, an insulating layer 61 is further formed over the entire surface, and a plurality of plugs 62a, 62b, and 62c are formed in portions of the insulating layer 61 having increased thickness. Plug 62a is connected to a first portion 31a of the first partition structure 31, and plug 62b is connected to the second partition structure 32. Additionally, plug 62c is connected to the pillar structure 20. More specifically, plug 62c is connected to the drain of the selected transistor.

[0069] Next, as Figure 9A and Figure 9B As described, the wiring 63 for shunting is formed on the insulating layer 61, plugs 62a and 62b. That is, the wiring 63 for shunting is formed above the first partition structure 31, the second partition structure 32, and the intermediate structure 40. Multiple plugs 62a and 62b are connected by the wiring 63. Therefore, the first portions 31a of the first partition structure 31 adjacent to each other in the Y direction are connected by plugs 62a. Furthermore, the first portions 31a and the second partition structure 32 of the first partition structure 31 are also connected by plugs 62a and 62b. In addition, the first portions 31a of the first partition structure 31 arranged in the X direction are also connected by plugs 62a. Therefore, a predetermined potential can be supplied to the common source region of the semiconductor substrate 100 by supplying the predetermined potential to the wiring 63 via plugs 62a and 62b, the first portions 31a and the second partition structure 32 of the first partition structure 31.

[0070] As described above, according to the manufacturing method of this embodiment, when the cavity 53 is formed in Figure 6A and Figure 6BDuring the process, the insulating structure portion 51 remains at the position corresponding to the second portion 31b of the first partition structure 31, thereby improving the stability of the structure when forming the cavity 53.

[0071] Furthermore, in this embodiment, the first portion 31a of the first partition structure 31 is formed in the same process as the second partition structure 32, and the second portion 31b of the first partition structure 31 is formed in the same process as the intermediate structure 40. Therefore, a semiconductor memory device with the above advantages can be formed without adding any special processes.

[0072] Figure 10 and Figure 11 This is a schematic plan view illustrating a method of manufacturing a semiconductor memory device in which the wiring used for shunting is changed.

[0073] In the manufacturing method, Figure 7A and Figure 7B After the process, insulating layer 61 in Figure 10 Formed over the entire surface during the process, similar to Figure 8A and Figure 8B The process involves multiple plugs 62a and 62c formed within portions of the thickened insulating layer 61. Plug 62a is connected to the first portion 31a of the first partition structure 31, and plug 62c is connected to the columnar structure 20.

[0074] Next, as Figure 11 As described, the wiring 63 for shunting is formed on the insulating layer 61 and the plug 62a. That is, the wiring 63 for shunting is formed above the first partition structure 31 along the first partition structure 31. The first portions 31a of the first partition structure 31 that are adjacent to each other in the Y direction are connected by the wiring 63 through the plug 62a. Therefore, a predetermined potential can be supplied to the common source region of the semiconductor substrate 100 through the plug 62a and the first portion 31a of the first partition structure 31 by supplying the predetermined potential to the wiring 63.

[0075] Figure 12 This is a schematic diagram illustrating the planar configuration of a semiconductor memory device with centralized wiring for shunting. For example... Figure 12 As described in the document, the wiring 63 used for shunting is as follows: Figure 9A The area provided as described, including the cabling 63 used for distribution, is as follows: Figure 11 The areas described herein and the areas in which no cabling for branching is provided may coexist.

[0076] Given the circuit, the first partition structure 31 becomes equivalent to the second partition structure 32, and this equivalent partition structure 30 is arranged in the X direction with a small pitch by first portions 31a adjacent to each other in the Y direction connected by wiring 63 for shunting. Furthermore, as described above, the conductive portions 31a1 of the first portion 31a of the first partition structure 31 and the conductive portions 32a1 of the second partition structure 32 extend from the upper end to the lower end of the stacked layer 10 and are connected to the common source region of the semiconductor substrate 100. Therefore, from the viewpoint of the entire cell array region, the source line resistance can be reduced by providing the aforementioned wiring 63 for shunting.

[0077] also, Figure 13A , Figure 13B , Figure 13C and Figure 13D The description below illustrates the configuration of the semiconductor memory device according to this embodiment, and will be compared to... Figure 13A , Figure 13B , Figure 13C and Figure 13D The semiconductor memory device described is a modified example according to this embodiment.

[0078] Figure 13A Corresponding to Figure 1A It also provides a schematic illustration of a two-dimensional pattern. Figure 13B It is an illustrative description along Figure 13A A sectional view of the section cut by line BB. Figure 13C It is an illustrative description corresponding to Figure 13B A cross-sectional view of the configuration at the position of plane CC. Figure 13D It is an illustrative description corresponding to Figure 13B A sectional view of the configuration at the location of plane DD. Incidentally, in Figure 13A , Figure 13B , Figure 13C and Figure 13D In one example, during the replacement of the conductive layer 11, when a portion of the metal material filling the slit is removed and the conductive layer 11 is separated in the Z direction, the slit-side portion of the conductive layer 11 is further back than the slit-side portion of the insulating layer 12, and it is assumed that the modified example described below has the same configuration.

[0079] Figure 14A , Figure 14B , Figure 14C and Figure 14D The configuration of the semiconductor memory device according to the first modified example of this embodiment is described. Figure 14A , Figure 14B , Figure 14C and Figure 14D The relationship between them is the same as Figure 13A , Figure 13B , Figure 13C and Figure 13D The interrelationship between them. In the modified example, the length of the second portion 31b of the first partition structure 31 in the Y direction is reduced. Therefore, during the replacement process, the metal material disappears only below the second portion 31b, causing the metal material to recede from both sides of the second portion 31b in the Y direction, and the conductive layer 11 is only absent below the second portion 31b. Therefore, each portion between adjacent first partition structures 31 and second partition structures 32 in the X direction can be configured as a block sharing a word line.

[0080] Figure 15A and Figure 15B The configuration of the semiconductor memory device according to the second modified example of this embodiment is described. Figure 15A and Figure 15B The relationship between them is the same as Figure 13A and Figure 13B The relationship between them. In the modified example, the first portion 31a and the second portion 31b of the first partition structure 31 are arranged alternately in a stitch pattern in the Y direction. As described, it is expected that the total length of the first portion 31a in the Y direction is longer than the total length of the second portion 31b in the Y direction. Therefore, it is expected that the length of each first portion 31a in the Y direction is longer than the length of each second portion 31b in the Y direction.

[0081] Figure 16A and Figure 16B The configuration of the semiconductor memory device according to the third modified example of this embodiment is described. Figure 16A and Figure 16B The relationship between them is the same as Figure 13A and Figure 13B The interrelationship between them. In this modified example, the entire first part 31a of the first partition structure 31 and the entire second partition structure (not shown) are formed of insulating material.

[0082] The basic configurations of the first, second, and third modified examples are the same as those of the above embodiments, and the same advantages of the above embodiments can also be obtained from the first, second, and third modified examples.

[0083] Although specific embodiments have been described, these embodiments are merely illustrative and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein may be embodied in various other forms; furthermore, various omissions, substitutions, and changes may be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications falling within the scope and spirit of the invention.

Claims

1. A semiconductor memory device, comprising: A stacked layer body comprising a structure in which multiple conductive layers and multiple insulating layers are alternately stacked in a first direction; Multiple columnar structures, each comprising a semiconductor layer extending through the stacked body in the first direction; Multiple partition structures, each extending in the stacked layer in the first direction and in the second direction intersecting the first direction, and dividing the multiple columnar structures into multiple groups in the third direction intersecting the first and second directions; and An intermediate structure is provided between the partition structures that are adjacent to each other in the third direction, the intermediate structure extending from one end of the stacked layer in the first direction and terminating at a position between the one end and the other end of the stacked layer in the first direction. in The partitioning structure includes a first partitioning structure comprising at least two first portions and at least one second portion arranged in the second direction, the second portions being located between the first portions that are adjacent to each other in the second direction. Each of the first portions extends from one end of the stacked layer to the other end in the first direction, and The second portion extends from one end of the stacked layer in the first direction and terminates at the location between the one end and the other end of the stacked layer. The second part divides a predetermined number of conductive layers upwards from the third party. The intermediate structure is divided into conductive layers in the direction of the third party, the same number as the predetermined number of conductive layers divided by the second part. The predetermined number is 2 or more. Relative to the position between one end and the other end of the stacked layer, a plurality of conductive layers located on the other end side of the stacked layer overlap with the second portion in the first direction, and each of the overlapping portions of the conductive layers extends continuously from one of the two first portions to the other of the two first portions in the second direction, the two first portions being adjacent to each other in the second direction via the second portion.

2. The semiconductor memory device according to claim 1, wherein The second part is formed of the same material as the intermediate structure.

3. The semiconductor memory device according to claim 1, wherein... The second part is formed of insulating material.

4. The semiconductor memory device according to claim 1, wherein The predetermined number of conductive layers serve as the gate electrodes of the NAND string's select transistors.

5. The semiconductor memory device according to claim 1, wherein... Each of the first portions includes a first conductive portion extending from one end of the stacked layer to the other end.

6. The semiconductor memory device according to claim 1, wherein The total length of the at least two first parts in the second direction is longer than the total length of the at least one second part in the second direction.

7. The semiconductor memory device according to claim 5, wherein The partitioning structure further includes a second partitioning structure, which is adjacent to the extension portion upwards via the intermediate structure on the third side. The extension portion includes the at least two first portions and the at least one second portion of the first partitioning structure. The second partition structure includes a second conductive portion that extends from one end of the stacked layer to the other end in the first direction along the second direction of the extension portion of the first partition structure.

8. The semiconductor memory device according to claim 5, further comprising: The semiconductor portion, on which the stacked layer body is provided, The first conductive portion is connected to the semiconductor portion.

9. The semiconductor memory device according to claim 1, further comprising: The wiring overlaps with the first partition structure when viewed from the first direction, and the wiring electrically connects the first portions that are adjacent to each other in the second direction.

10. The semiconductor memory device of claim 1, wherein The width of one of the at least two second parts in the direction of the third party is less than the width of one of the at least two first parts in the direction of the third party.

11. A semiconductor memory device, comprising: A stacked layer body comprising a structure in which multiple conductive layers and multiple insulating layers are alternately stacked in a first direction; Multiple columnar structures, each comprising a semiconductor layer extending through the stacked body in the first direction; and Multiple partition structures, each extending within the stacked layer in a first direction and a second direction intersecting the first direction, further divide the multiple columnar structures into multiple groups in a third direction intersecting the first and second directions. in The partitioning structure includes a first partitioning structure comprising at least two first portions and at least one second portion arranged in the second direction, the second portions being located between the first portions that are adjacent to each other in the second direction. Each of the first portions includes a first conductive portion extending in the first direction from one end of the stacked layer in the first direction to the other end in the first direction. The second portion extends from one end of the stacked layer in the first direction and terminates at a position between the one end and the other end of the stacked layer. The device further includes wiring that overlaps with the first partition structure when viewed from the first direction, the wiring electrically connecting the first portions adjacent to each other in the second direction. Relative to the position between one end and the other end of the stacked layer, a plurality of conductive layers located on the other end side of the stacked layer overlap with the second portion in the first direction, and each of the overlapping portions of the conductive layers extends continuously from one of the two first portions to the other of the two first portions in the second direction, the two first portions being adjacent to each other in the second direction via the second portion.

12. The semiconductor memory device of claim 11, wherein... The second part is formed of insulating material.

13. The semiconductor memory device of claim 11, wherein... The second part divides a predetermined number of conductive layers upwards from the third party, and The predetermined number of conductive layers serve as the gate electrodes of the NAND string's select transistors.

14. The semiconductor memory device of claim 11, further comprising: The semiconductor portion, on which the stacked layer body is provided, The first conductive portion is connected to the semiconductor portion.

15. The semiconductor memory device of claim 11, wherein... The partitioning structure further includes a second partitioning structure adjacent to the extended portion on the third side upwards, the extended portion including the at least two first portions and the at least one second portion of the first partitioning structure, and The second partition structure includes a second conductive portion that extends from one end of the stacked layer to the other end in the first direction along the second direction of the extension portion of the first partition structure.

16. The semiconductor memory device of claim 15, wherein The wiring further electrically connects the first part to the second partition structure.

17. The semiconductor memory device of claim 11, wherein... The width of one of the at least two second parts in the direction of the third party is less than the width of one of the at least two first parts in the direction of the third party.

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