Light emitting display device

Abstract

A light emitting display device includes a substrate configured to include a display area having a plurality of pixel areas, and a non-display area surrounding the display area, and a planarization layer disposed at the display area and partially disposed at the non-display area. The planarization layer is configured to include an uneven pattern portion disposed at the non-display area, and the uneven pattern portion is configured to include a plurality of recesses.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2020-0111580, filed on September 2, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to light-emitting display devices. Background Technology

[0004] Emitting-light displays are self-emissive display devices, and unlike liquid crystal displays, they do not require an additional light source, allowing them to be manufactured in a compact and slim form. Furthermore, emitting-light displays are advantageous in terms of power consumption due to their low-voltage operation, and they also excel in color reproduction, response speed, viewing angle, and contrast. Therefore, emitting-light displays have been researched as the next generation of displays.

[0005] The light-emitting display device displays images by emitting light from a light-emitting part, which includes a light-emitting device layer inserted between two electrodes.

[0006] The light-emitting display device includes a display panel comprising a display area having a plurality of pixels for displaying images and a non-display area surrounding the display area. The light-emitting display device also includes a black edge pattern disposed along the edge of the screen (or front surface) of the display panel to prevent external light from being reflected by a metallic layer disposed in the non-display area.

[0007] Emitting light displays have issues related to color difference (or difference in color impression) between the display area and a black edge pattern set at the edge of the display panel. For example, when the emitting light display is off (or not driven), the screen edge of the display panel appears black due to the black edge pattern caused by the reflection of external light, while the display area appears non-black due to the reflection of external light. Therefore, there may be a difference in color impression between the display area and the edge of the display panel. Summary of the Invention

[0008] The inventors of this disclosure have recognized the aforementioned problems and have conducted various experiments to reduce or minimize color difference (or difference in color impression) between the display area and the edge of the display panel. Through these experiments, the inventors have invented a light-emitting display device with a novel structure that can prevent or minimize color difference (or difference in color impression) between the display area and the non-display area of ​​the display panel.

[0009] Therefore, this disclosure aims to provide a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0010] One aspect of this disclosure is to provide a light-emitting display device that minimizes or prevents color difference (or difference in color impression) between the display area and the non-display area of ​​a display panel.

[0011] One aspect of this disclosure is to provide a light-emitting display device that can minimize or prevent color difference (or difference in color impression) between the display area and the non-display area of ​​a display panel by increasing the light extraction efficiency in the pixels.

[0012] To achieve these and other aspects of the inventive concept, as specifically embodied and broadly described herein, the light-emitting display device includes: a substrate configured to include a display area having a plurality of pixel areas and a non-display area surrounding the display area; and a planarization layer disposed in the display area and partially disposed in the non-display area, the planarization layer being configured to include an uneven pattern portion disposed in the non-display area, and the uneven pattern portion being configured to include a plurality of recesses. The uneven pattern portion may include a plurality of recesses and protrusions disposed between the plurality of recesses. The uneven pattern portion may include a wavy pattern. The non-display area may include pad areas. The planarization layer may be disposed in the remaining non-display area of ​​the non-display area excluding the pad areas. The planarization layer may be disposed only partially in the non-display area. In other words, the planarization layer may not be completely disposed in the non-display area. A portion of the non-display area may not overlap with the planarization layer. The non-display area may include pad areas and the planarization layer may not be disposed in the pad areas.

[0013] In another aspect, a light-emitting display device includes: a substrate configured to include a display area having a plurality of pixel areas and a non-display area surrounding the display area; a pixel circuit portion at the display area of ​​the substrate; a peripheral circuit portion at the non-display area of ​​the substrate; a planarization layer at the pixel circuit portion and the peripheral circuit portion; and a light-emitting portion above the planarization layer at each of the plurality of pixel areas, wherein the planarization layer at the peripheral circuit portion includes an uneven pattern portion, and the uneven pattern portion is configured to include a plurality of recesses.

[0014] In another aspect, a light-emitting display device includes: a substrate configured to include a display area having a plurality of pixel areas and a non-display area surrounding the display area; and a planarization layer disposed in the display area and partially disposed in the non-display area, the planarization layer including a plurality of recesses. The non-display area may include pad areas. The planarization layer may be disposed in the remaining non-display areas of the non-display area. The planarization layer may be partially disposed in the non-display area, and / or the planarization layer may not be disposed in the pad areas. The planarization layer may include protrusions disposed on a surface between the plurality of recesses. The planarization layer may have a wavy shape.

[0015] According to embodiments of this disclosure, color difference between the display area and the non-display area of ​​a display panel can be minimized or prevented.

[0016] Furthermore, according to embodiments of this disclosure, the light extraction efficiency of pixels can be improved, and color difference between the display area and the non-display area of ​​the display panel can be minimized or prevented. Attached Figure Description

[0017] This invention includes accompanying drawings to provide a further understanding of the present disclosure, and the drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0018] Figure 1 An embodiment of a light-emitting display device according to the present disclosure is shown.

[0019] Figure 2 yes Figure 1 The equivalent circuit diagram of the pixel shown.

[0020] Figure 3 This is a cross-sectional view showing the cross-sectional structure of a pixel according to an embodiment of the present disclosure.

[0021] Figure 4 It shows Figure 3 The planar structure of the light extraction pattern shown.

[0022] Figure 5 It is along Figure 1 The cross-sectional view taken from I-I'.

[0023] Figure 6 It is along Figure 1 The cross-sectional view taken from section II-II'.

[0024] Figure 7 It is along Figure 1 The cross-sectional view taken from section III-III'.

[0025] Figure 8 A planarization layer according to another embodiment of this disclosure is shown.

[0026] Figure 9 It shows Figure 8 The cross-sectional structure of the uneven pattern portion and the first to third uneven pattern portions shown.

[0027] Figure 10 A planarization layer according to another embodiment of this disclosure is shown.

[0028] Figure 11 It is along Figure 10 A cross-sectional view taken from IV-IV'.

[0029] Figure 12 It is along Figure 10 The cross-sectional view taken from V-V'.

[0030] Figure 13 A light-emitting display device according to another embodiment of the present disclosure is shown.

[0031] Figure 14 It is along Figure 13 A schematic cross-sectional view of section VI-VI'.

[0032] Figure 15A The color difference (or difference in color impression) between the non-display area and the display area in a light-emitting display device of the related technology is shown.

[0033] Figure 15B The color difference (or difference in color impression) between the non-display area and the display area in an embodiment of the present disclosure is shown. Detailed Implementation

[0034] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following description of embodiments with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0035] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the details shown. The same reference numerals always refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the essential points of this disclosure. Where the terms “comprising,” “having,” and “including” are used as described in this specification, an additional part may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0036] When interpreting an element, the element is interpreted as including a range of errors or tolerances, even though there is no explicit description of such a range of errors or tolerances.

[0037] When describing positional relationships, for example, when the positional relationship between two parts is described as “above,” “over,” “below,” and “adjacent,” one or more other parts may be placed between the two parts, unless more restrictive terms such as “immediately adjacent” or “directly” are used.

[0038] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, "at least one or more of the first element, the second element, and the third element" means a combination of all elements derived from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0039] Features of various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other in various ways and be technically driven, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be carried out independently of each other or together in a mutually dependent manner.

[0040] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Since the scale of each element shown in the drawings differs from the actual scale for ease of description, embodiments of the present disclosure are not limited to the scale shown. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0041] Figure 1 An embodiment of a light-emitting display device according to the present disclosure is shown.

[0042] Reference Figure 1 The light-emitting display device according to the embodiments of the present disclosure may include a display panel 10 and a panel driving circuit section 30.

[0043] The display panel 10 may include a substrate 100 and an opposing substrate 300 that are bonded to each other.

[0044] The substrate 100 includes a thin-film transistor, and the substrate 100 may be a transistor array substrate, a lower substrate, a base substrate, or a first substrate. The substrate 100 may be a transparent glass substrate or a transparent plastic substrate. For example, the substrate 100 may be a transparent glass substrate.

[0045] The substrate 100 according to embodiments of the present disclosure may include a display area AA and a non-display area IA.

[0046] The display area AA is the area used to display images. The display area AA can be a pixel array area, an active area, a display area, or a screen. For example, the display area AA can be set in the central area of ​​the display panel 10.

[0047] The display area AA according to embodiments of this disclosure may include gate lines, data lines, pixel driving power lines, and a plurality of pixels P. Each of the plurality of pixels P may be disposed at each pixel area defined by the gate lines and the data lines.

[0048] Each of the multiple pixels P can be defined as the smallest unit area that actually emits light.

[0049] According to embodiments of this disclosure, in a plurality of pixels P, three pixels arranged adjacently or along the length direction of a gate line (or data line) constitute a unit pixel. A unit pixel may include at least one red pixel, at least one green pixel, and at least one blue pixel, but embodiments of this disclosure are not limited thereto. For example, each of the at least one red pixel, at least one green pixel, and at least one blue pixel may be a sub-pixel.

[0050] According to another embodiment of this disclosure, in a plurality of pixels P, four pixels arranged adjacently or along the length direction of a gate line (or data line) constitute a unit pixel. The unit pixel may include a red pixel, a green pixel, a blue pixel, and a white pixel, but the embodiments of this disclosure are not limited thereto. As one embodiment, the unit pixel may include at least one red pixel, at least one green pixel, at least one blue pixel, and at least one white pixel.

[0051] Each of the plurality of pixels P may include pixel circuitry and a light-emitting portion connected to the pixel circuitry. The light-emitting portion may include a light-emitting device layer inserted between a first electrode and a second electrode.

[0052] The light-emitting device layers disposed at each of the plurality of pixels P can individually emit light of different colors or can collectively emit white light. According to embodiments of this disclosure, if the plurality of pixels P collectively emit white light, each of the red, green, and blue pixels may include a color filter (or wavelength conversion member or wavelength conversion layer) that converts white light into other colors. In this case, the color filter according to embodiments of this disclosure may not be included in the white pixel. At least a portion of the white pixel according to another embodiment of this disclosure may include a color filter whose color is the same as any one of the red, green, and blue pixels.

[0053] The non-display area IA is the area where no image is displayed. The non-display area IA can be a peripheral circuit area, a signal supply area, a non-active area, or a border area. The non-display area IA can surround the display area AA.

[0054] The non-display area IA can be disposed on the periphery of the display panel 10. According to embodiments of this disclosure, the non-display area IA may include a first non-display area to a fourth non-display area IA1, IA2, IA3, and IA4 disposed on the periphery of the substrate 100. For example, the non-display area IA may include a first non-display area IA1 disposed on or adjacent to a first side of the display area AA, a second non-display area IA2 disposed on or adjacent to a second side of the display area AA, a third non-display area IA3 disposed on or adjacent to a third side of the display area AA, and a fourth non-display area IA4 disposed on or adjacent to a fourth side of the display area AA. For example, each of the first non-display area IA1 and the fourth non-display area IA4 may be parallel to a first direction X, and each of the second non-display area IA2 and the third non-display area IA3 may be parallel to a second direction Y perpendicular to the first direction X.

[0055] Any of the first to fourth non-display areas included in the non-display area IA may include a pad area. The pad area may be located at one or more of the first to fourth non-display areas IA1, IA2, IA3, and IA4 included in the non-display area IA exposed to the outside, without overlapping (or being covered by) the opposing substrate 300. For example, the pad area may be located at the first non-display area IA1.

[0056] The display panel 10 or the substrate 100 may also include a peripheral circuit section 50 disposed in the non-display area IA.

[0057] The peripheral circuit section 50 (or panel embedded circuit section) may include a plurality of pad sections 51 and a plurality of link sections 53 disposed in the first non-display area IA1, a first gate drive circuit 55 disposed in the second non-display area IA2, and a second gate drive circuit 57 disposed in the third non-display area IA3.

[0058] Multiple pad portions 51 may be disposed in the pad area of ​​the first non-display area IA1 and spaced apart from each other along the first direction X.

[0059] Each of the plurality of pad portions 51 according to embodiments of the present disclosure may include a plurality of data pads, at least one pixel drive power pad, and a plurality of common power pads. A first pad portion of the plurality of pad portions 51 connected to a first data line may further include a plurality of gate pads. Furthermore, a last pad portion of the plurality of pad portions 51 connected to the last data line may further include a plurality of gate pads.

[0060] Each of the plurality of data pads can receive data signals provided from the panel driving circuit section 30. Each of the plurality of data pads can receive gate control signals and gate circuit drive power provided from the panel driving circuit section 30. For example, the gate control signal may include at least one gate enable signal and a plurality of gate clocks. For example, the gate circuit drive power may include high-level power and low-level power.

[0061] At least one pixel driving power pad can receive pixel driving power supplied from the panel driving circuit section 30. Each of the plurality of common power pads can receive pixel common power supplied from the panel driving circuit section 30.

[0062] Each of the plurality of link portions 53 may be disposed in a link area between the pad area of ​​the first non-display area IA1 and the first side of the display area AA. The plurality of link portions 53 may be disposed in the link area of ​​the first non-display area IA1 and spaced apart from each other along the first direction X.

[0063] Each of the multiple connection units 53 may include multiple data link lines. The multiple data link lines may connect multiple data pads and multiple data lines in a one-to-one relationship.

[0064] The first gate driving circuit 55 can be located at the second non-display area IA2. The second gate driving circuit 57 can be located at the third non-display area IA3.

[0065] According to embodiments of this disclosure, the first gate driving circuit 55 can be electrically connected to each of the plurality of gate lines disposed in the display area AA, and the second gate driving circuit 57 can be electrically connected to each of the gate lines disposed in the display area AA. For example, the first gate driving circuit 55 can be connected to one side of each gate line, and the second gate driving circuit 57 can be connected to the other side of each gate line.

[0066] According to another embodiment of this disclosure, the first gate driving circuit 55 can be electrically connected to each of the odd (or even) gate lines among the plurality of gate lines disposed in the display area AA, and the second gate driving circuit 57 can be electrically connected to each of the even (or odd) gate lines among the plurality of gate lines disposed in the display area AA. For example, the second gate driving circuit 55 can be connected to one side of each of the odd-numbered gate lines, and the second gate driving circuit 57 can be connected to the other side of each of the even-numbered gate lines.

[0067] The first gate drive circuit 55 can output a sequentially offset gate signal based on a gate control signal provided by a first gate control signal line 54 connected to the first pad of the plurality of pads 51 and gate circuit drive power. The second gate drive circuit 57 can output a sequentially offset gate signal based on a gate control signal provided by a second gate control signal line 56 connected to the last pad of the plurality of pads 51 and gate circuit drive power.

[0068] Each of the first gate drive circuit 55 and the second gate drive circuit 57 can be implemented in a shift register comprising multiple stages integrated into a non-display area 1A of the substrate 100 according to the thin-film transistor manufacturing process. The multiple stages can be interdependently connected and sequentially driven according to a gate start signal of a gate control signal, at least one gate clock, and gate circuit drive power, so that the multiple stages can sequentially output gate signals (or gate pulses) corresponding to the gate clock signal.

[0069] The peripheral circuit section 50 may also include a plurality of common electrode contacts 58 disposed at the first non-display area IA1.

[0070] Multiple common electrode contacts 58 may be disposed between multiple connecting portions 53. Each of the multiple common electrode contacts 58 may be disposed between two adjacent connecting portions 53 along a first direction X. Each of the multiple common electrode contacts 58 may provide common pixel power supplied through multiple common power pads to a second electrode of each of the multiple pixels. For example, a second electrode disposed in display area AA and commonly connected to each of the multiple pixels P may include an extension extending toward a first non-display area IA, and the extension of the second electrode may overlap at least a portion or all of each of the multiple common electrode contacts 58.

[0071] The peripheral circuit section 50 may also include a test circuit section 59 disposed at the fourth non-display area IA4.

[0072] The test circuit section 59 provides a switch control signal and a test data signal from the test device via a test pad provided at the first non-display area IA1 or the fourth non-display area IA4 to the data line. For example, the test data signal may be a data signal used for pixel illumination testing, but embodiments of this disclosure are not limited thereto.

[0073] The test circuit section 59 according to embodiments of this disclosure may include multiple transistors, switch control lines, and multiple signal supply lines.

[0074] Multiple transistors may include a gate electrode, a first source / drain electrode, and a second source / drain electrode. For example, the first source / drain electrode of each of the multiple transistors may be connected to a data line in a one-to-one relationship.

[0075] Multiple transistors can be grouped into multiple groups. For example, the multiple transistors can be divided into groups one through three or groups one through four. For example, the transistors included in the first group can be connected to the data line connected to the red pixel, the transistors included in the second group can be connected to the data line connected to the green pixel, and the transistors included in the third group can be connected to the data line connected to the blue pixel. In addition, the transistors included in the fourth group can be connected to the data line connected to the white pixel.

[0076] The switch control line can be connected to each gate electrode of multiple transistors.

[0077] Multiple signal supply lines can be connected to transistors in each of the first to third groups of multiple transistors.

[0078] The first signal supply line in a plurality of signal supply lines can be connected to the second source / drain electrodes of the respective transistors included in the first group of transistors. The first signal supply line can provide a first test data signal to the transistors included in the first group.

[0079] The second signal supply line in the multiple signal supply lines can be connected to each of the second source / drain electrodes of the transistors included in the second group of transistors. The second signal supply line can provide a second test data signal to the transistors included in the second group.

[0080] The third signal supply line in a set of multiple signal supply lines can be connected to each of the second source / drain electrodes of the transistors included in the third group of multiple transistors. The third signal supply line can provide a third test data signal to the transistors included in the third group.

[0081] Additionally, the fourth signal supply line among the multiple signal supply lines can be connected to each of the second source / drain electrodes of the transistors included in the fourth group of transistors. The fourth signal supply line can provide a fourth test data signal to the transistors included in the fourth group.

[0082] The peripheral circuit section 50 may also include at least one power sharing line PSL disposed in the fourth non-display area IA4 (see Figure 7 ) and multiple metallic patterns MP (see Figure 7 ).

[0083] At least one power sharing line (PSL) can be located at the fourth non-display area IA4, parallel to the first direction X, and can be connected to the end of the pixel driving power line located at the display area AA. At least one power sharing line (PSL) can receive pixel driving power from at least one pixel driving power pad located at the first non-display area IA1 through the second non-display area IA2 and / or the third non-display area IA3, and can jointly provide pixel driving power to the pixel driving power line. In this case, pixel driving power can be simultaneously provided to both ends of each of the pixel driving power lines, thereby minimizing the voltage drop of the pixel driving power in each of the pixel driving power lines.

[0084] Multiple metal patterns MP can be disposed on the substrate 100 of the fourth non-display area IA4, overlapping with at least one power sharing line PSL. For example, the multiple metal patterns MP can be arranged in at least one row (or column) to be spaced apart from each other along the first direction X. At least one of the multiple metal patterns MP can be electrically connected to at least one power sharing line PSL, thereby reducing the line resistance of at least one power sharing line PSL.

[0085] The display panel 10 or substrate 100 may also include a planarization layer disposed in the display area AA and the non-display area IA, excluding the pad area of ​​the non-display area IA.

[0086] The planarization layer may include uneven patterned portions. For example, the planarization layer according to an embodiment of the present disclosure may include uneven patterned portions disposed on the portion of the non-display area IA other than the pad area of ​​the non-display area IA. The uneven patterned portions may not be disposed on the pad area.

[0087] The uneven pattern portion may include a plurality of recesses recessed from the surface of the planarization layer. The uneven pattern portion may also include a plurality of protrusions disposed between each of the recesses. For example, the plurality of protrusions are disposed protrudingly between each of the recesses. The uneven pattern portion disposed at the non-display area IA can scatter external light incident through the substrate 100. Some of the light scattered by the uneven pattern portion can be emitted to the outside through the substrate 100 to fog (or blur) the non-display area IA, thereby reducing or minimizing the color difference (or difference in color impression) between the non-display area IA and the display area AA caused by external light reflection. For example, when the display panel 10 is off or a black image is displayed on the display panel 10, the uneven pattern portion can reduce or minimize the color difference (or difference in color impression) between the non-display area IA and the display area AA caused by external light reflection from the peripheral circuit portion 50 disposed at the non-display area IA. This will be described in detail later.

[0088] The opposing substrate 300 can be bonded to the substrate 100 using an adhesive component (or a transparent adhesive). For example, the opposing substrate 300 is relatively smaller than the substrate 100, thereby allowing the opposing substrate 300 to be bonded to the remaining area of ​​the substrate 100 except for the pad portion 51. The opposing substrate 300 can be an upper substrate, a second substrate, or a package substrate. The opposing substrate 300 can be bonded to the first surface of the substrate 100 using a substrate bonding process using an adhesive component.

[0089] The panel driving circuit section 30 (or the panel external circuit section) can be connected to the pad section 51 of the display panel 10. The panel driving circuit section 30 drives (or emits light) multiple pixels P set on the display area AA based on video data provided from the host driving system, thereby displaying an image corresponding to the video data in the display area AA.

[0090] The panel driving circuit section 30 according to the embodiments of the present disclosure may include a plurality of flexible circuit films 31, a plurality of data driving integrated circuits 33, a printed circuit board 35, a timing controller 37, and a power circuit section 39.

[0091] One side (or input junction) of each of the plurality of flexible circuit films 31 can be attached to the printed circuit board 35 using a film attachment process employing an anisotropic conductive film. The other side (or output junction) of each of the plurality of flexible circuit films 31 can be attached to the pad portion 51 of the substrate 100 using a film attachment process employing anisotropic conductive film. Each of the plurality of flexible circuit films 31 can be bent or folded toward the rear surface of the opposing substrate 300 to surround a side surface of the opposing substrate 300. For example, one side of each of the plurality of flexible circuit films 31 can be disposed on the rear surface of the opposing substrate 300.

[0092] Each of the plurality of data-driven integrated circuits 33 can be individually mounted at each of the plurality of flexible circuit films 31. The plurality of data-driven integrated circuits 33 can receive pixel data and data control signals from the timing controller 37, convert the pixel data into an analog data signal for each pixel according to the data control signals, and provide the analog data signal for each pixel to a corresponding data line. For example, the flexible circuit film 31 and the data-driven integrated circuits 33 can be referred to as a data-driven circuit, but the embodiments of this disclosure are not limited thereto.

[0093] The printed circuit board 35 can support the timing controller 37 and the power circuit section 39, and can transmit signals and power between the components of the panel drive circuit section 30. For example, the printed circuit board 35 can be disposed on the rear surface of the opposing substrate 300.

[0094] The timing controller 37 is mounted on the printed circuit board 35 and can receive video data and timing synchronization signals from the host drive system via a user connector located on the printed circuit board 35. The timing controller 37 can generate pixel data by aligning the video data to a pixel arrangement suitable for the display area AA based on the timing synchronization signals, and can provide the generated pixel data to the corresponding data driver integrated circuit 33. Furthermore, the timing controller 37 can generate each of a data control signal and a gate control signal based on the timing synchronization signals. The data control signals can control the driving timing of each of the plurality of data driver integrated circuits 33, and the gate control signals can control the driving timing of the first gate drive circuit 55 and the second gate drive circuit 57.

[0095] The power circuit section 39 is mounted on the printed circuit board 35. The power circuit section 39 can generate various voltages for displaying images on the display panel 10 by using externally supplied input power, and can provide the generated voltages to the corresponding circuits.

[0096] Figure 2 This is an explanation Figure 1 The equivalent circuit diagram of the pixel shown is shown.

[0097] Reference Figure 2 According to the embodiments of this disclosure, the pixel P includes a pixel circuit PC and a light-emitting part EP.

[0098] The pixel circuit PC may include a first switching thin-film transistor Tsw1, a second switching thin-film transistor Tsw2, a driving thin-film transistor Tdr, and a capacitor Cst. The thin-film transistors Tsw1, Tsw2, and Tdr may be N-type thin-film transistors (TFTs), but the embodiments of this disclosure are not limited thereto.

[0099] In one implementation, at least one of the first switching thin-film transistor Tswl, the second switching thin-film transistor Tsw2, or the driving thin-film transistor Tdr may include a semiconductor layer (or activation layer) based on any one of amorphous silicon, polycrystalline silicon, oxide, and organic materials.

[0100] In another embodiment, some of the thin-film transistors, including the first switching thin-film transistor Tswl, the second switching thin-film transistor Tsw2, and the driving thin-film transistor Tdr, may include a semiconductor layer based on a low-temperature polycrystalline silicon (poly-Si) material with good response characteristics, and the remaining thin-film transistors may include a thin-film transistor based on a semiconductor layer of an oxide material with good cutoff current characteristics.

[0101] The first switching thin-film transistor Tsw1 may include a gate electrode connected to a first gate line GLa connected to a gate line GL, a first source / drain electrode connected to a closed data line DL, and a second source / drain electrode connected to a first node n1 corresponding to the gate electrode of the driving thin-film transistor Tdr. The first switching thin-film transistor Tsw1 may provide a data voltage to the first node n1 corresponding to the gate electrode of the driving thin-film transistor Tdr, the data voltage being provided to the data line DL according to a first gate signal GSa having a gate on-voltage level provided to the first gate line GLa.

[0102] The second switching thin-film transistor Tsw2 may include a gate electrode connected to a second gate line GLb connected to a gate line GL, a first source / drain electrode connected to a closed reference line RL, and a second source / drain electrode connected to a second node n2 corresponding to the source electrode of the driving thin-film transistor Tdr. The second switching thin-film transistor Tsw2 may provide a reference voltage Vref to the second node (n2), i.e., the source electrode of the driving thin-film transistor Tdr, which is provided to the reference line RL according to a second gate signal GSb having a gate on-voltage level provided to the second gate line GLb.

[0103] A capacitor Cst can be disposed between the gate electrode and the source electrode of the driving thin-film transistor Tdr. According to embodiments of this disclosure, the capacitor Cst may include a first capacitor electrode composed of the gate electrode of the driving thin-film transistor Tdr, a second capacitor electrode composed of the source electrode of the driving thin-film transistor Tdr, and a dielectric layer disposed in the overlapping region between the first and second capacitor electrodes. A differential voltage can be applied to the capacitor Cst between the gate electrode and the source electrode of the driving thin-film transistor Tdr, and then the driving thin-film transistor Tdr can be switched according to the applied voltage.

[0104] The driving thin-film transistor Tdr may include a gate electrode that is connected together with the second source / drain electrode of the first switching thin-film transistor Tsw1 and the first capacitor electrode of the capacitor Cst; a source electrode that is connected together with the first source / drain electrode of the second switching thin-film transistor Tsw2, the second capacitor electrode of the capacitor Cst, and the light-emitting part EP; and a drain electrode that is connected to the pixel driving power line PL. The driving thin-film transistor Tdr can control the amount of current flowing from the pixel driving power line PL to the light-emitting part EP by turning on the voltage of the capacitor Cst.

[0105] The light-emitting part EP can emit light proportionally to the driving force of the pixel circuit PC and the data current flowing from the pixel driving power line PL to the low potential power supply VSS.

[0106] The light-emitting part EP according to the embodiments of this disclosure may include a first electrode, a light-emitting device layer, and a second electrode. For example, the light-emitting part EP may be a self-emissive part, a light-emitting part, or a point light source, but the embodiments of this disclosure are not limited thereto.

[0107] The first electrode can be electrically connected to the source electrode of the driving thin-film transistor Tdr of the pixel circuit PC. The first electrode can be an anode electrode, a pixel electrode, or a transparent electrode, but the embodiments of this disclosure are not limited thereto.

[0108] A light-emitting device layer can be disposed above the first electrode. According to embodiments of this disclosure, the light-emitting device layer can be individually disposed at each of a plurality of pixels. In this case, the light-emitting device layer of each pixel can emit light of a different color. Alternatively, a light-emitting device layer according to another embodiment of this disclosure can be shared for multiple pixels. In this case, the light-emitting device layer in each pixel can emit the same white light.

[0109] The light-emitting device layer according to the embodiments of this disclosure may be an organic light-emitting layer, a quantum dot light-emitting layer, or an inorganic light-emitting layer, but the embodiments of this disclosure are not limited thereto. For example, the light-emitting device layer may include a hole functional layer disposed at the first electrode, an organic light-emitting layer disposed at the hole functional layer, and an electronic functional layer disposed at the organic light-emitting layer.

[0110] The second electrode can be disposed on the light-emitting device layer. The second electrode can be connected to multiple pixels, but the embodiments of this disclosure are not limited thereto. For example, the second electrode can be a cathode electrode, a common electrode, or a reflective electrode, but the embodiments of this disclosure are not limited thereto.

[0111] The reference line RL can be used as a sensing line for sensing changes in the characteristics of the thin-film transistor Tdr and / or the characteristics of the light-emitting device layer from an external sensing driving mode for pixel P. For example, the external sensing driving mode and external compensation method based on the structure of pixel P according to embodiments of this disclosure are substantially the same as the sensing modes and external compensation methods disclosed in Korean Patent Publications Nos. 10-2016-0093179, 10-2017-0054654, or 10-2018-0002099, all of which are incorporated herein by reference. Detailed descriptions of the relevant information are omitted.

[0112] In the above embodiments of the present invention, the pixel circuit PC includes three transistors and one capacitor. However, the number of transistors and capacitors constituting the pixel circuit PC can be varied.

[0113] Figure 3 This is a cross-sectional view showing the cross-sectional structure of a pixel according to an embodiment of the present disclosure. Figure 4 It shows Figure 3 The planar structure of the light extraction pattern shown.

[0114] Reference Figure 3 and Figure 4 The light-emitting display panel 10 (or light-emitting display device) according to the embodiments of the present disclosure may include a substrate 100 and a counter substrate 300.

[0115] The substrate 100 can typically be formed of a glass material, but embodiments of the present disclosure are not limited thereto. The substrate 100 can also be formed of a flexible or foldable transparent plastic material, such as polyimide.

[0116] The substrate 100 may include a plurality of pixel regions PA defined in the display area AA.

[0117] Each of the plurality of pixel regions PA may include a circuit region CA and a light-emitting region EA. The circuit region CA may be spatially separated from the light-emitting region EA within the pixel region PA. The light-emitting region EA may be defined as the remainder of the pixel region PA excluding the circuit region CA. For example, the circuit region CA may be a non-light-emitting region or a non-aperture region. For example, the light-emitting region EA may be an aperture region.

[0118] The substrate 100 according to the embodiments of the present disclosure may include a buffer layer 110, a pixel circuit section, a protective layer 130, a planarization layer 170, and a light-emitting section EP.

[0119] The buffer layer 110 may be disposed over the entire area of ​​the first surface (or front surface) 100a of the substrate 100. The buffer layer 110 may prevent materials contained in the substrate 100 from diffusing into the transistor layer during high-temperature steps of the manufacturing process of the thin-film transistor, or it may prevent external water or moisture from penetrating into the emitter device. According to some embodiments of this disclosure, the buffer layer 110 may be optionally omitted.

[0120] The pixel circuit section may include a driving thin-film transistor Tdr disposed at the circuit region CA of the pixel region PA.

[0121] The driving thin-film transistor Tdr according to the embodiments of the present disclosure may include an active layer 111, a gate insulating film 113, a gate electrode 115, an insulating intermediate layer 117, a drain electrode 119d, and a source electrode 119s.

[0122] The active layer 111 may include a channel region 111c, a drain region 111d, and a source region 111s disposed in the driving thin-film transistor region of the circuit region CA. The drain region 111d and the source region 111s may be spaced apart from each other in parallel, and the channel region 111c is inserted between the drain region 111d and the source region 111s.

[0123] The active layer 111 can be formed from a semiconductor material based on any one of amorphous silicon, polycrystalline silicon, oxide and organic materials.

[0124] The gate insulating film 113 can be disposed on the channel region 111c of the active layer 111. For example, the gate insulating film 113 can be disposed in an island shape only on the channel region 111c of the active layer 111, or it can be disposed on the entire surface of the buffer layer 110 or the substrate 100 including the active layer 111.

[0125] The gate electrode 115 can be disposed on the gate insulating film 113 and overlap with the channel region 111c of the active layer 111.

[0126] An insulating intermediate layer 117 can be disposed on the gate electrode 115 and the drain region 111d and source region 111s of the active layer 111. The insulating intermediate layer 117 can be disposed over the entire area of ​​the light-emitting region EA and the circuit region CA. For example, the insulating intermediate layer 117 can be formed of inorganic or organic materials.

[0127] The drain electrode 119d can be electrically connected to the drain region 111d of the active layer 111 via a drain contact hole formed in the insulating intermediate layer 117 that overlaps with the drain region 111d of the active layer 111.

[0128] The source electrode 119s can be electrically connected to the source region 111s of the active layer 111 via a source contact hole formed in the insulating intermediate layer 117 that overlaps with the source region 111s of the active layer 111.

[0129] The drain electrode 119d and the source electrode 111s can be formed of the same metallic material. For example, each of the drain electrode 119d and the source electrode 111s can be formed as a single-layer structure of the same or different metallic material as the gate electrode, a single-layer structure of an alloy of the same or different metallic material as the gate electrode, or a double-layer structure of the same or different metallic material as the gate electrode.

[0130] Additionally, the pixel circuit section may also include a capacitor and a first switching thin-film transistor and a second switching thin-film transistor disposed together with the driving thin-film transistor Tdr in the circuit region CA. Each of the first and second switching thin-film transistors is fabricated in the circuit region CA of the pixel region PA, wherein each of the first and second switching thin-film transistors is implemented with the same structure as the driving thin-film transistor Tdr. A repeated description of this structure will be omitted. The capacitor may be fabricated in the overlapping region between the overlapping gate electrode GE and the overlapping source electrode SE, with an insulating interlayer 117 inserted between the gate electrode GE and the source electrode SE, and the gate electrode GE and the source electrode SE are included in the driving thin-film transistor Tdr.

[0131] Furthermore, the thin-film transistors fabricated in the pixel circuit section may have characteristics related to the shift of the threshold voltage with light. To prevent this phenomenon, the display panel or the first substrate 100 may also include a light-shielding layer 101 disposed below the active layer 111 of at least one of the driving thin-film transistor Tdr, the first switching thin-film transistor, or the second switching thin-film transistor. The light-shielding layer 101 is fabricated between the substrate 100 and the active layer 111, and the light-shielding layer 101 prevents light from passing through the substrate 100 and incident on the active layer 111, thereby minimizing the change in the threshold voltage in the transistor caused by external light.

[0132] A protective layer 130 may be formed over the substrate 100 to cover (or coat) the pixel circuit portion. The protective layer 130 covers (or coats) the drain electrode 119d of the driving thin-film transistor Tdr, the source electrode 119s of the driving thin-film transistor Tdr, and the insulating intermediate layer 117. The protective layer 130 may be disposed over the entire area of ​​the pixel region CA and the light-emitting region EA. For example, the protective layer 130 may be referred to as a passivation layer. According to some embodiments of this disclosure, the protective layer 130 may be optionally omitted.

[0133] A planarization layer 170 can be disposed above the substrate 100 to cover (or coat) the protective layer 130. When the protective layer 130 is omitted, the planarization layer 170 can be formed above the substrate 100 to cover (or coat) the pixel circuit area. The planarization layer 170 can be disposed over the entire area of ​​the circuit region CA and the light-emitting region EA. Furthermore, the planarization layer 170 can be disposed over the entire display area and the remaining portion of the non-display area, excluding the pad area. For example, the planarization layer 170 may include an extension (or expansion) extending from the display area to the remaining portion of the non-display area, excluding the pad area. Therefore, the planarization layer 170 can have a relatively large size compared to the display area. For example, the planarization layer 170 can be disposed at the display area AA and partially disposed in the non-display area. The planarization layer 170 can be disposed in the remaining non-display area of ​​the non-display area, excluding the pad area.

[0134] The planarization layer 170 according to embodiments of this disclosure has a relatively large thickness, such that the planarization layer 170 can provide a planarized surface in the display area AA. For example, the planarization layer 170 can be formed of organic materials such as photopolymer acrylic, benzocyclobutene, polyimide, and fluoropolymers, but embodiments of this disclosure are not limited thereto.

[0135] The planarization layer 170 may include a light extraction pattern 180 disposed at the pixel region PA. The light extraction pattern 180 may be disposed on the upper surface 170a of the planarization layer 170, overlapping with the light-emitting region EA of the pixel region PA. The light extraction pattern 180 is disposed on the planarization layer 170 of the light-emitting region EA with a curved (or uneven) shape, thereby changing the travel path of light emitted from the light-emitting device layer EDL to increase the light extraction efficiency of pixel P. Compared with the light-emitting region EA of the pixel region PA, the light extraction pattern 180 may have a relatively large size. For example, the light extraction pattern 180 may be an uneven pattern portion, a microlens, a light scattering pattern, a fine structure, an optical path controller, a microlens portion, or a microlens array portion, but the embodiments of this disclosure are not limited thereto.

[0136] According to embodiments of the present disclosure, the light extraction pattern 180 may be disposed on the planarization layer 170 overlapping with at least one light-emitting region EA of a plurality of pixels P constituting a unit pixel. As one embodiment, the light extraction pattern 180 may be disposed on the planarization layer 170 overlapping with the light-emitting regions EA of green and / or blue pixels included in a unit pixel, based on the luminous efficiency, external light extraction efficiency, and brightness of each of the plurality of pixels P constituting a unit pixel; however, embodiments of the present disclosure are not limited thereto. As another embodiment, the light extraction pattern 180 may be disposed on the planarization layer 170 overlapping with the light-emitting region EA of white pixels among the plurality of pixels P constituting a unit pixel, or it may be disposed on the planarization layer 170 overlapping with at least one light-emitting region EA of green, blue, and white pixels included in a unit pixel; however, embodiments of the present disclosure are not limited thereto.

[0137] The light extraction pattern 180 according to embodiments of this disclosure may include a plurality of recesses 181 and protrusions 183 disposed between the plurality of recesses 181. For example, the recesses 181 may be recesses, depressions, valleys, or grooves. The protrusions 183 may be convex, ridges, or embossed portions.

[0138] Each of the plurality of recesses 181 can be configured to be recessed from the upper surface 170a of the planarization layer 170. Each of the plurality of recesses 181 can have the same depth relative to the upper surface 170a of the planarization layer 170. However, some of the plurality of recesses 181 may have different depths due to errors or tolerances in the patterning process of the light extraction pattern 180.

[0139] Multiple recesses 181 can be arranged in parallel with a zigzag pattern along the second direction Y, while being spaced apart from each other along the first direction X. For example, the multiple recesses 181 can be arranged in a grid shape with constant intervals, and adjacent recesses 181 can be alternately arranged along the second direction Y. Three adjacent recesses 181 can be arranged in a two-dimensional triangle shape, and the line segments between the centers of the three adjacent recesses 181 can form a two-dimensional triangle shape TS. Furthermore, multiple recesses 181 can each be surrounded by six recesses 181 arranged around them. In this case, the six recesses 181 arranged to surround one recess 181 can be arranged in a two-dimensional hexagon shape HS, and the line segments between the centers of the six recesses 181 arranged to surround one recess 181 can form a two-dimensional hexagon shape HS. For example, the protrusion 183 and the multiple recesses 181 can be arranged in a two-dimensional honeycomb shape or a hexagonal shape.

[0140] The spacing (or interval) between the recesses 181 arranged in a plurality of pixels P constituting a unit pixel can be the same or different from each other. In this paper, the spacing between the recesses 181 can be the distance (or interval) between the center points of two adjacent recesses 181.

[0141] As one implementation, the spacing between the recesses 181 provided at the red, green, and blue pixels constituting a unit pixel can be the same or different from each other. For example, the spacing between the recesses 181 provided at the green pixel can be different from the spacing between the recesses 181 provided at the blue pixel.

[0142] In another embodiment, the spacing between the recesses 181 provided at the red, green, blue, and white pixels constituting a unit pixel can be the same or different from each other. For example, the spacing between the recesses 181 provided at one or more of the white and green pixels can be different from the spacing between the recesses 181 provided at one or more of the red and blue pixels.

[0143] The protrusion 183 can be disposed at the planarization layer 170 overlapping with the light-emitting portion EP to have a shape in which the external extraction efficiency of light emitted from the pixel P can be maximized based on the effective light-emitting area of ​​the light-emitting portion EP. The protrusion 183 can increase the external extraction efficiency of light emitted from the light-emitting portion EP by changing the travel path of light emitted from the light-emitting portion EP toward the substrate 100.

[0144] The protrusion 183 can be configured to individually surround each of the plurality of recesses 181. For example, the protrusion 183 may include a bottom surface (or substrate surface) of each of the recesses 181, and an inclined surface sloping in various directions from the bottom surface. Thus, the planarization layer 170 overlapping at least a portion of the light-emitting region EA may include the plurality of recesses 181 surrounded by the protrusions 183. The protrusion 183 surrounding a recess 181 may be configured in a two-dimensional hexagonal shape (or honeycomb shape). For example, the protrusion 183 may be arranged to have a hexagonal shape (or honeycomb structure).

[0145] According to embodiments of this disclosure, the light extraction pattern 180 can be formed by etching the planarization layer 170 of the light-emitting portion EP using a photolithography process with photoresist after forming a mask pattern over the planarization layer 170. For example, a positive photoresist can be used as the photoresist to improve productivity.

[0146] The light-emitting part EP is disposed at the light extraction pattern 180 of the light-emitting area EA, and the light-emitting part EP can emit light toward the substrate 100 according to the bottom light emission type, but the embodiments of the present disclosure are not limited thereto.

[0147] The light-emitting part EP according to the embodiments of this disclosure may include a first electrode E1, a light-emitting device layer EDL, and a second electrode E2.

[0148] The first electrode E1 is disposed above the planarization layer 170 of the pixel region PA, and the first electrode E1 can be electrically connected to the source electrode 119s of the driving thin-film transistor Tdr. One end of the first electrode E1 near the circuit region CA extends to the source electrode 119s of the driving thin-film transistor Tdr, and can then be electrically connected to the source electrode 119s of the driving thin-film transistor through the electrode contact hole CH formed in the planarization layer 170 and the protective layer 130.

[0149] The first electrode E1 is in direct contact with the light extraction pattern 180, thereby having a shape corresponding to the light extraction pattern 180. Since the first electrode E1 is disposed (or deposited) on the planarization layer 170 and is implemented to have a relatively small thickness, the first electrode E1 can have a surface morphology (or second surface shape) corresponding to the surface morphology (or first surface shape) of the light extraction pattern 180, which includes protrusions 183 and a plurality of recesses 181. For example, the first electrode E1 can be formed in a conformal shape based on the surface shape (morphology) of the light extraction pattern 180 by a deposition process of a transparent conductive material, thereby allowing the first electrode E1 to have a cross-sectional structure whose shape is the same as that of the light extraction pattern 180.

[0150] The light-emitting device layer (EDL) is disposed on the first electrode E1, and the EDL can directly contact the first electrode E1. Since the EDL is disposed (or deposited) on the first electrode E1 and is implemented to have a relatively large thickness compared to the first electrode E1, the EDL can have a surface morphology (or third surface shape) different from the surface morphology of each of the protrusions 183 and the plurality of recesses 181 or the surface morphology of the first electrode E1. For example, the EDL is formed by a deposition process into a non-conformal shape that is not conformal to the surface shape (or morphology) of the first electrode E1, thereby allowing the EDL to have a cross-sectional structure whose shape differs from that of the first electrode E1.

[0151] The light-emitting device layer (EDL) according to embodiments of this disclosure can be implemented with a thickness that gradually increases toward the bottom surface of the recess 181 or the protrusion 183. For example, the EDL can be implemented with a first thickness above the top of the protrusion 183, a second thickness above the bottom surface of the recess 181, wherein the second thickness is relatively greater than the first thickness, and a third thickness above the inclined surface (or curved surface) of the protrusion 183, wherein the third thickness is relatively less than the first thickness. In this document, each of the first, second, and third thicknesses can be the shortest distance between the first electrode E1 and the second electrode E2.

[0152] The light-emitting device layer (EDL) according to embodiments of this disclosure includes two or more light-emitting layers for emitting white light. As one embodiment, the EDL may include a first light-emitting layer and a second light-emitting layer to emit white light by mixing a first light and a second light. For example, the first light-emitting layer may include any layer selected from a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer to emit the first light. For example, the second light-emitting layer may include a light-emitting layer capable of emitting a second light, thereby obtaining white light in the light-emitting portion (EP) by mixing the first light with the blue, green, red, yellow, or yellow-green light-emitting layer.

[0153] In another embodiment, the light-emitting device layer (EDL) may include any one selected from a blue light-emitting layer, a green light-emitting layer, and a red light-emitting layer. For example, when pixel P is a red pixel, the EDL for the red pixel may include a red light-emitting layer. When pixel P is a green pixel, the EDL for the green pixel may include a green light-emitting layer. When pixel P is a blue pixel, the EDL for the blue pixel may include a blue light-emitting layer.

[0154] The second electrode E2 is disposed on the light-emitting device layer EDL, and the second electrode E2 can directly contact the light-emitting device layer EDL. The second electrode E2 can be formed (or deposited) on the light-emitting device layer EDL to have a thickness relatively smaller than the thickness of the light-emitting device layer EDL. Because the second electrode E2 can be formed (or deposited) on the light-emitting device layer EDL to have a relatively small thickness, it can therefore have a surface morphology corresponding to the surface morphology of the light-emitting device layer EDL. For example, by a deposition process, the second electrode E2 can be formed into a conformal shape corresponding to the surface shape (or morphology) of the light-emitting device layer EDL, thereby allowing the second electrode E2 to have the same cross-sectional structure as the light-emitting device layer EDL.

[0155] The second electrode E2 according to embodiments of this disclosure may include a metallic material with high reflectivity to reflect incident light emitted from the light-emitting device layer EDL toward the substrate 100. For example, the second electrode E2 may include any one of the materials selected from aluminum (Al), silver (Ag), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), or barium (Ba), or a single-layer or multi-layer structure of an alloy of two or more of the materials selected from aluminum (Al), silver (Ag), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), or barium (Ba).

[0156] The light-emitting part EP is disposed at the light extraction pattern 180, therefore, a non-planar part 185 disposed at the light-emitting area EA can be included.

[0157] The non-planar portion (or non-flat portion) 185 may have a wavy shape. The non-planar portion (or non-flat portion) 185 may include a plurality of recesses 185a and a protrusion 185b between each of the plurality of recesses 185a.

[0158] In the non-planar portion 185, each of the plurality of recesses 185a may overlap with each of the plurality of recesses 181 of the light extraction pattern 180, and the protrusion 185b may overlap with at least a portion of the protrusion 183 of the light extraction pattern 180. The travel path of light emitted from the light-emitting portion EP can be altered to the substrate 100 by the non-planar portion 185 having the plurality of recesses 185a and protrusions 185b, thereby improving or maximizing the external extraction efficiency of light emitted from the light-emitting portion EP.

[0159] The substrate 100 according to embodiments of the present disclosure may further include a wavelength conversion layer 150. The wavelength conversion layer 150 may be disposed between the substrate 100 and the planarization layer 170 to overlap with at least a portion of the light-emitting region EA of at least one of the plurality of pixel regions PA.

[0160] According to an embodiment of the present disclosure, the wavelength conversion layer 150 may be disposed between the protective layer 130 and the planarization layer 170 to overlap with at least a portion of the light-emitting region EA. According to another embodiment of the present disclosure, the wavelength conversion layer 150 may be disposed between the substrate 100 and the insulating intermediate layer 117 or between the insulating intermediate layer 117 and the protective layer 130 to overlap with at least a portion of the light-emitting region EA.

[0161] The wavelength conversion layer 150 can have a size relatively larger than the light-emitting region EA. For example, the wavelength conversion layer 150 can be relatively larger than the light-emitting region EA, and relatively smaller than the light extraction pattern 180 of the planarization layer 170.

[0162] The wavelength conversion layer 150 according to the first embodiment of this disclosure includes a color filter that transmits only the wavelength of light emitted from the light-emitting unit EP that corresponds to the color in the pixel toward the substrate 100. For example, the wavelength conversion layer 150 may transmit only red, green, or blue wavelengths. As one embodiment, in the light-emitting display device according to this disclosure, when a unit pixel includes adjacent first to third pixels, the wavelength conversion layer disposed at the first pixel may include a red color filter, the wavelength conversion layer disposed at the second pixel may include a green color filter, and the wavelength conversion layer disposed at the third pixel may include a blue color filter. Furthermore, a unit pixel may also include a white pixel without a wavelength conversion layer.

[0163] The wavelength conversion layer 150 according to the second embodiment of this disclosure may include quantum dots. For example, the wavelength conversion layer of the first pixel may include CdSe or InP quantum dots, the wavelength conversion layer of the second pixel may include CdZnSeS quantum dots, and the wavelength conversion layer of the third pixel may include ZnSe quantum dots, but the embodiments of this disclosure are not limited thereto. The quantum dots included in the wavelength conversion layer 150 are re-emitted according to the light emitted from the light-emitting portion EP to the substrate 100, thereby improving the color realization rate of the pixel or the light-emitting display device.

[0164] The first substrate 100 according to embodiments of the present disclosure may further include a dam layer 190.

[0165] The dam layer 190 (or dam pattern) can define the light-emitting region EA of the pixel region PA. The dam layer 190 can be disposed at the edge of the planarization layer 170 and the first electrode E1. The dam layer 190 can overlap with at least a portion of the edge of the wavelength conversion layer 150. For example, the dam layer 190 can be formed of an organic material such as a benzocyclobutene (BCB)-based resin, an acrylic resin, or a polyimide resin. For example, the dam layer 190 can be formed of a photosensitizer including a black pigment. In this case, the dam layer 190 can also serve as a light-shielding member between adjacent pixels.

[0166] According to an embodiment of the present disclosure, the embankment layer 190 may be disposed above the upper surface 170a of the planarization layer 170 to cover (or coat) the edge of the circuit region CA of the first electrode E1 extending to the pixel region PA.

[0167] According to another embodiment of this disclosure, the embankment layer 190 can be configured to cover (or coat) the edge of the light extraction pattern 180. The light-emitting device layer EDL can be disposed on the first electrode E1, the embankment layer 190, and the step difference between the first electrode E1 and the embankment layer 190. When the light-emitting device layer EDL is disposed with a small thickness at the step difference between the first electrode E1 and the embankment layer 190, electrical contact (or short circuit) between the second electrode E2 and the first electrode E1 may occur due to the reduced thickness of the light-emitting device layer EDL. To prevent this problem, one end 191 of the embankment layer 190 is disposed at the edge of the light extraction pattern 180, thereby reducing the step difference between the first electrode E1 and the embankment layer 190. For example, one end 191 of the embankment layer 190 can define the end of the light-emitting region EA in the pixel region PA, or it can define the boundary line between the circuit region CA and the light-emitting region EA. The end 191 of the embankment layer 190 can be located above the recess 181 of the light extraction pattern 180. Therefore, in the two-dimensional structure, the size of the light-emitting region EA defined by the embankment layer 190 can be relatively smaller than the size of the light extraction pattern 180 of the planarization layer 170.

[0168] Each of the light-emitting device layer EDL and the second electrode E2 of the light-emitting part EP is also disposed above the embankment layer 190. For example, the light-emitting device layer EDL is disposed above the substrate 100 on which the first electrode E1 and the embankment layer 190 are disposed, and the second electrode E2 is disposed to cover (or coat) the light-emitting device layer EDL.

[0169] The opposing substrate 300 may be an opaque glass substrate, an opaque plastic substrate, or an opaque metal substrate, but the embodiments of this disclosure are not limited thereto.

[0170] The substrate 100 and the opposing substrate 300 can be joined together by the adhesive member 200.

[0171] An adhesive component 200 may be disposed between the substrate 100 and the opposing substrate 300, thereby bonding the substrate 100 and the opposing substrate 300 together via the adhesive component 200. For example, the adhesive component 200 may include a thermosetting transparent adhesive or a photocurable transparent adhesive. The adhesive component 200 may contain an absorbent material for absorbing external water or moisture that permeates into the light-emitting part EP.

[0172] The adhesive component 200 is configured to surround the display area AA and can directly contact the planarization layer 170 disposed in the non-display area IA.

[0173] Compared to the adhesive component 200, the opposing substrate 300 can have a relatively large size to ensure margin in the substrate bonding process and thus prevent the adhesive component 200 from overflowing. For example, each side surface (or sidewall) of the adhesive component 200 can be covered (or coated) by the opposing substrate 300. For example, each side surface (or sidewall) of the opposing substrate 300 can protrude outward from each side surface of the adhesive component 200.

[0174] Furthermore, the first substrate 100 according to embodiments of this disclosure may also include an encapsulation layer disposed between the adhesive member 200 and the light-emitting portion EP. The encapsulation layer may include a first inorganic layer configured to completely surround the light-emitting portion EP, an organic layer disposed on the first inorganic layer, and a second inorganic layer configured to completely surround the organic layer. The second inorganic layer may directly contact the edge of the first inorganic layer. The organic layer may be sealed by the first and second inorganic layers. The adhesive member 200 may be configured to surround the second inorganic layer.

[0175] Furthermore, the first substrate 100 according to embodiments of the present disclosure may also include an optical film disposed on a second surface 100b opposite to the first surface 100a.

[0176] The second surface 100b of the first substrate 100 may be the rear surface or the light extraction surface of the first substrate 100.

[0177] The optical film may also include a polarizing film attached to the second surface 100b of the substrate 100. The polarizing film modifies external light reflected by the film transistors and / or lines disposed in the display area into a circularly polarized state to improve the visibility and contrast of the light-emitting display device. For example, the optical film may be configured as a circularly polarizing film.

[0178] Figure 5 It is along Figure 1 The cross-sectional view shown at I-I' illustrates the first uneven pattern portion according to an embodiment of this disclosure. In the following text, repeated descriptions of the remaining elements, other than the first uneven pattern portion and related elements, may be omitted or will be briefly given.

[0179] Reference Figure 1 and Figure 5 In the first substrate 100 or display panel 10 according to the embodiments of the present disclosure, the planarization layer 170 may include a first extension 170a, which extends or extends from the first side AAa of the display area AA to the pad portion 51 of the first non-display area IA1.

[0180] The end portion 170s1 (or the first side of the planarization layer) of the first extension 170a can be disposed between the side surface of the substrate 100 and the first side AAa of the display area AA. According to embodiments of this disclosure, the first extension 170a can be disposed in the remaining portion of the first non-display area IA1, excluding the pad area 51a. For example, in the first non-display area IA1 of the substrate 100, the first extension 170a can be disposed in the remaining portion, excluding one edge of the link area 51b adjacent to the pad area 51a. Therefore, the first side 170s1 of the planarization layer 170 can be disposed between the pad portion 51 and the first side AAa of the display area AA.

[0181] The distance between the side surface of the substrate 100 and the first side 170s1 of the planarization layer 170 or the distance between the pad portion 51 and the first side 170s1 of the planarization layer 170 can be preset based on the process margin of the film attachment process for attaching the flexible circuit film 31 to the pad portion 51.

[0182] The planarization layer 170 may also include an uneven pattern portion 180a disposed at the first extension 170a. For example, the uneven pattern portion 180a disposed at the first extension 170a of the planarization layer 170 may be a first uneven pattern portion 180a.

[0183] The first uneven pattern portion 180a may include a plurality of first recesses 181a and a first protrusion 183a disposed between the plurality of recesses 181a. The first recesses 181a and the first protrusions 183a in the first uneven pattern portion 180a are structurally identical to the recesses 181 and protrusions 183 disposed in the light extraction pattern 180 disposed in the light-emitting region EA of the pixel region PA, therefore, their repeated description can be omitted.

[0184] The first uneven pattern portion 180a may be covered (or coated) by the adhesive component 200. For example, the adhesive component 200 may be in direct contact with the first uneven pattern portion 180a.

[0185] According to embodiments of the present disclosure, the spacing (or interval) between the first recesses 181a of the first uneven pattern portion 180a disposed in the first non-display area IA1 can be the same as the spacing (or interval) between the recesses 181 of the light extraction pattern 180 disposed in the display area AA. According to embodiments of the present disclosure, the number of first recesses 181a per unit area of ​​the first uneven pattern portion 180a disposed in the first non-display area IA1 can be the same as the number of recesses 181 per unit area of ​​the light extraction pattern 180 disposed in the display area AA.

[0186] The first uneven pattern portion 180a can scatter external light incident through the first non-display area IA1. For example, some of the light incident on the first non-display area IA1 of the substrate 100 can be scattered at the first uneven pattern portion 180a between the data link lines of the peripheral circuit portion 50 disposed in the first non-display area IA1 of the substrate 100. Some of the light scattered by the first uneven pattern portion 180a can pass through the data link lines again and then be emitted to the outside (or outside) through the substrate 100 again. Therefore, according to the mixing of the first light reflected by the data link lines and the second light scattered by the first uneven pattern portion 180a in the first non-display area IA1 of the substrate 100, the visibility of the first light can be reduced or minimized, and the data link lines of the peripheral circuit portion 50 may be invisible due to the haze or blurring of the first light. According to the embodiments of the present disclosure, when external light is incident on the first non-display area IA1 of the substrate 100, the first non-display area IA1 may have a constant haze value due to the mixing of the first light and the second light.

[0187] The first uneven pattern portion 180a may also be provided at the first extension portion 170a of the planarization layer 170 provided at the first non-display area IA1 of the substrate 100 and at some portions of the planarization layer 170 of the outermost pixel area PA adjacent to the first non-display area IA1 of the substrate 100.

[0188] In a light-emitting display device including a first uneven pattern portion 180a, the first non-display area IA1 of the substrate 100 becomes blurred due to the light scattered by the first uneven pattern portion 180a from external light, thereby minimizing or reducing the visibility of the peripheral circuit portion 50 disposed in the first non-display area IA1. Therefore, when the display panel 10 is in a closed state or when a black image is displayed on the display panel 10, the color difference (or difference in color impression) between the non-display area IA and the display area AA caused by the reflection of external light by the peripheral circuit portion 50 disposed in the non-display area IA can be reduced or minimized by the uneven pattern portion (or the first uneven pattern portion 180a).

[0189] Figure 6 It is along Figure 1 The cross-sectional view shown in II-II' illustrates the second uneven pattern portion according to an embodiment of this disclosure. In the following, repeated descriptions of the remaining elements, other than the second uneven pattern portion and related elements, may be omitted or will be briefly given.

[0190] Reference Figure 1 and Figure 6In the first substrate 100 or display panel 10 according to the embodiments of the present disclosure, the planarization layer 170 may include: a second extension 170b that extends or extends from the second side AAb of the display area AA to the second non-display area IA2; and a third extension 170c that extends or extends from the third side AAc of the display area AA to the third non-display area IA3.

[0191] The second extension 170b can extend from the second side AAb of the display area AA to the end of the second non-display area IA2. For example, the end 170s2 of the second extension 170b (or the second side of the planarization layer) can be positioned or aligned on the side surface of the substrate 100. For example, the second extension 170b can cover (or coat) the entire second non-display area IA2.

[0192] The third extension 170c can extend from the third side AAc of the display area AA to the end of the third non-display area IA3. For example, the end 170s3 of the third extension 170c (or the third side of the planarization layer) can be positioned or aligned on the side surface of the substrate 100. For example, the third extension 170c can cover (or coat) the entire third non-display area IA3.

[0193] The planarization layer 170 may also include uneven pattern portions 180b disposed at each of the second extension 170b and the third extension 170c. For example, the uneven pattern portions 180b disposed at the second extension 170b and the third extension 170c of the planarization layer 170 may be second uneven pattern portions 180b.

[0194] The second uneven pattern portion 180b can be provided at the entire planarization layer 170 at each of the second non-display area IA2 and the third non-display area IA3.

[0195] The second uneven pattern portion 180b may include a plurality of second recesses 181b and a second protrusion 183b disposed between the plurality of second recesses 181b. Each of the second recesses 181b and the second protrusions 183b of the second uneven pattern portion 180b may be configured to have the same structure as each of the recesses 181 and protrusions 183 of the light extraction pattern 180 disposed at the light emission region EA of the pixel region PA, and therefore, may be omitted or will be briefly described repeatedly.

[0196] Some (or a portion) of the second uneven pattern portion 180b may be covered (or coated) by the adhesive member 200, but embodiments of the present disclosure are not limited thereto. The entire second uneven pattern portion 180b may be covered (or coated) by the adhesive member 200. For example, the adhesive member 200 may be in direct contact with the second uneven pattern portion 180b.

[0197] According to embodiments of the present disclosure, the spacing (or interval) between the second recesses 181b of the second uneven pattern portions 180b provided at each of the second non-display areas IA2 and IA3 can be the same as the spacing (or interval) between the recesses 181 of the light extraction pattern 180 provided at the display area AA. According to embodiments of the present disclosure, the number of second recesses 181b per unit area in the second uneven pattern portions 180b provided at each of the second non-display areas IA2 and IA3 can be the same as the number of recesses 181 per unit area in the light extraction pattern 180 provided at the display area AA.

[0198] The second uneven pattern portion 180b can scatter external light incident through the second non-display area IA2 and the third non-display area IA3. For example, some of the light incident on the second non-display area IA2 and the third non-display area IA3 can be scattered at the second uneven pattern portion 180b by the gate drive circuits 55 and 57 of the peripheral circuit portion 50, which is disposed at each of the second non-display area IA2 and the third non-display area IA3 of the substrate 100. Some of the light scattered by the second uneven pattern portion 180b can pass through the gate drive circuits 55 and 57 again, and can then be emitted to the outside (or outside) again through the substrate 100. Therefore, by mixing the third light reflected by the gate drive circuits 55 and 57 with the fourth light scattered by the second uneven pattern portion 180b, the visibility of the third light can be reduced or minimized, and the gate drive circuits 55 and 57 of the peripheral circuit portion 50 may become invisible due to the haze or blur of the third light. According to embodiments of this disclosure, when external light is incident on the second non-display area IA2 and the third non-display area IA3 of the substrate 100, each of the second non-display area IA2 and the third non-display area IA3 may have a constant haze value due to the mixing of the third light and the fourth light.

[0199] The second uneven pattern portion 180b may also be disposed at the second extension portion 170b and the third extension portion 170c of the planarization layer 170 and at some portions of the planarization layer 170 adjacent to each of the outermost pixel regions PA in the second non-display regions IA2 and the third non-display regions IA3, wherein the planarization layer 170 is disposed at each of the second non-display regions IA2 and the third non-display regions IA3 of the substrate 100.

[0200] In a light-emitting display device including a second uneven pattern portion 180b, each of the second non-display area IA2 and the third non-display area IA3 of the substrate 100 becomes blurred due to the scattering of external light by the second uneven pattern portion 180b, thereby minimizing or reducing the visibility of the peripheral circuit portion 50 provided at each of the second non-display area IA2 and the third non-display area IA3. Therefore, when the display panel 10 is in a closed state or when a black image is displayed on the display panel 10, the color difference (or difference in color impression) between each of the second non-display area IA2 and the third non-display area IA3 and the display area AA caused by the reflection of external light by the peripheral circuit portion 50 provided at each of the second non-display area IA2 and the third non-display area IA3 can be reduced or minimized by the uneven pattern portion (or the second uneven pattern portion 180b).

[0201] Figure 7 It is along Figure 1 The cross-sectional view shown in III-III' illustrates the third uneven pattern portion according to an embodiment of this disclosure. In the following text, repeated descriptions of the remaining portions, excluding the third uneven pattern portion and related elements, may be omitted or will be briefly given.

[0202] Reference Figure 1 and Figure 7 In the first substrate 100 or display panel 10 according to the embodiments of the present disclosure, the planarization layer 170 may include a fourth extension 170d that extends or extends from the fourth side AAd of the display area AA to the fourth non-display area IA4.

[0203] The fourth extension 170d can extend from the fourth side AAd of the display area AA to the end of the fourth non-display area IA4. For example, the end 170s4 of the fourth extension 170d (or the fourth side of the planarization layer) can be positioned or aligned on the side surface of the substrate 100. For example, the fourth extension 170d can cover (or coat) the entire fourth non-display area IA4.

[0204] The planarization layer 170 may also include an uneven pattern portion 180c disposed at the fourth extension 170d. For example, the uneven pattern portion 180c disposed at the fourth extension 170d of the planarization layer 170 may be a third uneven pattern portion 180c.

[0205] A third uneven pattern section 180c can be set at the entire planarization layer 170, which is set at the fourth non-display area IA4.

[0206] The third uneven pattern portion 180c may include a plurality of third recesses 181c and a third protrusion 183c disposed between the plurality of third recesses 181c. Each of the third recesses 181c and the third protrusions 183c of the third uneven pattern portion 180c may be configured with the same structure as the recesses 181 and protrusions 183 of the light extraction pattern 180 disposed at the light emission region EA of the pixel region PA, and therefore, may be omitted or will be briefly described repeatedly.

[0207] Some (or a portion) of the third uneven pattern portion 180c may be covered (or coated) by the adhesive member 200, but embodiments of the present disclosure are not limited thereto. The entire third uneven pattern portion 180c may be covered (or coated) by the adhesive member 200. For example, the adhesive member 200 may be in direct contact with the third uneven pattern portion 180c.

[0208] According to embodiments of the present disclosure, the spacing (or interval) between the third recesses 181c of the third uneven pattern portion 180c disposed in the fourth non-display area IA4 can be the same as the spacing (or interval) between the recesses 181 of the light extraction pattern 180 disposed in the display area AA. According to embodiments of the present disclosure, the number of third recesses 181c per unit area in the third uneven pattern portion 180c disposed in the fourth non-display area IA4 can be the same as the number of recesses 181 per unit area in the light extraction pattern 180 disposed in the display area AA.

[0209] The third uneven pattern portion 180c can scatter external light incident through the fourth non-display area IA4 of the substrate 100. For example, some of the light incident on the fourth non-display area IA4 of the substrate 100 can be scattered at the third uneven pattern portion 180c by the test circuit portion 59 of the peripheral circuit portion 50 disposed at the fourth non-display area IA4 of the substrate 100. Some of the light scattered by the third uneven pattern portion 180c can pass through the test circuit portion 59 again and can then be emitted to the outside (or outside) through the substrate 100 again. Therefore, according to the mixing of the fifth light reflected by the test circuit portion 59 and the sixth light scattered by the third uneven pattern portion 180c, the visibility of the fifth light can be reduced or minimized, and the test circuit portion 59 may become invisible due to the haze or blur of the fifth light. According to the embodiments of the present disclosure, when external light is incident on the fourth non-display area IA4 of the substrate 100, the fourth non-display area IA4 may have a constant haze value due to the mixing of the fifth and sixth light.

[0210] The third uneven pattern portion 180c may also be provided at the fourth extension portion 170d of the planarization layer 170 provided at the fourth non-display area IA4 of the substrate 100 and at some portions of the planarization layer 170 of the outermost pixel area PA adjacent to the fourth non-display area IA4.

[0211] In a light-emitting display device including a third uneven pattern section 180c, the fourth non-display area IA4 of the substrate 100 becomes blurred due to the scattering of external light by the third uneven pattern section 180c, thereby minimizing or reducing the visibility of the peripheral circuit section 50 disposed at the fourth non-display area IA4. Therefore, when the display panel 10 is in a closed state or when a black image is displayed on the display panel 10, the color difference (or difference in color impression) between the fourth non-display area IA4 and the display area AA caused by the reflection of external light by the peripheral circuit section 50 disposed at the fourth non-display area IA4 can be reduced or minimized by the uneven pattern section (or the third uneven pattern section 180c).

[0212] Figure 8 A planarization layer according to another embodiment of this disclosure is shown. Figure 9 It shows Figure 8 The light extraction pattern and the cross-sectional structure of each of the first to third uneven pattern portions are shown. In the following text, repeated descriptions of elements other than the light extraction pattern and the cross-sectional structures of each of the first to third uneven pattern portions may be omitted or will be briefly given.

[0213] Reference Figure 8 and Figure 9 According to another embodiment of the present disclosure, the planarization layer 170 may be disposed in the display area AA and the non-display area IA other than the pad area 51a of the substrate 100.

[0214] The planarization layer 170 may include a light extraction pattern 180, and a first uneven pattern portion to a third uneven pattern portion 180a, 180b and 180c.

[0215] The light extraction pattern 180 and the first to third uneven pattern portions 180a, 180b and 180c can have different sizes than each other. For example, depending on the area of ​​the metal layer for reflecting external light in each corresponding region, the size of each of the light extraction pattern 180 and the first to third uneven pattern portions 180a, 180b and 180c can be configured to have different haze values ​​for each corresponding region.

[0216] The light extraction pattern 180 can be set at the light-emitting area EA of each pixel area PA of the display area AA. The light extraction pattern 180 may include a plurality of recesses 181 and protrusions 183 disposed between the plurality of recesses 181.

[0217] Multiple recesses 181 may be spaced apart from each other. According to embodiments of the present disclosure, the multiple recesses 181 may be configured to be spaced apart from each other along a first direction X and a second direction Y. For example, two adjacent recesses 181 may have a first interval L1 between them. The first interval L1 may be the distance between the center points of two adjacent recesses 181 along the first direction X or the second direction Y. For example, the first interval L1 between two adjacent recesses 181 or the first interval L1 between multiple recesses 181 may be the spacing between the recesses 181 or the spacing of the light extraction pattern 180.

[0218] The protrusion 183 may be configured to surround each of a plurality of recesses 181. For example, the protrusion 183 may be configured to project outwards and have a first diameter Dl and a first height Hl. The protrusion 183 according to embodiments of the present disclosure may include a bottom surface BS, a top surface, and a curved surface between the bottom surface BS and the top surface. For example, the protrusion 183 may have a Gaussian curve cross-sectional structure or may have a pointed cross-sectional structure at the top. For example, the top of the protrusion 183 may have a pointed tip.

[0219] The emission efficiency of the light-emitting part can be determined based on the shape of the protrusion 183. The light extraction efficiency can be determined based on the shape of the protrusion 183 of the light extraction pattern 180 and the shape of the light-emitting device layer EDL.

[0220] The protrusion 183 may have a tangential inclination that gradually decreases from the top to the bottom surface BS. For example, the tangential inclination may be defined by the angle between the curved portion and a horizontal line parallel to the bottom surface BS of the protrusion 183.

[0221] The protrusion 183 may have a maximum tangent slope between half the height H / 2 and the top. For example, the protrusion 183 may include a first tangent slope at half the height H / 2 and a second tangent slope at 4 / 5 of the height. The second tangent slope may be greater than the first tangent slope, such that light emitted from the light-emitting device layer EDL is not trapped in the light-emitting element ED but is extracted to the outside as much as possible.

[0222] The first uneven pattern portion 180a may be disposed in the remaining portion of the first non-display area IA1, excluding the pad area 51a. The first uneven pattern portion 180a may include a plurality of first recesses 181a and a first protrusion 183a disposed between the plurality of first recesses 181a.

[0223] The plurality of first recesses 181a may be spaced apart from each other. According to embodiments of the present disclosure, the plurality of first recesses 181a may be configured to be spaced apart from each other along a first direction X and a second direction Y. For example, two adjacent first recesses 181a may have a second gap L2 between them. The second gap L2 may be the distance between the center points of two adjacent first recesses 181a along the first direction X or the second direction Y. For example, the second gap L2 between two adjacent first recesses 181a or between the plurality of first recesses 181a may be the spacing between the first recesses 181a or the spacing between the first uneven pattern portions 180a.

[0224] According to embodiments of the present disclosure, the second interval L2 between two adjacent first recesses 181a can be narrower or smaller than the first interval L1 between two adjacent recesses 181 provided in the display area AA. For example, the spacing L2 of the first recesses 181a can be smaller than the spacing L1 of the recesses 181. According to embodiments of the present disclosure, the number of first recesses 181a per unit area in the first uneven pattern portion 180a provided in the first non-display area IA1 can be greater than the number of recesses 181 per unit area in the light extraction pattern 180 provided in the display area AA.

[0225] The first protrusion 183a may be configured to surround each of a plurality of first recesses 181a. For example, the first protrusion 183a may be configured to project forward and have a second diameter D2 and a second height H2. The first protrusion 183a according to embodiments of the present disclosure may include a bottom surface BS, a top surface, and a curved surface between the bottom surface BS and the top surface. For example, the first protrusion 183a may have a Gaussian curve cross-sectional structure or may have a pointed cross-sectional structure at the top. For example, the top of the first protrusion 183a may have a pointed tip. For example, the second diameter D2 may be smaller than the first diameter D1. For example, the second height H2 may be the same as or smaller than the first height H1.

[0226] The second uneven pattern portion 180b may be disposed at each of the second non-display area IA2 and the third non-display area IA3. The second uneven pattern portion 180b may include a plurality of second recesses 181b and a second protrusion 183b disposed between the plurality of second recesses 181b.

[0227] The plurality of second recesses 181b may be spaced apart from each other. According to embodiments of the present disclosure, the plurality of second recesses 181b may be configured to be spaced apart from each other along a first direction X and a second direction Y. For example, two adjacent second recesses 181b have a third interval L3 between them. The third interval L3 may be the distance between the center points of two adjacent second recesses 181b along the first direction X or the second direction Y. For example, the third interval L3 between two adjacent second recesses 181b or between the plurality of second recesses 181b may be the spacing between the second recesses 181b or the spacing between the second uneven pattern portions 180b.

[0228] According to embodiments of the present disclosure, the third interval L3 between two adjacent second recesses 181b can be narrower or smaller than the first interval L1 between two adjacent recesses 181 disposed in the display area AA. For example, the spacing L3 of the second recesses 181b can be smaller than the spacing L1 of the recesses 181, and can be larger than the spacing L2 of the first recesses 181a. According to embodiments of the present disclosure, the number of first recesses 181a per unit area in the first uneven pattern portion 180a disposed in the first non-display area IA1 can be greater than the number of second recesses 181b per unit area in the second uneven pattern portion 180b disposed in each of the second non-display areas IA2 and the third non-display area IA3. According to embodiments of the present disclosure, the number of second recesses 181b per unit area in the second uneven pattern portion 180b can be greater than the number of recesses 181 per unit area in the light extraction pattern 180 disposed in the display area AA.

[0229] The second protrusion 183b may be configured to surround each of a plurality of second recesses 181b. For example, the second protrusion 183b may be configured to project forward and have a third diameter D3 and a third height H3. The second protrusion 183b according to embodiments of the present disclosure may include a bottom surface BS, a top surface, and a curved surface between the bottom surface BS and the top surface. For example, the second protrusion 183b may have a Gaussian curve cross-sectional structure or may have a pointed cross-sectional structure at the top. For example, the top surface may have a pointed tip. For example, the third diameter D3 may be smaller than the first diameter D1 and may be the same as or smaller than the second diameter D2. For example, the third height H3 may be the same as or smaller than the first height H1 and may be the same as or smaller than the second height H2.

[0230] The third uneven pattern portion 180c may be disposed at the fourth non-display area IA4. The third uneven pattern portion 180c may include a plurality of third recesses 181c and a third protrusion 183c disposed between the plurality of third recesses 181c.

[0231] The plurality of third recesses 181c may be spaced apart from each other. According to embodiments of the present disclosure, the plurality of third recesses 181c may be configured to be spaced apart from each other along a first direction X and a second direction Y. For example, two adjacent third recesses 181c have a fourth interval L4 between them. The fourth interval L4 may be the distance between the center points of two adjacent third recesses 181c along the first direction X or the second direction Y. For example, the fourth interval L4 between two adjacent third recesses 181c or between the plurality of third recesses 181c may be the spacing between the third recesses 181c or the spacing between the third uneven pattern portions 180c.

[0232] According to embodiments of the present disclosure, the fourth interval L4 between two adjacent third recesses 181c can be narrower or smaller than the first interval L1 between two adjacent recesses 181 provided in the display area AA. For example, the spacing L4 of the third recesses 181c can be smaller than each of the spacing L1 of the recesses 181 and the spacing L3 of the second recesses 181b, and can be larger than the spacing L2 of the first recesses 181a. According to embodiments of the present disclosure, the number of first recesses 181a per unit area in the first uneven pattern portion 180a provided in the first non-display area IA1 can be greater than the number of third recesses 181c per unit area in the third uneven pattern portion 180c provided in the fourth non-display area IA4. According to embodiments of the present disclosure, the number of third recesses 181c per unit area in the third uneven pattern portion 180c provided at the fourth non-display area IA4 can be greater than the number of second recesses 181b per unit area in the second uneven pattern portion 180b provided at each of the second non-display areas IA2 and the third non-display areas IA3, and can be greater than the number of recesses 181 per unit area in the light extraction pattern 180 provided at the display area AA.

[0233] The third protrusion 183c may be configured to surround each of a plurality of third recesses 181c. For example, the third protrusion 183c may be configured to project forward and have a fourth diameter D4 and a fourth height H4. The third protrusion 183c according to embodiments of the present disclosure may include a bottom surface BS, a top surface, and a curved surface between the bottom surface BS and the top surface. For example, the third protrusion 183c may have a Gaussian curve cross-sectional structure or may have a pointed cross-sectional structure at the top. For example, the top of the third protrusion 183c may have a pointed tip. For example, the fourth diameter D4 may be smaller than the first diameter D1, may be the same as or smaller than the second diameter D2, and may be the same as or smaller than the third diameter D3. For example, the fourth height H4 may be the same as or smaller than the first height H1, may be the same as or smaller than the second height H2, and may be the same as or smaller than the third height H3.

[0234] Each of the first to third uneven pattern portions 180a, 180b, and 180c located in each of the first to fourth non-display areas IA1, IA2, IA3, and IA4 scatters external light incident through the substrate 100 and the peripheral circuit portion, thereby minimizing or reducing the visibility of the peripheral circuit portion 50 located in the first to fourth non-display areas IA1, IA2, IA3, and IA4. Therefore, when the display panel 10 is in a closed state or when a black image is displayed on the display panel 10, the color difference (or difference in color impression) between the display area AA and each of the first to fourth non-display areas IA1, IA2, IA3, and IA4 can be reduced or minimized. For example, the haze characteristics (or blurring characteristics) of the non-display area IA by means of the first to third uneven pattern portions 180a, 180b and 180c provided in the non-display area IA can be the same as or similar to the haze characteristics of the display area AA by means of the scattering of external light by the light extraction pattern 180 provided in the display area AA, and therefore, the color difference (or difference in color impression) between the fourth non-display area IA4 and the display area AA can be reduced or minimized.

[0235] Figure 10 A planarization layer according to another embodiment of this disclosure is shown. Figure 11 It is along Figure 10 A cross-sectional view taken from IV-IV'. Figure 12 It is along Figure 10 A cross-sectional view taken at V-V', which shows the setting... Figure 10 The light extraction pattern is shown over the entire area of ​​the planarization layer of the display area. The following descriptions of the first to third uneven pattern portions, excluding the light extraction pattern, are related to... Figure 8 and Figure 9 The descriptions are the same, and repeated descriptions of the first to third uneven pattern portions may be omitted or will be given briefly.

[0236] Reference Figures 10 to 12 According to another embodiment of the present disclosure, the light extraction pattern 180 can be disposed on the entire upper surface of the planarization layer 170, which is disposed at the display area AA. For example, according to another embodiment of the present disclosure, the light extraction pattern 180 can be disposed at the light-emitting area EA of each pixel area PA and also at the circuit area. Therefore, the entire upper surface of the planarization layer 170 disposed on the substrate 100 can be provided with the light extraction pattern 180 and uneven pattern portions having uneven pattern portions 180a, 180b and 180c.

[0237] As an implementation, the light extraction pattern 180 may include a plurality of recesses 181 and protrusions 183, which are disposed on the entire upper surface of the planarization layer 170 disposed at the display area AA. The first uneven pattern portion 180a may include a plurality of first recesses 181a and first protrusions 183a, which are disposed on the entire upper surface of the planarization layer 170 corresponding to the remaining first non-display areas IA (excluding the pad area 51a). The second uneven pattern portion 180b may include a plurality of second recesses 181b and second protrusions 183b, which are disposed on the entire upper surface of the planarization layer 170 corresponding to the second non-display areas IA2 and the third non-display areas IA3. The third uneven pattern portion 180c may include a plurality of third recesses 181c and third protrusions 183c, the plurality of third recesses 181c and third protrusions 183c being disposed on the entire upper surface of the planarization layer 170 corresponding to the fourth non-display area IA4.

[0238] Therefore, the light extraction pattern 180, provided across the entire surface of the display area AA, scatters external light incident on the display area AA, thus providing haze characteristics (or blurring characteristics) more uniformly to the entire area of ​​the display area AA. This reduces or minimizes color difference (or difference in color impression) between each area within the display area AA caused by reflection of external light at the display area AA. Furthermore, each of the first to third uneven pattern portions 180a, 180b, and 180c, provided at each of the first to fourth non-display areas IA1, IA2, IA3, and IA4, scatters external light incident through the substrate 100 and the peripheral circuit portion. This minimizes or reduces the visibility of the peripheral circuit portion 50 provided at the first to fourth non-display areas IA1, IA2, IA3, and IA4. Therefore, when the display panel 10 is in a closed state or when a black image is displayed on the display panel 10, the color difference (or difference in color impression) between the display area AA and each of the first to fourth non-display areas IA1, IA2, IA3, and IA4 can be minimized or reduced. For example, the haze characteristics of the non-display area IA, which are based on the light scattered by the first to third uneven pattern portions 180a, 180b and 180c provided in the non-display area IA, can be the same as or similar to the haze characteristics of the display area AA, which are based on the light scattered by the light extraction pattern 180 provided in the display area AA. This can minimize or reduce the color difference (or difference in color impression) between the display area AA and the non-display area IA.

[0239] Figure 13A light-emitting display device according to another embodiment of the present disclosure is shown, and Figure 14 It is along Figure 13 The cross-sectional view taken from VI-VI', where, Figure 13 and Figure 14 The light-emitting display device through Figures 1 to 12 An edge pattern layer is additionally provided in the light-emitting display device to achieve this. In the following text, repeated descriptions of the remaining components other than the edge pattern layer and related elements may be omitted or will be given briefly.

[0240] Combination Figure 8 or Figure 10 For reference Figure 13 and Figure 14 In another embodiment of the light-emitting display device according to the present disclosure, an edge pattern layer 400 may be disposed at the edge of a second surface (or light extraction surface) 100b opposite to a first surface (or front surface) 100a of the substrate 100. The edge pattern layer 400 may be disposed along the edge of the second surface 100b of the substrate 100 to overlap with each of the first to fourth non-display areas IA1, IA2, IA3, and IA4 of the substrate 100. According to embodiments of the present disclosure, the edge pattern layer 400 may overlap with at least a portion or all of the first to fourth non-display areas IA1, IA2, IA3, and IA4, respectively. For example, the edge pattern layer 400 may be configured to cover (or coat) all areas between the end of the display area AA and the end of the substrate 100.

[0241] The edge pattern layer 400 may overlap with at least a portion of the uneven pattern portions 180a, 180b, 180c, which are disposed at each of the first to fourth non-display areas IA1, IA2, IA3 and IA4 of the substrate 100.

[0242] The edge pattern layer 400 according to embodiments of this disclosure may include a light-absorbing material. For example, the edge pattern layer 400 may be formed of a black material such as black ink. The edge pattern layer 400 is made of a black material and formed with a thickness t1 of 1.0 μm to 1.5 μm, thereby achieving translucent properties.

[0243] According to embodiments of this disclosure, when the edge pattern layer 400 is made of a black material and has a thickness tl exceeding 1.5 μm, the edge pattern layer 400 may be opaque due to its relatively large thickness. When the edge pattern layer 400 has a thickness that results in opacity, the first non-display area to the fourth non-display areas IA1, IA2, IA3 and IA4 appear black because they block external light incident on the peripheral circuit section 50, thus creating a problem related to color difference (or difference in color impression) between the display area AA and the non-display area IA.

[0244] According to embodiments of this disclosure, when the edge pattern layer 400 is made of a black material and has a thickness t1 of less than 1.0 μm, the edge pattern layer 400 may be transparent due to its relatively small thickness. When the edge pattern layer 400 has a thickness that results in transparency, reflected light RL1 reflected by the peripheral circuit section 50 passes through the edge pattern layer 400, thus causing a problem related to the visibility of the peripheral circuit section 50.

[0245] Therefore, the edge pattern layer 400 is made of black material and has a thickness tl of 1.0 μm to 1.5 μm, which reduces the visibility of the peripheral circuit section 50 caused by external light and thus minimizes the color difference (or difference in color impression) between the display area AA and the non-display area IA.

[0246] The edge pattern layer 400 absorbs or blocks some of the external light incident on the peripheral circuit section 50 located at each of the first to fourth non-display areas IA1, IA2, IA3, and IA4, and can absorb at least some of the reflected light RL1 reflected by the peripheral circuit section 50. Therefore, the edge pattern layer 400 can reduce or minimize the visibility of the peripheral circuit section 50 reflected by the metal layer located at the peripheral circuit section 50. Furthermore, the edge pattern layer 400 can transmit scattered light SL1 scattered by the uneven pattern section and then incident through the substrate 100. Therefore, the scattered light SL1 passing through the edge pattern layer 400 blurs the reflected light RL1 reflected by the peripheral circuit section 50, and then passes through the edge pattern layer 400, thereby reducing or minimizing the visibility of the peripheral circuit section 50, and reducing or minimizing the color difference (or difference in color impression) between the display area AA and the non-display area IA of the substrate 100. Therefore, when the display panel 10 is in the off state or a black image is displayed on the display panel 10, the color difference (or difference in color impression) between the display area AA and each of the first to fourth non-display areas IA1, IA2, IA3 and IA4 can be reduced or minimized. For example, the haze characteristics of the non-display area IA based on the reflected light RL1 caused by the peripheral circuit section 50 and the scattered light SL1 caused by the first to third uneven pattern sections 180a, 180b and 180c provided in the non-display area IA can be the same as or similar to the haze characteristics of the display area AA based on the reflected light RL2 caused by the signal line and the scattered light SL2 caused by the light extraction pattern 180 provided in the display area AA.

[0247] Furthermore, the edge pattern layer 400 may be disposed between the substrate 100 and the optical film. For example, the optical film may be a polarizing film. The optical film may be attached to the entire second surface 100b of the substrate 100, including the edge pattern layer 400, by a film lamination process using an adhesive.

[0248] Figure 15A This illustrates the color difference (or difference in color impression) between the non-display area and the display area in a light-emitting display device of the related art. Figure 15B The color difference (or difference in color impression) between the non-display area and the display area in an embodiment of the present disclosure is shown. Figure 15A The light-emitting display device shown in the related art includes a black edge pattern disposed in a non-display area, and the light-emitting display device according to the embodiments of the present disclosure includes an edge pattern layer disposed in a non-display area.

[0249] As in Figure 15AAs shown, the light-emitting display device according to the related technology includes a black edge pattern disposed in the non-display area IA, the black edge pattern being displayed as black, so that the color difference between the non-display area IA and the display area AA is clearly visible.

[0250] At the same time, such as in Figure 15B As shown, the light-emitting display device according to an embodiment of the present disclosure includes an uneven pattern portion and a semi-transparent edge pattern layer disposed at a non-display area IA. Due to the scattered light caused by the uneven pattern portion, the non-display area IA is displayed as non-black, thereby reducing or minimizing the color difference between the non-display area IA and the display area AA. Furthermore, in the case of the light-emitting display device according to an embodiment of the present disclosure, when the display panel is in a closed state or a black image is displayed on the display panel, the haze characteristics between the non-display area IA and the display area AA become similar due to the scattered light from the light extraction pattern disposed at the display area AA and the scattered light from the uneven pattern portion disposed at the non-display area IA, thereby reducing or minimizing the color difference between the non-display area IA and the display area AA.

[0251] It will be apparent to those skilled in the art that the above-described disclosure is not limited to the embodiments and drawings described above, and that various substitutions, modifications, and variations can be made to the disclosure without departing from its spirit or scope. Therefore, the scope of protection of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of protection of this disclosure.

Claims

1. A light emitting display apparatus comprising: a substrate configured to include a display area having a plurality of pixel areas and a non-display area surrounding the display area; and a planarization layer disposed at the display area and partially disposed at the non-display area, wherein the planarization layer is configured to include an uneven pattern portion disposed at the non-display area, and wherein the uneven pattern portion is configured to include a plurality of recesses, wherein the non-display area includes a first non-display area to a fourth non-display area surrounding the display area, wherein the uneven pattern portion includes: a first uneven pattern portion disposed at a first non-display area, wherein the first non-display area is disposed at a first side of the display area and includes a pad area; a second uneven pattern portion disposed at each of a second non-display area and a third non-display area, wherein the second non-display area is disposed at a second side of the display area, the third non-display area is disposed at a third side parallel to the second side of the display area; and a third uneven pattern portion disposed at a fourth non-display area, wherein the fourth non-display area is disposed at a fourth side parallel to the first side of the display area, wherein a number of recesses per unit area of the first uneven pattern portion is greater than a number of recesses per unit area of each of the second uneven pattern portion and the third uneven pattern portion, or wherein a pitch between center points of two adjacent recesses disposed at the first uneven pattern portion is less than a pitch between center points of two adjacent recesses disposed at each of the second uneven pattern portion and the third uneven pattern portion.

2. The light-emitting display device according to claim 1, wherein the planarization layer is disposed at the remaining non-display area except for the pad area; and / or wherein the planarization layer is partially disposed at the non-display area only; and / or wherein the uneven pattern portion includes a protrusion disposed between the plurality of recesses and / or has a wavy shape. 3.The light emitting display apparatus of claim 2, wherein, the uneven pattern portion surrounds the display area.

4. The light-emitting display device according to claim 3, wherein a number of recesses per unit area of the uneven pattern portion disposed at each of the first non-display area to the fourth non-display area is different from each other, and / or wherein a pitch between center points of two adjacent recesses in the uneven pattern portion disposed at each of the first non-display area to the fourth non-display area is different from each other. 5.The light emitting display apparatus of claim 1, further comprising: a plurality of gate lines disposed at the display area; and a gate driving circuit disposed at one or more of the second non-display area and the third non-display area and connected to the plurality of gate lines, respectively, and / or wherein the first non-display area further includes a link area between the pad area and the display area; and wherein the uneven pattern portion disposed at the first non-display area is disposed at the link area.

6. The light-emitting display device according to claim 1, wherein The number of recessed portions per unit area of the third uneven pattern portion is greater than the number of recessed portions per unit area of the second uneven pattern portion.

7. The light-emitting display device according to claim 1, wherein A pitch between center points of two adjacent recessed portions provided at the third uneven pattern portion is less than a pitch between center points of two adjacent recessed portions provided at the second uneven pattern portion.

8. The light emitting display apparatus of claim 1, further comprising a peripheral circuit portion over the substrate at the non-display region, wherein The uneven pattern portion is provided at the peripheral circuit portion.

9. The light emitting display apparatus of any one of claims 1 to 8, wherein The display region is configured to include a pixel array including pixels provided at each of the plurality of pixel regions, wherein the pixels are configured to include a light emitting portion and a non-light emitting portion surrounding the light emitting portion, and The planarization layer provided at the light emitting portion is configured to include a light extraction pattern including a plurality of recessed portions and a protruding portion surrounding each of the plurality of recessed portions.

10. The light emitting display apparatus of claim 9, wherein The light emitting portion includes a non-planar portion including a plurality of recessed portions and a protruding portion between each of the plurality of recessed portions, and wherein each of the plurality of recessed portions of the non-planar portion overlaps each of the plurality of recessed portions of the light extraction pattern, and the protruding portion of the non-planar portion overlaps at least a portion of the protruding portion of the light extraction pattern.

11. The light emitting display apparatus of claim 9, wherein, The planarization layer provided at the non-light emitting portion is configured to include a light extraction pattern including a plurality of recessed portions and a protruding portion surrounding each of the plurality of recessed portions.

12. A light emitting display apparatus comprising: a substrate configured to include a display region having a plurality of pixel regions and a non-display region surrounding the display region; a pixel circuit portion at the display region of the substrate; a peripheral circuit portion at the non-display region of the substrate; a planarization layer at the pixel circuit portion and the peripheral circuit portion; and a light emitting portion over the planarization layer of each of the plurality of pixel regions, wherein the planarization layer at the peripheral circuit portion includes an uneven pattern portion, wherein the uneven pattern portion is configured to include a plurality of recessed portions, wherein the uneven pattern portion includes: a first uneven pattern portion provided at a first non-display region, wherein the first non-display region corresponds to a first side of the display region and includes a pad region; a second uneven pattern portion provided at each of a second non-display region corresponding to a second side of the display region and a third non-display region corresponding to a third side of the display region, wherein the third side of the display region is parallel to the second side of the display region; and a third uneven pattern portion provided at a fourth non-display region corresponding to a fourth side of the display region, wherein the fourth side of the display region is parallel to the first side of the display region, wherein a number of recesses per unit area of the first uneven pattern portion is greater than a number of recesses per unit area of each of the second uneven pattern portion and the third uneven pattern portion, or wherein a pitch between center points of two adjacent recesses provided at the first uneven pattern portion is smaller than a pitch between center points of two adjacent recesses provided at each of the second uneven pattern portion and the third uneven pattern portion.

13. The light-emitting display device according to claim 8 or 12, wherein The peripheral circuit portion includes: a plurality of pad portions provided at the pad region of the first non-display region; a link portion between each of the plurality of pad portions and the first side of the display region; a first gate driver circuit provided at the second non-display region; and a second gate driver circuit provided at the third non-display region, wherein the planarization layer is configured to be provided at a remaining portion of the peripheral circuit portion except for the pad portions and some of the link portions adjacent to the pad portions.

14. The light-emitting display device according to any one of claims 1 to 8 and 12, wherein, a size of the planarization layer is greater than a size of the display region, and / or wherein an area of the planarization layer is greater than an area of the display region.

15. The light-emitting display device according to any one of claims 1 to 8 and 12, further comprising: a counter substrate provided at a remaining portion except for an edge portion of the substrate; and an adhesive member interposed between the substrate and the counter substrate.

16. The light-emitting display device according to claim 15, wherein An edge portion of the adhesive member directly contacts the uneven pattern portion of the planarization layer provided at the non-display region.

17. The light-emitting display device according to any one of claims 1 to 8 and 12, further comprising an edge pattern layer provided along an edge portion of the substrate overlapping at least a portion of the uneven pattern portion, wherein the uneven pattern portion is provided at a first surface of the substrate, and wherein the edge pattern layer is provided at a second surface of the substrate opposite to the first surface.

18. The light-emitting display device according to claim 17, wherein The edge pattern layer has a thickness of 1.0 pm to 1.5 pm.

19. The light-emitting display device according to any one of claims 1 to 8 and 12, further comprising a color filter provided between the planarization layer and the substrate, the color filter overlapping at least some of the plurality of pixel regions.

20. The light-emitting display device according to claim 12, wherein A number of recesses per unit area of the third uneven pattern portion is greater than a number of recesses per unit area of the second uneven pattern portion.

21. The light-emitting display device according to claim 12, wherein A pitch between center points of two adjacent recesses provided at the third uneven pattern portion is smaller than a pitch between center points of two adjacent recesses provided at the second uneven pattern portion.

22. A light-emitting display device comprising: a substrate configured to include a display region having a plurality of pixel regions and a non-display region surrounding the display region; and a planarization layer provided at the display region and partially provided at the non-display region, wherein the planarization layer includes a plurality of recesses, wherein the non-display area includes: a first non-display area disposed at a first side of the display area and including a pad area; a second non-display area disposed at a second side of the display area; a third non-display area disposed at a third side parallel to the second side of the display area; and a fourth non-display area disposed at a fourth side parallel to the first side of the display area, wherein a number of recesses per unit area of the planarization layer disposed at the first non-display area is greater than a number of recesses per unit area of the planarization layer disposed at each of the second non-display area, the third non-display area, and the fourth non-display area, or wherein a pitch between center points of two adjacent recesses of the planarization layer disposed at the first non-display area is smaller than a pitch between center points of two adjacent recesses of the planarization layer disposed at each of the second non-display area, the third non-display area, and the fourth non-display area.

23. The light-emitting display device according to claim 22, wherein the planarization layer is disposed at the remaining non-display area except for the pad area; and / or wherein the planarization layer is disposed only partially at the non-display area; and / or wherein the planarization layer includes a protrusion disposed between the plurality of recesses disposed at a surface and / or has a wavy shape.

24. The light emitting display device of claim 23, wherein a number of recesses per unit area of the planarization layer disposed at the display area is the same as a number of recesses per unit area of the planarization layer disposed at the remaining non-display area except for the pad area; and / or wherein a pitch between center points of two adjacent recesses of the planarization layer disposed at the display area is the same as a pitch between center points of two adjacent recesses of the planarization layer disposed at the remaining non-display area except for the pad area.

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