Semiconductor device

Abstract

An embodiment provides a semiconductor device capable of improving avalanche tolerance. The semiconductor device of the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The third semiconductor region is provided above a part of the second semiconductor region. The fourth semiconductor region is provided above another part of the second semiconductor region, is located at a position lower than the third semiconductor region, and has a second conductivity type impurity concentration higher than that of the second semiconductor region. The second electrode includes: a first part and a second part that are separated from each other in a second direction, and the fourth semiconductor region is located between the first part and the second part; and a third part that is provided above the first part and above the second part and is arranged side by side with the third semiconductor region in the second direction. The fourth semiconductor region is in contact with the first part, the second part, and the third part.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-157486 (filing date: September 18, 2020). This application includes all the contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Art

[0004] Semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are used for applications such as power conversion. Regarding semiconductor devices, it is desired to improve avalanche tolerance. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device capable of improving avalanche tolerance.

[0006] The semiconductor device of the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided above the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided above the first semiconductor region. The third semiconductor region is provided above a part of the second semiconductor region. The fourth semiconductor region is provided above another part of the second semiconductor region, is located below the third semiconductor region, and has a higher impurity concentration of the second conductivity type than the second semiconductor region. The gate electrode is arranged side by side with a part of the first semiconductor region, the second semiconductor region, and a part of the third semiconductor region in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region with a gate insulating layer therebetween. The second electrode is provided above the gate electrode, above the third semiconductor region, and above the fourth semiconductor region, and is electrically connected to the third semiconductor region and the fourth semiconductor region. The second electrode includes: a first part and a second part that are separated from each other in the second direction, and the fourth semiconductor region is located between the first part and the second part; and a third part that is provided above the first part and above the second part and is arranged side by side with the third semiconductor region in the second direction. The fourth semiconductor region is in contact with the first part, the second part, and the third part. Description of the Drawings

[0007] Figure 1is a perspective cross-sectional view of a semiconductor device according to the first embodiment.

[0008] Figure 2 is a cross-sectional view of an enlarged part of the semiconductor device according to the first embodiment.

[0009] Figure 3 of (a) to Figure 5 of (b) is a cross-sectional view showing a manufacturing method of the semiconductor device according to the first embodiment.

[0010] Figure 6 is a cross-sectional view of a part of a semiconductor device according to the first modification of the first embodiment.

[0011] Figure 7 is a cross-sectional view of a part of a semiconductor device according to the second modification of the first embodiment.

[0012] Figure 8 is a perspective cross-sectional view of a semiconductor device according to the third modification of the first embodiment.

[0013] Figure 9 is a perspective cross-sectional view of a semiconductor device according to the second embodiment.

[0014] Figure 10 is a perspective cross-sectional view of a semiconductor device according to the third embodiment. Detailed Embodiments

[0015] Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

[0016] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as in reality. Even when showing the same part, there are cases where the sizes and ratios are shown differently according to the drawings.

[0017] In the present specification and each drawing, the same reference numerals are given to elements that are the same as those already described, and detailed descriptions are appropriately omitted.

[0018] In the following description and drawings, n + 、n、n - and p + 、p notations represent the relative levels of the respective impurity concentrations. That is, the notation with “+” appended indicates a relatively higher impurity concentration compared to the notation without either “+” or “-” appended, and the notation with “-” indicates a relatively lower impurity concentration compared to the notation without either appended. When both p-type impurities and n-type impurities are contained in each region, these notations represent the relative levels of the net impurity concentration after compensating these impurities.

[0019] Regarding each of the embodiments described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0020] (First Embodiment)

[0021] Figure 1 It is a perspective cross-sectional view showing a semiconductor device of the first embodiment.

[0022] The semiconductor device 100 of the first embodiment is a MOSFET. The semiconductor device 100 includes an n- - type (first conductivity type) drift region 1 (first semiconductor region), a p-type (second conductivity type) substrate region 2 (second semiconductor region), an n- + type semiconductor region 3 (third semiconductor region), a p- + type contact region 4 (fourth semiconductor region), an n- + type drain region 8, a lower electrode 10 (first electrode), an upper electrode 20 (second electrode), and a gate electrode 30.

[0023] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the n- - type drift region 1 toward the p-type substrate region 2 is set as the Z direction (first direction). Two directions perpendicular to the Z direction and orthogonal to each other are set as the X direction (second direction) and the Y direction (third direction). In addition, for the sake of explanation, the direction from the n- - type drift region 1 toward the p-type substrate region 2 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the n- - type drift region 1 and the p-type substrate region 2 and have nothing to do with the direction of gravity.

[0024] The lower electrode 10 is provided on the lower surface of the semiconductor device 100. The n- + type drain region 8 is provided above the lower electrode 10 and is electrically connected to the lower electrode 10. The n- - type drift region 1 is provided above the n- + type drain region 8. The n- - type drift region 1 is electrically connected to the lower electrode 10 via the n- + type drain region 8. The n-type impurity concentration in the n- - type drift region 1 is lower than the n-type impurity concentration in the n- + type drain region 8.

[0025] The p-type substrate region 2 is provided above the n- - type drift region 1. The n- + type semiconductor region 3 is provided above a part of the p-type substrate region 2. The p- +The p-type contact region 4 is disposed above another part of the p-type base region 2. p + The p-type contact region 4 is located at a position lower than that of the n + -type semiconductor region 3. The p + -type impurity concentration in the p-type contact region 4 is higher than the p-type impurity concentration in the p-type base region 2. The gate electrode 30 is separated from a part of the n - -type drift region 1, the p-type base region 2, and a part of the n + -type semiconductor region 3 in the X direction with the gate insulating layer 31 therebetween.

[0026] The upper electrode 20 is disposed above the n + -type semiconductor region 3, the p + -type contact region 4, and the gate electrode 30, and is electrically connected to the n + -type semiconductor region 3 and the p + -type contact region 4. The p-type base region 2 is electrically connected to the upper electrode 20 via the p + -type contact region 4. The upper electrode 20 is electrically separated from the gate electrode 30.

[0027] Figure 2 It is a cross-sectional view showing an enlarged part of the semiconductor device of the first embodiment.

[0028] As Figure 1 and Figure 2 shown, the upper electrode 20 includes a first part 21, a second part 22, and a third part 23.

[0029] The first part 21 and the second part 22 are located at positions lower than that of the n + -type semiconductor region 3 and are separated from each other in the X direction. The p + -type contact region 4 is located between the first part 21 and the second part 22. The first part 21 and the second part 22 are separated from the gate insulating layer 31 in the X direction. The third part 23 is disposed above the p + -type contact region 4, above the first part 21, and above the second part 22. The third part 23 is arranged side by side with the n + -type semiconductor region 3 in the X direction. The p + -type contact region 4 is in contact with the first part 21, the second part 22, and the third part 23.

[0030] The lower ends of the first part 21 and the second part 22 are separated from the n - -type drift region 1 in the Z direction. The lower ends of the first part 21 and the second part 22 are located at a position higher than that of the p +At a position below the lower end of the p-type contact region 4 and in contact with the p-type base region 2. For example, the length of the first portion 21 in the X direction is shorter than the length of the first portion 21 in the Z direction. The length of the second portion 22 in the X direction is shorter than the length of the second portion 22 in the Z direction.

[0031] For example, the p-type base region 2, n + -type semiconductor region 3, p + -type contact region 4, the first portion 21, the second portion 22, the third portion 23, and the gate electrode 30 are provided in multiple numbers in the X direction. Above each p-type base region 2, a pair of n + -type semiconductor regions 3 separated from each other in the X direction are provided. The third portion 23 is located between the pair of n + -type semiconductor regions 3. Each p-type base region 2, each n + -type semiconductor region 3, each p + -type contact region 4, each first portion 21, each second portion 22, each third portion 23, and each gate electrode 30 extend in the Y direction.

[0032] The operation of the semiconductor device 100 will be described.

[0033] In a state where a voltage positive with respect to the upper electrode 20 is applied to the lower electrode 10, a voltage higher than the threshold value is applied to the gate electrode 30. A channel (inversion layer) is formed in the p-type base region 2. Electrons flow through the channel and the n - -type drift region 1 toward the lower electrode 10. As a result, the semiconductor device 100 becomes in a conductive state. After that, if the voltage applied to the gate electrode 30 becomes lower than the threshold value, the channel in the p-type base region 2 disappears, and the semiconductor device 100 becomes in a cutoff state.

[0034] When the semiconductor device 100 switches from the conductive state to the cutoff state, the electric field strength in the n - -type drift region 1 increases, and avalanche breakdown may occur temporarily. If avalanche breakdown occurs, a large number of holes and electrons are generated. The electrons are discharged toward the lower electrode 10, and the holes are discharged toward the upper electrode 20 through the p-type base region 2 and the p + -type contact region 4.

[0035] An example of the material of each component of the semiconductor device 100 will be described.

[0036] n - -type drift region 1, p-type base region 2, n + -type semiconductor region 3, p + -type contact region 4, and n +The drain region 8 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. In the case of using silicon as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The gate electrode 30 includes a conductive material such as polysilicon. The gate insulating layer 31 includes an insulating material such as silicon oxide. The lower electrode 10 and the upper electrode 20 include metals such as titanium, tungsten, and aluminum.

[0037] As Figure 2 shown, the upper electrode 20 may also include a plurality of metal layers 20a to 20d. The metal layer 20a includes titanium. The metal layer 20b includes titanium nitride. The metal layer 20c includes tungsten. The metal layer 20d includes aluminum. The metal layer 20a is disposed along the surfaces of the p-type substrate region 2, the n + -type semiconductor region 3, and the p + -type contact region 4. The metal layer 20b is disposed above the metal layer 20a along the metal layer 20a. The metal layer 20c is disposed above the metal layer 20b and fills the space between the n + -type semiconductor regions 3. The metal layer 20d is disposed above the metal layer 20c. The first portion 21, the second portion 22, and the third portion 23 include respective portions of the metal layers 20a to 20c.

[0038] Figures 3 to 5 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment.

[0039] An example of a method of manufacturing the semiconductor device 100 according to the embodiment will be described. First, a substrate Sub including an n + -type semiconductor layer 8a and an n + -type semiconductor layer 1a is prepared. The n - -type semiconductor layer 1a is disposed above the n + -type semiconductor layer 8a. P-type impurities are ion-implanted into the upper surface of the substrate Sub to form a p-type semiconductor region 2a. By reactive ion etching (RIE), openings OP1 are formed in the upper surface of the substrate Sub. A plurality of openings OP1 are formed in the X direction, and each opening OP1 extends in the Y direction. The openings OP1 are arranged side by side with a part of the n - -type semiconductor layer 1a and the p-type semiconductor region 2a in the X direction.

[0040] The substrate Sub is thermally oxidized to form an insulating layer 31a. The insulating layer 31a is formed along the inner surfaces of the respective openings OP1 and the upper surfaces of the respective p-type semiconductor regions 2a. As Figure 3 shown in (a) of, a conductive layer 30a that fills the plurality of openings OP1 is formed above the insulating layer 31a by chemical vapor deposition (CVD). The conductive layer 30a includes polysilicon.

[0041] By wet etching or chemical dry etching (CDE), the upper surface of the conductive layer 30a is recessed until the upper surface of the conductive layer 30a is positioned below the upper surface of each p-type semiconductor region 2a. As a result, the conductive layer 30a is divided into a plurality of parts, and gate electrodes 30 are formed inside each opening OP1. By thermal oxidation, an insulating layer 31b is formed on the upper surface of each gate electrode 30. N-type impurities are ion-implanted into the upper surface of the p-type semiconductor region 2a to form an n + -type semiconductor region 3a. As shown in Figure 3 (b), an insulating layer 31c that fills a plurality of openings OP1 is formed above the insulating layers 31a and 31b by CVD. The insulating layer 31c contains silicon oxide.

[0042] By RIE, a part of the insulating layer 31c, the insulating layer 31a, the n + -type semiconductor region 3a, and the p-type semiconductor region 2a is removed to form an opening OP2. By CVD, an insulating layer 41a is formed along the inner surface of the opening OP2 and the upper surface of the insulating layer 31c. The insulating layer 41a contains silicon nitride. By CVD, as shown in Figure 4 (a), an insulating layer 42a is formed inside the opening OP2. The insulating layer 42a contains silicon oxide.

[0043] By wet etching, a part of the insulating layer 41a formed along the side surface of the opening OP2 is removed. As a result, the insulating layers 41b and 42a remain above a part of the p-type semiconductor region 2a. Using the insulating layers 41b and 42a as a mask, another part of the p-type semiconductor region 2a is removed by RIE. As a result, as shown in Figure 4 (b), a pair of openings OP3 are formed at the bottom of the opening OP2.

[0044] The insulating layer 42a is removed. By thermal oxidation, an insulating layer 43a is formed inside each opening OP3. As shown in Figure 5 (a), p-type impurities are ion-implanted into the p-type semiconductor region 2a between the insulating layers 43a to form a p + -type contact region 4.

[0045] The insulating layers 41b and 43a are removed by wet etching. An upper electrode 20 that fills the upper parts of the opening OP2 and the opening OP3 is formed. When the insulating layers 41b and 43a are removed, the side surfaces of the insulating layer 31a and the side surfaces of the insulating layer 31c may also be recessed in the X direction. As a result, the contact area between the n + -type semiconductor region 3a and the upper electrode 20 can be increased. As the upper electrode 20, a plurality of metal layers 20a to 20d may be formed as shown in Figure 2 . For example, the metal layers 20a to 20c are formed by CVD. The metal layer 20d is formed by sputtering. For the n+ The back surface of the n-type semiconductor layer 8a is polished until the n- + type semiconductor layer 8a reaches a specified thickness. As shown in Figure 5 (b) of FIG., a lower electrode 10 is formed on the back surface of the n- + type semiconductor layer 8a. Through the above steps, the semiconductor device 100 of the first embodiment is manufactured.

[0046] The effects of the first embodiment will be described.

[0047] The semiconductor device 100 includes an npn parasitic bipolar transistor (hereinafter referred to as a parasitic transistor) composed of an n- - type drift region 1, a p-type base region 2, and an n- + type semiconductor region 3. As described above, at the time of avalanche breakdown, holes are discharged through the p-type base region 2 and the p- + type contact region 4. At this time, the lower the resistance to holes, the more the voltage drop caused by the flow of holes can be reduced. By reducing the voltage drop, the rise in the potential of the p-type base region 2 is suppressed, and the operation of the parasitic transistor can be suppressed.

[0048] In the semiconductor device 100, the upper electrode 20 includes a first portion 21 to a third portion 23. The p- + type contact region 4 is in contact with the first portion 21 to the third portion 23. Thus, compared with the case where the upper electrode 20 does not include the first portion 21 and the second portion 22, the contact area between the p- + type contact region 4 and the upper electrode 20 can be increased. Due to the increase in the contact area, the discharge path of holes to the upper electrode 20 increases, and the resistance to holes is reduced. As a result, the operation of the parasitic transistor can be suppressed. That is, the avalanche tolerance of the semiconductor device 100 can be improved.

[0049] In addition, as shown in Figure 4 (b) of FIG. and Figure 5 (a) of FIG., an insulating layer 43a is formed in each opening OP3 for setting the first portion 21 and the second portion 22, and then p-type impurities are ion-implanted between the insulating layers 43a to form a p- + type contact region 4. When activating the p-type impurities, the diffusion in the X direction is suppressed by the insulating layer 43a. For example, even when the position of the opening OP3 is shifted, the diffusion of p-type impurities to the vicinity of the gate insulating layer 11 can be suppressed. Thereby, the deviation of the threshold voltage of each semiconductor device 100 can be suppressed, and the reliability of the semiconductor device 100 can be improved.

[0050] For example, the length of each of the first portion 21 and the second portion 22 in the X direction is compared with that of the p- +The length in the X direction of the p-type contact region 4 is short. Thus, the contact area between the p-type contact region 4 and the first to third portions 21 to 23 can be further increased, and the resistance to holes can be reduced. +

[0051] From the viewpoints of improving the avalanche withstand voltage and ease of processing, the ratio of the length in the Z direction to the length in the X direction of the first portion 21 is preferably greater than 1 and less than 20. The ratio of the length in the Z direction to the length in the X direction of the second portion 22 is preferably greater than 1 and less than 20.

[0052] (First modification example)

[0053] Figure 6 It is a cross-sectional view showing a part of a semiconductor device according to a first modification example of the first embodiment.

[0054] Figure 6 Compared with the semiconductor device 100, the semiconductor device 110 shown further includes a p-type contact region 5a (fifth semiconductor region) and a p-type contact region 5b. + +

[0055] p + The p-type contact region 4, the first portion 21, and the second portion 22 are disposed in the X direction between the p-type contact regions 5a and 5b. The first portion 21 is disposed in the X direction between the p-type contact regions 4 and 5a. The second portion 22 is disposed in the X direction between the p-type contact regions 4 and 5b. + + + + The p-type contact regions 5a and 5b are in contact with the first portion 21 and the second portion 22, respectively, and are separated from the gate insulating layer 11.

[0056] When the p-type contact regions 5a and 5b are provided, holes flowing into the p-type base region 2 at the time of avalanche breakdown are discharged to the upper electrode 20 through the p-type contact regions 4, 5a, and 5b. By providing the p-type contact regions 5a and 5b, the discharge path of holes to the upper electrode 20 is increased, and the resistance to holes can be further reduced. + + +

[0057] For example, the p-type impurity concentration in the p-type contact region 5a is lower than the p-type impurity concentration in the p-type contact region 4. The p-type impurity concentration in the p-type contact region 5b is lower than the p-type impurity concentration in the p-type contact region 4. + + + +The p-type impurity concentration in the type contact region 4. Thus, the p- + influence of the type contact regions 5a and 5b on the threshold voltage can be reduced. For example, the increase in the threshold voltage can be suppressed. The deviation of the threshold voltage due to the deviation of the impurity concentration and position of the p- + type contact regions 5a and 5b can be suppressed.

[0058] p- + type contact regions 5a and 5b can be formed simultaneously with the p- + type contact region 4. Specifically, when performing the process shown in (a) of Figure 5 , if the width (the length in the X direction) of the insulating layer 43a is narrow, a part of the p-type impurity diffuses through the insulating layer 43a. In other words, the width of the insulating layer 43a is the size in the X direction of the opening OP3. The p-type impurity that diffuses through the insulating layer 43a forms the p- + type contact regions 5a and 5b that are in contact with the insulating layer 43a. After that, the insulating layer 43a is removed, and the upper electrode 20 is formed, thereby forming the p- + type contact regions 5a and 5b that are in contact with the first part 21 and the second part 22 respectively.

[0059] According to this method, by adjusting the width of the insulating layer 43a, the widths and the p-type impurity concentration of the p- + type contact regions 5a and 5b can be controlled. In addition, by making the p-type impurity diffuse through the insulating layer 43a, the diffusion of the p-type impurity to the vicinity of the insulating layer 31a can be suppressed.

[0060] (Second modified example)

[0061] Figure 7 is a cross-sectional view showing a part of a semiconductor device according to a second modified example of the first embodiment.

[0062] Figure 7 Compared with the semiconductor device 100, the semiconductor device 120 shown further includes p- + type contact region 6a (sixth semiconductor region) and p- + type contact region 6b.

[0063] p- + type contact region 6a is provided between the bottom of the first part 21 and the p-type base region 2. The p- + type contact region 6b is provided between the bottom of the second part 22 and the p-type base region 2. The p- + type contact regions 6a and 6b are in contact with the first part 21 and the second part 22 respectively. At least a part of the p- + type contact region 6a and at least a part of the p- + type contact region 6b are located deeper than the p-+ position below the p-type contact region 4. p + The p-type contact regions 6a and 6b can also be connected to the p + type contact region 4.

[0064] For example, the first part 21 is located in the Z direction between the p + type contact region 6a and the third part 23. The second part 22 is located in the Z direction between the p + type contact region 6b and the third part 23. p + The p-type contact regions 6a and 6b are separated from the n - type drift region 1 in the Z direction.

[0065] When the p + type contact regions 6a and 6b are provided, holes flowing toward the p-type substrate region 2 during avalanche breakdown are discharged upward through the p + type contact regions 4, 6a, and 6b. By providing the p + type contact regions 6a and 6b, the resistance to holes can be further reduced.

[0066] For example, the p + type impurity concentration in the p-type contact region 6a is preferably lower than the p + type impurity concentration in the p-type contact region 4. p + type impurity concentration in the p-type contact region 6b is preferably lower than the p + type impurity concentration in the p-type contact region 4. p + The distance in the X direction between the p-type contact region 6a and the gate insulating layer 31 is shorter than the p + distance in the X direction between the p-type contact region 4 and the gate insulating layer 31. p + The distance in the X direction between the p-type contact region 6b and the gate insulating layer 31 is shorter than the p + distance in the X direction between the p-type contact region 4 and the gate insulating layer 31. By making the p + type impurity concentration in each of the p-type contact regions 6a and 6b lower than the p + type impurity concentration in the p-type contact region 4, the influence of the p + type contact regions 6a and 6b on the threshold voltage can be reduced. For example, the rise of the threshold voltage can be suppressed. The deviation of the threshold voltage due to the p + type contact regions 6a and 6b can be suppressed due to the deviation of the impurity concentration and position.

[0067] p + type contact regions 6a and 6b are, for example, formed by Figure 4It is formed by ion-implanting a p-type impurity into the bottom of the opening OP3 at any time after the opening OP3 is formed and before the insulating layer 43a is formed, as shown in (b).

[0068] Similar to the first modification, the semiconductor device 120 may further include p + type contact regions 5a and 5b. Thereby, the resistance to holes during avalanche breakdown can be further reduced. The p + type contact regions 6a and 6b may be connected to the p + type contact regions 5a and 5b, respectively.

[0069] (Third Modification)

[0070] Figure 8 FIG. is a perspective cross-sectional view of a semiconductor device according to a third modification of the first embodiment.

[0071] Figure 8 The semiconductor device 130 shown includes a conductive portion 35 in addition to the semiconductor device 100.

[0072] The conductive portion 35 is disposed in the n - type drift region 1 with an insulating layer 36 interposed therebetween. The gate electrode 30 is disposed above the conductive portion 35 with an insulating layer 37 interposed therebetween. The gate electrode 30 is electrically separated from the conductive portion 35. The conductive portion 35 extends in the Y direction. For example, the end portion of the conductive portion 35 in the Y direction is lifted upward and is electrically connected to the upper electrode 20 via the connection portion 35c.

[0073] When the semiconductor device 130 is in the off state, due to the potential difference between the n - type drift region 1 and the conductive portion 35, the depletion layer extends from the interface between the n - type drift region 1 and the insulating layer 36 toward the n - type drift region 1. By the extension of this depletion layer, the breakdown voltage of the semiconductor device 130 can be increased. Alternatively, while maintaining the breakdown voltage of the semiconductor device 130, by increasing the n-type impurity concentration in the n - type drift region 1, the on-resistance of the semiconductor device 130 can be reduced.

[0074] Similar to the first modification, the semiconductor device 130 may further include p + type contact regions 5a and 5b. Alternatively, similar to the second modification, the semiconductor device 130 may further include p + type contact regions 6a and 6b.

[0075] (Second Embodiment)

[0076] Figure 9 FIG. is a perspective cross-sectional view of a semiconductor device according to the second embodiment.

[0077] Figure 9 The difference between the semiconductor device 200 shown and the semiconductor device 100 is that it includes a p + -type collector region 7 (seventh semiconductor region) and an n-type buffer region 9 instead of the n + -type drain region 8. The semiconductor device 200 is an IGBT.

[0078] The p + -type collector region 7 is disposed between the lower electrode 10 and the n - -type drift region 1 and is electrically connected to the lower electrode 10. The n-type buffer region 9 is disposed between the p + -type collector region 7 and the n - -type drift region 1. The n-type impurity concentration in the n-type buffer region 9 is higher than the n-type impurity concentration in the n - -type drift region 1.

[0079] The operation of the semiconductor device 200 will be described.

[0080] With the lower electrode 10 being applied with a voltage positive with respect to the upper electrode 20, a voltage higher than the threshold is applied to the gate electrode 30. A channel (inversion layer) is formed in the p-type substrate region 2. Electrons flow through the channel and the n - -type drift region 1 toward the lower electrode 10. Holes are injected from the lower electrode 10 into the n - -type drift region 1. Thus, the semiconductor device 200 becomes in a conducting state. Electrons and holes are injected into the n - -type drift region 1 to generate conductivity modulation, whereby the resistance of the semiconductor device 200 is significantly reduced. Thereafter, if the voltage applied to the gate electrode 30 becomes lower than the threshold, the channel in the p-type substrate region 2 disappears and the semiconductor device 200 becomes in a cutoff state.

[0081] When the semiconductor device 200 switches to the cutoff state, the holes accumulated in the n - -type drift region 1 are discharged upward to the upper electrode 20 through the p-type substrate region 2 and the p + -type contact region 4. Therefore, in the semiconductor device 200, since the upper electrode 20 includes the first portion 21 to the third portion 23, the resistance to holes can be reduced. According to the second embodiment, similarly to the first embodiment, the avalanche withstand of the semiconductor device 200 can be improved.

[0082] The semiconductor device 200 may also include p + -type contact regions 5a and 5b in the same manner as the first modification of the first embodiment. Alternatively, the semiconductor device 200 may also include p +Type contact regions 6a and 6b.

[0083] (Third Embodiment)

[0084] Figure 10 is a perspective cross-sectional view showing a semiconductor device of the third embodiment.

[0085] The semiconductor device 300 of the third embodiment is different from the semiconductor device 100 in that it includes a first insulating portion 41 and a second insulating portion 42 instead of the first portion 21 and the second portion 22.

[0086] The first insulating portion 41 and the second insulating portion 42 are located below the n + -type semiconductor region 3 and are separated from each other in the X direction. The p + -type contact region 4 is provided between the first insulating portion 41 and the second insulating portion 42. The first insulating portion 41 and the second insulating portion 42 are separated from the gate insulating layer 31 in the X direction.

[0087] The upper electrode 20 includes an electrode portion 25. The electrode portion 25 corresponds to the third portion 23 of the semiconductor device 100. The electrode portion 25 is provided above the p + -type contact region 4, the first insulating portion 41, and the second insulating portion 42. The electrode portion 25 is arranged side by side with the n + -type semiconductor region 3 in the X direction. The p + -type contact region 4 is in contact with the first insulating portion 41, the second insulating portion 42, and the electrode portion 25.

[0088] For example, the lower ends of the first insulating portion 41 and the second insulating portion 42 are separated from the n - -type drift region 1 in the Z direction. The lower ends of the first insulating portion 41 and the second insulating portion 42 are located below the lower end of the p + -type contact region 4 and are in contact with the p-type substrate region 2.

[0089] The first insulating portion 41 and the second insulating portion 42 are formed after the process shown in (a) of Figure 5 without removing the insulating layer 43a in the opening OP3, but only removing the insulating layer 43a above the opening OP3. After forming the first insulating portion 41 and the second insulating portion 42, the upper electrode 20 is formed in the same manner as the process shown in (b) of Figure 5 .

[0090] According to the semiconductor device 300, when forming the p +When the p-type impurity diffuses in the X direction at the type contact region 4, the diffusion is suppressed by the first insulating portion 41 and the second insulating portion 42. For example, even when the position of the opening OP3 is shifted, the diffusion of the p-type impurity to the vicinity of the gate insulating layer 11 can be suppressed. As a result, the deviation of the threshold voltage of each semiconductor device 300 can be suppressed, and the reliability of the semiconductor device 300 can be improved.

[0091] As described above, several embodiments of the present invention have been illustrated, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope. In addition, the foregoing embodiments can be implemented in combination with each other.

Claims

1. A semiconductor device, comprising: A first electrode; A first semiconductor region of a first conductivity type, disposed above the first electrode and electrically connected to the first electrode; A second semiconductor region of a second conductivity type, disposed above the first semiconductor region; A third semiconductor region of a first conductivity type, disposed above a part of the second semiconductor region; A fourth semiconductor region of a second conductivity type, disposed above another part of the second semiconductor region, located at a position lower than the third semiconductor region, and having a higher impurity concentration of the second conductivity type than the second semiconductor region; A gate electrode, arranged side by side with a part of the first semiconductor region, the second semiconductor region, and a part of the third semiconductor region in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region, with a gate insulating layer therebetween; And A second electrode, disposed above the gate electrode, above the third semiconductor region, and above the fourth semiconductor region, and electrically connected to the third semiconductor region and the fourth semiconductor region, The second electrode includes: A first part and a second part, separated from each other in the second direction, and the fourth semiconductor region is located between the first part and the second part; And A third part, disposed above the first part and above the second part, and arranged side by side with the third semiconductor region in the second direction, The lower end of the first part and the lower end of the second part are separated from the first semiconductor region in the first direction and in contact with the second semiconductor region, and the fourth semiconductor region is in contact with the first part, the second part, and the third part.

2. The semiconductor device according to claim 1, Further comprising a fifth semiconductor region of a second conductivity type in contact with the first portion, The impurity concentration of the second conductivity type in the fifth semiconductor region is higher than the impurity concentration of the second conductivity type in the second semiconductor region, The fifth semiconductor region is separated from the gate insulating layer, The first portion is located between the fourth semiconductor region and the fifth semiconductor region in the second direction.

3. The semiconductor device according to claim 2, The impurity concentration of the second conductivity type in the fifth semiconductor region is lower than the impurity concentration of the second conductivity type in the fourth semiconductor region.

4. The semiconductor device according to any one of claims 1 to 3, The ratio of the length of the first portion in the first direction to the length of the first portion in the second direction is greater than 1 and less than 20, The ratio of the length of the second portion in the first direction to the length of the second portion in the second direction is greater than 1 and less than 20.

5. The semiconductor device according to any one of claims 1 to 3, The length of the first portion in the second direction and the length of the second portion in the second direction are each shorter than the length of the fourth semiconductor region in the second direction.

6. The semiconductor device according to any one of claims 1 to 3, It also has a seventh semiconductor region of a second conductivity type, and the seventh semiconductor region of the second conductivity type is disposed between the first electrode and the first semiconductor region.

7. A semiconductor device includes: A first electrode; A first semiconductor region of a first conductivity type, disposed above the first electrode and electrically connected to the first electrode; A second semiconductor region of a second conductivity type, disposed above the first semiconductor region; A third semiconductor region of a first conductivity type, disposed above a part of the second semiconductor region; A fourth semiconductor region of a second conductivity type, disposed above another part of the second semiconductor region, located at a position lower than the third semiconductor region, and having a higher impurity concentration of the second conductivity type than the second semiconductor region; A gate electrode, arranged side by side with a part of the first semiconductor region, the second semiconductor region, and a part of the third semiconductor region in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region, with a gate insulating layer therebetween; A second electrode, disposed above the gate electrode, above the third semiconductor region, and above the fourth semiconductor region, and electrically connected to the third semiconductor region and the fourth semiconductor region. The second electrode includes: a first part and a second part, separated from each other in the second direction, and the fourth semiconductor region is located between the first part and the second part; and a third part, disposed above the first part and above the second part, and arranged side by side with the third semiconductor region in the second direction, and the fourth semiconductor region is in contact with the first part, the second part, and the third part; And A fifth semiconductor region of a second conductivity type, which is in contact with the first portion and separated from the gate insulating layer. The impurity concentration of the second conductivity type in the fifth semiconductor region is higher than that in the second semiconductor region. The first portion is located between the fourth semiconductor region and the fifth semiconductor region in the second direction.

8. A semiconductor device includes: A first electrode; A first semiconductor region of a first conductivity type, disposed above the first electrode and electrically connected to the first electrode; A second semiconductor region of a second conductivity type, disposed above the first semiconductor region; A third semiconductor region of a first conductivity type, disposed above a part of the second semiconductor region; A fourth semiconductor region of a second conductivity type, disposed above another part of the second semiconductor region, at a position lower than the third semiconductor region, and having a higher impurity concentration of the second conductivity type than the second semiconductor region; A gate electrode, which is arranged side by side with a part of the first semiconductor region, the second semiconductor region, and a part of the third semiconductor region across the gate insulating layer in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; A second electrode, disposed above the gate electrode, above the third semiconductor region, and above the fourth semiconductor region, and electrically connected to the third semiconductor region and the fourth semiconductor region. The second electrode includes: a first portion and a second portion, which are separated from each other in the second direction, and the fourth semiconductor region is located between the first portion and the second portion; and a third portion, disposed above the first portion and above the second portion, and arranged side by side with the third semiconductor region in the second direction. The fourth semiconductor region is in contact with the first portion, the second portion, and the third portion; and A sixth semiconductor region of a second conductivity type, which is disposed between the bottom of the first portion and the second semiconductor region, in contact with the first portion, and the impurity concentration of the second conductivity type in the sixth semiconductor region is higher than that in the second semiconductor region.

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