Drive circuit and inverter device

Abstract

The purpose is to obtain a drive circuit and an inverter device that can achieve high-speed operation. The drive circuit of the present invention has: a first drive unit that controls the on-off of the upper bridge arm of the inverter circuit; a second drive unit that controls the on-off of the lower bridge arm of the inverter circuit; a first switch element that has a first terminal connected to the power supply supplied to the first drive unit, a second terminal connected to the power supply supplied to the second drive unit, and a control terminal; a boost circuit that boosts a control signal that is high when the lower bridge arm is in an on state and low when the lower bridge arm is in an off state to turn on the first switch element; a second switch element that conducts between the control terminal and the boost circuit when the control signal is high, and disconnects between the control terminal and the boost circuit when the control signal is low; and a first switch unit that short-circuits the control terminal and the grounding terminal when the control signal is low.

Description

Technical Field

[0001] The invention relates to a drive circuit and an inverter device. Background Art

[0002] Patent Document 1 discloses a bootstrap diode simulation circuit for use in a half-bridge switching circuit. The half-bridge switching circuit includes transistors connected to each other in a totem pole configuration at a load node and a drive circuit for driving the transistors. In addition, the half-bridge switching circuit includes a bootstrap capacitor for supplying power to the drive circuit on the high voltage side.

[0003] The bootstrap diode simulation circuit has an LDMOS transistor. The LDMOS transistor has a gate, a back gate, a source, and a drain. The drain of the LDMOS transistor is coupled to a high-voltage side supply node, and the source is coupled to a low-voltage side supply node. A gate control circuit is electrically coupled to the gate of the LDMOS transistor. A dynamic back gate bias circuit is electrically coupled to the back gate of the LDMOS transistor. The dynamic back gate bias circuit can operate in a manner that a voltage close to the drain voltage of the LDMOS transistor but slightly lower is applied to the back gate when the LDMOS is turned on, so that the back gate is dynamically biased.

[0004] Patent Document 1: Japanese Patent Application No. 2007-513543

[0005] In Patent Document 1, the transition of the LDMOS transistor to the off state is achieved by setting the voltage across the capacitor connected to the gate of the LDMOS transistor to 0 V. In this structure, when the LDMOS transistor transitions to the on state, the capacitor needs to be charged from 0 V. Therefore, the transition to the on state may take time. Summary of the invention

[0006] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a drive circuit and an inverter device capable of high-speed operation.

[0007] The drive circuit of the present invention comprises: a first drive unit, which controls the on-off of an upper bridge arm of an inverter circuit; a second drive unit, which controls the on-off of a lower bridge arm of the inverter circuit; a first switch element, which comprises a first terminal, a second terminal and a control terminal for controlling the on-off between the first terminal and the second terminal, wherein the first terminal is connected to a power supply supplied to the first drive unit, and the second terminal is connected to a power supply supplied to the second drive unit; a boost circuit, which boosts a control signal which is a high level when the lower bridge arm is in an on state and a low level when the lower bridge arm is in an off state, and supplies the control signal to the control terminal, thereby making the first bridge arm in an on state. 1 switch element is turned on; a second switch element, which is connected between the control terminal and the boost circuit, conducts between the control terminal and the boost circuit when the control signal is at the high level, and disconnects between the control terminal and the boost circuit when the control signal is at the low level; and a first switch unit, which disconnects between the control terminal and the ground terminal when the control signal is at the high level, and short-circuits the control terminal and the ground terminal when the control signal is at the low level. If the first switch element is turned on, current flows from the power supply supplied to the second drive unit to the power supply supplied to the first drive unit, and the power supply supplied to the first drive unit is charged.

[0008] The inverter device of the present invention comprises: an inverter circuit having an upper bridge arm and a lower bridge arm; a drive circuit; and a first power supply connected between a connection point between the upper bridge arm and the lower bridge arm and the drive circuit, the drive circuit comprising: a first drive unit supplied with the first power supply to control the on-off of the upper bridge arm; a second drive unit supplied with a second power supply to control the on-off of the lower bridge arm; a first switching element having a first terminal, a second terminal and a control terminal for controlling the on-off between the first terminal and the second terminal, the first terminal being connected to the first power supply, and the second terminal being connected to the second power supply; a boost circuit which controls the on-off of the lower bridge arm by switching the first terminal to the second terminal when the lower bridge arm is in the on state. When the lower bridge arm is in the disconnected state, the control signal of the low level is boosted and supplied to the control terminal, thereby turning on the first switch element; the second switch element is connected between the control terminal and the boost circuit, and makes the control terminal and the boost circuit conductive when the control signal is at the high level, and disconnects the control terminal and the boost circuit when the control signal is at the low level; and the first switch unit disconnects the control terminal and the grounding terminal when the control signal is at the high level, and short-circuits the control terminal and the grounding terminal when the control signal is at the low level. If the first switch element is turned on, current flows from the second power supply to the first power supply, and the first power supply is charged.

[0009] Effects of the Invention

[0010] In the drive circuit and inverter device according to the present invention, a second switch element is provided to disconnect the boost circuit from the control terminal of the first switch element. Therefore, the first switch element can be turned off in a state where electric charge is accumulated in the boost circuit. Therefore, the transition of the first switch element to the on state can be accelerated, and high-speed operation can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a diagram showing the configuration of the inverter device according to the first embodiment.

[0012] Figure 2 It is a diagram showing waveforms of the inverter device according to the first embodiment.

[0013] Figure 3 This is a diagram showing the configuration of a drive circuit according to the first embodiment.

[0014] Figure 4 This is a diagram for explaining the structure of the back gate bias circuit according to the first embodiment.

[0015] Figure 5 It is a diagram showing the structure of an inverter device according to the first comparative example.

[0016] Figure 6 It is a diagram showing the structure of an inverter device according to the second comparative example.

[0017] Figure 7 It is a diagram showing the structure of an inverter device according to the third comparative example.

[0018] Figure 8 It is a diagram showing the structure of a driving circuit according to the third comparative example.

[0019] Fig. 9 It is a diagram showing waveforms of the inverter device according to the third comparative example.

[0020] Fig.10 This is a diagram for explaining the operation of the driving circuit according to the third comparative example.

[0021] Fig.11 This is a diagram showing waveforms of the driving circuit according to the first embodiment.

[0022] Fig.12 This is a diagram showing a configuration of a drive circuit according to a modification of the first embodiment.

[0023] Fig.13 This is a diagram showing the structure of a driving circuit according to the second embodiment.

[0024] Fig.14 It is a cross-sectional view of an LDMOS transistor, namely, a first switching element.

[0025] Fig.15 It is a cross-sectional view of a first switching element according to the second embodiment.

[0026] Fig.16 This is a diagram showing the structure of a driving circuit according to the third embodiment.

[0027] Fig.17 This is a diagram for explaining the function of the booster circuit according to the third embodiment.

[0028] Fig.18 This is a diagram for explaining the functions of the clamp circuit and the timer circuit according to the third embodiment.

[0029] Fig.19 This is a diagram showing the structure of a driving circuit according to a fourth embodiment.

[0030] Fig. 20 This is a diagram showing an example of a VS potential detection circuit according to a fourth embodiment.

[0031] Fig.21 This is a diagram showing a modification of the VS potential detection circuit according to the fourth embodiment.

[0032] Fig. 22 This is a diagram showing the structure of a driving circuit according to the fifth embodiment.

[0033] Fig.23 This is a diagram showing the structure of a driving circuit according to a sixth embodiment.

[0034] Fig.24 This is a diagram showing waveforms of a driving circuit according to the sixth embodiment. DETAILED DESCRIPTION

[0035] The drive circuit and inverter device according to each embodiment of the present invention will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and repeated descriptions may be omitted. In addition, when a connection is mentioned below, an electrical connection is included.

[0036] Implementation method 1.

[0037] Figure 1 1 is a diagram showing a configuration of an inverter device 1 according to Embodiment 1. The inverter device 1 includes an inverter circuit 80, a drive circuit 100, and a power supply VB.

[0038] The inverter circuit 80 includes an upper arm 81 and a lower arm 82 connected in series with the upper arm 81. The upper arm 81 and the lower arm 82 each include a switching element such as an IGBT (Insulated Gate Bipolar Transistor) and a freewheeling diode. A load 90 is connected to the connection point between the upper arm 81 and the lower arm 82.

[0039] The drive circuit 100 drives the inverter circuit 80. The drive circuit 100 is also called HVIC (High Voltage IC). The drive circuit 100 includes a signal control unit 23, a first drive unit 21 that controls the on / off of the upper bridge arm 81, and a second drive unit 22 that controls the on / off of the lower bridge arm 82.

[0040] Furthermore, the drive circuit 100 has a first power terminal 13 connected to the power supply VB supplied to the first drive unit 21 and a second power terminal 10 connected to the power supply VCC supplied to the second drive unit 22. In addition, the drive circuit 100 has a power terminal 15 and a ground terminal 17. The power supply VB is connected between the connection point of the upper bridge arm 81 and the lower bridge arm 82 and the first power terminal 13. The power supply VCC is connected between the second power terminal 10 and the ground terminal 17. The voltage VS at the connection point of the upper bridge arm 81 and the lower bridge arm 82 is input to the power terminal 15. VS is a power supply reference on the high voltage side, and GND is a power supply reference on the low voltage side.

[0041] Furthermore, the drive circuit 100 has signal input terminals 11, 12 and signal output terminals 14, 16. A high-voltage side control signal HIN is input to the signal input terminal 11. A low-voltage side control signal LIN is input to the signal input terminal 12. A control terminal for controlling the on-off of the switch element of the upper bridge arm 81 is connected to the signal output terminal 14. A control terminal for controlling the on-off of the switch element of the lower bridge arm 82 is connected to the signal output terminal 16.

[0042] The first drive unit 21 receives the high-voltage side control signal HIN via the signal control unit 23. The first drive unit 21 outputs the high-voltage side output signal HO from the signal output terminal 14 according to the high-voltage side control signal HIN, and controls the on-off of the upper bridge arm 81. The second drive unit 22 receives the low-voltage side control signal LIN via the signal control unit 23. The second drive unit 22 outputs the low-voltage side output signal LO from the signal output terminal 16 according to the low-voltage side control signal LIN, and controls the on-off of the lower bridge arm 82.

[0043] Figure 21 is a diagram showing waveforms of the inverter device 1 according to Embodiment 1. In the inverter circuit 80 , the voltage VS rises to the load voltage HV when the upper arm 81 is driven. The power supply VB is provided to supply a voltage higher than the voltage VS to the control terminal of the upper arm 81 .

[0044] Figure 3 1 is a diagram showing a configuration of a drive circuit 100 according to Embodiment 1. Here, a circuit for charging the power supply VB from the power supply VCC will be described. Figure 3 In the embodiment of the present invention, the first driving unit 21, the second driving unit 22 and the signal control unit 23 are omitted.

[0045] The driving circuit 100 includes a first switching element 30. The first switching element 30 is a HVMOS (High Voltage Metal-Oxide-Semiconductor) that replaces a bootstrap diode and a bootstrap resistor. The first switching element 30 is also called an analog MOS.

[0046] The first switch element 30 has a first terminal, a second terminal, and a control terminal for controlling the on-off between the first terminal and the second terminal. In the first switch element 30, the first terminal is connected to the first power supply terminal 13, and the second terminal is connected to the second power supply terminal 10. The first switch element 30 is, for example, an LDMOS (Laterally Diffused MOS) transistor having a back gate bias circuit 32 connected to the back gate. When the first switch element 30 is an LDMOS transistor, the first terminal is a drain, the second terminal is a source, and the control terminal is a gate.

[0047] The drive circuit 100 includes a boost circuit 34. The boost circuit 34 includes a diode 34a, a capacitor 34b, and a buffer 34c. The signal input terminal 12 is connected to one end of the capacitor 34b via the buffer 34c. The other end of the capacitor 34b is connected to the cathode of the diode 34a and the drain of the second switch element 36. The anode of the diode 34a is connected to the second power supply terminal 10. The boost circuit 34 boosts the low-voltage side control signal LIN and supplies it to the control terminal of the first switch element 30, thereby turning on the first switch element 30.

[0048] The first switch section S1 is connected to the control terminal of the first switch element 30. The first switch section S1 is composed of two switch elements S1a and S1b connected in series and an inverter S1c. One end of the first switch section S1 is connected to the control terminal of the first switch element 30, and the other end is connected to the ground terminal. The gates of the switch elements S1a and S1b are connected to the signal input terminal 12 via the inverter S1c and the delay circuit 40. That is, the control terminal for switching the first switch section S1 on and off is connected to the signal input terminal 12.

[0049] The first switch section S1 disconnects the control terminal of the first switch element 30 from the ground terminal when the low-voltage side control signal LIN is at a high level, and short-circuits the control terminal of the first switch element 30 from the ground terminal when the low-voltage side control signal LIN is at a low level. In this way, the first switch section S1 applies 0V to the control terminal of the first switch element 30.

[0050] The second switch element 36 is connected between the control terminal of the first switch element 30 and the boost circuit 34. The second switch element 36 is, for example, an NMOS. The source of the second switch element 36 is connected to the control terminal of the first switch element 30. The drain of the second switch element 36 is connected to the boost circuit 34. The gate of the second switch element 36 is connected to the second switch unit S2.

[0051] A clamp circuit 38 composed of a Zener diode is connected between the source and gate of the second switching element 36. The clamp circuit 38 protects the gate-source voltage of the second switching element 36. A limiting resistor R1 is connected between a connection point between the boost circuit 34 and the second switching element 36 and a connection point between the second switch unit S2 and the second switching element 36.

[0052] The second switch section S2 is composed of two switch elements S2a and S2b connected in series and an inverter S2c. One end of the second switch section S2 is connected to the gate of the second switch element 36, and the other end is connected to the ground terminal. The gates of the switch elements S2a and S2b are connected to the signal input terminal 12 via the inverter S2c. That is, the control terminal for switching the second switch section S2 on and off is connected to the signal input terminal 12.

[0053] The second switch unit S2 controls the second switch element 36. The second switch unit S2 is turned off when the low-voltage side control signal LIN is at a high level. Thus, the second switch element 36 is set to an on state. In addition, the second switch unit S2 is turned on when the low-voltage side control signal LIN is at a low level. Thus, the second switch element 36 is set to an off state.

[0054] Thus, the second switch element 36 is turned on when the low-voltage side control signal LIN is at a high level, and conducts between the control terminal of the first switch element 30 and the boost circuit 34. In addition, the second switch element 36 is turned off when the low-voltage side control signal LIN is at a low level, and disconnects between the control terminal of the first switch element 30 and the boost circuit 34.

[0055] The delay circuit 40 delays the operation of the first switch S1 in response to the low voltage control signal LIN relative to the operation of the second switch element 36 in response to the low voltage control signal LIN. The delay circuit 40 can cause the first switch S1 to operate after the second switch S2 operates.

[0056] Figure 4 1 is a diagram for explaining the structure of the back gate bias circuit 32 involved in the first embodiment. The back gate bias circuit 32 is provided for the purpose of voltage protection of the LDMOS transistor and the suppression of parasitic operation. In the back gate bias circuit 32, a plurality of diodes Di are connected in series. The anode side of the plurality of diodes Di is connected to the power supply VCC. The cathode side of the plurality of diodes Di is connected to the back gate of the first switching element 30 via the resistor R2.

[0057] The bias value of the back gate bias circuit 32 is set by adjusting the potential difference with the power supply VCC according to the forward voltage VF corresponding to the number of stages of the diode Di. The bias value is determined, for example, according to the threshold voltage Vth of the first switching element 30. The bias value is determined so that the bias value is less than or equal to the withstand voltage of the diode between the back gate and the source of the first switching element 30.

[0058] Here, if the drain voltage of the first switching element 30 is lower than the back gate voltage, the current flows from the back gate toward the power supply VB through the diode between the back gate and the drain. If the recovery current flows through the diode between the back gate and the drain, it becomes the cause of the surge. Therefore, it is preferred that the back gate potential decreases toward the GND direction within the withstand voltage of the diode between the back gate and the source. However, if the back gate potential is reduced, the back gate bias effect tends to become larger. Therefore, it is necessary to pay attention to the Vth change of the LDMOS.

[0059] In the drive circuit 100, the first switch element 30 is driven by a boost circuit 34. In the boost circuit 34, when the low-voltage side control signal LIN is at a low level, charge is accumulated from the power supply VCC to the capacitor 34b. When the low-voltage side control signal LIN is at a high level, the voltage of the capacitor 34b is boosted by the buffer 34c, and the boost circuit 34 turns on the first switch element 30. If the first switch element 30 is turned on, current flows from the second power supply terminal 10 to the first power supply terminal 13, and the power supply VB supplied to the first drive unit is charged. In addition, the diode 34a can prevent the current from flowing back to the power supply VCC during the boost operation. The power supply VB is composed of a capacitor BSC. The capacitor BSC is also called a bootstrap capacitor.

[0060] Figure 51 is a diagram showing the structure of the inverter device 801 involved in the first comparative example. As methods for configuring the power supply VB, there are generally a floating power supply method and a bootstrap power supply method. When the power supply VB has a small current consumption, the inexpensive bootstrap power supply method is often used. The case where the power supply VB has a small current consumption is, for example, in a small-capacity inverter system, when the load is only the gate of a power transistor. In the inverter device 801 involved in the first comparative example, the power supply VB is charged by the bootstrap power supply method.

[0061] In the inverter device 801, the power source VCC and the power source VB are connected via a diode BSD and a resistor BSR. At this time, when the VB voltage is lower than the VCC voltage, such as when the N-side IGBT is turned on, charging is performed through the path shown by the solid line 91. In addition, when the P-side IGBT is turned on, the current flows through the path shown by the dotted line 92.

[0062] In this structure, an area for adding the diode BSD and the resistor BSR is required. In addition, the diode BSD may be destroyed by a recovery current generated when it is biased from forward to reverse.

[0063] Figure 6 1 is a diagram showing the structure of an inverter device 801a according to the second comparative example. In the inverter device 801a, the diode BSD and the resistor BSR are built into the HVIC. In this case, damage due to the recovery current may also occur. In addition, when charging the capacitor BSC, the charging efficiency may decrease due to the parasitic element.

[0064] Figure 7 It is a diagram showing the structure of an inverter device 801b involved in the third comparative example. Figure 8 801b is a diagram showing the structure of a drive circuit 800b according to the third comparative example. In the inverter device 801b, the function of the diode BSD is replaced by the HVMOS 830 built into the drive circuit 800b. The HVMOS 830 is, for example, an LDMOS transistor. The drain of the HVMOS 830 is connected to the power supply VB, and the source is connected to the power supply VCC. In addition, the drive circuit 800b has a drive unit 831 and a back gate bias circuit 832. The drive unit 831 has a boost circuit 834 for biasing the LDMOS transistor in the triode region when the capacitor BSC is charged.

[0065] Fig. 9801b of the third comparative example. When the low-voltage side control signal LIN is at a low level, charge is accumulated from the power supply VCC to the capacitor of the boost circuit 834. At this time, the gate voltage VG of the HVMOS 830 becomes VCC-VF. Here, VF is the forward voltage of the diode of the boost circuit 834. Since VF is smaller than VCC, VCC≈VG. In addition, the voltage VBS at this time becomes VCC-Vth. Here, the voltage VBS is the voltage across the capacitor BSC, and Vth is the threshold voltage of the HVMOS 830.

[0066] When the low voltage side control signal LIN is at a high level, the voltage of the capacitor of the booster circuit 834 is boosted by the buffer, and the HVMOS 830 is turned on. At this time, the gate voltage VG of the HVMOS 830 becomes, for example, 2×VCC. In addition, the capacitor BSC is charged by the current IBS.

[0067] If the low-voltage side control signal LIN becomes low level again, the voltage of the capacitor of the boost circuit 834 decreases according to the output of the buffer. When the power supply VB is charged, the source voltage, gate voltage, and drain voltage of the HVMOS 830 become VCC≈VG≈VB. At this time, the gate-source voltage VGS of the HVMOS 830 is not ensured. Therefore, the HVMOS 830 becomes disconnected.

[0068] In this way, in the manner of setting each node of HVMOS 830 to VCC≈VG≈VB, when the power supply VB is not charged, HVMOS 830 becomes on and a charging current flows. When the low-voltage side control signal LIN is at a low level, the boundary point of the on-off of HVMOS 830 becomes VB potential = VCC-Vth. Here, Vth is the threshold voltage of HVMOS 830. At this time, the back gate potential falls within the withstand voltage of the diode between the back gate and the source, and is set within a range less than or equal to VCC-Vth. Therefore, in the driving circuit 800b, the back gate potential is set to VCC-Vth.

[0069] Fig.10 1 is a diagram for explaining the operation of the driving circuit 800b involved in the third comparative example. In the driving circuit 800b, the gate of the HVMOS 830 is HiZ. Therefore, the gate voltage is always maintained. At this time, even if the voltage of the power supply VCC drops, the gate voltage is maintained. Therefore, the gate-source voltage VGS of the HVMOS 830 corresponding to VG-VCC is ensured, and it is possible to generate a current reverse flow mode from the power supply VB to the power supply VCC.

[0070] In addition, if the VS potential changes during inverter driving, displacement current may flow into the gate via the parasitic capacitance Ca between the drain and the gate of the HVMOS 830. As a result, the gate voltage VG may rise, causing malfunction or false turn-on of the HVMOS 830. At this time, a current reverse flow mode may occur.

[0071] Fig.11 1 is a diagram showing waveforms of the drive circuit 100 according to Embodiment 1. In this embodiment, the first switch element 30 is turned off by applying 0 V to the control terminal. This allows for a turn-off logic that is independent of VCC and VB to be configured.

[0072] When the low voltage side control signal LIN is at a low level, the first switch section S1 and the second switch section S2 are in a short circuit state. At this time, the gate-source voltage VGS of the second switch element 36 becomes 0 V. Therefore, the second switch element 36 becomes an off state, and the capacitor 34b of the boost circuit 34 and the control terminal of the first switch element 30 are disconnected.

[0073] When the low-voltage side control signal LIN is at a high level, the first switch section S1 and the second switch section S2 are in an open state. At this time, the gate-drain voltage VGD of the second switch element 36 becomes VCC-VF. Here, VF is the forward voltage of the diode 34a. As a result, the second switch element 36 becomes in an on state. Therefore, the capacitor 34b of the boost circuit 34 is connected to the control terminal of the first switch element 30. In addition, since the first switch section S1 is in an open state, the boost voltage is supplied to the first switch element 30 through the boost circuit 34.

[0074] exist Fig.11 , the voltage VG of the control terminal of the first switching element 30 is indicated by a solid line 93a. In addition, as a comparative example, the gate voltage VG of the HVMOS 830 in the inverter device 801b is indicated by a dotted line 93b. In addition, the voltage VBS of the present embodiment is indicated by a solid line 94a. In addition, as a comparative example, the voltage VBS of the inverter device 801b is indicated by a dotted line 94b.

[0075] In the inverter device 801b of the comparative example, the difference between the gate voltage when the HVMOS 830 is in the off state and the Vth of the HVMOS 830 is small. Therefore, when the VS potential changes, the HVMOS 830 may be turned on by mistake. As a result, as shown by the dotted line 94b, a current reverse flow mode may occur, and the voltage VBS may drop.

[0076] In contrast, in the present embodiment, when the first switch element 30 is in the off state, the voltage VG of the control terminal is 0 V. Therefore, the voltage VG has a sufficient margin with respect to the Vth of the first switch element 30 shown by the dotted line 93c. Therefore, even when the displacement current flows into the control terminal due to the VS potential fluctuation, the first switch element 30 can be prevented from being erroneously turned on. Therefore, the current reverse flow mode can be suppressed.

[0077] In the inverter device 801b according to the comparative example, the gate of the HVMOS 830 becomes HiZ, and the gate voltage VG is maintained even if the voltage of the power supply VCC drops. As a result, as shown by the dotted line 94b, a current reverse flow mode may occur, and the voltage VBS may drop.

[0078] On the other hand, in the present embodiment, when the first switching element 30 is in the off state, the voltage VG of the control terminal is 0 V. Therefore, the increase of VGS of the first switching element 30 can be suppressed, and the occurrence of the current reverse flow mode can be suppressed.

[0079] Furthermore, by providing the second switch element 36, the first switch element 30 is turned off in a state where the charge is accumulated in the boost circuit 34. Therefore, it is not necessary to charge the capacitor 34b from 0 V when the first switch element 30 is turned on. Therefore, the first switch element 30 can be turned on at a higher speed, and the drive circuit 100 can be operated at a higher speed.

[0080] In addition, for example, when the second switch section S2 in the gate drain type transistor is not provided, the control terminal of the first switch element 30 is set to 0V by the first switch section S1. At this time, an excessively large discard current is generated from the power supply VCC via the diode 34a. In order to avoid this, it is considered to insert a resistor between the control terminal of the first switch element 30 and the drain terminal of the first switch section S1 to suppress the discard current. However, in this structure, when the first switch element 30 is turned off, the time constant between the gate capacitance of the first switch element 30 and the inserted resistor may hinder the high-speed turning off operation.

[0081] In contrast, in the present embodiment, the boost circuit 34 is disconnected from the control terminal of the first switch element 30 by the second switch element 36 and the second switch section S2. Thus, it is possible to suppress the discard current from flowing into the first switch section S1. In addition, it is possible to suppress the overcurrent flowing through the second switch section S2 when the second switch section S2 is in the on state by the limiting resistor R1. Therefore, it is possible to achieve a high-speed disconnection operation while suppressing the discard current.

[0082] In the present embodiment, the boost circuit 34 boosts the control signal and supplies it to the control terminal of the first switch element 30, thereby turning on the first switch element 30. The second switch element 36 is turned on when the control signal is at a high level, so that the control terminal of the first switch element 30 and the boost circuit 34 are connected. In addition, the second switch element 36 is turned off when the control signal is at a low level, and the control terminal of the first switch element 30 is disconnected from the boost circuit 34. In addition, the first switch unit S1 disconnects the control terminal of the first switch element 30 from the grounding terminal when the control signal is at a high level. In addition, the first switch unit S1 short-circuits the control terminal of the first switch element 30 from the grounding terminal when the control signal is at a low level. In the present embodiment, the control signal is a signal synchronized with the low-voltage side control signal LIN. Not limited to this, the control signal can be high when the lower bridge arm 82 is in the on state and low when the lower bridge arm 82 is in the off state.

[0083] In addition, at least one of the upper bridge arm 81 and the lower bridge arm 82 may be formed of a wide bandgap semiconductor. The wide bandgap semiconductor is, for example, silicon carbide, gallium nitride-based materials, or diamond. According to this embodiment, high-speed operation of the drive circuit 100 can be achieved. Therefore, when the inverter circuit 80 is formed of a wide bandgap semiconductor, its performance can also be effectively utilized.

[0084] In addition, in the present embodiment, the drive circuit 100 drives the IGBT, but the present invention is not limited thereto, and the drive circuit 100 may also drive a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0085] In the inverter device 1, the drive circuit 100 drives a half-bridge circuit. However, the present invention is not limited thereto, and the drive circuit 100 may drive a full-bridge circuit or a three-phase inverter circuit.

[0086] Fig.12 1 is a diagram showing the structure of a drive circuit 100a according to a modification of the first embodiment. The drive circuit 100a drives a three-phase inverter circuit. The drive circuit 100a has a U-phase first drive unit, a V-phase first drive unit, and a W-phase first drive unit for driving the upper bridge arms of the U-phase, V-phase, and W-phase. In addition, the drive circuit 100a has a U-phase second drive unit, a V-phase second drive unit, and a W-phase second drive unit for driving the lower bridge arms of the U-phase, V-phase, and W-phase. The U-phase first drive unit, the V-phase first drive unit, the W-phase first drive unit, the U-phase second drive unit, the V-phase second drive unit, and the W-phase second drive unit control the on and off of the corresponding bridge arms according to the signal from the signal control unit 23.

[0087] The signal control unit 23 and the second U-phase drive unit, the second V-phase drive unit, and the second W-phase drive unit are supplied with power VCC. The first U-phase drive unit, the first V-phase drive unit, and the first W-phase drive unit are supplied with power VBU, power VBV, and power VBW, respectively.

[0088] The driving circuit 100a includes first switching elements 30_U, 30_V, and 30_W for charging the power source VBU, the power source VBV, and the power source VBW. The first switching elements 30_U, 30_V, and 30_W are controlled by control units 33_U, 33_V, and 33_W, respectively. The control units 33_U, 33_V, and 33_W each have Figure 3 The boost circuit 34, the second switching element 36, the first switching unit S1, and the second switching unit S2 are shown. In this way, when driving a full-bridge circuit or a three-phase inverter circuit, a first switching element and a control unit are provided for each upper arm.

[0089] These modifications can be appropriately applied to the drive circuit and inverter device according to the following embodiments. In addition, since the drive circuit and inverter device according to the following embodiments have many common points with the first embodiment, the description will focus on the differences with the first embodiment.

[0090] Implementation method 2.

[0091] Fig.13 2 is a diagram showing a structure of a driving circuit 200 according to Embodiment 2. In this embodiment, the structure of a first switching element 230 is different from that of the first switching element 30 according to Embodiment 1. The back gate of the first switching element 230 is connected to a ground terminal. The first switching element 230 is a well MOS transistor.

[0092] Here, a problem in the case of using an LDMOS transistor as the first switching element 30 will be described. Fig.14 2 is a cross-sectional view of a LDMOS transistor, i.e., a first switch element 30. The first switch element 30 comprises: a semiconductor layer 30a of a first conductivity type; and a first semiconductor region 30b of a second conductivity type, which is electrically connected to a first terminal 30f of the first switch element 30 and is formed on the surface of the semiconductor layer 30a. Here, the first conductivity type is a P type, and the second conductivity type is an N type. This is not limited to this, and the first conductivity type may be an N type, and the second conductivity type may be a P type.

[0093] A second semiconductor region 30c of the first conductivity type electrically connected to the back gate is formed on the surface of the first semiconductor region 30b. A third semiconductor region 30d of the second conductivity type electrically connected to the second terminal 30e of the first switching element is formed on the surface of the second semiconductor region 30c. In addition, a control terminal 30g of the first switching element 30 is connected to a channel region between the third semiconductor region 30d and the first semiconductor region 30b via a gate insulating film.

[0094] like Fig.14 As shown, the LDMOS transistor has parasitic transistors Tr1, Tr2, and Tr3. When the VS negative surge generated during inverter driving is large, the parasitic transistors Tr2 and Tr3 become the starting point, and the LDMOS transistor and its peripheral circuits form a thyristor. If the thyristor is activated, latch-up occurs, and there is a possibility of damage due to the amount of current.

[0095] In order to suppress the operation of the parasitic transistor, it is preferred to firmly fix the potential of the P-type island separation closest to the LDMOS transistor by the GND potential. This can suppress the inflow of current into the resistor Rsub. Therefore, the VBE of the parasitic transistor Tr3, which is the starting point of the thyristor, can be suppressed.

[0096] Fig.15 2 is a cross-sectional view of the first switch element 230 according to Embodiment 2. The first switch element 230 includes: a semiconductor layer 230a of the first conductivity type; and a first semiconductor region 230b of the second conductivity type, which is electrically connected to the first terminal 230f and formed on the surface of the semiconductor layer 230a. A second semiconductor region 230c of the first conductivity type is formed adjacent to the first semiconductor region 230b on the surface of the semiconductor layer 230a. A third semiconductor region 230d of the second conductivity type, which is electrically connected to the second terminal 230e, is formed on the surface of the second semiconductor region 230c. A back gate electrode BG electrically connected to a grounding terminal is electrically connected to a region of the second semiconductor region 230c that is separated from the third semiconductor region 230d. The control terminal 230g of the first switch element 230 is connected to a channel region between the third semiconductor region 230d and the first semiconductor region 230b via a gate insulating film. The breakdown voltage between the second terminal 230 e of the first switching element 230 and the back gate electrode BG is higher than the voltage of the power source VCC supplied to the second driving unit 22 .

[0097] The withstand voltage between the back gate and the source of the well MOS transistor is sufficiently higher than that of the LDMOS transistor. Therefore, the control by the back gate bias circuit is not required, and the back gate can be connected to the ground terminal. Therefore, the drive circuit 200 can be miniaturized.

[0098] The potential of the back gate of the first switching element 230 is the GND potential, which is the same as the potential of the substrate. Therefore, the parasitic transistor Tr2 that becomes the starting point of thyristor generation does not exist in the first switching element 230. Therefore, the generation of latch can be suppressed when a VS negative surge occurs. Thus, malfunction and damage can be suppressed.

[0099] This configuration can be adopted when the maximum value of the potential difference between the boosted control terminal voltage and the ground terminal of the first switching element 230 is within the control terminal-back gate withstand voltage of the first switching element 230. The control terminal-back gate withstand voltage corresponds to the withstand voltage of the gate oxide film.

[0100] Implementation 3

[0101] Fig.16 3 is a diagram showing the structure of a drive circuit 300 according to Embodiment 3. This embodiment differs from Embodiment 1 in the structure of a boost circuit 334. The drive circuit 300 includes an oscillation circuit 350, a clamp circuit 344, a clamp detection circuit 346, and a timer circuit 348. The oscillation circuit 350 outputs an oscillation waveform using the high level of the low-voltage side control signal LIN as an enable signal.

[0102] The boost circuit 334 is connected to the output of the oscillation circuit 350. The boost circuit 334 includes a first boost circuit and a second boost circuit that boosts a signal that is in an opposite phase to that of the first boost circuit. The first boost circuit includes a diode 334a, a capacitor 334b, and a buffer 334c. The second boost circuit includes a diode 334d, a capacitor 334e, and a buffer 334f. A signal in an opposite phase to that of the buffer 334c is input to the buffer 334f. The boost circuit 334 operates by a charge pump method.

[0103] The output of the boost circuit 334 is connected to the clamp circuit 344 and the second switch element 36 via a diode 342. The clamp circuit 344 includes a diode 344a and Zener diodes 344b and 344c. The clamp circuit 344 controls the voltage supplied from the boost circuit 334 to the control terminal of the first switch element 30 to be less than or equal to a predetermined threshold voltage. In addition, the clamp circuit 344 is provided with a clamp detection circuit 346 for detecting that the voltage supplied from the boost circuit 334 to the control terminal of the first switch element 30 has reached the threshold voltage.

[0104] If the clamp detection circuit 346 detects that the voltage is clamped, the timer circuit 348 is started. If the clamp detection circuit 346 detects that the voltage supplied from the boost circuit 334 to the control terminal of the first switching element 30 has reached the threshold voltage, the timer circuit 348 stops the boost operation of the boost circuit 334 for a predetermined time. The output of the timer circuit 348 is connected to the oscillation circuit 350. If the clamp detection circuit 346 detects that the voltage is clamped, the timer circuit 348 stops the oscillation circuit 350 for a predetermined time. If the predetermined time has passed, the boost operation is started again.

[0105] Fig.17 This is a diagram for explaining the function of the boost circuit 334 according to the third embodiment. Fig.17 In FIG. 9 , the voltage VG of the control terminal of the first switching element 30 is shown by a solid line 95a. In addition, as a comparative example, Figure 8 The voltage VG of the driving circuit 800b is shown by a dotted line 95b. In addition, the voltage VBS of the present embodiment is shown by a solid line 96a. In addition, as a comparative example, an example of the voltage VBS of the driving circuit 800b is shown by a dotted line 96b.

[0106] In the comparative example, the voltage VG depends on the power supply VCC. Therefore, the voltage VGS may vary due to the voltage of the power supply VCC. Therefore, when the voltage of the power supply VCC is low, sufficient charging capacity may not be obtained. In addition, when the voltage of the power supply VCC is high, the voltage VGS may exceed the withstand voltage of the gate oxide film of the HVMOS 830, causing damage.

[0107] In addition, in the driving circuit 800b involved in the comparative example, the gate terminal of the HVMOS 830 becomes a HiZ state during the boosting process. Therefore, in particular, during low-frequency operation or high-temperature operation, due to the influence of gate leakage or junction leakage, the voltage VG may drop as shown by the dotted line 95b. At this time, the voltage VG is lower than the threshold value Vth shown by the dotted line 95c, so that the HVMOS 830 cannot maintain the on state, and the voltage VBS may drop as shown by the dotted line 96b. That is, it may not be possible to implement charging stably. In addition, if a capacitor with a large capacitance is provided in order to maintain the voltage VG of the HVMOS 830, the delay of the boosting operation becomes larger.

[0108] In contrast, in the present embodiment, two boost circuits are provided that are synchronized with the inverted signals. In particular, the two-stage boost circuit is driven by the oscillation circuit 350, and the control terminal of the first switching element 30 is continuously excited by the charge pump operation. Thus, a stable boost operation can be achieved even in low-frequency operation or high-temperature operation. In addition, there is no need to provide a capacitor with a large capacitance to maintain the voltage VG, and both the maintenance of the voltage VG and high-speed operation can be achieved.

[0109] Fig.18 3 is a diagram for explaining the functions of the clamp circuit 344 and the timer circuit 348 according to the third embodiment. Fig.18 In FIG. 1 , the voltage VG of the control terminal of the first switching element 30 is indicated by a solid line 97a. In addition, as a comparative example, the voltage VG when the clamp circuit 344 is not present is indicated by a dotted line 97b. In addition, as a comparative example, the voltage VG when the timer circuit 348 is not present is indicated by a dotted line 97c. Fig.18 , the current consumption of the power supply VCC accompanying the voltage boosting operation is shown by a solid line 98a. In addition, as a comparative example, the current consumption when the clamp circuit 344 is not present is shown by a dotted line 98b. Also, as a comparative example, the current consumption when the timer circuit 348 is not present is shown by a dotted line 98c.

[0110] In the absence of the clamp circuit 344, as shown by the dotted line 97b, the voltage VG may exceed the gate-back gate withstand voltage of the first switching element 30. The gate-back gate withstand voltage corresponds to the gate oxide film withstand voltage. In this embodiment, the clamp voltage can be set arbitrarily. Therefore, it is possible to suppress the voltage VG from exceeding the withstand voltage of the first switching element 30.

[0111] In addition, in the absence of the timer circuit 348, as shown by the dotted line 97c, the clamp is continuously applied during the charge pump period. At this time, as shown by the dotted line 98c, the charge used for boosting becomes a discarded current. In contrast, in this embodiment, if the clamp detection circuit 346 detects the voltage clamp, the timer circuit 348 stops the boosting operation during the clamp timer period. As a result, it is possible to reduce unnecessary boosting operations and suppress current consumption.

[0112] Implementation method 4.

[0113] Fig.19 4 is a diagram showing a structure of a driving circuit 400 according to Embodiment 4. The driving circuit 400 is different from the driving circuit 100 in that it includes a VS potential detection circuit 452 and an operation circuit 454. The VS potential detection circuit 452 is a voltage detection circuit that outputs an enable signal when the voltage VS at the connection point between the upper bridge arm 81 and the lower bridge arm 82 is less than or equal to a predetermined value.

[0114] The operation circuit 454 outputs a control signal synchronized with the boost circuit 34. The operation circuit 454 outputs a control signal in such a manner that the control signal becomes high when the low voltage side control signal LIN is high or the enable signal is input, and becomes low when the low voltage side control signal LIN is low and the enable signal is not input.

[0115] The driving circuit 800b involved in the comparative example presumes that the lower bridge arm 82 is in the on state when the low-voltage side control signal LIN is at a high level, and charges the power supply VB. At this time, the charging period may be short and the charging may be insufficient. In fact, there is also a state where the voltage VS is 0V during the period other than the period when the low-voltage side control signal LIN is at a high level. For example, the voltage VS becomes 0V just after the power supply VCC is turned on and before the inverter circuit 80 is driven.

[0116] In this embodiment, the control signal is generated by operating the low voltage side control signal LIN and the enable signal from the VS potential detection circuit 452. The VS potential detection circuit 452 detects the voltage VS, and when the voltage VS is less than or equal to a predetermined value, the control signal is set to a high level regardless of the value of the low voltage side control signal LIN. In this way, a sufficient charging period of the power supply VB can be ensured, and insufficient charging can be suppressed. That is, it is possible to ensure that Figure 5 The external bootstrap power supply shown has the same charging period.

[0117] Fig. 20 : is a diagram showing an example of a VS potential detection circuit 452 involved in embodiment 4. As the VS potential detection circuit 452, a voltage detection type VS potential detection circuit 452a can be used. The VS potential detection circuit 452a has a Wilson current mirror circuit. In the VS potential detection circuit 452a, if the voltage VS rises and exceeds the set voltage predetermined by the detection voltage setting unit 456, the HVMOS 454 is turned on. As a result, the current mirror operates. Along with the operation of the current mirror, a low level is output as a VSDET signal. When the voltage VS is less than or equal to the set voltage of the detection voltage setting unit 456, the current mirror becomes saturated and does not operate. That is, a high level is output as a VSDET signal. The set voltage of the detection voltage setting unit 456 is set by a diode, a Zener diode, a resistor, etc.

[0118] Fig.214 is a diagram showing a modified example of the VS potential detection circuit 452 involved in Embodiment 4. As the VS potential detection circuit 452, a current detection type VS potential detection circuit 452b may also be used. In the VS potential detection circuit 452b, if the voltage VS rises and the current value corresponding to the voltage generated at both ends of the detection current setting section 458 is greater than or equal to IREF, the HVMOS 460 is turned on. As a result, the current mirror operates. Along with the operation of the current mirror, a low level is output as a VSDET signal. When the current value corresponding to the voltage generated at both ends of the detection current setting section 458 is less than or equal to IREF, the current mirror becomes saturated and does not operate. That is, a high level is output as a VSDET signal. IREF is set by a resistor or the like.

[0119] Implementation method 5.

[0120] Fig. 22 1 is a diagram showing the structure of a drive circuit 500 according to Embodiment 5. The drive circuit 500 differs from the drive circuit 100 in that it has a voltage detection circuit 562 and an operation circuit 564. The voltage detection circuit 562 has a series circuit of resistors 562a and 562b. The series circuit of resistors 562a and 562b is connected between a power supply VCC and a ground terminal. An input of a comparator 562c is connected to the connection point between the resistor 562a and the resistor 562b. A reference power supply 562d is connected to the other input of the comparator 562c. The output of the comparator 562c is connected to the operation circuit 564.

[0121] The comparator 562c compares the voltage obtained by dividing the power supply VCC with the voltage of the reference power supply 562d, and outputs the comparison result to the operation circuit 564. Thus, the voltage detection circuit 562 outputs an enable signal when the voltage of the power supply VCC supplied to the second driving unit 22 is less than or equal to a predetermined value.

[0122] The operation circuit 564 outputs a control signal that becomes high level when the low voltage side control signal LIN is high level and the enable signal is input, and becomes low level when the low voltage side control signal LIN is low level or the enable signal is not input.

[0123] The voltage detection circuit 562 is an overvoltage detection circuit that detects the rise of the power supply VCC and stops the driving of the first switching element 30. The voltage of the reference power supply 562d is set to match the voltage at the connection point of the resistors 562a and 562b when the power supply VCC becomes an overvoltage state. When the power supply VCC is within the recommended operating range, the output of the comparator 562c becomes a high level corresponding to the enable signal.

[0124] When the voltage VS rises during the charging period of the power supply VB, or when a driving signal is given to the first switching element 30 when the voltage VS is high, the above-mentioned current reverse flow mode may occur. If the current reverse flow mode occurs, the power supply VCC rises. In the present embodiment, when the power supply VCC exceeds the recommended operating range and becomes an overvoltage state within the absolute maximum rated range, the output of the comparator 562c becomes a low level. At this time, regardless of the value of the low-voltage side control signal LIN, the control signal becomes a low level. As a result, the drive of the first switching element 30 is stopped. Therefore, it is possible to suppress the damage caused by the rise of the power supply VCC exceeding the device withstand voltage.

[0125] In addition, a hysteresis may be provided in the comparator 562c. After the overvoltage is detected, the threshold of the comparator 562c decreases to a certain level. The decreased threshold is set within the recommended operating range of the power supply VCC. Thus, the power supply VCC decreases to a sufficiently safe level, so that the first switch element 30 can be driven.

[0126] Implementation method 6.

[0127] Fig.23 6 is a diagram showing a structure of a driving circuit 600 according to Embodiment 6. The driving circuit 600 is different from the driving circuit 100 in that it includes a VS potential detection circuit 452 and an operation circuit 665. The VS potential detection circuit 452 is a voltage detection circuit that outputs an enable signal when the voltage VS at the connection point between the upper bridge arm 81 and the lower bridge arm 82 is less than or equal to a predetermined value.

[0128] The operation circuit 665 has a dead time adjustment circuit 666. The dead time adjustment circuit 666 outputs a signal LINA and a signal HINA according to the low voltage side control signal LIN and the high voltage side control signal HIN. In addition, the operation circuit 665 has a D flip-flop 668. The clock input signal LINA and the signal HINA are not ORed to the D flip-flop 668. The signal LINB after the signal LINA is delayed is input to the D input of the D flip-flop 668. The logical product between the output of the VS potential detection circuit 452 and the output of the D flip-flop 668, that is, the intermediate signal QB, is input to the boost circuit 34 as a control signal.

[0129] Fig.24 6 is a diagram showing waveforms of the drive circuit 600 according to Embodiment 6. The intermediate signal QB switches from a low level to a high level according to the falling edge of the high-voltage side control signal HIN, and switches from a high level to a low level according to the falling edge of the low-voltage side control signal LIN. The operation circuit 665 outputs a control signal in such a manner that the intermediate signal QB is at a high level and an enable signal is input, and the control signal is at a low level when the intermediate signal QB is at a low level or there is no enable signal input.

[0130] The signal that causes the VS potential change varies depending on the type of load 90 connected to the inverter circuit 80. For example, the load 90 includes an inductive load and a capacitive load. In the present embodiment, the load 90 of the inverter circuit 80 is assumed to be an inductive load, and the VS potential change is estimated using the low-voltage side control signal LIN and the high-voltage side control signal HIN. The inductive load is, for example, a motor.

[0131] First, the conditions for generating a positive VS potential change are described. It is assumed that the low-voltage side output signal LO is at a high level and the lower bridge arm 82 is turned on, and then the low-voltage side output signal LO changes to a low level. At this time, the current flows back through the diode of the upper bridge arm 81 due to the energy stored in the inductance of the load 90. At this time, the VS potential generates a positive displacement.

[0132] Next, the conditions for generating negative VS potential changes are described. It is assumed that the high-voltage side output signal HO changes to a low level from the state where the high-voltage side control signal HIN is at a high level and the upper bridge arm 81 is turned on. At this time, the current flows back from the diode of the lower bridge arm 82 due to the energy stored in the inductance of the load 90. At this time, the VS potential generates a negative displacement.

[0133] like Fig.24 As shown in the period T1, in the initial state after the power is turned on, the intermediate signal QB becomes high level. At this time, if the voltage VS is less than or equal to the predetermined value, VSDET = H, the control signal becomes high level. That is, the voltage VG becomes high level, and the first switch element 30 becomes turned on. At this time, the boost circuit 34 boosts the voltage and the power supply VB is charged.

[0134] During period T2, the low voltage side control signal LIN changes from low level to high level. This change does not cause the VS potential to change. Therefore, the voltage VG maintains a high level, and the boosting circuit 34 continues to boost the voltage and the power supply VB continues to charge.

[0135] During period T3, the low-voltage side control signal LIN changes from a high level to a low level. This change is a condition for the positive VS potential change. Therefore, before the gate logic of the lower bridge arm 82 changes, the voltage VG becomes a low level, and the boosting of the boost circuit 34 and the charging of the power supply VB are stopped. During period T4, the boosting of the boost circuit 34 and the charging of the power supply VB are also kept stopped.

[0136] During period T5, the high-side control signal HIN changes from a high level to a low level. This change is a condition for the generation of a negative VS potential change. At this time, the intermediate signal QB becomes a high level. However, at this time point, since it is before the generation of the VS potential change, VSDET = L, the voltage VG maintains a low level. That is, the boosting of the boost circuit 34 and the charging of the power supply VB remain stopped.

[0137] During period T6, VS potential changes and becomes VSDET = H. As a result, voltage VG becomes high level, and boosting circuit 34 starts boosting voltage and charging power supply VB starts. Period T7 is the same as period T3.

[0138] As described above, in the driving circuit 800b involved in the comparative example, since the power supply VB is charged only when the low-voltage side control signal LIN is at a high level, it is possible that a shortage of the charging period occurs. In the present embodiment, when the load 90 is an inductive load, the VS potential can be estimated in detail using the low-voltage side control signal LIN and the high-voltage side control signal HIN, and the VS potential detection circuit 452. Thus, a sufficient charging period can be ensured. In addition, when the VS potential is high, the first switching element 30 is turned on, which can suppress the generation of a current reverse flow mode. Therefore, a highly stable and efficient charging operation can be achieved.

[0139] Furthermore, the technical features described in each embodiment may be used in combination.

[0140] Description of the label

[0141] 1 inverter device, 10 second power supply terminal, 11, 12 signal input terminals, 13 first power supply terminal, 14 signal output terminal, 15 power supply terminal, 16 signal output terminal, 17 grounding terminal, 21 first drive unit, 22 second drive unit, 23 signal control unit, 30 first switching element, 30_U, 30_V, 30_W first switching element, 30a semiconductor layer, 30b first semiconductor region, 30c second semiconductor region, 30d third semiconductor region, 30e second terminal, 30f first terminal, 30g control terminal, 32 back gate bias circuit, 33_U, 33_V, 33_W control unit, 34 boost circuit, 34a diode, 34b capacitor, 34c buffer, 36 second switching element, 38 clamp circuit, 40 delay circuit, 80 inverter circuit , 81 upper bridge arm, 82 lower bridge arm, 90 load, 100 drive circuit, 100a drive circuit, 200 drive circuit, 230 first switch element, 230a semiconductor layer, 230b first semiconductor region, 230c second semiconductor region, 230d third semiconductor region, 230e second terminal, 230f first terminal, 230g control terminal, 300 drive circuit, 334 boost circuit, 334a diode, 334b ​​capacitor, 334c buffer, 334d diode, 334e capacitor, 334f buffer, 342 diode, 344 clamp circuit, 344a diode, 344b, 344c Zener diodes, 346 clamp detection circuit, 348 timer circuit, 350 oscillation circuit, 400 drive circuit, 452, 452a, 452b VS potential detection circuit, 454 operation circuit, 456 detection voltage setting unit, 458 detection current setting unit, 500 drive circuit, 562 voltage detection circuit, 562a, 562b resistors, 562c comparator, 562d reference power supply, 564 operation circuit, 600 drive circuit, 665 operation circuit, 666 dead time adjustment circuit, 668 D flip-flop, 800b drive circuit, 801, 801a, 801b inverter device, 831 drive unit, 832 back gate bias circuit, 834 booster circuit path, BG back gate electrode, BSC capacitor, BSD diode, BSR resistor, Ca parasitic capacitance, Di diode, HIN high-voltage side control signal, HO high-voltage side output signal, LIN low-voltage side control signal, LO low-voltage side output signal, QB intermediate signal, R1 limiting resistor, R2 resistor, Rsub resistor, S1 first switch part, S1a, S1b switching elements, S1c inverter, S2 second switch part, S2a, S2b switching elements, S2c inverter, Tr1, Tr2, Tr3 parasitic transistors.

Claims

1. A driving circuit, characterized in that: have: A first driving unit, which controls the on-off of an upper bridge arm of an inverter circuit; a second driving unit for controlling the on-off of the lower bridge arm of the inverter circuit; a first switching element having a first terminal, a second terminal, and a control terminal for controlling the on-off between the first terminal and the second terminal, wherein the first terminal is connected to a power source supplied to the first driving unit, and the second terminal is connected to a power source supplied to the second driving unit; a boost circuit for boosting a control signal which is a high level when the lower bridge arm is in an on state and a low level when the lower bridge arm is in an off state, and supplies the boosted control signal to the control terminal, thereby turning on the first switch element; a second switch element connected between the control terminal and the boost circuit, which conducts between the control terminal and the boost circuit when the control signal is at the high level, and disconnects between the control terminal and the boost circuit when the control signal is at the low level; as well as a first switch unit that disconnects the control terminal and the ground terminal when the control signal is at the high level, and short-circuits the control terminal and the ground terminal when the control signal is at the low level, When the first switching element is turned on, current flows from the power source supplied to the second driving unit to the power source supplied to the first driving unit, and the power source supplied to the first driving unit is charged.

2. The driving circuit according to claim 1, characterized in that: The second driving unit controls the on / off of the lower bridge arm according to the low-voltage side control signal. The control signal is synchronized with the low-voltage side control signal.

3. The driving circuit according to claim 1, characterized in that: With back gate bias circuit, The first switching element is an LDMOS transistor having a back gate connected to the back gate bias circuit.

4. The driving circuit according to claim 2, characterized in that: With back gate bias circuit, The first switching element is an LDMOS transistor having a back gate connected to the back gate bias circuit.

5. The driving circuit according to claim 1, characterized in that: The first switching element comprises: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type, which is electrically connected to the first terminal and is formed on a surface of the semiconductor layer; the second semiconductor region of the first conductivity type, formed on the surface of the semiconductor layer adjacent to the first semiconductor region; The third semiconductor region of the second conductivity type is electrically connected to the second terminal and is formed on the surface of the second semiconductor region; as well as a back gate electrode electrically connected to a region of the second semiconductor region that is separated from the third semiconductor region and electrically connected to a ground terminal, The control terminal is connected to a channel region between the third semiconductor region and the first semiconductor region via a gate insulating film. A withstand voltage between the second terminal and the back gate electrode is higher than a voltage of a power supply supplied to the second driving unit.

6. The driving circuit according to claim 2, characterized in that: The first switching element comprises: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type, which is electrically connected to the first terminal and is formed on a surface of the semiconductor layer; the second semiconductor region of the first conductivity type, formed on the surface of the semiconductor layer adjacent to the first semiconductor region; The third semiconductor region of the second conductivity type is electrically connected to the second terminal and is formed on the surface of the second semiconductor region; as well as a back gate electrode electrically connected to a region of the second semiconductor region that is separated from the third semiconductor region and electrically connected to a ground terminal, The control terminal is connected to a channel region between the third semiconductor region and the first semiconductor region via a gate insulating film. A withstand voltage between the second terminal and the back gate electrode is higher than a voltage of a power supply supplied to the second driving unit.

7. The driving circuit according to any one of claims 1 to 6, characterized in that: The booster circuit includes a first booster circuit and a second booster circuit that boosts a signal having an opposite phase to that of the first booster circuit.

8. The driving circuit according to any one of claims 1 to 6, characterized in that: A clamp circuit is provided for controlling the voltage supplied from the booster circuit to the control terminal to be less than or equal to a predetermined threshold voltage.

9. The driving circuit according to claim 8, characterized in that: A timer circuit is provided, and when the clamp circuit detects that the voltage supplied from the boost circuit to the control terminal has reached the threshold voltage, the timer circuit stops the boosting operation of the boost circuit for a predetermined time.

10. The driving circuit according to any one of claims 1 to 6, characterized in that: have: a voltage detection circuit, which outputs an enable signal when the voltage at the connection point between the upper bridge arm and the lower bridge arm is less than or equal to a predetermined value; as well as Operational circuit, The second driving unit controls the on / off of the lower bridge arm according to the low-voltage side control signal. The operation circuit outputs the control signal in a manner such that it becomes a high level when the low-voltage side control signal is at a high level or there is an input of the enable signal, and becomes a low level when the low-voltage side control signal is at a low level and there is no input of the enable signal.

11. The driving circuit according to any one of claims 1 to 6, characterized in that: have: a voltage detection circuit that outputs an enable signal when a voltage of a power source supplied to the second drive unit is less than or equal to a predetermined value; as well as Operational circuit, The second driving unit controls the on / off of the lower bridge arm according to the low-voltage side control signal. The operation circuit outputs the control signal in a manner such that it becomes a high level when the low-voltage side control signal is at a high level and the enable signal is input, and becomes a low level when the low-voltage side control signal is at a low level or the enable signal is not input.

12. The driving circuit according to any one of claims 1 to 6, characterized in that: have: a voltage detection circuit, which outputs an enable signal when the voltage at the connection point between the upper bridge arm and the lower bridge arm is less than or equal to a predetermined value; as well as Operational circuit, The first driving unit controls the on / off of the upper bridge arm according to the high-voltage side control signal. The second driving unit controls the on / off of the lower bridge arm according to the low-voltage side control signal. The operation circuit outputs the control signal in a manner that the intermediate signal becomes a high level when the intermediate signal is a high level and there is an input of the enable signal, and becomes a low level when the intermediate signal is a low level or there is no input of the enable signal, wherein the intermediate signal switches from a low level to a high level according to a falling edge of the high-voltage side control signal, and switches from the high level to the low level according to a falling edge of the low-voltage side control signal.

13. The driving circuit according to claim 12, characterized in that: The load of the inverter circuit is an inductive load.

14. The driving circuit according to any one of claims 1 to 6, characterized in that: The second switch element is an NMOS.

15. The driving circuit according to any one of claims 1 to 6, characterized in that: have: a second switch section that sets the second switch element to an on state when the control signal is at the high level, and sets the second switch element to an off state when the control signal is at the low level; as well as A limiting resistor is connected between a connection point between the boost circuit and the second switching element and a connection point between the second switching unit and the second switching element.

16. The driving circuit according to any one of claims 1 to 6, characterized in that: A delay circuit is provided for delaying the operation of the first switch element in response to the control signal relative to the operation of the second switch element in response to the control signal.

17. An inverter device, characterized in that: have: An inverter circuit having an upper bridge arm and a lower bridge arm; Driving circuit; as well as a first power supply connected between a connection point between the upper bridge arm and the lower bridge arm and the driving circuit, The driving circuit comprises: a first driving unit, which is supplied with the first power supply and controls the on / off of the upper bridge arm; a second driving unit, which is supplied with a second power supply and controls the on / off of the lower bridge arm; a first switch element having a first terminal, a second terminal, and a control terminal for controlling on / off between the first terminal and the second terminal, wherein the first terminal is connected to the first power source, and the second terminal is connected to the second power source; a boost circuit for boosting a control signal which is a high level when the lower bridge arm is in an on state and a low level when the lower bridge arm is in an off state, and supplies the boosted control signal to the control terminal, thereby turning on the first switch element; a second switch element connected between the control terminal and the boost circuit, which conducts between the control terminal and the boost circuit when the control signal is at the high level, and disconnects between the control terminal and the boost circuit when the control signal is at the low level; as well as a first switch unit that disconnects the control terminal and the ground terminal when the control signal is at the high level, and short-circuits the control terminal and the ground terminal when the control signal is at the low level, When the first switching element is turned on, current flows from the second power supply to the first power supply, and the first power supply is charged.

18. The inverter device according to claim 17, characterized in that: At least one of the upper bridge arm and the lower bridge arm is formed of a wide bandgap semiconductor.

19. The inverter device according to claim 18, characterized in that: The wide bandgap semiconductor is silicon carbide, gallium nitride or diamond.

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