Semiconductor device

Abstract

The semiconductor device of the embodiment is a semiconductor device that makes the first transistor driven in a normally-on state be driven in a normally-off state, and includes a first circuit, a second circuit, and a first diode. The first circuit is connected to a power supply voltage and a ground voltage, detects the power supply voltage, and outputs the transition state of the power supply voltage. The second circuit is connected to the power supply voltage, the ground voltage, the first circuit, and the second transistor, and outputs the drive voltage of the second transistor connected in series with the first transistor based on the output of the first circuit. The anode of the first diode is connected to the drive terminal of the first transistor, and the cathode is connected to the output terminal of the second transistor.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-157674 (filing date: September 18, 2020). This application incorporates all the contents of the base application by reference thereto. Technical Field

[0003] The embodiment relates to a semiconductor device. Background Art

[0004] Compared with a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) using Si (silicon), a power device using GaN (gallium nitride) has advantages such as a fast switching speed, a low recovery loss, and a fast charge and discharge of the output capacitance. Although most transistors using GaN are generally normally on type, development is widely underway to use these advantages as normally off type transistors.

[0005] However, for a circuit converted to such a normally off type, there are the following problems depending on the conversion circuit: the gate drive ability cannot be adjusted, a dedicated negative power supply circuit and a dedicated gate driver are required, the gate current loop becomes longer via an n-type MOSFET, or there is a large trade-off between prevention of malfunction at the time of turning off the gate driver power supply and standby power. Summary of the Invention

[0006] The embodiment provides a semiconductor device capable of performing a normally on operation.

[0007] According to one embodiment, a semiconductor device is a semiconductor device that makes a first transistor driven in a normally on state be driven in a normally off state, and includes a first circuit, a second circuit, and a first diode. The first circuit is connected to a power supply voltage and a ground voltage, detects the power supply voltage, and outputs a transition state of the power supply voltage. The second circuit is connected to the power supply voltage, the ground voltage, the first circuit, and the second transistor, and outputs a drive voltage of a second transistor connected in series with the first transistor based on an output of the first circuit. An anode of the first diode is connected to a drive terminal of the first transistor, and a cathode thereof is connected to an output terminal of the second transistor. Brief Description of the Drawings

[0008] Figure 1 It is a circuit diagram showing an example of a semiconductor device according to one embodiment.

[0009] Figure 2 It is a circuit diagram showing an example of mounting of a semiconductor device according to one embodiment.

[0010] Figure 3 It is a diagram showing the on / off state of a transistor according to an embodiment.

[0011] Figure 4 It is a circuit diagram showing an example of mounting a semiconductor device according to an embodiment.

[0012] Figure 5 It is a diagram showing the on / off state of a transistor according to an embodiment.

[0013] Figure 6 It is a circuit diagram showing an example of mounting a semiconductor device according to an embodiment.

[0014] Figure 7 It is a circuit diagram showing an example of mounting a semiconductor device according to an embodiment.

[0015] Figure 8 It is a circuit diagram showing an example of mounting a semiconductor device according to an embodiment.

[0016] Figure 9 It is a circuit diagram showing an example of mounting a semiconductor device according to an embodiment.

[0017] Figure 10 It is a circuit diagram showing an example of a semiconductor device according to an embodiment.

[0018] Figure 11 It is a circuit diagram showing an example of mounting a semiconductor device according to an embodiment.

[0019] Figure 12 It is a circuit diagram showing an example of mounting a semiconductor device according to an embodiment.

[0020] Figure 13 It is a circuit diagram showing an example of mounting a semiconductor device according to an embodiment. Detailed Embodiment

[0021] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, unless otherwise specifically negated, D represents the position of the drain.

[0022] (First Embodiment)

[0023] Figure 1 It is a circuit diagram showing an example of the position of a semiconductor device according to an embodiment. The semiconductor device 1 is a circuit for performing normally-off driving of the normally-on type first transistor Q1.

[0024] The first transistor Q1 is a power device using, for example, GaN, and is a FET that performs a normally-on operation.

[0025] The second transistor Q2 is a p-type MOSFET that shares a source with the first transistor Q1 and is connected in series. According to the characteristics of the second transistor Q2, the first transistor Q1 performs a normally-off operation.

[0026] Hereinafter, the drains of the first transistor Q1 and the second transistor Q2 are defined as the drain and source of the transistors that perform normally-off operations, respectively. The semiconductor device 1 solves various problems during the normally-off operation of the first transistor Q1 by controlling the voltages applied to the source and the gates of the respective transistors.

[0027] When the first transistor Q1 performs a normally-off operation via the semiconductor device 1, the first transistor Q1 is driven by the voltage applied to the gate, and based on the potential difference between the drain terminal DRAIN and the source terminal SOURCE, a drain current is output from the source terminal SOURCE. For example, an external load is connected to the drain side of the first transistor Q1, i.e., the drain terminal DRAIN, and the first transistor Q1 operates as a circuit that switches the load based on the voltage applied to the gate.

[0028] The semiconductor device 1 is a circuit that controls the voltages of the gate of the first transistor Q1, the gate of the second transistor Q2, and the drain of the second transistor Q2, and is connected to the power supply voltage terminal VDD, the gate voltage application terminal GATE, and the ground terminal GND. The semiconductor device 1 includes a first diode 10, a first circuit 20, and a second circuit 30. In addition, the gate voltage application terminal GATE is connected to the gate of the first transistor Q1.

[0029] The power supply voltage terminal VDD is connected via the semiconductor device 1 to the node shared by the sources of the first transistor Q1 and the second transistor Q2, and applies the power supply voltage to the semiconductor device 1. The ground terminal GND sets the ground potential of the semiconductor device 1. In addition, in the drawings, it is connected to the ground point within the semiconductor device 1, but is not limited to this method, and it may also be grounded outside the semiconductor device 1. The ground terminal GND is not limited to actual grounding, and may also be connected to a potential of 0V, or may be connected to a specified ground potential within the device. It is hoped that the ground terminal GND in the following description will be understood to have the same interpretation.

[0030] The first diode 10 is a protection circuit for the first transistor Q1 and the second transistor Q2. The anode of the first diode 10 is connected to the gate of the first transistor Q1, and its cathode is connected to the drain of the second transistor Q2.

[0031] The first circuit 20 is a circuit that detects the voltage of the power supply voltage. The first circuit 20 is connected between the power supply voltage terminal VDD and the ground terminal GND. The first circuit 20 compares the state of the power supply voltage. More specifically, it compares the power supply voltage with the threshold voltage of the first transistor Q1, detects the voltage difference, and outputs it to the second circuit 30.

[0032] The second circuit 30 is a circuit with low standby power and is a circuit that outputs a voltage for driving the second transistor Q2 to operate properly. The second circuit 30 is connected to the power supply voltage terminal VDD, the ground voltage GND, the first circuit 20, and the gate of the second transistor Q2. The second circuit 30 is a circuit that appropriately drives the second transistor Q2 when receiving a signal detecting the voltage state from the first circuit 20. Additionally, it can also be set as a circuit 35 that combines the first circuit 20 and the second circuit 30. The circuit 35 does not require an external signal input.

[0033] In the case of the power supply voltage rising, the first circuit 20 detects that the voltage is higher than the absolute value of the threshold voltage of the first transistor Q1, that is, the case where the first transistor Q1 is in the cut-off state. The first circuit 20 outputs the change in this voltage to the second circuit 30. When receiving this signal, the second circuit 30 applies a driving voltage that turns on the second transistor Q2 to the gate of the second transistor Q2 after the first transistor Q1 is cut off.

[0034] Conversely, in the case of the power supply voltage falling, the first circuit 20 outputs the meaning that the voltage is decreasing to the second circuit 30 in a state where the power supply voltage is higher than the absolute value of the threshold voltage of the first transistor Q1, that is, in a state where the first transistor Q1 is cut off. When receiving this signal, the second circuit 30 applies a driving voltage that turns off the second transistor Q2 to the gate of the second transistor Q2 before the first transistor Q1 is turned on.

[0035] By using such a first circuit 20 and a second circuit 30, even when the voltage applied to the power supply voltage terminal rises or falls at a high slew rate, it is possible to avoid the second transistor Q2 being turned on while the first transistor Q1 is turned on. Additionally, even in a state of voltage fluctuation where the power supply voltage vibrates near the threshold voltage of the first transistor Q1, it is also possible to avoid the state where both the first transistor Q1 and the second transistor Q2 are turned on. And in this way, the circuit 35 can perform a normally-off operation of the first transistor Q1 without requiring an external signal input by having a passive circuit connected to the power supply. In this embodiment, the circuit 35 corresponds to the first circuit 20 and the second circuit 30.

[0036] Next, some descriptions will be given of a specific mounting example of the semiconductor device 1.

[0037] (Mounting Example 1)

[0038] Figure 2 This is a circuit diagram of a semiconductor device 1 showing an installation example. The semiconductor device 1 includes a first resistor 200, a second diode 201, a third transistor 202, a second resistor 203, a fourth transistor 300, and a third resistor 301. As shown in the figure, as an example, the first resistor 200, the second diode 201, the third transistor 202, and the second resistor 203 are configured as part of a first circuit 20, and the fourth transistor 300 and the third resistor 301 are configured as part of a second circuit 30.

[0039] The first resistor 200 is connected between a power supply voltage terminal VDD and the second diode 201.

[0040] The anode of the second diode 201 is connected to a ground terminal GND, and the cathode is connected to the power supply voltage terminal VDD via the first resistor 200. The second diode 201 is a Zener diode, and the Zener diode has a Zener voltage that is equal to or greater than the absolute value of the threshold voltage of the first transistor Q1 and lower than a constant value Vdd of the power supply voltage (for example, the maximum value of the voltage applied to the power supply, about 15V).

[0041] When a voltage equal to or higher than the Zener voltage of the second diode 201 is applied to the power supply terminal VDD, the first resistor 200 and the second diode 201 operate as a circuit that outputs a constant voltage (Zener voltage) from the connection node; otherwise, they operate as a circuit that outputs a voltage based on the voltage applied to the power supply voltage terminal VDD.

[0042] The third transistor 202 is, for example, a p-type MOSFET. The source is connected to the power supply voltage terminal VDD, the drain is connected to the ground terminal GND via the second resistor 203, and the gate is connected to the cathode of the second diode 201. The third transistor 202 is a transistor having the following characteristics: the threshold voltage is negative, and its absolute value is lower than (the constant value Vdd of the power supply voltage) - (the Zener voltage of the second diode 201).

[0043] The second resistor 203 is connected between the drain of the third transistor 202 and the ground terminal GND. According to the current flowing through the third transistor 202, the potential of the drain of the third transistor is defined by the resistance value of the second resistor 203. For example, the first circuit 20 outputs the voltage of the drain of the third transistor 202.

[0044] The fourth transistor 300 is, for example, a p-type MOSFET. Its source is connected to the power supply voltage terminal VDD, its drain is connected to the ground terminal GND via the third resistor 301, and its gate is connected to the drain of the third transistor 202. The fourth transistor 300 is a transistor having the following characteristics: the threshold voltage is negative, and the absolute value thereof is lower than the constant value Vdd of the power supply voltage.

[0045] The third resistor 301 is provided between the drain of the fourth transistor 300 and the ground terminal GND.

[0046] According to this structure, the first circuit 20 outputs a voltage based on the voltage applied to the power supply voltage terminal VDD, and the second circuit 30 outputs a voltage obtained based on the voltage output from the first circuit 20 to the gate of the second transistor Q2.

[0047] Here, the operations of the first transistor Q1 and the second transistor Q2 in the case where the voltage applied to the power supply voltage terminal VDD changes are described.

[0048] First, the case where the voltage applied to the power supply voltage terminal VDD rises from 0 to the voltage Vdd is described. When the voltage applied to the power supply voltage terminal VDD exceeds the threshold voltage of the first transistor Q1, the first transistor Q1 is turned off. At this timing, since the Zener voltage of the first diode 201 is not exceeded, no current flows through the first resistor 200, the gate-source voltage of the third transistor 202 becomes 0, and the third transistor 202 continues to be in the off state. And, since no current flows through the second resistor 203, the fourth transistor 300 becomes conductive, and the voltage generated by its drain current and the third resistor 301 is applied to the gate of the second transistor Q2, and the second transistor Q2 continues to be in the off state.

[0049] In addition, when the voltage applied to the power supply voltage terminal VDD becomes higher and exceeds the Zener voltage of the first diode 201, the gate-source voltage of the third transistor 202 becomes the voltage between the terminals of the first resistor 200. In this state, in the case where the voltage applied to the power supply voltage terminal VDD is lower than the sum of the Zener voltage and the absolute value of the threshold voltage of the third transistor 202, the states of the third transistor 202 and the fourth transistor 300 do not change. That is, the third transistor 202 is in the off state, the fourth transistor 300 is in the conductive state, and the second transistor Q2 is in the off state.

[0050] In addition, when the voltage applied to the power supply voltage terminal VDD becomes high and exceeds the sum of the Zener voltage and the absolute value of the threshold voltage of the third transistor 202, the gate-source voltage of the third transistor 202 is lower than the threshold voltage of the third transistor 202, and the third transistor 202 conducts. When the third transistor 202 conducts, the voltage generated by the drain current of the third transistor 202 and the second resistor 203 is applied to the gate of the fourth transistor 300.

[0051] In this state, the voltage applied to the gate of the fourth transistor 300 rises as the voltage applied to the power supply voltage terminal VDD increases, gradually turning off the fourth transistor 300. When the voltage applied to the power supply voltage terminal VDD exceeds the absolute value of the threshold of the fourth transistor 300, the fourth transistor 300 turns off. That is, the voltage applied to the gate of the second transistor Q2 decreases as the voltage applied to the power supply voltage terminal VDD increases, and at the timing when it is lower than the threshold voltage of the second transistor Q2, the second transistor Q2 conducts.

[0052] If the above situations are summarized, for example, when the voltage applied to the power supply voltage terminal VDD rises from 0 to the voltage Vdd, first, the first transistor Q1 changes from conduction to cutoff. After the state transitions of the third transistor 202 and the fourth transistor 300, the second transistor Q2 changes from cutoff to conduction. In this way, it can be configured to generate a time margin from the cutoff of the first transistor Q1 to the conduction of the second transistor Q2, and these two transistors do not conduct simultaneously.

[0053] Next, the case where the voltage applied to the power supply voltage terminal VDD drops from the voltage Vdd to 0 will be described.

[0054] When the voltage applied to the power supply voltage terminal VDD drops until the voltage between the terminals of the first resistor 200, which is Vdd - (the Zener voltage of the second diode 201), is lower than the threshold voltage of the third transistor 202, the third transistor 202 changes from the conducting state to the cutoff state.

[0055] As a result, the fourth transistor 300 changes to the conducting state, and when the voltage formed by the drain current of the fourth transistor 300 and the third resistor 301 exceeds the threshold voltage of the second transistor Q2, the second transistor Q2 changes to the cutoff state.

[0056] After that, the voltage applied to the power supply voltage terminal VDD further drops, and when it is lower than the threshold voltage of the first transistor Q1, the first transistor Q1 becomes conducting.

[0057] If the above situations are summarized, for example, when the voltage applied to the power supply voltage terminal VDD drops from the voltage Vdd to 0, first, through the state transition of the third transistor 202 and the fourth transistor 300, the second transistor Q2 changes from conducting to cutoff, and then the first transistor Q1 changes to the conducting state. In this way, it can be configured to generate a time margin from the cutoff of the second transistor Q2 to the conduction of the first transistor Q1, and these two transistors do not conduct simultaneously.

[0058] The driving forces for turning on and off the second transistor Q2 during the rise and fall of the voltage applied to the power supply voltage terminal VDD are respectively determined by the value of the third resistor 301 and the on-resistance value of the fourth transistor 300. By setting the resistance value of the third resistor 301 to be greater than the on-resistance value of the fourth transistor 300, the second transistor Q2 can be turned off faster than it can be turned on.

[0059] Figure 3 is a diagram showing Figure 2 the voltages of the components in the circuit. The solid line represents the voltage applied to the power supply voltage terminal VDD, the dotted line represents the gate-source voltage Vgs1 of the first transistor Q1, and the dashed line represents the gate-source voltage Vgs2 of the second transistor Q2.

[0060] In addition, Vth1 is the threshold voltage of the first transistor Q1, and Vth2 is the threshold voltage of the second transistor Q2. Vref is the voltage to be detected in the first circuit 20, that is, the Zener voltage of the second diode 201.

[0061] Regarding the ON (conducting) and OFF (cutoff) below, the upper part represents the on / off state of the first transistor Q1, and the lower part represents the on / off state of the second transistor Q2.

[0062] As Figure 3 shown, regardless of whether the voltage applied to the power supply voltage terminal VDD is rising or falling, when turning on or off the first transistor Q1 and the second transistor Q2, both transistors change through the cutoff state. Therefore, these two transistors do not conduct at the same timing.

[0063] In Figure 2 the circuit configuration, in the steady state where the first transistor Q1 is in the cutoff state, the voltage Vdd is applied to the gate of the second transistor Q2, so the second transistor Q2 can be driven with a low on-resistance.

[0064] As described above, even in the case where the conversion rate of the voltage applied to the power supply voltage terminal VDD is high or the voltage applied to the power supply voltage terminal VDD vibrates, it is possible to avoid the first transistor Q1 and the second transistor Q2 from simultaneously becoming conducting states.

[0065] In addition, in the steady state after the power supply voltage rises, since the fourth transistor 300 is in the cut-off state, no standby current flows, and it is possible to balance the driving force difference for preventing the first transistor Q1 and the second transistor Q2 from conducting simultaneously and low power consumption. As a result, the standby power of the entire circuit is defined by the first resistor 200 and the current flowing through the second resistor 203. By setting these two resistor values to larger values, the overall power consumption can also be made low. Setting the resistor value to a larger value can be, for example, a resistor value of several tens of kΩ. In this case, when the power supply voltage is around 15V, it becomes ～ about 1 mA of power consumption, and it can be set to a low consumption current as a driving circuit for the transistor.

[0066] (Mounting Example 2)

[0067] Figure 4 FIG. is a circuit diagram showing the configuration of the semiconductor device 1 of mounting example 2 different from the above mounting example 1. The semiconductor device 1 includes a fifth transistor 210 and a third diode 211. The fifth transistor 210 and the third diode 211 form Figure 1 the first circuit 20 and the second circuit 30 in.

[0068] The fifth transistor 210 is, for example, a transistor that performs a normally-on operation. The drain is connected to the power supply voltage terminal VDD, the source is connected to the ground terminal GND via the third diode 211, and the gate is connected to the ground terminal GND. The fifth transistor has the following characteristics: for example, the threshold voltage is negative, the absolute value thereof is equal to or greater than the absolute value of the threshold voltage of the first transistor Q1, and is lower than the voltage Vdd.

[0069] The third diode 211 is, for example, a Zener diode. The anode is connected to the ground terminal GND, and the cathode is connected to the source of the fifth transistor 210. The Zener voltage of the third diode 211 is equal to or greater than the absolute value of the threshold voltage of the first transistor Q1, and is lower than the voltage Vdd - (the absolute value of the threshold voltage of the second transistor Q2).

[0070] The connection node of the source of the fifth transistor 210 and the cathode of the third diode 211 is connected to the gate of the second transistor Q2, and the voltage of this node becomes the driving voltage of the second transistor Q2.

[0071] Here, the operations of the first transistor Q1 and the second transistor Q2 in the case of a voltage change applied to the power supply voltage terminal VDD will be described.

[0072] First, the case where the voltage applied to the power supply voltage terminal VDD rises from 0 to the voltage Vdd will be described. When the voltage applied to the power supply voltage terminal VDD exceeds the threshold voltage of the first transistor Q1, the first transistor Q1 is turned off. At this timing, since the fifth transistor 210 is turned on, the second transistor Q2 remains in the off state.

[0073] When the voltage applied to the power supply voltage terminal VDD further rises and exceeds the absolute value of the threshold voltage of the fifth transistor 210 and the Zener voltage of the third diode 211, the fifth transistor 210 is turned off, and the gate voltage of the second transistor Q2 is boosted to the Zener voltage (or a voltage below the Zener voltage).

[0074] When the voltage applied to the power supply voltage terminal VDD further rises and the voltage between the gate and source of the second transistor Q2 is lower than the threshold voltage, the second transistor Q2 is turned on.

[0075] If the above situations are summarized, for example, when the voltage applied to the power supply voltage terminal VDD rises from 0 to the voltage Vdd, first, the first transistor Q1 changes from on to off. Through the fifth transistor 210 and the third diode 211, the Zener voltage (or a voltage below the Zener voltage) of the third diode 211 appears on the gate of the second transistor Q2, and then the second transistor Q2 changes from off to on. In this way, it can be configured that a time margin is generated from the turn-off of the first transistor Q1 to the turn-on of the second transistor Q2, and these two transistors do not conduct simultaneously.

[0076] Next, the case where the voltage applied to the power supply voltage terminal VDD drops from the voltage Vdd to 0 will be described.

[0077] First, when the voltage applied to the power supply voltage terminal VDD is lower than the threshold voltage of the fifth transistor 210, the fifth transistor 210 is turned on. Since the fifth transistor 210 is turned on, through the drain current, the potential of the gate of the second transistor Q2 exceeds the threshold voltage, and the second transistor Q2 is turned off.

[0078] After that, the voltage applied to the power supply voltage terminal VDD exceeds the threshold of the first transistor Q1, and thus the first transistor Q1 becomes on.

[0079] If the above situations are summarized, for example, when the voltage applied to the power supply voltage terminal VDD drops from the voltage Vdd to 0, first, the fifth transistor 210 becomes on, and then the second transistor Q2 changes from on to off. After that, the first transistor Q1 changes from off to on. In this way, it can be configured that a time margin is generated from the turn-off of the first transistor Q1 to the turn-on of the second transistor Q2, and these two transistors do not conduct simultaneously.

[0080] The turn-on and turn-off driving forces of the second transistor Q2 during the rising and falling of the voltage applied to the power supply voltage terminal VDD are determined by the on-resistance value of the fifth transistor 210 and the operating resistance of the third diode 211, respectively. By configuring the operating resistance of the third diode 211 to have a value larger than the on-resistance of the fifth transistor 210, the turn-off of the second transistor Q2 can be faster than the turn-on.

[0081] Figure 5 is a diagram showing Figure 4 the voltages of the components in the circuit. The solid line represents the voltage applied to the power supply voltage terminal VDD, the dotted line represents the gate-source voltage Vgs1 of the first transistor Q1, and the dashed line represents the gate-source voltage Vgs2 of the second transistor Q2.

[0082] In addition, Vth1 is the threshold voltage of the first transistor Q1, Vth2 is the threshold voltage of the second transistor Q2, and Vref is the Zener voltage of the third diode 211.

[0083] Regarding the ON and OFF below, the upper part represents the conduction / non-conduction state of the first transistor Q1, and the lower part represents the conduction / non-conduction state of the second transistor Q2.

[0084] As shown in this Figure 5 regardless of whether the voltage applied to the power supply voltage terminal VDD is rising or falling, the timing of turning on or off the first transistor Q1 and the second transistor Q2 transitions through a state where both transistors are in the off state. Therefore, these two transistors will not be in the on state at the same timing.

[0085] In the steady state where the first transistor Q1 is in the off state, the voltage difference between the voltage of the power supply voltage terminal VDD and the Zener voltage of the third diode 211 is applied to the gate of the second transistor Q2. Therefore, compared with Figure 2 the circuit structure of Figure 4 in the circuit configuration of

[0086] the on-resistance of the second transistor Q2 becomes higher. In addition, in the steady state after the VDD voltage rises, since the first transistor Q1 is in the off state, no standby current flows, and it is possible to balance both the driving force difference for preventing conduction and low power consumption. Compared with Embodiment 1, it has the following characteristics: since the applied voltage for turning on the second transistor Q2 becomes lower, the on-resistance of the second transistor Q2 has a tendency to increase, but its circuit components are fewer than those in Embodiment 1, and lower power consumption is achieved.

[0087] As described above, even in a case where the slew rate of the voltage applied to the power supply voltage terminal VDD is high or the voltage applied to the power supply voltage terminal VDD vibrates, it is possible to avoid the first transistor Q1 and the second transistor Q2 from simultaneously becoming in an on state.

[0088] In addition, in a steady state after the power supply voltage rises, since the fifth transistor 210 is in an off state, no standby current flows, and it is possible to balance the driving force difference for preventing the first transistor Q1 and the second transistor Q2 from simultaneously conducting and low power consumption. Figure 4 The structure shown and Figure 2 compared with the structure shown, the applied voltage for turning on the second transistor Q2 becomes lower, so the on-resistance of the second transistor Q has a tendency to increase, but it is possible to achieve fewer circuit components and lower power consumption than in Mounting Example 1.

[0089] (Mounting Example 3)

[0090] Figure 6 is a circuit diagram showing the configuration of the semiconductor device 1 of Mounting Example 3. The first circuit 20 includes a reference voltage generation circuit 21 and a voltage comparison circuit 22. The second circuit 30 includes an output buffer 31.

[0091] The reference voltage generation circuit 21 generates a reference voltage Vref. Figure 6 An example is shown, but it is not limited to this example, and any circuit configured as a circuit capable of outputting the reference voltage Vref may be used.

[0092] The voltage comparison circuit 22 compares the voltage generated by the reference voltage generation circuit 21 with the voltage applied to the power supply voltage terminal VDD. For example, with respect to the input of a general comparator, it is formed by inputting the output of the reference voltage generation circuit 21 and the voltage between a plurality of resistors that divide the power supply voltage terminal VDD and the ground terminal GND in a predetermined ratio. The voltage comparison circuit 22 detects a voltage greater than the absolute value of the threshold voltage of the first transistor Q1 and outputs it to the output buffer 31.

[0093] The output buffer 31 controls the output of the voltage comparison circuit 22 and applies it to the gate of the second transistor Q2.

[0094] Figure 7 is a circuit of the output buffer 31 showing a mounting example. The output buffer 31 includes, for example, a sixth transistor M1, a seventh transistor M2, a fourth resistor R1, and a fifth resistor R2.

[0095] The sixth transistor M1 is a p-type MOSFET, the source is connected to the power supply voltage terminal VDD, and the gate is connected to the output of the voltage comparison circuit 22.

[0096] The seventh transistor M2 is an n-type MOSFET, whose source is connected to the ground terminal GND and whose gate is connected to the output of the voltage comparison circuit 22.

[0097] The fourth resistor R1 is connected between the drain of the sixth transistor M1 and the output terminal.

[0098] The fifth resistor R2 is connected between the drain of the seventh transistor M2 and the output terminal.

[0099] The resistance value of the fifth resistor R2 is larger than that of the fourth resistor R1. By setting the resistance values of the fourth resistor R1 and the fifth resistor R2 in this way, it is possible to make the resistance value in the current path when the second transistor Q2 is turned on larger than the resistance value in the current path when the second transistor Q2 is turned off. As a result, the driving force for turning off the second transistor Q2 can be made higher than the driving force for turning it on.

[0100] With such a resistor configuration, even when the conversion rate of the voltage applied to the power supply voltage terminal VDD is high or there is voltage oscillation, it is possible to avoid simultaneous conduction of the first transistor Q1 and the second transistor Q2.

[0101] Figure 8 It is a circuit showing another mounting example of the output buffer 31. The output buffer 31 has, for example, an eighth transistor M3 and a ninth transistor M4.

[0102] The eighth transistor M3 is a p-type MOSFET, whose source is connected to the power supply voltage terminal VDD and whose gate is connected to the output of the voltage comparison circuit 22.

[0103] The ninth transistor M4 is an n-type MOSFET, whose source is connected to the ground terminal GND, whose gate is connected to the output of the voltage comparison circuit 22, and whose drain is connected to the drain of the eighth transistor M8.

[0104] As can be seen above, the eighth transistor M3 and the ninth transistor M4 form a CMOS (Compulementary MOSFET: complementary MOS). In this mounting example, as an example, the gate width of the eighth transistor M3 is formed wider than the gate width of the ninth transistor M4.

[0105] By forming such a CMOS, it is possible to make the on-resistance value in the path where the second transistor Q2 is turned on larger than the on-resistance value in the path where the second transistor Q2 is turned off. As a result, the driving force for turning off the second transistor Q2 can be made higher than the driving force for turning on the second transistor Q2.

[0106] With such a configuration, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high or in the case of voltage oscillation, etc., it is possible to avoid simultaneous conduction of the first transistor Q1 and the second transistor Q2.

[0107] Figure 9 FIG. is a diagram showing another mounting example of the voltage comparison circuit 22. As shown in this figure, a hysteresis comparator can also be used as the voltage comparison circuit.

[0108] (Mounting Example 4)

[0109] Figure 10 FIG. is a circuit diagram showing the structure of the semiconductor device 1 of Mounting Example 3. In addition to Figure 1 the first circuit 20 and the second circuit 30, the semiconductor device 1 further has a third circuit 40.

[0110] The third circuit 40 is a circuit that, when a voltage is applied between the drain terminal DRAIN and the source terminal SOURCE before the start of the VDD power supply, takes into account both preventing the charging current to the capacitor 50 and preventing an overvoltage applied to the gate of the first transistor Q1. The capacitor 50 is externally connected between the power supply voltage and the ground voltage in the semiconductor device 1.

[0111] When charging the capacitor 50, based on the charged voltage, a current flows through each component of the semiconductor device 1. For example, this current flows in the order of the drain terminal DRAIN, the first transistor Q1, the power supply voltage terminal VDD, the capacitor 50, the ground terminal GND, the body diode of the component in the third circuit 40 that switches the first transistor Q1, the first diode 10, and the source terminal SOURCE. The third circuit 40 prevents this current.

[0112] Figure 11 FIG. is a circuit diagram showing a mounting example of the third circuit 40. The third circuit 40 has a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a fifth diode 404.

[0113] The first switch 400 is, for example, a p-type MOSFET, the source is connected to the power supply voltage terminal VDD, the gate is connected to the inverter output, and the inverter input is connected to the gate voltage application terminal GATE.

[0114] The second switch 401 is, for example, an n-type MOSFET, the source is connected to the ground terminal GND, the gate is connected to the inverter output, and the inverter input is connected to the gate voltage application terminal GATE.

[0115] One end of the sixth resistor 402 is connected to the drain of the first switch 400, and the other end is connected to the gate of the first transistor Q1. The sixth resistor 402 operates as a gate resistor for controlling the gate current of the first transistor Q1.

[0116] The anode of the fourth diode 403 is connected to the anode of the first diode 10 and the gate of the first transistor Q1, and the cathode is connected to the power supply voltage terminal VDD.

[0117] The anode of the fifth diode 404 is connected to the drain of the first switch 400 and is connected to the gate of the first transistor Q1 via the sixth resistor 402, and its cathode is connected to the drain of the second switch 401.

[0118] According to this configuration, it is possible to prevent the current flowing through the body diode of the second switch 401 for turning off the first transistor Q1 by the fifth diode 404 connected between the second switch 401, the second switch 400, and the sixth resistor 402. In addition, by connecting the fifth diode 404, when the gate voltage of the first transistor Q1 becomes a voltage lower than the ground voltage GND, although it cannot be clamped by the body diode of the second switch 401, it is possible to prevent an overvoltage at the gate of the first transistor Q1 by connecting the fourth diode 403 between the gate of the first transistor Q1 and the power supply voltage terminal VDD.

[0119] As described above, according to the third circuit 40 of the present mounting example, it is possible to achieve both prevention of the charging current to the capacitor 50 and prevention of an overvoltage of the gate voltage of the first transistor Q1.

[0120] (Mounting Example 5)

[0121] Figure 12 It is a circuit diagram showing another mounting example of the third circuit 40. The third circuit 40 includes a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a sixth diode 405.

[0122] The first switch 400 is, for example, a p-type MOSFET, the source is connected to the power supply voltage terminal VDD, the gate is connected to the output of the inverter, and the input of the inverter is connected to the gate voltage application terminal GATE.

[0123] The second switch 401 is, for example, an n-type MOSFET, the source is connected to the ground terminal GND, the gate is connected to the output of the inverter, and the input of the inverter is connected to the gate voltage application terminal GATE.

[0124] One end of the sixth resistor 402 is connected to the drain of the first switch 400, and the other end is connected to the gate of the first transistor Q1. The sixth resistor 402 operates as a gate resistor for controlling the gate current of the first transistor Q1.

[0125] The anode of the fourth diode 403 is connected to the anode of the first diode 10 and the gate of the first transistor Q1, and the cathode is connected to the power supply voltage terminal VDD.

[0126] The anode of the sixth diode 405 is connected to the gate of the first transistor Q1, and the cathode is connected to the drain of the second switch 401.

[0127] The current passing through the body diode of the second switch 401 for turning off the first transistor Q1 can be prevented by the sixth diode 405 connected between the second switch 401 and the gate of the first transistor Q1. In Mounting Example 4, since the gate resistor is in the gate current paths for both turning on and off the first transistor Q1, it is difficult to independently adjust the driving force. However, according to this mounting example, the gate current paths for turning on and off the first transistor Q1 can be made independent by the sixth diode 405 alone to adjust the driving force, and, similarly to the above mounting example, the charging current of the capacitor can be prevented.

[0128] (Mounting Example 6)

[0129] Figure 13 It is a circuit diagram showing another mounting example of the third circuit 40. The third circuit 40 includes a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a third switch 406.

[0130] The first switch 400 is, for example, a p-type MOSFET, the source is connected to the power supply voltage terminal VDD, the gate is connected to the inverter output, and the inverter input is connected to the gate voltage application terminal GATE.

[0131] The second switch 401 is, for example, an n-type MOSFET, the source is connected back-to-back with the third switch 406, the gate is connected to the inverter output, and the inverter input is connected to the gate voltage application terminal GATE.

[0132] One end of the sixth resistor 402 is connected to the drain of the first switch 400, and the other end is connected to the gate of the first transistor Q1. The sixth resistor 402 operates as a gate resistor for controlling the gate current of the first transistor Q1.

[0133] The anode of the fourth diode 403 is connected to the anode of the first diode 10 and the gate of the first transistor Q1, and the cathode is connected to the power supply voltage terminal VDD.

[0134] The third switch 406 is, for example, an n-type MOSFET, the drain is connected to the ground terminal GND, the gate is connected to the gate voltage application terminal GATE, and the source is connected back-to-back with the source of the second switch 401.

[0135] A bidirectional switch is formed by a third switch 406 connected between the second switch 401 and the ground potential, thereby preventing the current flowing through the second switch 401 of the first transistor Q1 from being cut off. In the above-described mounting example 5, when the first transistor Q1 is cut off, the driving force for cutting off only weakens by the amount of the forward voltage of the sixth diode 405 in the gate current path. However, according to the structure of the present mounting example, when the first transistor Q1 is cut off, since this voltage is the product of the on-resistance of the third switch 406 and the gate current, by using a switch element with a low on-resistance as the third switch 406, the driving force for cutting off can be enhanced.

[0136] Thus, even when a high voltage conversion rate is applied between the drain and source of the first transistor Q1, by suppressing the impedance of the cut-off current path formed by the second switch 401 and the third switch 406 to be low, it is possible to prevent the first transistor Q1 from being misturned on.

[0137] According to each of the embodiments described above, it is possible to appropriately control the first transistor Q1 and the second transistor Q2 without increasing the loop for driving the gate current of the first transistor Q1, and to make the first transistor Q1 that is normally-on driven into a normally-off driven state. According to the semiconductor device 1, it is possible to form a switch that can withstand a high voltage and safely perform a normally-off drive, and the high voltage is, for example, a situation where a high voltage of about 140V to 400V is applied to an external load.

[0138] In addition, in each of the above embodiments, although the second transistor Q2 is arranged outside the semiconductor device 1, the semiconductor device 1 may also have the second transistor Q2. In this case, the semiconductor device 1 may have an output terminal that is connected to the gate and source of the first transistor Q1 and outputs the drain current of the first transistor Q1.

[0139] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Claims

1. A semiconductor device that drives a normally - on first transistor to be normally - off, wherein: It has: A first circuit connected between a power supply voltage and a ground voltage, detecting the power supply voltage, and outputting a transition state of the power supply voltage; A second circuit connected to the power supply voltage, the ground voltage, the first circuit, and a second transistor, and outputting a driving voltage of the second transistor connected in series with the first transistor based on an output of the first circuit; And A first diode having an anode connected to a driving terminal of the first transistor and a cathode connected to an output terminal of the second transistor, The first circuit includes: A first resistor connected to the power supply voltage; A second diode as a Zener diode having an anode connected to the ground voltage and a cathode connected to the power supply voltage via the first resistor; A third transistor having a gate connected to the cathode of the second diode and a source connected to the power supply voltage; and A second resistor disposed between a drain of the third transistor and the ground voltage, The second circuit includes: A fourth transistor having a gate connected to the drain of the third transistor, a source connected to the power supply voltage, and a drain connected to a gate of the second transistor; And A third resistor disposed between a drain of the fourth transistor and the ground voltage.

2. The semiconductor device according to claim 1, wherein The first transistor is a FET using gallium nitride (GaN), and a source is connected to the power supply voltage, The second transistor is a p - type MOSFET, and a source is connected to a source of the first transistor.

3. The semiconductor device according to claim 2, wherein, It has: A fifth transistor having a drain connected to the power supply voltage, a gate connected to the ground voltage, and performing normally - on driving; and A third diode as a Zener diode having an anode connected to the ground voltage and a cathode connected to a source of the fifth transistor and a gate of the second transistor.

4. The semiconductor device according to claim 2, wherein The first circuit has: A reference voltage generation circuit that generates a reference voltage; And A voltage comparison circuit that compares the reference voltage with the power supply voltage, The second circuit has an output buffer that controls an output of the voltage comparison circuit and applies it to a gate of the second transistor.

5. The semiconductor device according to claim 2, wherein It further has a third circuit connected to a gate of the first transistor, which prevents a capacitor charging current and controls a driving voltage at a timing when the power supply voltage is turned on.

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