Device and method for controlling gradual changes in resistance in synaptic elements

Abstract

The present invention provides a memory device capable of generating a gradual resistance change for processing analysis information of a synaptic element for implementing a neuromorphic system. To address the aforementioned drawbacks, the present invention provides a memory device comprising: a memory array including a plurality of memory cells capable of selectively storing a logic state and a plurality of bit lines and word lines connected to the plurality of memory cells; a controller for controlling a write step and a read step; a write unit; and a read unit, wherein, in the write step, the controller causes the write unit to select one or more memory cells from the plurality of memory cells and sequentially apply a write voltage thereto to allow writing of a logic state, and in the read step, causes the read unit to apply a read voltage to the one or more memory cells selected for writing the logic state, and determines a synaptic weight based on the sum of currents flowing through the one or more memory cells, so that the selected one or more memory cells are identified as operating as a synaptic element.

Description

Technical Field

[0001] The present invention relates to a memory device capable of controlling gradual changes in conductivity when implementing a neuromorphic system. More particularly, the present invention relates to a memory device in which one or more memory cells selected from a memory array are identified as functioning as a synaptic element. Background Art

[0002] The AI ​​semiconductor industry is arguably in its infancy. Semiconductor design and manufacturing companies have recently begun releasing test products or early versions of their products. These are first-generation AI semiconductors based on CMOS and, from a materials perspective, are no different from existing semiconductors. Therefore, we expect to see the introduction and utilization of new materials in the second generation of AI semiconductors.

[0003] For the second generation of artificial semiconductors with an integration similar to that of biological neural networks, it is necessary to implement an artificial synapse with all the basic characteristics of a biological synapse as an element. The synapses of biological systems are accompanied by changes in synaptic weights in the process of processing signals delivered from neurons, and learning and storage functions are exhibited therethrough. Therefore, artificial synaptic elements are intended to simulate biological synapses to output changes in synaptic weights as current (or resistance), thereby exhibiting learning and storage functions. To this end, it is very important to develop an element in which a controllable and distinguishable gradual change in current (or resistance) occurs. In the most ideal artificial synaptic element, the gradual change in current (or resistance) can occur precisely in proportion to the number of pulses applied.

[0004] To achieve this goal, various artificial synaptic elements have been proposed and manufactured. Among the technologies being studied in the semiconductor field for manufacturing synaptic elements, low-resistance and high-resistance states are distinguished in a memory array, such as RRAM, PRAM, or MRAM, whose resistance can be changed. Information regarding these states is stored in each cell. Research has been conducted to achieve a digital on / off high-resistance change and to read the logical state of cells in the memory array based on this resistance change.

[0005] However, to realize artificial synaptic elements, not only does one element need to have various resistance states, but these resistance states also need to be controllable. Research and development of such elements using the aforementioned RRAM or PRAM elements is ongoing, but the results have been asymmetric and lack reproducibility. Furthermore, forming and controlling distinguishable resistance states simultaneously is insufficient. Summary of the Invention

[0006] Technical issues

[0007] An object of the present invention is to provide a memory device that is capable of inducing a gradual resistance change for information processing in a similar manner to synaptic elements used to implement neuromorphic systems.

[0008] Technical Solution

[0009] To achieve the above-mentioned object, one aspect of the present invention provides a memory device, which includes: a memory array including a plurality of memory cells capable of selectively storing logic states and a plurality of bit lines and word lines connected to the plurality of memory cells; a controller for controlling a write step and a read step; a write unit; and a read unit, wherein, in the write step, the controller selects one or more memory cells from the plurality of memory cells through the write unit and sequentially applies a write voltage to the selected one or more memory cells to allow a logic state to be written therein, and in the read step, the controller applies a read voltage to the one or more memory cells selected to have the logic state written therein through the read unit, so as to determine a synaptic weight by the sum of currents flowing through the one or more memory cells, thereby allowing the selected one or more memory cells to be identified as operating as one synaptic element.

[0010] Another aspect of the present invention provides a method for determining synaptic weights in a memory device, the memory device including a memory array including a plurality of memory cells capable of selectively storing logic states, bit lines and word lines connected to the plurality of memory cells, the method comprising the following steps: (a) selecting one or more memory cells from the plurality of memory cells and sequentially applying a write voltage to the selected one or more memory cells to write a logic state; (b) applying a read voltage to the one or more memory cells selected to have the logic state written therein; and (c) determining the synaptic weight by summing currents flowing through the one or more memory cells selected to have the logic state written therein through the applied read voltage, wherein the selected one or more memory cells are identified as functioning as one synaptic element.

[0011] Another aspect of the present invention provides a neuromorphic system, which includes: an input signal unit that generates an input signal; a synaptic part that includes multiple synaptic units that receive the signal of the input signal unit and generate current according to set weights, and a multiplier that amplifies the current generated in the synaptic units; and an output signal unit that generates an output signal by receiving the current generated from the synaptic part, wherein each of the synaptic units includes multiple memory cells that are connected to each other and can selectively store logical states, an amplification factor is set in each of the multiple memory cells, and the current flowing through the multiple memory cells through the input signal is amplified by the multiplier by the amplification factor.

[0012] Another aspect of the present invention provides a method for operating a synaptic device of a neuromorphic system in a neuromorphic system, the neuromorphic system including a plurality of synaptic units, the synaptic units including a plurality of memory cells connected to each other and located in a plurality of memory arrays having a cross-point structure, the cross-point structure including input electrode lines and output electrode lines crossing each other, the plurality of memory cells selectively storing logic states, the method comprising the following steps: (a) setting an amplification factor for each of the plurality of memory arrays; (b) selecting and combining one or more memory cells from each of the plurality of memory arrays for which the amplification factors are set, and setting a plurality of synaptic units including the plurality of memory cells; (c) applying an input signal to the plurality of synaptic units; (d) measuring a current flowing through the memory cells of the synaptic units by the input signal applied to each memory array, and adding the currents; and (e) amplifying the current measured for each memory array according to the set amplification factor of the memory array, and measuring the sum of the amplified currents in the respective memory arrays.

[0013] Another aspect of the present invention provides a method for operating a synaptic device of a neuromorphic system in a neuromorphic system, the neuromorphic system including a plurality of synaptic units, the synaptic units including a plurality of memory cells connected to each other and located in a memory array having a cross-point structure, the cross-point structure including input electrode lines and output electrode lines crossing each other, the plurality of memory cells selectively storing logic states, the method comprising the following steps: (a) setting an amplification factor for each output electrode line of the memory array; (b) selecting and combining one or more memory cells connected to the output electrode lines for which the amplification factor is set, and setting a plurality of synaptic units including the plurality of memory cells; (c) applying an input signal to the plurality of synaptic units; (d) measuring a current flowing through the memory cells of the synaptic units by the input signal applied to each output electrode line; and (e) amplifying the current measured for each output line according to the set amplification factor of the output electrode line, and measuring the sum of the amplified currents in the respective output electrode lines.

[0014] Beneficial effects

[0015] According to the present invention, a synaptic element capable of controlling a gradual resistance change with a highly linear ratio by a method for determining a synaptic weight can be provided in a memory device and a memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A diagram showing a configuration of a memory device according to the present invention;

[0017] Figure 2 An example of selecting a plurality of memory cells in a memory device according to the present invention is shown;

[0018] Figure 3 shows that a gradual conductivity change occurs in a memory device according to the invention;

[0019] Figure 4 shows a configuration example of a memory cell applied to a memory device according to the present invention;

[0020] Figure 5 An example of selecting a plurality of memory cells in a memory device according to the present invention is shown;

[0021] Figure 6 is a diagram illustrating a method for determining synaptic weights according to the present invention;

[0022] Figure 7 is a diagram illustrating a typical reading method in a memory array having a cross-point structure including memory cells having a switching function;

[0023] Figure 8 is a diagram illustrating a reading method for a memory array having a cross-point structure including memory cells having a switching function according to the present invention;

[0024] Figure 9 is a diagram illustrating a writing and reading method for a memory array including a cross-point structure having memory cells having selective memory elements according to the present invention;

[0025] Figure 10 is a diagram illustrating an inference method by a vector-matrix multiplication operation;

[0026] Figure 11 is a diagram illustrating a vector-matrix multiplication operation using a memory array having a cross-point structure;

[0027] Figure 12 is a configuration diagram of a neuromorphic system according to the present invention;

[0028] Figure 13 is a diagram illustrating a neuromorphic system according to the present invention;

[0029] Figure 14 is a diagram illustrating a neuromorphic system and an operating method thereof according to the present invention;

[0030] Figure 15 is a diagram illustrating a neuromorphic system and an operating method thereof according to the present invention;

[0031] Figure 16 is a diagram illustrating a neuromorphic system and an operating method thereof according to the present invention;

[0032] Figure 17 is a diagram illustrating a neuromorphic system and a method of operating the same according to the present invention; and

[0033] Figure 18 is a diagram illustrating a neuromorphic system and an operating method thereof according to the present invention. DETAILED DESCRIPTION

[0034] Hereinafter, the configuration and operation of the embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations will be omitted because they will obscure the present invention with unnecessary details. In addition, when an element is referred to as "including" or "comprising" a component, it does not exclude another component, but may further include another component unless the context clearly indicates otherwise.

[0035] According to the present invention, a memory device is provided, comprising: a memory array including a plurality of memory cells, each capable of selectively storing a logic state, bit lines and word lines connected to the plurality of memory cells; a controller for controlling a write step and a read step; a write unit; and a read unit, wherein, in the write step, the controller selects one or more memory cells from the plurality of memory cells via the write unit and sequentially applies a write voltage to write a logic state. In the read step, the controller applies a read voltage to the one or more memory cells selected by the read unit to write the logic state therein, and determines a synaptic weight by summing the currents flowing through the memory cells. Thus, the selected one or more memory cells are identified as operating as a synaptic element.

[0036] like Figure 1 As shown, the memory array 10 may have a cross-point structure in which word lines 11 as horizontal address lines and bit lines 12 as vertical address lines are arranged in a grid structure, and memory cells 13 are arranged at the intersections of the word lines 11 and the bit lines 12. However, this is for ease of explanation, and the present invention is not limited thereto.

[0037] The controller 20 selects a portion of the plurality of memory cells 13 from the cross-point memory array 10 through the write unit 30 and sequentially applies voltage to the selected memory cells to program the logic state. The number of selected memory cells can be determined based on the weight of the synaptic element. For example, when a memory cell can store a logic state of one bit and 128 synaptic weights are required, 128 memory cells are selected. When the selected 128 memory cells are turned on, current is caused to flow in the read step to read the 128 synaptic weights. Alternatively, when 256 synaptic weights are required, 256 memory cells are selected in the write step and these selected memory cells are programmed to the on state. Then, the 256 synaptic weights can be read in the read step.

[0038] Figure 2 An example of a memory cell selected in this manner is shown in . Figure 2 (a) shows that 6 memory cells located at a 3x2 matrix in the memory array 10 are selected to form a synaptic element. Figure 2 (b) shows that a synaptic element is formed by 256 memory cells located in a 16x16 matrix.

[0039] Figure 2The synaptic element in (b) can represent 256 synaptic weights using 256 units (T1 to T256). Since 256 synaptic weights are preferably present in order to achieve an accurate image of the input image information when processing image information, it is very important to represent such synaptic weights.

[0040] In addition, based on the binary system in computers, the number of selected memory cells may preferably be 2 n Therefore, the number of memory cells selected is preferably one of 1, 2, 4, 8, 16, 32, 64, 128, 256, 1024, or 2048. When the number of memory cells exceeds 2048, the number of memory cells selected from the array becomes too many and control thereof becomes difficult. Therefore, the number of memory cells may preferably be 2048 or less.

[0041] In the read step, the sum of the currents flowing through the memory array 10 is measured by the voltage applied to the memory array 10, and the synaptic weight in the memory array 10 can be determined from this sum. The sum of the currents varies depending on the number of memory cells selected in this manner to have a logic state written therein, and the synaptic weight can be determined in various ways.

[0042] Figure 3 This current (conductivity) change is shown in FIG. In the memory device according to the present invention, the total current gradually changes according to the number of selected memory cells, and this change is linearly proportional to the number of selected memory cells. Since the conductivity increases and decreases with excellent symmetry, the memory cell is suitable for use as a synaptic element.

[0043] In addition, the plurality of memory cells capable of storing logic states in the present invention may be memory devices capable of storing logic states of one or more bits. When the logic state is not simply on or off but has several stages, a larger synaptic weight can be represented even when the number of memory cells is small. For example, when each memory cell represents only on or off, the number of selected memory cells required to represent 256 synaptic weights is 256. On the other hand, when the memory cells are formed of variable resistive elements and can represent four levels of resistance states, 256 synaptic weights can be represented using 64 memory cells.

[0044] Each of the plurality of memory cells that can store a logic state may include a nonvolatile memory element and a selector element. Nonvolatile memory is necessary in order to store the logic state in the memory cell with low power, and each memory cell 13 needs to include a selector element so that the memory cells are sequentially selected and the logic state is written thereto in a write step, and the total current flowing through the programmed memory cells is measured in a read step.

[0045] The non-volatile memory element may be any one of flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), or magnetic random access memory (MRAM). In particular, the non-volatile memory element may be a variable resistance element such as RRAM, PRAM, or MRAM. The variable resistance element may exhibit various resistance states according to an applied write voltage and / or current pulse, and store one or more bits of logic state through the resistance state.

[0046] Furthermore, the selector element may be any one of a transistor, a diode, or a two-terminal switch element. Each memory cell can be individually selected by the selector element included therein to pass through the writing step and the reading step.

[0047] In particular, the selector element may be a two-terminal switch element. Using a two-terminal switch element as a selector element for selecting a memory cell can improve integration and reduce power consumption. The two-terminal switch element may be any one of a bidirectional (Ovonic) threshold switch, a transition metal oxide switch, a mixed ionic electron conductor (MIEC) switch, a complementary resistance switch, or doped amorphous silicon.

[0048] In addition, the plurality of memory cells in the present invention may include a selective memory element that can store a logic state. A selective memory element refers to an element having both non-volatile memory characteristics and selector element characteristics. A selective memory element refers to an element that can store a logic state by changing resistance and simultaneously function as a selection element by causing a resistance change based on a constant voltage (i.e., a threshold voltage).

[0049] For example, in the case of a bidirectional threshold switch made of a chalcogenide material, different resistance states can be created by applying write voltages with different polarities, and writing and reading using the bidirectional threshold switch is possible. Chalcogenide materials without phase transitions can also be variable resistance elements and have unique switching characteristics that cause a constant resistance to change near a threshold voltage.

[0050] In this way, when using a variable resistance element including a chalcogenide material without phase change, such as an existing bidirectional threshold switch element, one or more memory cells can be selected by switching characteristics, and each logic state can be stored by the variable resistance characteristics.

[0051] Such an element can be represented as a selective memory element, and in this case, an additional memory element or selector element is not required. Therefore, a high-density memory device is achieved and power consumption can be reduced. As such a chalcogenide material, an In-Ge-As-Se alloy, a Te-Se alloy, an As-Se alloy, a Ge-Te alloy, a Ge-Se alloy, an As-Se-Te alloy, a Ge-As-Se alloy, a Ge-As-Sb alloy, a Ge-Sb-Te alloy, a Ge-Sb-Se alloy, a Ge-As-Te alloy, a Si-Ge-As-Se alloy, a Si-Te-As-Ge alloy, an In-Sb-Te alloy, an In-Sb-Se alloy, an In-Ge-As alloy, an In-Ge-Te alloy, an In-Te alloy, etc. can be used. However, in addition to the above materials, a material can also be used by which a logic state can be stored and a switching function can be enabled according to a resistance change.

[0052] Figure 4 An example of the memory cell 13 described above is shown in FIG. For reference, the shape and configuration of each memory cell can be modified in various ways. For example, the selector element or the memory element can be omitted, or the electrode can be omitted. Alternatively, the positions of the selector element and the memory element can be switched.

[0053] Figure 4(a) shows a memory cell including a memory element and a selector element. The word line 11, which is one of the access lines to the memory cell, passes through the plane vertically, and the bit line 12 passes through the plane in parallel. The memory cell 13 is arranged between these vertically intersecting word lines 11 and bit lines 12. Electrodes 1331 and 1332 are arranged between the memory element 1310 and the selector element 1320 connected to the word line 11 and the bit line 12. Between the electrodes 1331 and 1332, there are the memory element 1310, the selector element 1320, and the electrode 1333 for connecting therebetween. The memory element 1310 of the memory cell 13 can be any one of non-volatile memories such as flash memory, RRAM, PRAM, or MRAM, and the selector element 1320 can be any one of a transistor, a diode, or a two-terminal switching element. For example, the memory element 1310 can be any one of flash memory, RRAM, PRAM, or MRAM, and the selector element 1320 can be a transistor. As another example, the memory element 1310 may be any one of RRAM, PRAM, or MRAM, and the selector element 1320 may be a two-terminal switch element. Here, the two-terminal switch element may be a bidirectional threshold switch.

[0054] Additionally, the memory unit 13 may include a selective memory element. Figure 4 (b) shows an example in which the memory cell 13 includes a selective memory element 1330 and electrodes 1331 and 1332. The selective memory element 1330 may include a chalcogenide material without a phase change, which enables the memory cell to be selected using unique switching characteristics, and the logic state to be written using a variable resistance characteristic that appears according to the write conditions. An example of the selective memory element 1330 may be a bidirectional threshold switching element including a chalcogenide material. Although typically connected to an RRAM, PRAM, etc. to function as a selector element, the bidirectional threshold switching element may be used to exhibit both variable resistance characteristics and selection functions. The chalcogenide material may be an alloy including In-Ge-As-Se.

[0055] In addition, the write unit 30 according to the present invention is a memory device including a DC counter. The controller 20 sequentially selects one or more memory cells from the memory array 10 through the write unit 30 including the DC counter and sequentially programs the logic state. There may be one or more DC counters.

[0056] Furthermore, according to the present invention, the read unit 40 provides a memory device including an analog-to-digital converter (ADC). The ADC is a device for converting a continuous physical quantity into a digital value, and by using the ADC, the controller 20 can determine the synaptic weight by the flow of current flowing through the entire memory array 10.

[0057] The one or more memory cells selected to be programmed with a logic state in the write step may be a memory device in which all memory cells are connected to one of the bit lines. When the selected memory cells are connected to one bit line and only the current flowing through the connected bit line is measured, the current flowing through the entire memory array can be measured, which is effective in terms of device configuration.

[0058] In addition, the present invention can provide a memory device in which one or more cells selected for programming a logic state in a write step are connected to one of the word lines. Similarly, only the current flowing through the connected word line can be measured, which is efficient in terms of device configuration.

[0059] Figure 5 The configuration examples of various synaptic elements are shown. These are only for the convenience of explanation, and the present invention is not limited thereto. The number of column lines and row lines included in the memory cell array can be changed as needed.

[0060] Figure 5 (a) shows a structure in which the memory cells selected to have the logic states written therein, that is, the memory cells A1 to An forming a synapse element, are all connected to the same bit line BLA1. Thus, when the memory cells A1 to An forming a synapse element are connected to a single bit line, during a write step, the controller 20 applies voltages via a plurality of word lines WLA1 to WLAN and a single bit line BLA1 so that the logic states are sequentially stored in the memory cells A1 to An. The write unit 30 can sequentially apply voltages to the memory cells A1 to An via a DC counter so that the logic states are written therein. Here, one or more DC counters can be connected to the word lines to which the memory cells A1 to An are connected to control selective writing.

[0061] Thereafter, in a read step, the controller 20 causes the read unit 40 to determine the synaptic weight by summing the currents flowing through the memory cells A1 to An (i.e., synaptic elements). The read unit 40 may include an ADC to measure the sum of the currents at once, and when all selected cells are connected to a single bit line, the ADC may be connected to the bit line to assist in measuring the sum of the currents. Such an ADC may be a sense amplifier.

[0062] Figure 5(b) shows a structure in which the memory cells selected to have the logic states written therein, i.e., the memory cells B1 to Bm forming a synaptic element, are all connected to the same word line WLB1. Thus, when the memory cells B1 to Bm forming a synaptic element are connected to a single word line, during a write step, the controller 20 applies voltages via a plurality of bit lines BLB1 to BLBm and a single word line WLB1 so that the logic states are sequentially stored in the memory cells B1 to Bm. The write unit 30 can cause voltages to be sequentially applied to the memory cells B1 to Bm via a DC counter so that the logic states are written therein. Here, one or more DC counters can be connected to the bit lines to which the memory cells B1 to Bm are connected and control the selective writing. Thereafter, during a read step, the controller 20 causes the read unit 40 to determine the synaptic weight by summing the currents flowing through the memory cells B1 to Bm (i.e., the synaptic element). The read unit 40 may include an ADC to measure the sum of currents at a time, and when all selected cells are connected to one word line, the ADC may be connected to the word line to assist in measuring the sum of currents. Such an ADC may be a sense amplifier.

[0063] Figure 5 (c) shows a structure in which the memory cells selected to have the logic states written therein, i.e., the memory cells C1 to Cpk forming a synapse element, are all connected to multiple word lines and multiple bit lines. Thus, in a write step, the controller 20 sequentially applies voltages to the memory cells C1 to Cpk forming a synapse element via the multiple word lines WLC1 to WLCk and the multiple bit lines BLC1 to BLCp connected to the memory cells C1 to Cpk, and stores the logic states in the memory cells C1 to Cpk. The write unit 30 can sequentially apply voltages to the memory cells C1 to Cpk via a DC counter and write the logic states therein. Here, one or more DC counters can be connected to the bit lines and word lines connected to the memory cells C1 to Cpk to control selective writing. Thereafter, in a read step, the controller 20 causes the read unit 40 to measure the sum of the currents flowing through the memory cells C1 to Cpk (i.e., the synapse element) to determine the synapse weight. The read unit 40 may include an ADC to measure the sum of the currents at one time, and when the selected cell is connected to multiple word lines and bit lines, the ADC may also be connected to the word lines and bit lines to assist in measuring the sum of the currents. Such an ADC may be a sense amplifier.

[0064] The present invention provides a method for determining synaptic weights in a memory device, the memory device including a memory array having a plurality of memory cells selectively storing logic states, and bit lines and word lines connected to the plurality of memory cells, the method comprising the following steps: (a) selecting one or more memory cells from the plurality of memory cells and sequentially applying a write voltage to write a logic state therein; (b) applying a read voltage to the one or more memory cells selected to have the logic state written therein; and (c) determining the synaptic weight by summing currents flowing through the one or more memory cells selected to have the logic state written therein, wherein the selected one or more memory cells are identified as functioning as a synaptic element.

[0065] In a cross-point structured memory array, one or more memory cells are selected, logic states are written therein, and a synaptic weight is determined by the sum of currents flowing through the memory cells selected to have the logic states written therein in this manner, so that the selected one or more memory cells can be identified as operating as one synaptic element.

[0066] The number of selected memory cells can be determined based on the weight of the synaptic element. In a neuromorphic system, the signals X1 to X1 from the front neurons n Input signals are input to synapses, and output signals are output by weighting the input signals according to the weights set for each synapse. For this reason, it is important to have different weights for the respective synapses. When using synapses as memory elements, it is necessary to have various conductivities for each memory element in order to have various weights. To this end, in the present invention, a synapse element is configured with multiple memory cells instead of a single memory cell, thereby exhibiting various conductivities.

[0067] For example, when a memory cell can store a one-bit logic state and 128 synaptic weights are required, 128 cells are selected and turned on. Then, by passing current through the 128 cells in a read step, the 128 synaptic weights can be read. Similarly, when 256 synaptic weights are required, 256 cells are selected and turned on in a write step. Then, in a read step, the 256 synaptic weights can be read.

[0068] When Figure 6 When describing this in more detail in , if the input signal of X1 is applied to synapse W1 and a weight of 128 is set in synapse W1, then the synaptic weight for W1 turns on 128 units C1 to C 128 The input signal of X1 is applied to 128 cells, and the current output from them is measured.

[0069] Similarly, if the input signal of X2 is applied to synapse W2 and a weight of 256 is set in synapse W2, the synaptic weight for W2 turns on 256 units C1 to C2. 256 , and the input signal of X1 is applied to 256 units and the current output therefrom is measured.

[0070] This allows various synaptic weights to be set by measuring the current flowing through several memory cells simultaneously.

[0071] Meanwhile, the memory cell can be a memory device capable of storing one bit or multiple logic states. When the logic state is not simply on or off but has multiple stages, a larger synaptic weight can be represented even when the number of selected memory cells is small. For example, when each memory cell represents only on or off, the number of selected memory cells required to represent 256 synaptic weights is 256. On the other hand, when the memory cell is formed of a variable resistive element and can represent a four-level resistance state, 256 synaptic weights can be represented using 64 memory cells.

[0072] In addition, in the present invention, one or more memory cells capable of selectively storing a logic state provide a method for determining a synaptic weight in a memory device including a two-terminal switch element or a selective memory element, wherein, in the above step (b), the read voltage is within a range in which all one or more memory cells that have been selected to have the logic state written therein are not turned on, and the range is greater than a voltage applied to one or more memory cells that are not selected from the memory array.

[0073] A two-terminal switching element or a selective memory element has a switching function in which a large resistance change occurs when a voltage equal to or greater than a specific level is applied. The voltage that causes the resistance change in the two-terminal switching element or the selective memory element is expressed as a threshold voltage, and the phenomenon in which the resistance change occurs is expressed as conduction.

[0074] A typical read process in which a switching function is used in a memory array with a cross-point structure such as the present invention is performed by using the characteristics of the switching element to allow only a very low current to flow through cells that are not selected at a threshold voltage or lower voltage, and by applying to the selected cell a voltage that allows the logical state of the cell to be distinguished.

[0075] will pass Figure 7 A typical method for reading the current of a selected cell in a memory array including a cross-point structure of a two-terminal switching element or a selective memory element is described. Figure 7 In the inhWhen applied to unselected cells, in this area, cells with high resistance are not distinguished from cells with low resistance, and the flow of current is very small. read1 applied to the selected cell and makes V read1 Meet V th_A <V read1 <V th_B , where V th_A is the threshold voltage of the cell with low resistance, V th_B is the threshold voltage of a cell with high resistance and allows the logic state to be distinguished by the current flowing through the selected cell. Figure 7 In, according to V read1 , current I target,off flows through the cell with high resistance, and the current I target,on This method allows only one cell to be selected from the memory array and only the on or off state to be read in digital format. This is because when a read voltage is applied to a cell in the on state, the current flowing through that cell is so large that current measurement of other cells is impossible.

[0076] Will refer to Figure 8 Describes another method for reading the current of a selected memory cell. When V is applied to the unselected cells inh In this region, the current flows according to the resistance state of the cell are not distinguished from each other, and the current is very small. read1 (V th_A <V read1 <V th_B ) method is different, the reading voltage V read1 (V th_A <V read1 <V th_B ) at the threshold voltage V of the cell with low resistance th_A and the threshold voltage V of the cell with high resistance th_B Between, such as with 'V read2 'of Figure 8 As shown in , the read voltage is within the voltage range of the sub-threshold region in which all selected one or more cells are not turned on, and is within a range greater than the voltage applied to the unselected one or more cells. In other words, in Figure 8 In the example, read the voltage V read2 Greater than V inh , and is less than the threshold voltage V of the cell in the lowest resistance state among the selected cells th1In this way, when reading in the subthreshold region, simultaneous reading of multiple cells becomes possible. This is because, unlike typical methods, even when a read voltage is applied to a cell in the on state, the current flowing through the cell is not large, so the sum of the currents flowing through the multiple cells can be easily measured by applying the read voltage to the multiple cells simultaneously.

[0077] In the present invention, the two-terminal switching element may be any one of a bidirectional threshold switching element, a transition metal oxide switching element, a mixed ion-electron conductor switching element, a complementary resistance switching element, and doped amorphous silicon. In addition to the above materials, a material in which a switching function is enabled that causes a resistance change based on a threshold voltage may also be used.

[0078] Alternatively, a selective memory element refers to an element having both non-volatile memory characteristics and selector element characteristics. In other words, it means that it is capable of storing a logic state by a change in resistance, and also operates as a selector element by causing a change in resistance based on a constant voltage (i.e., a threshold voltage). Such an element can be represented as a selective memory element, and in this case, an additional memory element or a selector element is not required. Therefore, a high-density memory device is achieved, and power consumption can be reduced. An example of such a selective memory element can be a bidirectional threshold switching element comprising a chalcogenide material. This is because although a chalcogenide threshold switching element is generally connected to an RRAM, PRAM, etc. used as a selector element, it can be used only to exhibit both variable resistance characteristics and selection functions. As chalcogenide materials, In-Ge-As-Se alloys, Te-Se alloys, As-Se alloys, Ge-Te alloys, Ge-Se alloys, As-Se-Te alloys, Ge-As-Se alloys, Ge-As-Sb alloys, Ge-Sb-Te alloys, Ge-Sb-Se alloys, Ge-As-Te alloys, Si-Ge-As-Se alloys, Si-Te-As-Ge alloys, In-Sb-Te alloys, In-Sb-Se alloys, In-Ge-As alloys, In-Ge-Te alloys, In-Te alloys, etc. can be used. However, in addition to the above materials, materials that can store logical states and enable switching functions by resistance changes can also be used.

[0079] In addition, a method for determining synaptic weights is provided in a memory device including a two-terminal switch element or a selective memory element, wherein in the above step (a), a write voltage turns on one or more memory cells selected from the plurality of memory cells and has a first polarity for writing a first logic state and a second polarity for writing a second logic state, the first polarity and the second polarity being opposite to each other, and in the above step (b), a read voltage has the same polarity as the first polarity of the write voltage, wherein the one or more selected memory cells are identified as operating as a synaptic element.

[0080] When a voltage of a first polarity equal to or higher than a threshold voltage is applied to a memory cell including a two-terminal switching element or a selective memory element, and then the voltage of the first polarity is applied to the memory cell, the memory cell has a low threshold voltage in the direction of the first polarity to exhibit a low resistance state. Initially, even in the case of having a high threshold voltage of the first polarity and being in a high resistance state, when a voltage of the first polarity equal to or higher than the threshold voltage is applied, the memory cell also changes to a low resistance state. In addition, when a voltage of a second polarity equal to or higher than the threshold voltage is applied to the memory cell, which has an opposite polarity to the first polarity, and then the voltage of the first polarity is applied, the memory cell has a high threshold voltage in the direction of the first polarity and exhibits a high resistance state. Even in the case of having the first polarity and being in a low resistance state before the voltage of the second polarity is applied, when the threshold voltage of the second polarity or higher is applied, the memory cell also changes to having a high threshold voltage in the direction of the first polarity.

[0081] This is Figure 9 As shown in Figure 9 In the voltage-current curve diagram (a), when a first forward conduction voltage V of a first polarity (+) is applied along line 101, t And then when a read voltage of the same first polarity (+) is applied, the memory cell has a low threshold voltage V along line 102. t,LRS (In other words, a low resistance state.) However, when a voltage having a second polarity (-) equal to or greater than the threshold voltage is applied along line 103 having a polarity opposite to the first polarity (+) and then a read voltage of the first polarity (+) is applied, the memory cell exhibits a high threshold voltage V along line 104. t,HRS In this way, when the polarity of the write voltage is different in the write step, the resistance state becomes different, and the resistance difference can be obtained by Figure 9 (a) and Figure 9106 in (b). Thereafter, in a read step, as described above, the synaptic weight can be determined by measuring the current flowing through the selected memory cell by applying a read voltage within a range 105 in which the memory cell is not conducting and which is greater than a voltage applied to one or more cells not selected from the memory array.

[0082] The present invention provides a method for determining synaptic weights in which one or more memory cells selected to have a logic state written therein are all connected to one bit line. Furthermore, the present invention provides a method for determining synaptic weights in which one or more memory cells selected to have a logic state written therein are all connected to one word line. Connecting the memory cells selected in this manner to one word line or one bit line is effective in terms of device configuration.

[0083] In addition, the present invention provides a method for determining a synaptic weight, wherein the number of one or more memory cells having a logic state written therein selected in step (a) is any one of 1, 2, 4, 8, 16, 32, 64, 128, 256, 1024, and 2048, wherein the selected one or more memory cells are identified as operating as one synaptic element. This is because based on the binary system in computers, the number of selected cells is preferably 2 n Therefore, the number of cells to be selected is preferably any one of 1, 2, 4, 8, 16, 32, 64, 128, 256, 1024, and 2048. In the case of exceeding 2048, the number of cells to be selected from the array is too large, and thus control becomes difficult. Therefore, the number of cells to be selected is preferably 2048 or less.

[0084] In this invention, a new neuromorphic system and its operation method will be described.

[0085] In deep learning algorithms, vector-matrix multiplication (VMM) operations are key computational operations for both training and inference.

[0086] When referring to Figure 10 When describing the VMM method for image recognition, the image is divided into N×N regions, weights are set for each N×N region, and information such as brightness and darkness are input as various input signals. When expressed in a neuromorphic system, the input signal X i is the signal from the front neuron, the output current I tot is the output signal to the post-neuron, and W i is the weight by which the input signal is multiplied through the synapse. In this way, by totCompare with the reference value and find the synapse with the closest weight to identify the image, I tot It is the current obtained by summing the product of the input signal and the weight.

[0087] However, there are many problems in implementing such operations in existing computing systems, such as power consumption and device size.

[0088] To solve this problem, recent research is actively trying to solve this problem by using a cross-point structure using new memories such as resistive random access memory (RRAM), phase change random access memory (PRAM), and magnetic random access memory (MRAM).

[0089] The memory array of the cross-point structure has a structure in which input electrode lines and output electrode lines cross each other, and the input electrode lines and the output electrode lines are connected through memory cells at intersections where the input electrode lines and the output electrode lines cross each other.

[0090] Figure 11 A VMM using a cross-point memory array has been described in . Figure 11 In the embodiment, when the column metal line 121 is kept in the ground state, a vector X is applied to the row metal line 122, which can be represented as i When the input signal is , the current flowing through each memory at the intersection (i, j) becomes X i W ij Since the current flowing through these column lines 121 becomes the sum of the currents flowing through the memories located in the same column line 121, I j =X1*W 1j +X2*W 2j +X3*W 3j +...+X n *W nj ( Figure 11 where j is 1 to m).

[0091] In this way, the inference process is performed by comparing each of the m currents output through the column line 121 with the reference value.

[0092] Here, the input signal X i It can be a pulse with constant width and different height, a pulse with constant height and different width, or a pulse with constant width and height and different times. ij It can be expressed by the conductivity of the memory at each point of the memory array of the cross-point structure.

[0093] By the way, here, the weight W ijCorresponding to the conductivity of the memory. To improve the accuracy of inference, it is necessary to gradually store various values, that is, various conductivity values, in the memory. As the diversity increases, the accuracy of inference also increases. Therefore, for this purpose, new memories capable of storing conductivity values ​​at various stages are actively developed, but satisfactory results have not yet been achieved.

[0094] To improve the result, the present invention may provide a new neuromorphic system and a method of using the same, which is capable of using multiple memory cells instead of one memory cell to exhibit various conductivities W. ij That is, the weight is not expressed by configuring the synapse with one memory cell, but various weights can be freely set by configuring the synapse with multiple memory cells.

[0095] The novel neuromorphic system and method using the system provided by the present invention uses multiple units instead of one memory unit to represent W as a weight corresponding to a single input value. ij , and various conductivities can be expressed by setting a magnification factor according to the number of bits in each of a plurality of units. The magnification factor can follow the number of bits in the binary number system.

[0096] This is Figure 12 Simplify and express in. Figure 12 (a) shows a neuromorphic system including an input signal unit 200, a synaptic part 300 and an output signal unit 400, the synaptic part 300 includes a plurality of synaptic units 310 and a multiplier 320, the multiplier 320 is capable of amplifying the current flowing through these synaptic units and applying the input signal generated from the input signal unit 200 to the synaptic part 300, and the output signal unit 400 measures the current flowing through the synaptic part 300.

[0097] In this neuromorphic system, each synaptic unit 310 located in the synaptic part 300 includes a plurality of memory cells 311, and an amplification factor is set in each of these memory cells 311, and the current flowing through these memory cells is amplified by the amplification factor by the multiplier 320, so that the sum of these amplified currents can eventually become the current flowing through the synaptic unit 310. Since a plurality of memory cells to which the amplification factors are set are included in one synaptic unit 310, various weights can be expressed.

[0098] In this case, various shapes may appear depending on the positions of a plurality of memory cells and the connection of a multiplier for amplifying current.

[0099] First, the multiple memory cells included in a synaptic unit can be located in different memory arrays. In this case, the amplification factor is set in each memory array so that all memory cells located in the same memory array have the same amplification factor. One multiplier is connected to one memory array. Through this connection, the memory cells included in a synaptic unit are distributed across several memory arrays, and the weights are determined by the sum of the currents flowing through the memory cells.

[0100] This will refer to Figure 13 As in the general neuromorphic system with a crosspoint structure, the input signal X i Through the synaptic unit with weight W 11 To W n1 Here, the synaptic unit is conventionally configured with one memory cell, but in the present invention, the synaptic unit is configured with a plurality of memory cells, and the plurality of memory cells are again arranged in a plurality of memory arrays. Although Figure 13 , k memory arrays are shown in FIG. , and the number of memory arrays can be different depending on the needs, such as 2, 4, 16, 32, 64, etc.

[0101] Amplification factors mf(1) to mf(k) are set for the plurality of memory arrays, respectively, and the amplification factor may be 2 n (n includes 0 and positive integers) to represent the number of bits in the binary number system. For example, in Figure 12 In the example, the number of memory arrays is 8. Therefore, mf(1) is 2 7 , mf(2) is 2 6 , mf(3) is 2 5 , and the final mf(8) can be 2 0 .

[0102] exist Figure 13 In the synaptic unit W 11 There are k memory cells A1C configured 11 、A2C 11 、A3C 11 ,...,A k C 11 When the input signal X1 is input to each of the k memory cells, a current X1*A1C is generated in each of the k memory cells. 11 、X1*A2C 11 、X1*A3C 11 ,...,X1*A k C 11 .

[0103] The generated currents are amplified by multipliers mp(1) to mp(k), respectively, which are connected to memory arrays, respectively, where the amplification factors mf(1) to mf(k) are set according to the memory arrays in which the memory cells are located, respectively, and finally the following output signals are shown.

[0104] X1W 11 =X1*(A1C 11 *mf(1)+A2C 11 *mf(2)+...+A k C 11 *mf(k))

[0105] Finally, by summing the output signals of n synaptic units, the output signal I1 that can be used for inference can be obtained as follows: Figure 14 shown.

[0106] I1=X1*W 11 +X2*W 21 +X3*W 31 +...+X n *W n1

[0107] =X1*(A1C 11 *mf(1)+A2C 11 *mf(2)+...+A k C 11 *mf(k))

[0108] +X2*(A1C 21 *mf(1)+A2C 21 *mf(2)+...+A k C 21 *mf(k))+...

[0109] +X n *(A1C n1 *mf(1)+A2C n1 *mf(2)+...+A k C n1 *mf(k))

[0110] Therefore, it is necessary to amplify the current flowing through each memory cell of each synaptic unit according to the amplification factor and add these currents. As a result, the obtained value becomes equal to the value X1*A multiplied by the amplification factor mf(k) set in the memory array by the multiplier mp(k). k C 11 +X2*A k C 21 +...+Xn *A k C n1 The value obtained by amplifying and adding is the sum of the currents flowing through the same output electrode line in each memory array. Therefore, it can be expressed again as follows.

[0111] I1=(X1*A1C 11 +X2*A1C 21 +...+X n *A1C n1 )*mf(1)

[0112] +(X1*A2C 11 +X2*A2C 21 +...+X n *A2C n1 )*mf(2)+...

[0113] +(X1*A k C 11 +X2*A k C 21 +...+X n *A k C n1 )*mf(k)

[0114] When describing in more detail an operating method using such a neuromorphic system including a plurality of memory arrays, the operating method may include: (a) setting an amplification factor for each of the plurality of memory arrays; (b) selecting and combining one or more memory cells from each of the plurality of memory arrays for which the amplification factor is set, and setting a plurality of synaptic units including the plurality of memory cells; (c) applying an input signal to the plurality of synaptic units; (d) measuring a current flowing through the memory cells of the synaptic unit by the input signal applied for each memory array; and (e) amplifying the current measured for each memory array according to the set amplification factor of the memory array, and measuring the sum of the amplified currents in the respective memory arrays.

[0115] Amplification factors mf(1) to mf(k) are set for the memory arrays, respectively, and memory cells are selected from the memory arrays and combined to set a plurality of synaptic cells. Figure 14 In the synaptic unit W 11 becomes A1C 11 、A2C 11 、A3C 11 ,...,A k C 11 Combination of W 21 becomes A1C 21 、A2C21 、A3C 31 ,...,A k C 21 The combination of the last W n1 becomes A1C n1 、A2C n1 、A3C n1 ,...,A k C n1 combination.

[0116] When the input signal X1 to X n When applied to the synaptic units arranged in this manner, current flows in the memory cells included in each of these synaptic units. For example, X1*A1C 11 、X1*A2C 11 、X1*A3C 11 ,...,X1*A k C 11 The currents flowing through the synaptic unit W 11 Memory cell A1C in 11 、A2C 11 、A3C 11 ,..,A k C 11 .

[0117] In this way, the current flowing through the individual memory cells of the synaptic unit is measured and added for each memory array. Figure 14 In the example, the sum of the currents flowing through the memory array A1 is X1*A1C. 11 +X2*A1C 21 +...+X n *A1C n1 When the sum of the measured and added currents is multiplied by the amplification factor ((X1*A1C) set for each memory array 11 +X2*A1C 21 +...+X n *A1C n1 )*mf(1)), the sum of the amplified currents in each memory array A1 to Ak is measured, and I1 is derived, which is the current value required for inference.

[0118] On the other hand, when the memory cell includes a two-terminal switching element or a selective storage device and the total current flowing through a memory array is measured, when one memory cell is turned on due to being in a low resistance state, a large current flows in the turned-on memory cell, and therefore, a large voltage drop occurs, making it impossible to read the current change in other memory cells. Therefore, when the input signal is within the voltage range in which the memory cell can change to the low resistance state (refer to Figure 7 ), it is necessary to measure the input signal and the output signal corresponding to the input signal for each memory cell in a memory array, and then calculate the sum of these. To this end, the memory array may further include a capacitor capable of storing the current flowing to each output line.

[0119] On the other hand, even when the memory cells include two-terminal switching elements or selective memory elements and the sum of currents flowing through one memory array is measured, the voltage of the input signal can be set within a range in which neither the memory cells in the high resistance state nor the memory cells in the low resistance state formed by the characteristics of the two-terminal switching elements or selective memory elements are turned on (see Figure 8 ). Accordingly, since there are no turned-on memory cells, the overall power consumption can be reduced, and since a voltage drop does not occur significantly, the current flowing through a memory array can be measured simultaneously.

[0120] In order to obtain different current values ​​I j , repeat the above method for each output line of each memory array, as Figure 15 By converting the current value I1 to I m The current value is compared with the reference value to determine the closest current value through a constant function.

[0121] In addition, in the present invention, a plurality of memory cells may be located in a single memory array. Furthermore, in this case, it may be a neuromorphic system, wherein the memory array has a crosspoint structure including input electrode lines and output electrode lines that intersect each other, a multiplier is connected to each output electrode line, a plurality of memory cells of the synaptic unit are located in the plurality of output electrode lines, an amplification factor is set for each output electrode line, and the same amplification factor is set for all memory cells located in the same output electrode line, and a current flowing in each memory cell of the synaptic unit due to an input signal is amplified by the multiplier according to the amplification factor.

[0122] As mentioned above, n input signals X1 to X i Through n synaptic units with weights W 11 To W n1 To output an output signal, as in a general neuromorphic system of a crosspoint structure. Here, in the present invention, the synaptic unit is configured with a plurality of memory cells, and a plurality of memory cells can be provided for each output line in one memory array.

[0123] This is Figure 16 and Figure 17 As shown in the figure, the synaptic unit W 11 Includes multiple memory cells L1C 11 、L2C11 ,...L k C 11 The amplification factors mf(1) to mf(k) are respectively set to the output electrode lines on which a plurality of memory cells are respectively arranged, and thus the multipliers mp(1) to mp(k) are respectively connected to the output electrode lines. Here again, the amplification factor can be 2 n (n is a positive integer including 0) to represent the number of digits in the binary system. For example, in Figure 16 and Figure 17 In the example, the number k of output electrode lines with different amplification factors is 8. Therefore, mf(1) is 2 7 , mf(2) is 2 6 , mf(3) is 2 5 , and the final mf(8) can be 2 0 .

[0124] Figure 16 shows the case where output electrode lines with the same amplification factor are grouped together, Figure 17 A case is shown in which a multiplier is provided for each output electrode line because the amplification factor is different for each adjacent output electrode line.

[0125] exist Figure 16 In the synaptic unit W 11 There are k memory cells L1C configured 11 、L2C 11 、L3C 11 ,...,L k C 11 , and when the input signal X1 is input to each of the k memory cells, correspondingly, a current X1*L1C is generated in the k memory cells respectively. 11 、X1*L2C 11 、X1*L3C 11 、...、X1*L k C 11 .

[0126] Again, X2*L1C 21 、X2*L2C 21 、X2*L3C 21 ,...,X2*L k C 21 The current is respectively in W as the synaptic unit 21 generated in the memory cell.

[0127] The generated current is amplified by the amplification factor set according to the output electrode line where the memory cells are respectively located, and finally, the synaptic unit W 11 The output signal is shown below.

[0128] X1W 11 =X1*(L1C 11 *mf(1)+L2C 11 *mf(2)+...+L k C 11 *mf(k))

[0129] Finally, by summing the output signals of each synaptic unit, the output signal I1 that can be used for inference can be obtained as follows: Figure 16 shown.

[0130] I1=X1*W 11 +X2*W 21 +X3*W 31 +...+X n *W n1

[0131] =X1*(L1C 11 *mf(1)+L2C 11 *mf(2)+...+L k C 11 *mf(k))

[0132] +X2*(L1C 21 *mf(1)+L2C 21 *mf(2)+...

[0133] +L k C 21 *mf(k))+...+X n *(L1C n1 *mf(1)+L2C n1 *mf(2)+...+L k C n1 *mf(k))

[0134] Therefore, it is necessary to amplify the current flowing through each memory cell of each synaptic unit according to the amplification factor and add these currents. As a result, the obtained value becomes equal to the value X1*A by the amplification factor mf(k) set in the memory array. k C 11 +X2*A k C 21 +...+X n *A k C n1 The obtained value is amplified and added, and is the sum of the currents flowing through the same output electrode line in each memory array.

[0135] I1=(X1*A1C11 +X2*A1C 21 +...+X n *A1C n1 )*mf(1)

[0136] +(X1*A2C 11 +X2*A2C 21 +...+X n *A2C n1 )*mf(2)+...

[0137] +(X1*A k C 11 +X2*A k C 21 +...+X n *A k C n1 )*mf(k)

[0138] like Figure 16 As shown, Figure 17 Unlike the case where the output electrode lines are adjacent to each other as shown, output electrode lines having the same amplification factor in one memory array may have a different amplification factor for each adjacent electrode line.

[0139] When describing an operating method using a neuromorphic system, in which a synaptic unit includes multiple memory cells, and the multiple memory cells are located in one memory, in more detail, the operating method may be a method of operating a synaptic device for a neuromorphic system, the method comprising: (a) setting an amplification factor for each output electrode line of the memory array; (b) selecting and combining one or more memory cells connected to the output electrode line for which the amplification factor is set, and setting multiple synaptic units including the multiple memory cells; (c) applying an input signal to the multiple synaptic units; (d) measuring a current flowing through the memory cells of the synaptic unit by the input signal applied to each output electrode line; and (e) amplifying the current measured for each output line according to the set amplification factor of the output electrode line, and measuring the sum of the amplified currents in the respective output electrode lines.

[0140] Amplification factors mf(1) to mf(k) are set for the output electrode lines, respectively. Here, a plurality of synaptic units are set by selecting and combining memory cells. Figure 16 In the synaptic unit W 11 It is L1C 11 、L2C 11 、L3C 11 ,...,L k C 11 combination.

[0141] When the input signal X1 to X n When applied to the synaptic units arranged in this manner, current flows in the memory cells included in each of these synaptic units. For example, X1*L1C 11 、X1*L2C 11 、X1*L3C 11 、...、X1*L k C 11 The currents flowing through the synaptic unit W 11 Memory cell L1C in 11 、L2C 11 、L3C 11 ,...,L k C 11 .

[0142] In this way, for each output electrode line, the currents flowing through the individual memory cells of the synaptic unit are measured and added. Figure 16 , flows through the memory output electrode line L 1-1 The sum of the currents is X1*L1C 11 +X2*L1C 21 +...+X n *L1C n1 When the sum of the measured and added currents is multiplied by the value of each output electrode line ((X1*L1C 11 +X2*L1C 21 +...+X n *L1C n1 )*mf(1)) set the amplification factor, measure each output electrode line L 1-1 To L k-1 The sum of the amplified currents in is used to derive I1 as the current value required for estimation.

[0143] On the other hand, when the memory cell includes a two-terminal switching element or a selective storage device and the sum of the currents flowing through one output electrode line is measured, when one memory cell is turned on due to being in a low resistance state, a large current flows in the turned-on memory cell, and therefore, a large voltage drop occurs, making it impossible to read the current changes in other memory cells on the same output electrode line. Therefore, when the input signal is within the voltage range in which the memory cell can change to a low resistance state (refer to Figure 7 ), it is necessary to measure the input signal and the output signal corresponding to the input signal for each memory cell in an output electrode line one by one, and then calculate their sum. To this end, the memory array may further include a capacitor capable of storing the current flowing for each output line.

[0144] On the other hand, even when the memory cell includes a two-terminal switching element or a selective memory element and the sum of currents flowing through one output electrode line is measured, the voltage of the input signal can be set within a range in which neither the memory cell in the high resistance state nor the memory cell in the low resistance state is turned on due to the characteristics of the two-terminal switching element or the selective memory element (see Figure 8 ). Accordingly, since there is no turned-on memory cell, the overall power consumption can be reduced, and since a voltage drop does not occur significantly, the total current flowing through the memory cells on one output electrode line can be measured at a time.

[0145] In addition, in order to obtain different current values ​​I j , repeat the above method for each output line of each memory array, as Figure 18 By converting the current value I1 to I m The current value is compared with the reference value to determine the closest current value through a constant function.

[0146] In addition, in the present invention, the plurality of memory cells capable of storing logic states may be a memory device capable of storing logic states of one or more bits. When the logic state is not just on or off but has several stages, a larger synaptic weight can be expressed even when the number of memory cells is small.

[0147] Each of a plurality of memory cells capable of storing a logic state may include a nonvolatile memory element and a selector element. A nonvolatile memory is required to store the logic state in the memory cell with low power consumption, and each memory cell needs to include a selector element to sequentially select the memory cell and write the logic state thereto in a write step, and to measure the sum of currents flowing through the programmed memory cells in a read step.

[0148] The non-volatile memory element may be any one of flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), or magnetic random access memory (MRAM). In particular, the non-volatile memory element may be a variable resistance element such as RRAM, PRAM, or MRAM. The variable resistance element may exhibit various resistance states depending on an applied input signal, and store one or more bits of logic state through the resistance state.

[0149] Furthermore, the selector element may be a memory device that is any one of a transistor, a diode, or a two-terminal switching element. Each memory cell can be individually selected by the selector element included therein and subjected to a writing step and a reading step.

[0150] In particular, the selector element may be a two-terminal switch element. Using a two-terminal switch element as a selector element for selecting a memory cell can improve integration and reduce power consumption. The two-terminal switch element may be any element, such as a bidirectional threshold switch, a transition metal oxide switch, a mixed ion electron conductor (MIEC) switch, a complementary resistance switch, or doped amorphous silicon.

[0151] In addition, in the present invention, each of the plurality of memory cells capable of storing a logic state may include a selective memory element. A selective memory element refers to an element having both non-volatile memory characteristics and selector element characteristics. A selective memory element refers to an element capable of storing a logic state by changing resistance and simultaneously operating as a selector element by causing a change in resistance based on a constant voltage (i.e., a threshold voltage).

[0152] For example, in the case of a bidirectional threshold switch made of chalcogenide materials, different resistance states can be generated by applying write voltages with different polarities. Chalcogenide materials without phase transitions can also be variable resistance elements and have unique switching characteristics that result in a constant resistance change near the threshold voltage.

[0153] In this way, when using a variable resistance element including a chalcogenide material without phase change, such as an existing bidirectional threshold switch element, one or more memory cells can be selected by switching characteristics, and each logic state can be stored therein by the variable resistance characteristics.

[0154] Such an element can be represented as a selective memory element, and in this case, an additional memory element or selector element is not required. Therefore, a high-density memory device is achieved and power consumption can be reduced. As such a chalcogenide material, an In-Ge-As-Se alloy, a Te-Se alloy, an As-Se alloy, a Ge-Te alloy, a Ge-Se alloy, an As-Se-Te alloy, a Ge-As-Se alloy, a Ge-As-Sb alloy, a Ge-Sb-Te alloy, a Ge-Sb-Se alloy, a Ge-As-Te alloy, a Si-Ge-As-Se alloy, a Si-Te-As-Ge alloy, an In-Sb-Te alloy, an In-Sb-Se alloy, an In-Ge-As alloy, an In-Ge-Te alloy, an In-Te alloy, etc. can be used. However, in addition to the above materials, any material that can store a logic state and can perform a switching function by a resistance change is not particularly limited.

[0155] In addition, in the present invention, the output signal unit may include an analog-to-digital converter, and the sum of the currents received from the output signal unit is an analog signal, which may be digitized and output by the analog-to-digital converter. The analog-to-digital converter may be a sense amplifier.

Claims

1. A memory device, comprising: a memory array comprising a plurality of bit lines and a plurality of word lines crossing each other, and a plurality of memory cells disposed one by one at each intersection of the plurality of bit lines and the plurality of word lines, wherein the plurality of memory cells are capable of selectively storing logic states, and the plurality of bit lines and the plurality of word lines are connected to the plurality of memory cells; a controller for controlling the writing step and the reading step; a write unit; and Reading unit, The controller is configured to, in the write step, select two or more memory cells from the plurality of memory cells as a synaptic element through the write unit, apply write voltages to the selected two or more memory cells in sequence to allow a logic state to be written in the selected two or more memory cells, and, in the read step, apply a read voltage to the two or more memory cells selected to have the logic state written therein through the read unit, so as to determine a synaptic weight by a sum of currents flowing through the two or more memory cells, thereby allowing the selected two or more memory cells to be identified as operating as the one synaptic element.

2. The memory device according to claim 1, wherein The plurality of memory cells capable of selectively storing the logic states can respectively store logic states of one or more bits.

3. The memory device according to claim 1, wherein Each of the plurality of memory cells capable of selectively storing the logic state includes a nonvolatile memory element and a selector element, and the selector element is any one of a transistor, a diode, or a two-terminal switch element.

4. The memory device according to claim 1, wherein The plurality of memory cells capable of selectively storing the logic states comprise selective memory elements.

5. The memory device according to claim 1, wherein The writing unit includes a DC counter. The memory device according to claim 1 , wherein: The reading unit includes an analog-to-digital converter.

7. The memory device according to claim 1, wherein The two or more memory cells selected to have logic states written therein in the writing step are all memory cells connected to one bit line among the plurality of bit lines.

8. The memory device according to claim 1, wherein The two or more memory cells selected to have logic states written therein in the writing step are memory cells all connected to one word line among the plurality of word lines.

9. The memory device according to claim 1, wherein The number of the two or more memory cells selected to have logic states written therein in the writing step is any one of 1, 2, 4, 8, 16, 32, 64, 128, 256, 1024, or 2048.

10. A method for determining synaptic weights in a memory device, the memory device comprising a memory array including a plurality of bit lines and a plurality of word lines crossing each other, and a plurality of memory cells placed one by one at each intersection of the plurality of bit lines and the plurality of word lines, wherein: The plurality of memory cells are capable of selectively storing logic states, the plurality of bit lines and the plurality of word lines are connected to the plurality of memory cells, and the method comprises the following steps: (a) selecting two or more memory cells from the plurality of memory cells as a synapse element, and sequentially applying write voltages to the selected two or more memory cells to write logic states; (b) applying a read voltage to the two or more memory cells selected to have the logic state written therein; and (c) determining a synaptic weight by the sum of currents flowing through the two or more memory cells selected to have a logic state written therein, by means of an applied read voltage, The selected two or more memory cells are identified as functioning as the one synaptic element.

11. The method according to claim 10, wherein: Each of the plurality of memory cells capable of selectively storing logic states is a memory cell capable of storing a logic state of one or more bits.

12. The method according to claim 10, wherein: The plurality of memory cells capable of selectively storing the logic states include two-terminal switching elements or selective memory devices, and The read voltage in step (b) is within a range in which all two or more memory cells that have been selected to have logic states written therein are not turned on, and the range is greater than a voltage applied to two or more memory cells that have not been selected from the memory array.

13. The method according to claim 12, wherein: The write voltage in step (a) turns on the two or more memory cells selected from the plurality of memory cells and has a first polarity for writing a first logic state and a second polarity for writing a second logic state, the first polarity being opposite to the second polarity, The read voltage in step (b) has the same polarity as the first polarity of the write voltage, and The selected two or more memory cells are identified as functioning as the one synaptic element.

14. The method according to claim 10, wherein: The two or more memory cells selected to have logic states written therein are memory cells that are all connected to one of the bit lines.

15. The method according to claim 10, wherein The two or more memory cells selected to have logic states written therein are memory cells that are all connected to one of the word lines.

16. The method according to claim 10, wherein The number of the two or more memory cells selected to have logic states written therein in step (a) is any one of 1, 2, 4, 8, 16, 32, 64, 128, 256, 1024, or 2048.

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