Semiconductor material with tunable dielectric constant and tunable thermal conductivity

Abstract

Layered structures for semiconductor applications are described herein. The layered structures include a starting material and a fully depleted, porous layer having high resistivity formed over the starting material. In some embodiments, the layered structures also include an epitaxial layer grown over the fully depleted, porous layer. Additionally, processes for fabricating the layered structures, including forming the fully depleted, porous layer and growing an epitaxial layer over the porous layer, are described herein.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to 35 USC §119(e) of U.S. Provisional Patent Application No. 62 / 876,330, filed July 19, 2019, and No. 62 / 891,885, filed August 26, 2019, each of which is incorporated herein by reference in its entirety. Background Technology

[0003] Silicon (Si)-based substrates for semiconductor devices have become widely used in radio frequency (RF) applications. The continuous innovation and rapid development of RF communication electronics have increased the demand for smaller and faster semiconductor devices. This necessitates improved substrate technologies that minimize RF losses, RF noise, and nonlinear signal distortion. In particular, silicon substrates with high effective resistivity and low effective dielectric constant, such as high resistivity (HR) low-doped silicon-on-insulator (SOI) substrates, have shown significant reductions in RF losses, noise, and signal distortion.

[0004] However, the effective resistivity of HR-SOI substrates depends largely on the interface between the Si layer and the buried oxide layer (e.g., SiO2). The current effective resistivity of HR-SOI substrates ranges from 20 to 300 ohm-cm.

[0005] Using a porous silicon (pSi) layer-based structure with a porosity greater than 20% and less than 60%, a thin pSi layer inserted between the Si layer and the buried oxide layer in an HR-SOI substrate has been shown to provide improved RF performance with a high resistivity greater than 3000 ohm-cm. However, the high porosity further reduces thermal conductivity (e.g., a porosity greater than 20% can reduce thermal conductivity by more than 20%), which can lead to a significant degradation in the thermal performance of the device. Furthermore, silicon dioxide (SiO2), a previously known material for this purpose, is a very poor thermal conductor. Specifically, depending on temperature, the initial thermal conductivity of pure silicon is approximately 142 W / mK, but the thermal conductivity of silicon dioxide (SiO2) is only about 1.5 W / mK, which is only slightly higher than the thermal conductivity of air (1 W / mK). Summary of the Invention

[0006] This invention relates to layered structures for semiconductor devices. Specifically, the layered structure includes a starting material layer and a fully depleted porous layer above the starting material. According to this configuration, the layered structure improves the thermal performance of the device while reducing degradation.

[0007] In some embodiments, the layered structure includes a starting material, such as a silicon substrate. According to one aspect of the embodiments, all or part of the starting material may be converted to form a porous layer with tunable electrical properties. Specifically, the porous layer may be tuned to increase the resistivity of the layered structure while minimizing the loss of thermal properties. Thus, the porous layer can be tuned during conversion or formation to improve the thermal performance of the layered structure while reducing degradation.

[0008] According to this configuration, by carefully adjusting the resistivity of the starting material, all or part of the starting material can be converted into a layer with a resistivity greater than 10,000 ohm-cm and low porosity, which will provide excellent resistivity performance while minimizing the loss of thermal properties. In some aspects of this embodiment, the layered structure can be adjusted such that the thermal conductivity is equal to at least 3 watts per meter Kelvin (W / mK).

[0009] By carefully adjusting the resistivity of the starting material, all or part of the starting material can be converted into a fully depleted porous layer with an increased band gap, which will provide improved performance at high temperatures (that is, no loss of resistivity during operation).

[0010] The layered structure includes a starting material and a fully depleted porous layer above the starting material. According to one aspect of this embodiment, the band gap of the fully depleted porous layer is adjusted to be greater than the band gap of the starting material.

[0011] The fully depleted porous layer is essentially the same as the starting material.

[0012] In some embodiments, the layered structure may further include an epitaxial layer formed over a fully depleted porous layer.

[0013] In some embodiments, the epitaxial layer comprises at least one of silicon, InP, cREO, Mo, AlGaInN, RE-III-N, and a metal.

[0014] In some embodiments, the starting material includes regions with varying resistivity. For example, the starting material may include multiple regions, wherein a first region of the starting material has a first resistivity and a second region of the starting material has a second resistivity. The first resistivity of the first region may differ from the second resistivity of the second region. Alternatively, the layered structure may include a fully depleted porous layer over the first region of the starting material and a partially depleted porous layer over the second region of the starting material.

[0015] A method for forming a layered structure is provided. For example, the method includes forming a fully depleted porous layer from a starting material, wherein a first band gap of the fully depleted porous layer is greater than a second band gap of the starting material. Attached Figure Description

[0016] This disclosure is described in detail with reference to the following accompanying drawings, which illustrate one or more different embodiments. The drawings are provided for illustrative purposes only and depict only typical or exemplary embodiments. These drawings are provided to facilitate an understanding of the concepts disclosed herein and should not be construed as limiting the breadth, scope, or applicability of these concepts. It should be noted that these drawings are not necessarily drawn to scale for clarity and ease of explanation.

[0017] Figure 1 Examples of layered structures according to some embodiments of the present disclosure are shown, the layered structures having a fully depleted porous layer formed on a starting material;

[0018] Figure 2 Examples of layered structures according to some embodiments of the present disclosure are shown, the layered structure having a fully depleted porous layer formed on a starting material, wherein the resistivity of the fully depleted porous layer is greater than 10000 ohm-cm;

[0019] Figure 3 The illustration shows some embodiments of the present disclosure. Figure 2 The diagram shows the sheet resistivity versus depth for a layered structure similar to the one shown.

[0020] Figures 4-9 Various examples of layered structures according to some embodiments of the present disclosure are shown, the layered structures having fully depleted porous layers with different starting materials;

[0021] Figures 10-13 Various examples of layered structures according to some embodiments of the present disclosure are shown, the layered structures having fully depleted porous layers with at least two different porosities;

[0022] Figure 14 Examples of layered structures according to some embodiments of the present disclosure are shown, the layered structure comprising a fully depleted porous layer having periodically alternating sublayers formed on a starting material;

[0023] Figure 15 The illustration shows some embodiments of the present disclosure. Figure 14 The diagram shows the porosity versus depth of a layered structure similar to the one shown.

[0024] Figure 16 Images of layered structures according to some embodiments of the present disclosure are shown, the layered structures having fully depleted porous layers containing periodically alternating sublayers formed on a starting material;

[0025] Figure 17 The illustration shows some embodiments of the present disclosure. Figure 16 The resistivity versus depth plot of a layered structure similar to the one shown.

[0026] Figures 18-21 Various examples of layered structures having epitaxial layers grown on fully depleted porous layers are shown according to some embodiments of the present disclosure;

[0027] Figure 22 Representatives and embodiments according to this disclosure are shown. Figure 1 Experimental data and graphs of different thermal conductivities for various examples of layered structures with similar structures, compared to silicon benchmarks.

[0028] Figure 23 The illustration shows some embodiments of the present disclosure. Figure 1 The diagram shows the photoluminescence and energy of a layered structure with band gaps Eg1 and Eg2, which is similar to the structure shown.

[0029] Figure 24 and Figure 25 X-ray diffraction patterns of various examples of layered structures having fully depleted porous layers according to some embodiments of the present disclosure are shown.

[0030] Figure 26 Examples of layered structures according to some embodiments of the present disclosure are shown, the layered structures having a fully depleted porous layer above a starting material including an additional porous layer;

[0031] Figure 27 and Figure 28 The illustration shows some embodiments of the present disclosure. Figure 26 Various examples of additional porous layers in layered structures similar to those shown;

[0032] Figure 29 An example of a previously known configuration of a layered structure is shown;

[0033] Figure 30 Examples of layered structures with fully depleted porous layers are shown according to some embodiments of the present disclosure;

[0034] Figure 31 Examples of layered structures with fully depleted porous layers and RF switching devices above the layered structures are shown according to some embodiments of the present disclosure.

[0035] Figure 32 A diagram showing the second harmonic distortion of a layered structure according to some embodiments of the present disclosure compared to a previously known structure;

[0036] Figure 33 A diagram showing the second harmonic distortion of a layered structure according to some embodiments of the present disclosure is shown;

[0037] Figure 34A transmission loss diagram of a radio frequency switch with a frequency up to 20 GHz according to some embodiments of the present disclosure is shown;

[0038] Figure 35 A graph showing the characteristic impedance of a radio frequency switch with a frequency up to 20 GHz according to some embodiments of the present disclosure;

[0039] Figure 36 The illustration shows some embodiments of the present disclosure. Figure 1 The diagram shows the second harmonic distortion of a similar layered structure at different operating temperatures.

[0040] Figure 37 A graph showing the effective dielectric constant versus frequency of various examples of layered structures according to some embodiments of the present disclosure;

[0041] Figure 38 Examples of layered structures according to some embodiments of the present disclosure are shown, the layered structure including a fully depleted porous layer and a sound device;

[0042] Figure 39 A flowchart illustrating an exemplary process for fabricating a layered structure with a fully depleted porous layer, according to some embodiments of the present disclosure, is shown; and

[0043] Figure 40 This is a flowchart illustrating an exemplary process for manufacturing a layered structure having a starting material layer and forming an epitaxial layer according to some embodiments of the present disclosure. Detailed Implementation

[0044] This disclosure relates to layered structures that allow hybrid acoustic, photonic, and electronic devices to be integrated on a single platform. For example, the layered structure uses a starting material and a fully depleted porous layer above the starting material, the fully depleted porous layer being tuned to have a resistivity greater than 10,000 ohm-cm while minimizing thermal conductivity loss. For example, the fully depleted porous layer has a band gap greater than that of the starting material, while being substantially identical to the starting material. The layered structure includes a fully depleted porous layer tuned to improve the resistivity of the layered structure while minimizing thermal property loss. This configuration allows the layered structure to minimize thermal property loss while reducing its attenuation. In this way, hybrid acoustic, photonic, and electronic devices can be integrated into the layered structure.

[0045] In some embodiments, a layered structure can be formed by forming a fully depleted porous layer from the starting material.

[0046] In some embodiments, all or part of the starting material may be converted to form a porous layer with tunable electrical properties. The porous layer may be tuned during conversion or formation to improve the resistivity of the layered structure while maintaining thermal properties and reducing the degradation of the layered structure.

[0047] Figure 1 An example of a layered structure having a fully depleted porous layer is shown according to an embodiment described herein. The layered structure 100 may include a starting material layer 102, on which a fully depleted porous layer 104 is formed. According to one aspect of this embodiment, the layered structure includes a first band gap Eg1 of the fully depleted porous layer and a second band gap Eg2 of the starting material. The relationship between the band gap (Eg1) of the fully depleted porous layer and the band gap (Eg2) of the starting material satisfies the following equation: Eg1 > Eg2. In other words, the first band gap Eg1 of the fully depleted porous layer is greater than the second band gap Eg2 of the starting material.

[0048] The fully depleted porous layer is essentially the same as the starting material. That is, the chemical elements in the starting material are the same as those in the fully depleted porous layer of the layered structure.

[0049] In the process of forming a layered structure 100 having a fully depleted porous layer 104 on the starting material layer 102, a layer comprising multiple pores is formed on top of the starting material, each pore having a region in its vicinity from which all free carriers have been removed. These pores are formed by passing an electrolytic current from the cathode to the anode through the starting material. This process uses 5-50 mA / cm². 2 The current density is [value missing], and the etching duration is approximately 10 seconds to 15 minutes. After the electrolytic current is passed through the starting material, a fully depleted porous layer is formed above the starting material. In the process of forming the layered structure, the fully depleted porous layer is adjusted such that the formed fully depleted porous layer can have a resistivity greater than 10000 ohm-cm, while minimizing the loss of thermal conductivity of the layered structure by minimizing the number of pores formed in the layer.

[0050] According to some embodiments, the layered structure can be tuned by using starting materials with resistivity in the range of 0.1-10 ohm-cm, so that all or part of the starting material can be converted into a fully depleted porous layer with high resistivity and low porosity. The fully depleted porous layer achieves excellent resistivity performance while minimizing the loss of thermal conductivity of the original starting material. In some aspects of this embodiment, the thermal conductivity of the layered structure is at least equal to 3 W / mK.

[0051] According to this structure, by carefully adjusting the resistivity of the starting material, all or part of the starting material can be converted into a layer with a resistivity greater than 10000 ohm-cm and low porosity. This layer achieves excellent performance while improving the dielectric constant of the layered structure. In some aspects of this embodiment, such as Figure 37 As shown, the dielectric constant of the layered structure is in the range of approximately 2 to 4 farads per meter.

[0052] According to another embodiment, the thickness of the fully depleted porous layer is between 10 and 20 μm, and the resistivity is greater than 10,000 ohm-cm.

[0053] Figure 2 An example of a layered structure 200 having a fully depleted porous layer according to an embodiment described herein is shown. The layered structure 200 may include a starting material layer 202, on which a fully depleted porous layer 204 is formed. According to one aspect of this embodiment, the layered structure includes a first band gap Eg1 of the fully depleted porous layer 204 and a second band gap Eg2 of the starting material 202. The relationship between the band gaps of the starting material 202 and the fully depleted porous layer 204 satisfies the formula: Eg1 > Eg2. In other words, the first band gap Eg1 of the fully depleted porous layer 204 is greater than the second band gap Eg2 of the starting material 202. The thickness of the fully depleted porous layer 204 is between 10 μm and 20 μm.

[0054] Figure 3 Examples according to the embodiments described herein are shown. Figure 2 The diagram shows the resistivity of the layered structure versus its depth. Figure 3 The figure shown plots the sheet resistivity of a layered structure with a fully depleted porous layer relative to the depth of the layered structure. In the layered structure with a fully depleted porous layer, the sheet resistivity is greater than 10,000 ohm-cm between a thickness of 0.1 μm and 26 μm. The layered structure can be adjusted such that a starting material 202 with a resistivity of 0.1-10 ohm-cm is converted into a fully depleted porous layer 204 with a sheet resistivity greater than 10,000 ohm-cm. This configuration allows for increasing the resistivity of the fully depleted porous layer while minimizing the loss of thermal conductivity to obtain an improved device.

[0055] According to some embodiments, various starting materials can be used in layered structures.

[0056] Figures 4-9 Various examples of layered structures according to embodiments described herein are shown, the layered structures having fully depleted porous layers with different starting materials. Figure 4In the example shown, a starting material 302 with a resistivity of 0.1-10 ohm-cm is used, wherein a fully depleted porous layer 304 is formed on top of the starting material 302. Using a starting material with a resistivity of 0.1-10 ohm-cm allows for the fabrication of layered structures in an efficient and cost-effective manner.

[0057] exist Figure 5 In the example shown, the starting material 302 may include multiple sublayers of the starting material. The starting material includes a first sublayer 302a of the starting material and a second sublayer 302b of the starting material above the first sublayer 302a, the first sublayer 302a having a first resistivity Rsh1 and the second sublayer 302b having a second resistivity Rsh2. Furthermore, according to one aspect of this configuration, the starting material 302 may include multiple sublayers vertically stacked between the second sublayer 302b and the nth sublayer 302n, where n represents an integer. The nth sublayer 302n may be composed of resistivity Rsh1. n Characterization is performed. The layered structure may have an interface between the starting material layer 302 and the fully depleted porous layer 304. This interface may be between the nth sublayer 302n of the starting material 302 and an adjacent layer (not shown). An additional layer may be present between the starting material 302 and the fully depleted porous layer 304.

[0058] exist Figure 6 In the example shown, the starting material 302 may include multiple sublayers of the starting material. The starting material includes a first sublayer 302a of the starting material and a second sublayer 302b of the starting material vertically stacked above the first sublayer 302a, the first sublayer 302a having a first resistivity Rsh1 and the second sublayer 302b having a second resistivity Rsh2. Furthermore, according to one aspect of this configuration, the starting material 302 may include a third sublayer 302c having a third resistivity Rsh3. The third sublayer 302c is disposed within the second sublayer 302b, with the surface of the third sublayer 302c disposed at the surface of the second sublayer 302b. The third sublayer 302c may have an interface with the fully depleted porous layer 104. This interface may be between the starting material 302c and an adjacent layer (not shown). An additional layer may be present between the starting material 302c and the fully depleted porous layer 304.

[0059] exist Figure 7 In the example shown, the starting material 302d is a silicon substrate. The layered structure 300E may have an interface between the starting material layer 302d and the fully depleted porous layer 304. This interface may be between the starting material and an adjacent layer (not shown). An additional layer may be present between the starting material 302d and the fully depleted porous layer 304.

[0060] exist Figure 8In the example shown, the starting material 302e may include a silicon substrate. The silicon substrate may include a specific crystal orientation, such as <110> or <100> The layered structure 300E may have interfaces between the layers, and these interfaces are... <100> Orientation and <110> Sudden rotation in crystal orientation between orientations. Alternatively, layered structures may include those with... <100> The oriented silicon substrate 302e and the surface formed on the silicon substrate 302e having <100> An interface exists between the fully depleted porous layer 304. This interface may be between the silicon substrate 302e and an adjacent layer (not shown). An additional layer may be present between the silicon substrate 302e and the fully depleted porous layer 304.

[0061] exist Figure 9 In the example shown, the starting material 302f may include a Group III-V alloy. Group III-V alloys may include specific crystal orientations, such as... <110> or <100> The layered structure 300F can have interfaces between the layers, and these interfaces are for... <100> Orientation and <110> Sudden rotation in crystal orientation between orientations. Alternatively, layered structures may include those with... <100> Oriented III-V alloy 302f and the formation on top of III-V alloy 302f with <100> An interface exists between the layers of the fully depleted porous layer 304. This interface may be between the III-V alloy 302f and an adjacent layer (not shown). An additional layer may be present between the III-V alloy 302f and the fully depleted porous layer 304.

[0062] According to another embodiment, the fully depleted porous layer may include sublayers of periodically alternating sublayers. The periodically alternating sublayers may include sublayers having two or more porosities. In some embodiments, the two alternating porosities may have a first porosity and a second porosity. In some embodiments, the two alternating porosities may be a high porosity and a low porosity. In another aspect of this embodiment, the fully depleted porous layer may include three or more sublayers, each with a different porosity. According to this configuration, sublayers with different porosities may be stacked vertically above the starting material, wherein the porosity gradually increases from one end of the fully depleted porous layer to the opposite end.

[0063] Figures 10-13 Various examples of layered structures according to embodiments described herein are shown, the layered structures having at least two completely depleted porous layers with different porosities. Figure 10In the example shown, the fully depleted porous layer includes a first sublayer 404a of the fully depleted porous layer and a second sublayer 404b of the fully depleted porous layer 404. The first sublayer 404a has a first porosity P1 and is above the starting material 402, and the second sublayer 404b has a second porosity P2 and is stacked vertically above the first sublayer of the fully depleted porous layer 404.

[0064] exist Figure 11 In the example shown, the fully depleted porous layer includes a first sublayer 404a and a second sublayer 404b of the fully depleted porous layer 404. The first sublayer 404a has a first porosity P1 and covers a first region above the starting material 402, and the second sublayer 404b has a second porosity P2 and covers a second region above the starting material 402. According to this configuration of the embodiment, the first and second sublayers are adjacent to each other and may include an interface between the first and second sublayers. According to another aspect of the embodiment, a layer serving as a transition layer may be present between the first and second sublayers.

[0065] exist Figure 12 In the example shown, the fully depleted porous layer includes a first sublayer 404a and a second sublayer 404b of the fully depleted porous layer 404. The first sublayer 404a has a first porosity P1 and covers a first region above the starting material 402, and the second sublayer 404b has a second porosity P2 and covers a second region above the starting material 402. The first sublayer 404a and the second sublayer 404b are deployed above the starting material 402 and are adjacent to each other in the horizontal direction. According to this configuration of the embodiment, the first and second sublayers are adjacent to each other, and an interface may be included between the first and second sublayers. According to another aspect of the embodiment, a layer serving as a transition layer may be present between the first and second sublayers.

[0066] exist Figure 13 In the example shown, the layered structure includes a top layer having various regions. The top layer includes a fully depleted porous layer on one side and an undepleted starting material layer 402 adjacent to the fully depleted porous layer. For example, the top layer includes a fully depleted porous layer 404 on one side of the layered structure, a starting material layer 402 adjacent to the fully depleted porous layer, and a fully depleted porous layer on the other side of the top layer. According to this configuration of the embodiment, the first sublayer and the second sublayer are adjacent to each other, and an interface may be included between the first sublayer and the second sublayer. According to another aspect of the embodiment, a layer as a transition layer may be provided between the first sublayer and the second sublayer.

[0067] Figure 14An example of a layered structure 500 is shown, comprising a fully depleted porous layer 504 having periodically alternating sublayers (504a and 504b) formed above a starting material 502. The periodically alternating sublayers are vertically stacked above the starting material layer 502 and are fully depleted. The periodically alternating sublayer 504 may include multiple sublayers, including a sublayer 504a with a first porosity deployed above the starting material 502 and a sublayer 504b with a second porosity above the sublayer 504a with the first porosity. According to this configuration of an embodiment, the sublayers with the first porosity and the sublayers with the second porosity may be repeated n times. In some embodiments, the fully depleted porous layer 504 may include 10-20 sublayers as periodically alternating sublayers. The layered structure 500 can be adjusted by varying the periodically alternating sublayers of the fully depleted porous layer 504, resulting in an increase in the resistivity of the fully depleted porous layer while minimizing the loss of thermal conductivity of the layered structure 500, to obtain an improved device.

[0068] The foregoing Figures 4-14 This is merely an illustration of the principles of this disclosure, and various modifications can be made by those skilled in the art without departing from the scope of this disclosure. The above embodiments are for illustrative purposes and not for limitation. For example, according to this disclosure, any combination of a starting material layer and a fully depleted porous layer can be used in a layered structure. In some examples, it can be... Figure 4 Starting materials and Figure 13 The configuration combines fully depleted porous layers. According to this configuration, the layered structure comprises fully depleted porous layers and incompletely depleted layers. In another example, it can be... Figure 8 Starting materials and Figure 11 The fully depleted porous layers are used in combination. With this configuration, the crystal orientation of the silicon substrate allows for the formation of fully depleted porous layers in a manner that increases the resistivity of the fully depleted porous layers to provide excellent performance, while minimizing the loss of thermal properties of the layered structure.

[0069] Figure 15 The embodiments described herein are illustrated with Figure 14 The diagram shows the porosity versus depth of a layered structure similar to the one shown. Figure 15 In the figure shown, the porosity of the layered structure is plotted relative to the depth of the layered structure. In the layered structure, a periodically alternating porosity is observed for the fully depleted porous layer 504, which begins at the surface of the fully depleted porous layer 504 and extends to the interface between the fully depleted porous layer 504 and the starting material 502, and no porosity is observed for the starting material.

[0070] Figure 16An image showing a layered structure according to an embodiment described herein, the layered structure having a fully depleted porous layer containing periodically alternating sublayers formed on a substrate. Figure 16 In the image shown, the fully depleted porous layer comprises periodically alternating sublayers with alternating porosities above the substrate (starting material).

[0071] In some embodiments, the fully depleted porous layer may include a plurality of vertically stacked sublayers. In some aspects of this embodiment, the plurality of sublayers may include graded porosity, such that sublayers with high porosity are deployed on the surface of the fully depleted porous layer, and sublayers with lower porosity are deployed at the interface between the fully depleted porous layer and the starting material.

[0072] In some embodiments, the fully depleted porous layer may include a plurality of vertically stacked sublayers. In some aspects of this embodiment, the plurality of sublayers may include graded porosity. The graded porosity may include a sublayer with low porosity at one end of the fully depleted porous layer and a sublayer with high porosity at the opposite end of the fully depleted porous layer. According to another embodiment, a sublayer with high porosity may be deployed at the interface between the fully depleted porous layer and the starting material, and a sublayer with low porosity may be deployed on the surface of the fully depleted porous layer.

[0073] Figure 17 The embodiments described herein are illustrated with Figure 16 The diagram shows the resistivity versus depth of a layered structure similar to the one shown. Figure 17 The figures shown depict the sheet resistivity of a layered structure with fully depleted porous layers relative to the depth of the layered structure. As shown in Table 1, in layered structures with fully depleted porous layers, the sheet resistivity is greater than 10,000 ohm-cm between thicknesses of 0.1 μm and 5.16 μm. The layered structure can be adjusted such that starting materials with resistivity from 0.1 to 10 ohm-cm are converted into fully depleted porous layers with sheet resistivity greater than 10,000 ohm-cm. This configuration allows for increased resistivity of the fully depleted porous layers while minimizing thermal conductivity loss to achieve improved devices.

[0074] Table 1 shows the resistivity of sample sheets at different depths of the example layered structure.

[0075]

[0076] As shown in Table 1, the sheet resistivity of the layered structure is greater than 10,000 ohm-cm from a depth of 0.0 μm (e.g., the surface of the layered structure) to a depth of 5.16 μm. For example, the layered structure is fully depleted and can provide a sheet resistivity greater than 20,000 ohm-cm from a depth of 0.0 μm (e.g., the surface of the layered structure) to a depth of 5.16 μm.

[0077] According to the foregoing embodiments, a layered structure with minimal loss of thermal conductivity can be obtained, while the resistivity increases exponentially. The layered structure described herein can be adjusted to regulate electrical and thermal properties. Specifically, the thermal conductivity of the layered structure is at least 3 W / mK.

[0078] Additionally or alternatively, according to some embodiments, the fully depleted porous layer may be matched with the lattice of the starting material along one crystal direction, but may be misaligned along a second crystal direction. Therefore, throughout the layered structure, the lattice strain between the fully depleted porous layer and the starting material layer is reduced through the interface between the fully depleted porous layer and the starting material layer.

[0079] In some embodiments, the periodically alternating sublayers may form a sound reflector. In some embodiments, the periodically alternating sublayers may form a coherent phonon structure.

[0080] According to some embodiments, the layered structure may include an epitaxial layer disposed above a fully depleted porous layer. According to some embodiments, the starting material layer may include a silicon substrate, wherein the fully depleted porous layer is formed above the starting material layer. The starting material layer is substantially identical to the fully depleted porous layer. The epitaxial layer may be formed above the fully depleted porous layer. According to some embodiments, the layered structure includes a silicon starting material layer, a fully depleted porous layer substantially identical to the silicon starting material layer, and an epitaxial layer formed above the fully depleted porous layer.

[0081] Figures 18-21 Various examples of layered structures according to embodiments described herein are shown, the layered structures having an epitaxial layer formed over a fully depleted porous layer. Figure 18 In the example shown, the layered structure 700A includes a starting material layer 702, a fully depleted porous layer 704 above the starting material, and an epitaxial layer 706 above the fully depleted porous layer 704.

[0082] exist Figure 19In the example shown, the layered structure 700B includes a starting material layer 702, a fully depleted porous layer 704 formed over the starting material layer 702, and a silicon semiconductor layer 706 formed over the fully depleted porous layer 704. For example, in the layered structure 700B, the epitaxial layer formed over the fully depleted porous layer is the silicon semiconductor layer 706. In some embodiments, the layered structure may include a starting material and an epitaxial layer, the starting material including a silicon substrate and the epitaxial layer including a silicon layer. The fully depleted porous layer may include a silicon substrate as a lower sublayer and a fully depleted silicon layer sandwiched between a top sublayer and a lower sublayer of the silicon substrate, formed by surface sealing the fully depleted porous layer. According to an embodiment, a semiconductor device may be epitaxially grown over the fully depleted porous layer. In some embodiments, the epitaxial layer is a silicon semiconductor layer. According to another embodiment, the epitaxial layer is a layer comprising one or more of the following compounds: InP, cREO, AlGaInN, and RE-III-N. In some embodiments, the semiconductor layer comprises silicon and one or more of the following: InP, cREO, Mo, AlGaInN, RE-III-N compounds, and other metal compounds. According to this configuration, the layered structure can maintain the thermal properties of the starting material while increasing the resistivity of the fully depleted porous layer to obtain an improved device.

[0083] exist Figure 20 In the example shown, the layered structure 700C includes a starting material layer 702, a fully depleted porous layer 704 above the starting material, a transition layer 712 formed above the fully depleted porous layer 704, and an epitaxial layer 706 formed above the transition epitaxial layer 712. The transition epitaxial layer 712 may be a silicon substrate, which provides a surface seal for the fully depleted porous layer. Alternatively, the transition epitaxial layer 712 may be an insulating layer between the fully depleted porous layer and the epitaxial layer 706. With this configuration, the layered structure can maintain the thermal properties of the starting material while increasing the resistivity of the fully depleted porous layer to obtain an improved device.

[0084] exist Figure 21 In the example shown, the layered structure 700D includes a starting material layer 702, a doped layer 714 above the starting material layer, a fully depleted porous layer 704 above the doped layer, a transition epitaxial layer 712 formed above the fully depleted porous layer 704, and an epitaxial layer 706 above the fully depleted porous layer 704.

[0085] In some embodiments, the starting material may be a silicon substrate having a resistivity of 0.1-10 ohm-cm. Using such a substrate allows for the fabrication of layered structures in an efficient and cost-effective manner. The doped layer 714 includes variations in silicon doping concentration to allow for adjustments to the layered structure and to provide additional thermal insulation for the layered structure as a whole. The fully depleted porous layer 704 may include a porosity in the range of 5%-60%. The thickness of the fully depleted porous layer may be in the range of 1-50 μm. The transition epitaxial layer 712 may be a silicon substrate to provide a surface seal for the fully depleted porous layer 704. Alternatively, the transition epitaxial layer 712 may be an insulating layer formed between the epitaxial layer above the transition epitaxial layer 712 and the fully depleted porous layer 704. The transition epitaxial layer 712 may have a thickness of less than 10 nm. The epitaxial layer 706 may have a thickness in the range of 1-10000 nm. According to this configuration, the layered structure can maintain the thermal properties of the starting material 702 while increasing the resistivity of the fully depleted porous layer to obtain an improved device. Furthermore, this configuration allows the layered structure to avoid degradation due to the loss of thermal insulation in devices with resistivity greater than 10000 ohm-cm.

[0086] Figure 22 The illustrations show representative examples and embodiments described herein. Figure 1 Experimental data for different thermal conductivities of various examples of layered structures similar to those shown, and plots against a silicon benchmark. Figure 22 The graph shown plots the change in thermal conductivity over time for pure silicon, porous silicon, and completely depleted silicon. Figure 22 As shown, depending on temperature, the thermal conductivity of pure silicon is approximately 142 W / mK, while that of porous silicate (pSi) is approximately 1.5 W / mK. According to the improvements of this disclosure, a fully depleted porous layer exhibits a thermal conductivity of 3 W / mK. The aforementioned configuration allows for an increase in the resistivity of the fully depleted porous layer while minimizing the loss of thermal conductivity to obtain an improved device.

[0087] Figure 23 The embodiments described herein are illustrated with Figure 1 The diagram shows the photoluminescence and energy of a layered structure similar to the one shown. Figure 23 The figures shown illustrate photoluminescence for a layered structure as energy increases, as illustrated by embodiments of this disclosure. This configuration allows for increased resistivity of the fully depleted porous layer while minimizing thermal conductivity loss to achieve an improved device.

[0088] Figure 24 and Figure 25 X-ray diffraction patterns are shown for various examples of layered structures with fully depleted porous layers according to embodiments described herein.

[0089] Figures 26-28Various examples of layered structures according to embodiments described herein are shown, the layered structure having a porous layer sandwiched between two layers of starting material. Figure 26 In the example shown, the layered structure 1100 includes a starting material layer 1102, a porous material layer 1101 above the starting material, a second layer of the starting material 1102 above the porous material layer 1101, and a fully depleted porous layer 1104 above the second layer of the starting material.

[0090] exist Figure 27 In the example shown, the porous material layer 1101 above the starting material 1102 is shown as a plurality of sublayers. The porous material layer 1101 may include a plurality of sublayers. The plurality of sublayers may be Bragg reflectors (DBRs) with high and low porosity distributions. In some embodiments, the plurality of sublayers may include a first porosity 1101a and a second porosity 1101b that alternate back and forth between the starting materials. According to this configuration, the layered structure can maintain the thermal properties of the starting material while increasing the resistivity of the fully depleted porous layer to obtain an improved semiconductor device.

[0091] exist Figure 28 In the example shown, the porous material layer 1101 sandwiched between two layers of starting material can be used for wafer dicing. In this configuration, the porous material layer may include a high-porosity layer embedded between sublayers having lower porosity. According to this configuration, the layered structure can maintain the thermal properties of the starting material while increasing the resistivity of the fully depleted porous layer to obtain an improved device.

[0092] In some embodiments, the layered structure is a layer of a radio frequency (RF) switch structure.

[0093] In some embodiments, the layered structure is a layer that integrates passive devices.

[0094] In some embodiments, the layered structure is a layer of a radio frequency (RF) filter.

[0095] Figure 29 An example of a previously known configuration of a layered structure is shown. Figure 29 In the example shown, the structure includes a silicon layer 1202 with crystal orientation (100), a polysilicon layer 1204, a transition layer (BOX) 1206, and a silicon layer 1208 with crystal orientation (100) above the transition layer 1206. Additionally, a device 1210 can be deployed above the silicon layer 1208. With this configuration, the device 1210 can generate radio frequency field lines 1212 that penetrate the polysilicon layer 1204 and into the substrate layer. This configuration results in a significant loss of efficiency.

[0096] On the other hand, the configuration employing a fully depleted porous layer exhibits excellent sheet resistivity properties and reduces RF penetration into the substrate layer. For example, as... Figure 30 As shown, according to the embodiments described herein, an example of a layered structure having a fully depleted porous layer. Figure 30 The layered structure shown includes a silicon layer 1302a with crystal orientation (100), a fully depleted porous layer 1304a, and a silicon layer 1306a with crystal orientation (100) above the fully depleted porous layer 1304a. Additionally, a device 1308a can be deployed above the silicon layer 1306a. This configuration, employing a fully depleted porous layer, exhibits excellent sheet resistivity properties and reduces radio frequency penetration into the substrate layer.

[0097] Figure 31 An example of a layered structure having a fully depleted porous layer and an RF switching device above the layered structure is shown, according to embodiments described herein. Figure 31 In the example shown, a patterned metal is deployed over an oxide layer formed over a fully depleted porous layer. This patterned metal can take the form of a coplanar waveguide or a crosstalk device.

[0098] Figure 32 A graph showing the second harmonic distortion of the layered structure according to the embodiments described herein compared to previously known structures is presented. Figure 32 The figures shown illustrate layered structures with fully depleted porous layers, using treatments 2A, 3A, 3B, and 4A as examples. Furthermore, various results demonstrate that the layered structure can be tuned to improve electrical properties while minimizing the loss of thermal properties.

[0099] Figure 33 A diagram showing the second harmonic distortion of the layered structure according to the embodiments described herein.

[0100] Figure 34 A characteristic transmission loss diagram of a radio frequency switch with a frequency up to 20 GHz according to an embodiment described herein is shown.

[0101] Figure 35 The characteristic impedance diagram of a radio frequency switch with a frequency up to 20 GHz according to an embodiment described herein is shown.

[0102] Figure 36 The embodiments described herein are illustrated with Figure 1 The diagram shows the second harmonic distortion of a layered structure similar to the one shown at different operating temperatures. Specifically, the diagram illustrates the second harmonic distortion as the input power (P) increases with temperature. in )change.

[0103] Figure 37The diagram illustrates the effective dielectric constant versus frequency for various examples of layered structures according to embodiments described herein. Specifically, the effective dielectric constant of the examples of layered structures is in the range of approximately 2-4 farads per meter for frequencies up to 20 GHz.

[0104] Figure 38 As an example of a layered structure according to embodiments described herein, the layered structure includes a fully depleted porous layer and a sound device. The layered structure 1800 may include a starting material layer 1802, wherein a fully depleted porous layer 1804 is formed over the starting material layer 1802, and a sound device 1815 is formed over the fully depleted porous layer 1804. According to this configuration, a sound signal 1816 flows from the sound device 1815 to the fully depleted porous layer. Conversely, a current 1814 travels from the substrate 1802 to the fully depleted porous layer 1804. Finally, a heat flow 1818 travels from the sound device through the fully depleted porous layer to the substrate.

[0105] Figure 39 This is a flowchart illustrating an exemplary process for manufacturing a layered structure having a fully depleted porous layer according to some embodiments of the present disclosure. Process 1900 includes forming a fully depleted porous layer from a starting material, the first band gap of the fully depleted porous layer being larger than the second band gap of the starting material. The fully depleted porous layer is substantially the same as the starting material.

[0106] In some embodiments, at 1902, the starting material is prepared using a suitable dry-in / dry-out porous silicon tool for forming a layered structure. The substrate may include gallium nitride, silicon carbide, sapphire, a silicon wafer, or any other suitable substrate having a predetermined crystal orientation. The substrate may be doped to adjust its resistivity. In some embodiments, the substrate may be a boron-doped silicon wafer to achieve a resistivity in the range of 0.1-10 ohm-cm. At 1904, the starting material is treated. The treatment is performed in a mixture of hydrofluoric acid and deionized water in a ratio of (5:2) and with a surfactant of (1 mL / L). At 1906, the formation of a fully depleted porous layer on top of the starting material is performed by passing an electrolytic current from cathode to anode through the starting material. The electrolytic current typically lasts for about 10 seconds to 15 minutes. The current density of the porous formation treatment is 5-50 mA / cm². 2 Within the range. At 1908, the completely depleted porous layer is treated through post-processing. Post-processing may include drying the layer and providing a sealing layer in preparation for application with additional layers or equipment.

[0107] Figure 40This is a flowchart illustrating an exemplary process for fabricating a layered structure having a starting material layer and forming an epitaxial layer according to some embodiments of the present disclosure. Process 2000 includes forming a fully depleted porous layer from the starting material, the first band gap of the fully depleted porous layer being larger than the second band gap of the starting material. The fully depleted porous layer is substantially identical to the starting material. Furthermore, a semiconductor layer is epitaxially grown over the fully depleted porous layer.

[0108] In some embodiments, at 2002, a starting material is prepared using a suitable dry-in / dry-out porous silicon tool for forming a layered structure. The substrate may include gallium nitride, silicon carbide, sapphire, a silicon wafer, or any other suitable substrate having a predetermined crystal orientation. The substrate may be doped to adjust its resistivity. In some embodiments, the substrate may be a boron-doped silicon wafer to achieve a resistivity in the range of 0.1-10 ohm-cm. At 2004, the starting material is treated. The treatment is performed in a mixture of hydrofluoric acid and deionized water in a ratio of (5:2) and a surfactant of (1 mL / L). At 2006, the formation of a fully depleted porous layer on top of the starting material is performed by passing an electrolytic current from cathode to anode through the starting material. The electrolytic current typically lasts for about 10 seconds to 15 minutes. The current density of the porous formation treatment is 5-50 mA / cm². 2 Within the range. At 2008, the fully depleted porous layer is treated by post-processing of the layer. Post-processing may include drying the layer and providing a sealing layer in preparation for application with additional layers or devices. After treating the fully depleted porous layer, at 2010, an epitaxial layer may be formed over the fully depleted porous layer.

[0109] The growth and / or deposition described herein can be performed using one or more of the following methods: chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), organometallic vapor phase epitaxy (OMVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), pulsed laser deposition (PLD), and / or physical vapor deposition (PVD).

[0110] As described herein, a layer refers to a material of generally uniform thickness covering a surface. A layer can be continuous or discontinuous (i.e., there are gaps between regions of the material). For example, a layer can completely or partially cover a surface, or it can be divided into discrete regions that collectively define the layer (i.e., regions formed using selective region extension).

[0111] Monolithic integration refers to the formation of a substrate on its surface by depositing layers that are typically deployed on the surface.

[0112] "Deployed on" means "present" or "above" the underlying material or layer. This layer may include intermediate layers such as transition layers necessary to ensure a suitable surface. For example, if a material is described as "deployed on" or "above" the substrate, this could mean (1) that the material is in close contact with the substrate; or (2) that the material is in contact with one or more transition layers located on the substrate.

[0113] A single crystal is a crystal structure that consists of essentially only one type of unit cell. However, single crystal layers may exhibit some crystal defects such as stacking faults, dislocations, or other common crystal defects.

[0114] A single domain is a crystal structure that consists of essentially only one unit cell and essentially only one orientation of that unit cell. In other words, a single-domain crystal does not exhibit twins or antidomains.

[0115] Single-phase refers to a crystal structure that is both a single crystal and a single domain.

[0116] A substrate refers to a material on which a deposited layer is formed. Exemplary substrates include, but are not limited to: bulk gallium nitride wafers, bulk silicon carbide wafers, bulk sapphire wafers, bulk germanium wafers, bulk silicon wafers, wherein the wafer comprises a single crystal material of uniform thickness; composite wafers, such as silicon-on-insulator wafers, which include a silicon layer disposed on a silicon dioxide layer disposed on a bulk silicon-processed wafer; or porous germanium, germanium on oxide and silicon, germanium on silicon, patterned germanium, germanium-tin on germanium, and / or the like; or any other material used as a base layer for forming a device thereon or therein. Examples of other materials suitable as base layers and bulk substrates, which vary with the application, include, but are not limited to, alumina, gallium arsenide, indium phosphide, silicon oxide, silicon dioxide, borosilicate glass, and pyrex glass. A substrate may have a single bulk wafer or a plurality of sublayers. A substrate may have a single bulk wafer or multiple sublayers. Specifically, a substrate (e.g., silicon, germanium, etc.) may include multiple discontinuous porous portions. Multiple discontinuous porous sections can have different densities and can be horizontally distributed or vertically layered.

[0117] A staggered substrate refers to a substrate that includes a surface crystal structure oriented at an angle associated with the crystal structure of the substrate. For example, a 6° staggered substrate. <100> Silicon wafers include those oriented towards, for example <110> Another principal crystal orientation, such as that of... <100> The crystal is oriented at a 6° angle. <100> Silicon wafers. Typically, but not always, the miscut angle can be as high as approximately 20°. Unless otherwise specified, the phrase "miscut substrate" includes miscut wafers with any host crystal orientation. That is, oriented towards... <011> Directional misalignment <111> Chip, orientation <110> Directional misalignment <100> Chips and Orientation <001> Directional misalignment <011> Chip.

[0118] A semiconductor is any solid material whose conductivity falls between that of an insulator and that of most metals. An example semiconductor layer is made of silicon. A semiconductor layer can comprise a single bulk wafer or multiple sublayers. Specifically, a silicon semiconductor layer can comprise multiple discontinuous porous portions. These discontinuous porous portions can have different densities and can be horizontally distributed or vertically layered.

[0119] The first layer described and / or depicted herein as "disposed on the second layer," "on the second layer," "formed above the second layer," or "above the second layer" may be immediately adjacent to the second layer, or one or more intermediate layers may be between the first and second layers. In cases where the first layer is described and / or depicted herein as "directly on the second layer or substrate" or "directly above the second layer or substrate," it may be immediately adjacent to the second layer or substrate without any intermediate layers, except for intermediate alloy layers that may be formed due to the mixing of the first and second layers or substrates. Furthermore, the first layer described and / or depicted herein as "on the second layer or substrate," "above the second layer or substrate," "directly on the second layer or substrate," or "directly above the second layer or substrate" may cover the entire second layer or substrate, or a portion of the second layer or substrate.

[0120] During layer growth, the substrate is placed on a substrate holder, so the top or upper surface is the surface of the substrate or layer furthest from the substrate holder, while the bottom or lower surface is the surface of the substrate or layer closest to the substrate holder. Any structure depicted and described herein may be part of a larger structure having additional layers above and / or below the depicted structure. For clarity, although these additional layers may be part of the disclosed structure, they may be omitted from the figures herein. Furthermore, the depicted structure may be repeated on a unit basis, even if such repetition is not depicted in the figures.

[0121] From the above description, it is clear that various techniques can be used to implement the concepts described herein without departing from the scope of this disclosure. The described embodiments should be considered illustrative rather than restrictive in all respects. It should also be understood that the techniques and structures described herein are not limited to the specific examples described herein, but can be implemented in other examples without departing from the scope of this disclosure. Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring that these operations be performed in the specific order or sequence shown, or that all illustrated operations be performed to achieve the desired result.

Claims

1. A layered structure comprising: a starting material layer; and a fully depleted porous layer over the starting material layer, wherein a first bandgap of the fully depleted porous layer is greater than a second bandgap of the starting material, and the fully depleted porous layer is substantially identical to the starting material, the chemical elements in the starting material being the same as the chemical elements of the fully depleted porous layer, wherein the starting material comprises a material with a resistivity in the range of 0.1 ohm-cm to 10 ohm-cm, and wherein the thermal conductivity of the layered structure is at least equal to 3 W / mK.

2. The layered structure of claim 1, wherein the fully depleted porous layer has a thickness between 10 pm - 20 pm, with a resistivity greater than 10000 ohm-cm.

3. The layered structure of claim 1, wherein the starting material comprises silicon.

4. The layered structure of claim 1, wherein the starting material comprises a plurality of layers stacked vertically, wherein the resistivity of the plurality of layers of the starting material varies.

5. The layered structure of claim 1, wherein the starting material layer is a silicon substrate with <111> or <100> crystal orientation.

6. The layered structure of claim 1, wherein the fully depleted porous layer comprises a first porosity in a first region and a second porosity in a second region.

7. The layered structure of claim 1, wherein the fully depleted porous layer is lattice matched to the starting material.

8. The layered structure of claim 6, wherein the fully depleted porous layer comprises a plurality of sub-layers stacked vertically, wherein the porosity of the plurality of sub-layers is graded with sub-layers having low porosity at the surface of the fully depleted porous layer and sub-layers having high porosity at the interface of the fully depleted porous layer and the starting material.

9. The layered structure of claim 6, wherein the fully depleted porous layer comprises periodically alternating sub-layers of a first porosity and a second porosity.

10. The layered structure of claim 9, wherein the first porosity is a high porosity and the second porosity is a low porosity.

11. The layered structure of claim 9, wherein the periodically alternating sub-layers of the first porosity and the second porosity form a sound reflector or a coherent phonon structure.

12. The layered structure of claim 1, wherein the dielectric constant of the layered structure is in the range of 2 Farads per meter2to 4 Farads per meter2.

13. The layered structure of any of the preceding claims, further comprising: an epitaxial layer grown over the fully depleted porous layer.

14. The layered structure of claim 13, wherein the epitaxial layer is a silicon semiconductor layer.

15. The layered structure of claim 13, wherein the epitaxial layer is selected from the group consisting of an InP layer, a cREO layer, a Mo layer, an AlGaInN layer, a RE-III-N layer, and a metal layer.

16. The layered structure of claim 13, wherein the layered structure is a layer of an RF switch structure; a layer of an integrated passive device; or a layer in an RF filter.

17. The layered structure of claim 13, wherein the starting material comprises a first region having a first resistivity and a second region having a second resistivity.

18. The layered structure of claim 17, wherein: a fully depleted porous layer is formed over the first region; and the layered structure further comprises a non-fully depleted porous layer formed over the second region.

19. A method of forming a layered structure, the method comprising: forming a fully depleted porous layer from a starting material, wherein a first bandgap of the fully depleted porous layer is greater than a second bandgap of the starting material, and the fully depleted porous layer is substantially the same as the starting material, the chemical elements in the starting material being the same as the chemical elements of the fully depleted porous layer, wherein the starting material comprises a material having a resistivity in a range of 0.1 ohm-cm to 10 ohm-cm, and wherein a thermal conductivity of the layered structure is at least equal to 3 W / mK.

20. The method of claim 19, wherein the starting material is a p-type boron-doped substrate.

21. The method of claim 19, further comprising: growing an epitaxial layer over the fully depleted porous layer.

22. The method of claim 19, wherein the starting material is a silicon substrate having a <111> or <100> crystal orientation.

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