Transistors and methods of forming integrated circuitry

Abstract

A transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically between the top and bottom source / drain regions, and a gate laterally adjacent to the channel region in operation. At least one of the top source / drain region, the bottom source / drain region, and the channel region is crystalline. All grains within the at least one of the top source / drain region, the bottom source / drain region, and the channel region have an average crystal size that differs from each other by no more than 0.064 pm 3 Other embodiments including methods are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to transistors and methods of forming integrated circuit systems. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines) are used to write to or read from the memory cells. Sense lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically specified as memory with a retention period of at least about 10 years. Volatile memory dissipates data and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention period of milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, these states are considered as "0" or "1". In other systems, at least some individual memory cells can be configured to store information at more than two levels or states.

[0004] A field-effect transistor (FET) is an electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is essentially prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. FETs are, of course, used in integrated circuit systems in addition to and / or outside of memory circuit systems. Attached Figure Description

[0005] Figure 1 This is a schematic cross-sectional view of a transistor according to an embodiment of the present invention.

[0006] Figure 2 This is a schematic cross-sectional view of a portion of the substrate construction during the process according to an embodiment of the present invention.

[0007] Figures 3 to 6 In the process according to one or more embodiments of the present invention Figure 2 The diagram of the structure is shown in sequence of cross-sectional views. Detailed Implementation

[0008] Embodiments of the present invention cover methods for forming integrated circuit systems comprising one or more transistors, and one or more transistors independent of the manufacturing method. Transistors manufactured according to the method embodiments may have any of the properties described herein in the structural embodiments. Figure 1 The image shows a first example transistor 14 as part of a construction 10 according to an embodiment of the invention. Construction 10 includes a substrate 11 having any one or more of a conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulator (i.e., electrically) material 12. Various materials have been vertically formed over the substrate 11. The materials may be... Figure 1 The material depicted is beside, vertically inward, or vertically outward. For example, components that are fabricated or fully fabricated in other parts of the integrated circuit system may be disposed above, around, or inside the substrate 11. Only one transistor 14 is shown, but configuration 10 may include, for example, multiple transistors of the same or different configurations fabricated in an array containing one or more transistors according to the invention.

[0009] Transistor 14 includes a top source / drain region 16, a bottom source / drain region 18, a channel region 20 vertically situated between the top source / drain region 16 and the bottom source / drain region 18, and a gate 22 (i.e., a conductive material) operatively adjacent to the channel region 20. A gate insulator 24 (e.g., silicon dioxide and / or silicon nitride) lies between the gate 22 and the channel region 20. For simplicity and clarity, only the example components depicted are shown. Figure 1 The image is shown as a vertical cross-section. Example source / drain regions and channel regions can extend, for instance, to... Figure 1 The form of a longitudinally extending line both in and out of the plane of the page. Alternatively, and by way of example only, the source / drain regions and channel regions in such examples may be circular, rectangular, elliptical, triangular, etc., in a horizontal cross-section (not shown). The gate insulator 24 and / or the gate 22 may surround such a structure, or alternatively, by way of example only, partially surround such a structure or only on one side in a vertical cross-section (not shown). The top source / drain region 16 and channel region 20 may be considered to have a top interface 38, and the bottom source / drain region 18 and channel region 20 may be considered to have a bottom interface 40. Interfaces 38 and / or 40 are shown as flat and horizontal, but other oriented interfaces may be used, such as diagonal, sawtooth and / or wavy interfaces, combinations of straight and curved sections, etc. Figure 1The illustration shows an example embodiment where the top source / drain region 16 includes material 52, the channel region 20 includes material 54, and the bottom source / drain region includes material 50. Any of materials 52, 54, and 50 may be undoped or doped with a conductivity-modifying dopant (e.g., phosphorus, arsenic, etc.). Examples of materials 52, 54, and 50 primarily comprise monocrystalline or polycrystalline silicon, including such materials as mixtures and / or alloys with germanium.

[0010] In one embodiment, the top source / drain region 16 comprises a semiconductor material (e.g., silicon, germanium, gallium, a combination thereof), the semiconductor material having a first conductivity-increasing dopant (e.g., one or more of phosphorus, arsenic, etc.), the concentration of the first conductivity-increasing dopant making the semiconductor material of the top source / drain region 16 conductive. The bottom source / drain region 18 comprises a semiconductor material that may be the same as or different from the top source / drain region 16, and has a second conductivity-increasing dopant therein, the concentration of the second conductivity-increasing dopant making the semiconductor material of the bottom source / drain region 18 conductive (e.g., at least 5 x 10⁻⁶). 19 dopant atoms / cm 3 The first and second dopants that increase conductivity may be identical or different in composition relative to each other, and in any case, may have the same or different relative concentrations relative to each other in the top source / drain region 16 and the bottom source / drain region 18, including variable concentrations. The upper portion 30 of the channel region 20 is adjacent to the top source / drain region 16 and has a non-conductive concentration therein (e.g., not exceeding at least 1 x 10⁻⁶). 18 dopant atoms / cm 3 The lower portion of the channel region 20 is adjacent to the bottom source / drain region 18 and contains a second conductivity-increasing dopant with a non-conductive concentration therein, wherein the upper portion 30 is vertically thicker than the lower portion 32. In one embodiment, the upper portion 30 does not exceed 33% of the vertical thickness T of the channel region 20, and in another embodiment, does not exceed 25%. In one embodiment, the upper portion 30 is vertically at least 2.0 times thicker than the lower portion 32, and in another embodiment, at least 2.5 times thicker.

[0011] In the upper portion 30 of the channel region 20, the concentration of the dopant with the first conductivity increase may be constant or not constant, wherein Figure 1 The illustration is intended to show an example embodiment where the concentration is not constant. The dopant with increased conductivity in portions 30 and 32 is shown using a dot-mapping method, wherein the concentration of the first dopant with increased conductivity in the upper portion 30 decreases as it moves vertically deeper into the upper portion 30. Similarly, the concentration of the second dopant with increased conductivity in the lower portion 32 may be constant or not, wherein... Figure 1 The concentration of the second conductivity-increasing dopant in the lower portion 32 is schematically shown to be non-constant. The second conductivity-increasing dopant in the lower portion 32 is schematically shown to increase as it moves vertically deeper into the lower portion 32. An example intermediate region 35 is vertically shown between the upper portion 30 and the lower portion 32. The intermediate region 35 may be doped with dopant of the opposite conductivity type to the dopant in the top source / drain region 16 and the bottom source / drain region 18, or may be undoped. Portions 30, 32, and 35 may also be additionally doped with dopant of the opposite conductivity-increasing type (i.e., n to p, or p to n).

[0012] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used in the above embodiments.

[0013] In one embodiment, at least one of the top source / drain region 16, the bottom source / drain region 18, and the channel region 20 is crystalline. In this document, “crystalline” without preceding numerical percentage or other quantitative adjectives means a material, region, and / or structure that is at least 90% crystalline by volume (i.e., has at least 90% grains by volume). In this document, “amorphous” without preceding numerical percentage or other quantitative adjectives means a material, region, and / or structure that is at least 90% amorphous by volume. All grains within at least one of the top source / drain region 16, the bottom source / drain region 18, and the channel region 20 have a phase difference of at least 0.064 cubic micrometers (μm). 3 The average grain size within the channel region (independent of or unrelated to the aspects described above regarding the upper and lower portions of the channel region). In one such embodiment, this average grain size differs from each other by 0.027 μm. 3 Within, in one of these embodiments at 0.008 μm 3 Within one embodiment, the average grain size of at least a majority (at least 75% in one embodiment) of all grains within at least one of the top source / drain region 16, the bottom source / drain region 18, and the channel region 20 differs from each other by 0.027 μm. 3 Within, in one such embodiment at 0.001 μm 3 Within, and in one such embodiment at 0.000125 μm 3As an example, such a very tight grain size distribution of all grains in the source / drain region and / or channel region can be obtained in a vertical transistor by laser annealing as described below. In one embodiment, all grains in at least one of the top source / drain region, bottom source / drain region, and channel region individually have a maximum through-size that differs from each other by within 0.4 micrometers (μm), in one embodiment by within 0.3 μm, and in another embodiment by within 0.2 μm. In one embodiment, all grains in at least one of the top source / drain region, bottom source / drain region, and channel region individually have a minimum through-size that differs from each other by within 0.4 μm, in one embodiment by within 0.3 μm, and in another embodiment by within 0.2 μm. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0014] Embodiments of the present invention cover methods and transistors independent of manufacturing methods as identified above. However, such methods may have any of the properties described above in the structural embodiments. Similarly, the above structural embodiments may be incorporated into and form any of the properties described below with respect to the method embodiments. Example methods can be used to form integrated circuit systems and are referenced... Figures 2 to 6 Description. The same labels have been used for the preceding constructions where appropriate.

[0015] refer to Figure 2 An operable circuit assembly 62 has been formed above substrate 11. This circuit assembly is schematically shown as being contained within material 60, which may be any combination of insulating, conductive, and semiconductive materials. Any existing or future-developed operable circuit assembly 62 can be fabricated, with transistors, capacitors, diodes, resistors, amplifiers, rectifiers, etc., being examples. In one embodiment, at least some of the operable circuit assemblies 62 are formed to include a lower transistor, wherein “lower” is used as a positional adjective to distinguish such a transistor from other transistors formed thereon, as will be apparent from the continuing discussion. In one embodiment, this lower transistor individually includes a lower top source / drain region, a lower bottom source / drain region, a lower channel region vertically situated between the lower top and bottom source / drain regions, and a lower gate operatively adjacent to the lower channel region. By way of example only, such a lower transistor may have any of the properties described above or otherwise. In one embodiment, forming such a lower transistor includes laser annealing of the material used to fabricate at least one of the individual lower top source / drain regions, lower bottom source / drain regions, and lower channel regions. In some embodiments, the operable circuit assembly 62 may be considered to have been formed relative to the stack or assemblies 61, and in one embodiment, it may comprise a multilayer assembly that can be vertically separated by an insulating material.

[0016] refer to Figure 3 An insulating material 64 (e.g., one or more of silicon dioxide, silicon nitride, aluminum oxide, etc.) is formed directly above the operable circuit assembly 62. In one embodiment, the insulating material 64 has a minimum thickness of not less than 1,000 angstroms, in another embodiment not less than 2,000 angstroms, and in yet another embodiment between 2,000 angstroms and 5,000 angstroms. The insulating material 64 may be homogeneous. Alternatively, the insulating material may comprise one or more regions, layers, etc., including conductive and / or semiconductive materials, provided that the material 64 is insulating overall.

[0017] refer to Figure 4 Bottom material 50, top material 52, and intermediate material 54 vertically positioned between bottom material 50 and top material 52 are formed directly above insulating material 64. In the final configuration of the transistor formed directly above insulating material 64, the bottom material, top material, and intermediate material respectively include a bottom source / drain region, a top source / drain region, and a channel region vertically positioned between the bottom and top source / drain regions. In the final configuration of the transistor, at least bottom material 50 and top material 52 include dopants that increase conductivity. Example materials 50, 52, and 54 are shown as a blanket layer on top of insulating material 64. The materials may be patterned during processing or later to have Figure 1 Examples of material 52, 54, and 50, or others. In any case, material 52, 54, and 50 may be considered as having been formed relative to a stack or assemblies 75, and in one embodiment, may comprise multilayer components that can be vertically separated by an insulating material (not shown).

[0018] refer to Figure 5 At least one of the bottom material, top material, and intermediate material is laser annealed (e.g., depicted by a vertically downward arrow 90) to melt at least one of the bottom material, top material, and intermediate material, and then at least one of the bottom material, top material, and intermediate material is crystallized. This is by way of example only. Figure 5The laser annealing is demonstrated after all materials 50, 52, and 54 have been deposited, and thus at least relative to the top material 52, although laser annealing may also occur relative to only material 52, only materials 52 and 54, or all materials 52, 54, and 50. Alternatively or additionally, one or more of the intermediate material 54 and the bottom material 50 may be laser annealed before any material is deposited on top of them. In any case, laser annealing activates dopants in at least one of the bottom material, top material, and intermediate material that increase conductivity (e.g., during a period that includes both melting and crystallization). In one embodiment, at least some of the melting and at least some of the activation occur simultaneously during laser annealing. In one of these embodiments, at least most of the activation occurs during melting. In any case, an insulating material 64, vertically positioned between the operable circuit assembly 62 and the bottom material 50, protects the operable circuit assembly 62 below it from the heat generated during laser annealing, which would otherwise render the operable circuit assembly 62 inoperable. In many embodiments, a skilled craftsman can select suitable insulating materials (e.g., one or more of silicon dioxide, silicon nitride, alumina, etc.) and their thickness to achieve this thermal insulation effect, wherein the minimum thickness of material 64 is expected to be between 2,000 angstroms and 5,000 angstroms. In some embodiments, the action of laser annealing forms materials 52, 54, and 50 to have any one or more of the properties described above with respect to such materials, said materials relative to Figure 1 Transistor 14 is shown and described.

[0019] By way of example only, laser annealing can be performed using wavelengths between 200 nanometers and 700 nanometers, at a speed of 0.1 J / cm². 2 Up to 2J / cm 2 The power (ideally 0.5 J / cm) 2 Up to 2J / cm 2 The laser annealing process involves pulse widths ranging from 5 nanoseconds to 250 nanoseconds, 1 to 100 laser emissions, and substrate temperatures from room temperature to 450°C. The laser power used for any annealing can be varied by the technician to control the surface roughness and grain size of the interface undergoing laser annealing. Additionally, the substrate temperature can be varied for different laser emissions, such as laser power and / or pulse width. Laser annealing melts the annealed material. Any material subjected to laser annealing immediately prior to such annealing can be doped to varying concentrations. Regardless, annealing activates dopants present in at least one of materials 52, 54, and 50, increasing their conductivity.

[0020] refer to Figure 6 Materials 52, 54, and 50 are shown as patterned to produce a similar effect. Figure 1 The main examples shown are the structures, etc. Subsequently, the gate insulator 24 and the gate 22 are formed laterally adjacent to the intermediate material 54.

[0021] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0022] The above-described processing or construction can be viewed as an array of components formed as a single stack or group of components, or formed within a single stack or group of components, the stack or group being above or part of an underlying substrate (but a single or two stacks / groups may individually have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array can also be formed at any location as part of the final construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / groups may be provided or fabricated above and / or below the stacks / groups shown in the figures or described above. Furthermore, the arrays of components may be the same or different relative to each other in different stacks / groups, and the different stacks / groups may have the same or different thicknesses relative to each other. Intermediate structures (e.g., additional circuitry and / or dielectric layers) may be disposed between vertically adjacent stacks / groups. Moreover, the different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be manufactured substantially simultaneously.

[0023] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can include multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, transportation vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0024] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” refers to a direction generally perpendicular to the surface of the host substrate (i.e., within 10 degrees) and relative to the substrate being processed during manufacturing, with vertical being a direction generally orthogonal to it. The reference to “exactly horizontal” refers to a direction along the surface of the host substrate (i.e., not forming degrees with said surface) and referential to the substrate being processed during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to a direction inclined at least 45° from exactly horizontal. Furthermore, with respect to field-effect transistors, “vertically extending,” “horizontally extending,” “horizontally extending,” etc., refer to the orientation of the transistor’s channel length along which current flows between the source / drain regions during operation. For bipolar junction transistors, terms such as "vertically extending," "vertically extending," "horizontally extending," and "horizontally extending" refer to the orientation of the substrate length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10°.

[0025] Furthermore, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) between the two stated areas / materials / components. And, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above another stated area / material / component is vertically outside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "direct" only requires that a portion of the stated area / material / component below another stated area / material / component is vertically inside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0026] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event may be continuous or discontinuous over any material they cover. When one or more example compositions are provided for any material, the material may comprise, consist primarily of, or consist of one or more of these compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0027] Additionally, the term “thickness” (without a directional adjective) used alone is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, “different compositions” requires only that the portions of two stated materials or regions that are in direct contact with each other are chemically and / or physically different, for example, in the case where the materials or regions are non-uniform. If two stated materials or regions are not in direct contact with each other, then in the case where such materials or regions are non-uniform, “different compositions” requires only that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, a material, region, or structure is “in direct contact” with another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures. In contrast, the words "above," "on," "near," "along," and "against" without the preceding "positive" encompass "direct contact" and constructions in which the intervention of materials, areas, or structures results in the stated materials, areas, or structures not being in physical contact with each other.

[0028] In this text, if, during normal operation, current can flow continuously from one region-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the regions-material-components are “electrically coupled” relative to each other. Another electronic component may be electrically coupled between and to the regions-material-components. Conversely, when regions-material-components are referred to as “directly electrically coupled,” there are no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled regions-material-components.

[0029] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing features of one series or orientation from features of another series or orientation, and for components that have been or may be formed along said "row" and "column". "Row" and "column" are used synonymously with respect to any series of areas, components, and / or features, and are not related to function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles.

[0030] The components of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive doped semiconducting / semiconductor / semiconductive materials. "Metallic material" is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds.

[0031] In this document, any use of "selectivity" in the terms etch, etching, removing, removal, deposition, forming, and / or formation refers to the action of a stated material relative to another stated material at a rate of at least 2:1 by volume. Additionally, any use of selective deposition, selective growth, or selective formation refers to the deposition, growth, or formation of one material relative to one or more stated materials at a ratio of at least 2:1 by volume, reaching a deposition, growth, or formation of at least a first 75 angstroms.

[0032] Unless otherwise indicated, the use of "or" in this document covers either one or both.

[0033] in conclusion

[0034] In some embodiments, a transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically located between the top source / drain region and the bottom source / drain region, and a gate laterally adjacent to the channel region in an operative manner. At least one of the top source / drain region, the bottom source / drain region, and the channel region is crystalline. All grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region have a phase difference of 0.064 μm from each other. 3 The average crystal size within.

[0035] In some embodiments, the transistor including a top source / drain region has a first conductivity-increasing dopant, the concentration of which makes the semiconductor material of the top source / drain region conductive. A bottom source / drain region has a second conductivity-increasing dopant, the concentration of which makes the semiconductor material of the bottom source / drain region conductive. A channel region is vertically located between the top source / drain region and the bottom source / drain region. A gate is operatively laterally adjacent to the channel region. An upper portion of the channel region is adjacent to the top source / drain region and has a non-conductive concentration of the first conductivity-increasing dopant. A lower portion of the channel region is adjacent to the bottom source / drain region and has a non-conductive concentration of the second conductivity-increasing dopant. The upper portion is vertically thicker than the lower portion.

[0036] In some embodiments, a method of forming an integrated circuit system includes forming an operable circuit assembly over a substrate. An insulating material is formed directly above the operable circuit assembly. A bottom material, a top material, and an intermediate material vertically positioned between the bottom material and the top material are formed directly above the insulating material. In the final configuration of the transistor positioned directly above the insulating material, the bottom material, top material, and intermediate material each include a bottom source / drain region, a top source / drain region, and a channel region vertically positioned between the bottom and top source / drain regions. In the final configuration of the transistor, at least the bottom material and the top material include a dopant that increases conductivity. At least one of the bottom material, top material, and intermediate material is laser-annealed to melt at least one of the bottom material, top material, and intermediate material, and then at least one of the bottom material, top material, and intermediate material is crystallized. The laser annealing activates the dopant that increases conductivity in at least one of the bottom material, top material, and intermediate material. An insulating material, vertically positioned between the operable circuit assembly and the bottom material, protects the operable circuit assembly below from the heat generated during laser annealing, which would otherwise render the operable circuit assembly inoperable. A gate insulator and gate are formed laterally adjacent to the intermediate material.

Claims

1. A transistor comprising: A top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region; At least one of the top source / drain region, the bottom source / drain region, and the channel region is crystalline, and all grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region have a phase difference of 0.064 µm from each other. 3 Average crystal size within; The top source / drain region has a dopant with increased first conductivity therein; The bottom source / drain region contains a dopant with a second conductivity increase; The upper portion of the channel region adjacent to the top source / drain region has a dopant with a non-conductive concentration of the first conductivity-increased dopant. and The lower portion of the channel region adjacent to the bottom source / drain region has a dopant with a non-conductive concentration of the second conductivity-increasing dopant, and the upper portion is vertically thicker than the lower portion.

2. The transistor of claim 1, wherein the average crystal size of all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region differs from each other by less than 0.027 µm. 3 Inside.

3. The transistor of claim 2, wherein the average crystal size of all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region differs from each other by less than 0.008 µm. 3 Inside.

4. The transistor of claim 1, wherein all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region individually have a maximum through-size that differs from each other by within 0.4 µm.

5. The transistor of claim 4, wherein all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region individually have a maximum through-size that differs from each other by within 0.3 µm.

6. The transistor of claim 5, wherein all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region individually have a maximum through-size that differs from each other by within 0.2 µm.

7. The transistor of claim 1, wherein all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region individually have a minimum through-size that differs from each other by within 0.4 µm.

8. The transistor of claim 7, wherein all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region individually have a minimum through-size that differs from each other by within 0.3 µm.

9. The transistor of claim 8, wherein all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region individually have a minimum through-size that differs from each other by within 0.2 µm.

10. The transistor of claim 1, wherein at least a majority of the average crystal size of all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region differs from each other by less than 0.027 µm. 3 Inside.

11. The transistor of claim 10, wherein at least 75% of the average crystal size of all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region differs from each other by 0.027 µm. 3 Inside.

12. The transistor of claim 10, wherein at least a majority of the average crystal size of all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region differs from each other by less than 0.001 µm. 3 Inside.

13. The transistor of claim 12, wherein at least 75% of the average crystal size of all the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region differs from each other by less than 0.027 µm. 3 Inside.

14. The transistor of claim 12, wherein at least a majority of the average crystal size of the grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region differs from each other by 0.000125 µm. 3 Inside.

15. A transistor comprising: A top source / drain region having a first dopant with increased conductivity, the concentration of which makes the semiconductor material of the top source / drain region conductive. Bottom source / drain region having a second dopant with increased conductivity, the concentration of which makes the semiconductor material of the bottom source / drain region conductive; The channel region is vertically located between the top and bottom source / drain regions; A gate that is operatively adjacent to the channel region; The upper portion of the channel region adjacent to the top source / drain region has a dopant with a non-conductive concentration of the first conductivity-increased dopant. and The lower portion of the channel region adjacent to the bottom source / drain region has a dopant with a non-conductive concentration of the second conductivity-increased dopant, and the upper portion is vertically thicker than the lower portion. At least one of the top source / drain region, the bottom source / drain region, and the channel region is crystalline, and all grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region have a phase difference of 0.064 µm from each other. 3 The average crystal size within.

16. The transistor of claim 15, wherein the first conductivity-increasing dopant and the second conductivity-increasing dopant are the same.

17. The transistor of claim 15, wherein the first conductivity-increasing dopant and the second conductivity-increasing dopant are different.

18. The transistor of claim 15, wherein the upper portion does not exceed 33% of the vertical thickness of the channel region.

19. The transistor of claim 18, wherein the upper portion does not exceed 25% of the vertical thickness of the channel region.

20. The transistor of claim 15, wherein the upper portion is vertically at least 2.0 times thicker than the lower portion.

21. The transistor of claim 20, wherein the upper portion is vertically at least 2.5 times thicker than the lower portion.

22. The transistor of claim 15, wherein the concentration of the dopant with the first conductivity increase in the upper portion of the channel region is not constant.

23. The transistor of claim 22, wherein the concentration of the first conductivity-increasing dopant in the upper portion of the channel region decreases as it moves vertically deeper into the upper portion.

24. The transistor of claim 23, wherein the upper portion does not exceed 33% of the vertical thickness of the channel region.

25. The transistor of claim 15, wherein the concentration of the dopant with the second conductivity increase in the lower portion of the channel region is not constant.

26. The transistor of claim 22, wherein the concentration of the second conductivity-increasing dopant in the lower portion of the channel region increases as it moves vertically deeper into the lower portion.

27. The transistor of claim 15, wherein, The concentration of the first conductivity-increasing dopant in the upper portion of the channel region is not constant and decreases as it moves vertically deeper into the upper portion; and The concentration of the second conductivity-increasing dopant in the lower portion of the channel region is not constant and increases as it moves vertically deeper into the lower portion.

28. A method for forming an integrated circuit system, comprising: An operable circuit assembly is formed above the substrate; An insulating material is formed directly above the operable circuit assembly; A bottom material, a top material, and an intermediate material vertically positioned between the bottom and top materials are formed directly above the insulating material. In the final configuration of the transistor positioned directly above the insulating material, the bottom material, top material, and intermediate material respectively include a bottom source / drain region, a top source / drain region, and a channel region vertically located between the bottom and top source / drain regions; in the final configuration of the transistor, at least the bottom material and the top material include dopants that increase conductivity. At least one of the bottom material, top material, and intermediate material is laser-annealed to melt at least one of the bottom material, top material, and intermediate material, and then the at least one of the bottom material, top material, and intermediate material is crystallized; the laser annealing activates the dopant with increased conductivity in at least one of the bottom material, top material, and intermediate material; the insulating material vertically positioned between the operable circuit assembly and the bottom material protects the operable circuit assembly below it from the heat generated during the laser annealing, which would otherwise render the operable circuit assembly inoperable; and A gate insulator and a gate are formed laterally adjacent to the intermediate material. The laser annealing wherein all grains within at least one of the top source / drain region, the bottom source / drain region, and the channel region are formed to have a phase difference of 0.064 µm from each other. 3 The average crystal size within.

29. The method of claim 28, wherein at least some of the melting and at least some of the activation occur simultaneously during the laser annealing.

30. The method of claim 29, wherein at least a majority of the activation occurs during the melting process.

31. The method of claim 28, wherein the laser annealing comprises a plurality of laser emissions, each comprising a pulse width of 5 to 250 nanoseconds.

32. The method according to claim 28, wherein, The top source / drain region has a first conductivity-increasing dopant therein, the concentration of which makes the semiconductor material of the top source / drain region conductive. The bottom source / drain region has a second dopant with increased conductivity, the concentration of which makes the semiconductor material of the bottom source / drain region conductive. and The laser annealing: At least for the top source / drain region; The upper portion of the channel region adjacent to the top source / drain region is formed as a dopant with a first conductivity increase having a non-conductive concentration therein; and The lower portion of the channel region adjacent to the bottom source / drain region is formed with a dopant having a second conductivity-enhancing dopant with a non-conductive concentration therein, and the upper portion is vertically thicker than the lower portion.

33. The method of claim 28, wherein the insulating material has a minimum thickness of not less than 1,000 angstroms.

34. The method of claim 33, wherein the insulating material has a minimum thickness of not less than 2,000 angstroms.

35. The method of claim 34, wherein the insulating material has a minimum thickness of 2,000 angstroms to 5,000 angstroms.

36. The method of claim 28, wherein the insulating material comprises silicon dioxide.

37. The method of claim 28, wherein the insulating material comprises silicon nitride.

38. The method of claim 28, further comprising forming at least some of the operable circuit components to include a lower transistor, the lower transistor individually including a lower top source / drain region, a lower bottom source / drain region, a lower channel region vertically located between the lower top and bottom source / drain regions, and a lower gate operably adjacent to the lower channel region.

39. The method of claim 38, wherein forming the lower transistor comprises laser annealing a material used to manufacture at least one of the individual lower top source / drain regions, the lower bottom source / drain regions, and the lower channel region.

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