Current-to-digital converter circuit, optical front-end circuit, computed tomography device and method

Abstract

A current-to-digital converter circuit comprises: an integrating amplifier (IAmp) having an input (12) adapted to receive a current signal (Ip) and an output (13) adapted to provide a voltage signal (Vout) which is a function of the integration of the current signal (Ip); a quantizer circuit (Op2) having an input coupled to the output (13) of the integrating amplifier (IAmp) and an output (14) adapted to provide a binary result signal (Scmp1) which is a function of a comparison of the voltage signal (Vout) with at least a first reference voltage signal (Vref1); a digital-to-analog converter circuit (Dac) switchably coupled to the input (12) of the integrating amplifier (IAmp) in dependence on the binary result signal (Scmp1); and a controlled current source (CCS) coupled to the output (13) of the integrating amplifier (IAmp) via a first switch (S1), the first switch being controlled in dependence on the binary result signal (Scmp1) in order to supply an auxiliary current (Iaux) to the output (13) of the integrating amplifier (IAmp).

Description

Technical Field

[0001] The present disclosure relates to the field of amplifiers, in particular to amplifiers forming part of a current-to-digital converter in an optical front end. Specifically, the present application relates to a current-to-digital converter circuit, an optical front end circuit, a computed tomography apparatus, and a method for providing an output voltage. Background Art

[0002] Low-noise and low-power amplifiers are needed in many fields. While many techniques exist to address flicker noise, such as chopping and auto-zeroing, fewer address thermal noise, which is considered a fundamental issue for amplifiers. The trade-off between a system's (in this case, an amplifier's) thermal noise and its speed is considered fundamental, and known improvements involve sacrificing power and / or area. Because this trade-off is so fundamental, most techniques revolve around increasing signal power to achieve a better signal-to-noise ratio (SNR).

[0003] This also applies to the optical front end, which detects light energy with the help of an optical sensor (such as a photodiode) and converts the energy into a voltage signal. The first amplifier in the optical front end (i.e., the amplifier that receives the current signal from the photodiode) is also called the front-end amplifier. The amplifier generally determines the noise performance of the optical front end and the upper system in which the optical front end is used. Such an upper system can be a computed tomography (CT) device. Known optical front-end amplifiers in past CT applications have solved the noise problem by consuming more power or by using a stacked differential pair approach when implementing the front-end amplifier. However, it turns out that this approach requires expensive low-threshold voltage transistors. Summary of the Invention

[0004] Thus, it can be seen that an object is to provide a current-to-digital converter circuit, an optical front-end circuit, a computed tomography apparatus, and a method for providing an output voltage having an improved noise-power trade-off design.

[0005] This object is achieved by the subject matter of the independent claims. Embodiments and developments are defined in the dependent claims.

[0006] In one embodiment, a current-to-digital converter circuit includes an integrating amplifier, a quantizer circuit, a digital-to-analog converter circuit, and a controlled current source. The integrating amplifier has an input adapted to receive a current signal and an output adapted to provide a voltage signal that is a function of an integral of the current signal. The quantizer circuit has an input coupled to the output of the integrating amplifier and an output adapted to provide a binary result signal that is a function of a comparison of the voltage signal with at least a first reference voltage signal. The digital-to-analog converter circuit is switchably coupled to the input of the integrating amplifier. The switchability is achieved based on the binary result signal. The controlled current source is coupled to the output of the integrating amplifier via a first switch, which is controlled based on the binary result signal to supply an auxiliary current to the output of the integrating amplifier.

[0007] An integrating amplifier integrates the current signal at its input and thereby provides a voltage signal. Within a quantizer circuit, this voltage signal is compared with a first reference voltage signal, thereby providing a binary result signal. As soon as the level of the binary result signal changes, for example, from 1 to 0 or from 0 to 1, a digital-to-analog converter circuit is triggered to inject charge into the input of the integrating amplifier to keep the voltage signal at the output of the integrating amplifier within a valid range. Simultaneously, i.e., triggered by a change in the level of the binary result signal, a controlled current source supplies an auxiliary current to the output of the integrating amplifier. Thus, charge associated with the level change or pulse of the binary result signal is provided to the output of the integrating amplifier. The binary result signal comprises a digital, in particular binary, representation of the current signal.

[0008] In the proposed current-to-digital converter circuit, the majority of the integrating amplifier's output charge is supplied by a controlled current source at the exact moment it is needed (i.e., when the level of the binary result signal changes). In this way, the integrating amplifier can create the output pulses of the binary result signal with very high precision, thereby satisfying linearity constraints and reducing power consumption.

[0009] In an exemplary embodiment, once the voltage signal at the output of the integrating amplifier falls below a first reference voltage signal, the level of the quantizer circuit output changes from 0 to 1. When triggered by this pulse of the binary result signal, charge is injected in a direction opposite to the current signal at the input of the integrating amplifier, with the amount of charge representing the previously integrated charge provided by the current signal before the level change of the binary result signal. Simultaneously, a controlled current source is activated to supply auxiliary current to the output of the integrating amplifier, thereby facilitating faster recharging of the output of the integrating amplifier. Consequently, the stability of the output at the output of the integrating amplifier is significantly improved, for example, by a factor of 4 to 20.

[0010] In a refinement, the auxiliary current is supplied when a pulse of the binary result signal occurs and for an amount of time that is less than a time constant implemented by the integrating amplifier.

[0011] The time constant implemented by the integrating amplifier is the time constant of the operational amplifier used to implement the integrating amplifier. The auxiliary current is supplied for a period of time that is less than the time constant of the integrating amplifier, for example, 1 / 10 of the time constant. This prevents the integrating amplifier from interfering with the auxiliary circuitry, resulting in a fast, essentially ring-free output. This design ensures that the majority of the charge required at the output of the integrating amplifier is provided by the auxiliary current, while the remaining charge is provided by the integrating amplifier itself.

[0012] In a modified embodiment, the controlled current source includes a current generating unit and a timing generating unit. The timing generating unit is configured to provide a charging clock signal, wherein a rising edge of the charging clock signal is generated when a rising edge of the binary result signal occurs, and a falling edge of the charging clock signal is generated when an auxiliary capacitor included in the timing generating unit is charged to a second reference voltage level. The auxiliary capacitor is charged with the aid of a bias current. The current generating unit is configured to provide the auxiliary current. To this end, it includes a current mirror component for mirroring the bias current or includes an adjustable resistor connected to a power supply potential.

[0013] When the binary result signal undergoes a level change, such as a rising edge of the binary result signal corresponding to a level change from 0 to 1, a first level change of the charging clock signal is generated. When the charging clock signal undergoes the first level change, such as a change from 0 to 1 or a rising edge of the charging clock signal, the bias current charges the auxiliary capacitor. Once the voltage drop across the auxiliary capacitor, resulting from the change in charging of the capacitor, reaches the level of a second reference voltage, a second level change of the charging clock signal is generated, such as a level change from 0 to 1 or a falling edge. Charging of the auxiliary capacitor is simultaneously stopped.

[0014] The current generating unit may include a current mirror component that mirrors a bias current to provide an auxiliary current, or alternatively, an adjustable resistor having one terminal connected to a power supply potential and providing the auxiliary current. In either of these alternatives, the auxiliary current is provided to the output of the integrating amplifier as long as the first switch is closed. As described above, the first switch is controlled based on the binary result signal. This function may be slightly delayed in time to achieve non-overlap. The charging clock signal changes with the binary result signal because the first level change of the charging clock signal is generated when the binary result signal changes level. Thus, the charging clock signal is synchronized with the binary result signal. The charging clock signal is used to control the first switch. For example, the first switch is closed when the charging clock signal undergoes a first level change, which is substantially consistent with the level change of the binary result signal. The first switch may be opened upon a second level change of the charging clock signal.

[0015] In another refinement, the current-to-digital converter circuit includes a control unit configured to provide a master clock signal for controlling the operation of at least the quantizer circuit. Thus, the provision of the binary result signal is substantially synchronized with the master clock signal. Consequently, the charging clock signal is also synchronized with or to the master clock signal.

[0016] In an improved solution, the integrating amplifier includes an operational amplifier and an integrating capacitor, wherein the integrating capacitor is coupled in a feedback loop of the operational amplifier between its output terminal and its inverting input terminal. The operational amplifier is implemented by a folded cascode, wherein each folded node is implemented by a transistor.

[0017] In a conventional folded cascode structure, the cascodes of the differential input pair transistors are biased by a current source. Therefore, this conventional folded structure can only stabilize at a rate determined by the constant current bias current. The folded cascode structure described above implements a folded node using transistors. Therefore, a signal current of the same polarity from the other branch is used to bias the cascode. This achieves rapid output settling and allows low-voltage operation.

[0018] In another improvement, the operational amplifier of the integrating amplifier is implemented by two or more stages.

[0019] In this embodiment, two or more stages are implemented by operational amplifiers configured as inverting amplifiers. In each stage of the stage, a folded cascode as described above can be used in embodiments. The output of the first stage of the stage, i.e., the operational amplifier that directly receives the current signal, represents the output of the integrating amplifier.

[0020] In an improved solution, the digital-to-analog converter circuit is implemented as a single-bit digital-to-analog converter based on switched capacitors. The switched capacitors are additionally switchably connected to corresponding terminals for supplying a third reference voltage. The switches of the switched capacitors are controlled according to the binary result signal.

[0021] While integrating the current signal in the integrating amplifier, the switched capacitor is charged to the level of the third reference voltage. Once the voltage signal reaches the level of the first reference voltage signal, the level of the binary result signal switches, and the switched capacitor is connected to the input of the integrating amplifier. Thus, an amount of charge corresponding to the previously integrated current signal is additionally supplied to the input of the integrator circuit.

[0022] In an exemplary embodiment, the second reference voltage is selected to be proportional to or equal to the third reference voltage.

[0023] In an alternative embodiment, the digital-to-analog converter circuit is implemented as an M-bit digital-to-analog converter based on a plurality of capacitors, where M is an integer greater than or equal to 2.

[0024] In a further development, the quantizer circuit is implemented as a single-bit clocked comparator amplifier. The clocked comparator amplifier has a clock input supplied by a master clock signal. For each pulse of the master clock signal, the result of the comparison of the voltage signal with the first reference voltage signal is provided at the output of the quantizer circuit in the form of a binary result signal.

[0025] In an alternative embodiment, the quantizer circuit is implemented as an M-bit clocked quantizer. This implementation is used in combination with the M-bit digital-to-analog converter described above.

[0026] In one embodiment, the optical front-end circuit includes a current-to-digital converter circuit as described above, wherein the current signal at the input of the integrating amplifier includes the photocurrent of a photodiode that is connectable to the input. The optical front-end circuit also includes a sampling capacitor, an analog-to-digital (ADC) circuit, and a computing circuit. The sampling capacitor is coupled to the output of the integrating amplifier via a second switch. The second switch is controlled by a sampling clock signal. The ADC circuit is coupled to the sampling capacitor via a third switch via its input, and the third switch is controlled by a conversion clock signal. The ADC circuit has an output at which a digital signal is provided. The digital signal varies with the current signal and includes N bits, where N is an integer greater than or equal to 1. The computing unit is coupled to the output of the ADC circuit and the output of the quantizer circuit. The computing circuit is prepared to provide a digital word signal by combining the binary result signal with the digital signal.

[0027] The optical front-end circuit performs digital conversion of the optical signal (i.e., the light energy received by the photodiode). To this end, the photocurrent supplied by the photodiode is provided to the input of the current-to-digital converter circuit. An integrating amplifier, along with the resulting quantizer circuit, provides a coarse digital value with one or more bits in the form of a binary result signal. Under the control of a sampling clock signal, the voltage signal at the output of the integrating amplifier is sampled onto a sampling capacitor. Under the control of a conversion clock signal, the charge stored on the sampling capacitor is converted into a digital signal by an ADC circuit. A computation circuit combines the digital value provided by the binary result signal with the digital value provided by the digital signal to produce a digital word signal.

[0028] By means of a current-to-digital converter circuit used in an optical front-end circuit, good noise performance is achieved while consuming less power and without increasing process options compared to prior art implementations.

[0029] Thus, the optical front-end circuit described above consists of a coarse analog-to-digital conversion performed within the current digitizer circuit and a fine analog-to-digital conversion performed after the coarse conversion. Each time the coarse conversion is completed, i.e., once the binary result signal provides one or M bits, the controlled current source of the current digitizer circuit is coupled to the output of the integrating amplifier to more quickly recharge the output. The ADC circuit that performs the fine analog-to-digital conversion of the current signal, which provides the less significant bits of the digital word signal, can be implemented as a sigma-delta ADC or a successive approximation ADC. The current digitizer circuit can also be used to implement an ADC circuit.

[0030] In an improved solution, the control unit is configured to provide both a sampling clock signal and a conversion clock signal based on the master clock signal, wherein the conversion clock signal and the sampling clock signal have different clock frequencies or substantially equal clock frequencies.

[0031] When the conversion clock signal is different from the sampling clock signal, the ADC circuit implementing the fine ADC conversion operates at a clock rate different from the rate at which the voltage signal is sampled onto the sampling capacitor. The sampling clock signal rate may be a fraction of the master clock signal rate, while the conversion clock signal rate may be a multiple of the master clock signal rate.

[0032] In a further development, the computing circuit is arranged to provide the digital words as correlated double samples.

[0033] To this end, the calculation circuit stores a digital value resulting from a combination of coarse and fine analog-to-digital conversions for a transition of a reset level of the current signal and a subsequently determined digital value corresponding to a transition of a signal current level of the current signal, and provides these two values using a digital word signal.

[0034] In the optical front-end circuitry, calibration is used to amplify the bits of the coarse ADC (i.e., current-to-digital converter circuitry) to form a final data word provided as a digital word signal. The digital word signal is provided as a combination of the bits provided as a binary result signal multiplied by a factor and the bits of the digital signal. During calibration, the factor is adjusted. In an exemplary method, two known current values are provided to the optical front-end circuitry to calibrate the factor. The factor is determined using a value provided by converting the two current values using the binary result signal and the digital signal.

[0035] By keeping the sampling clock rate independent of the conversion clock rate, multiple coarse ADCs can be multiplexed into a single fine ADC. By using a master clock signal at a higher rate than the sampling clock signal, the noise requirements of the fine ADC can be relaxed.

[0036] In one embodiment, a computed tomography device has an optical front end according to one of the above-described embodiments.

[0037] Thus, the optical front-end circuit as described above is ready for use in a computed tomography apparatus.

[0038] In one embodiment, a method for providing an output voltage includes at least the following steps:

[0039] Supply current signal,

[0040] The current signal is converted into an output voltage by means of charge integration in the integrating amplifier.

[0041] quantizing the output voltage and thereby providing a binary result signal having at least one bit,

[0042] While the binary result signal is being provided, an auxiliary current is substantially simultaneously provided to the output of the integrating amplifier for recharging said output and for adding an additional charge amount to the current signal in dependence on the binary result signal.

[0043] Because the output of the integrating amplifier is recharged with the aid of an auxiliary current, the settling time of the integrating amplifier is significantly shortened. Because the auxiliary current is supplied for a limited time, which is one-quarter or less of the time constant implemented within the integrating amplifier, the auxiliary current does not interfere with the integrating amplifier. This is particularly advantageous when the integrating amplifier is implemented with two or more stages, which would induce a higher level of settling behavior. Since the proposed concept only supplies the auxiliary current for a shorter time, the settling behavior is improved.

[0044] The method can be implemented by the current-to-digital converter circuit defined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present invention is explained in detail below using exemplary embodiments with reference to the accompanying drawings. Components and circuit elements that are functionally identical or have the same function are given the same reference numerals. For circuit parts or components that functionally correspond to other circuit parts or components, their description will not be repeated in each of the following figures.

[0046] In the attached figure:

[0047] Figure 1 An example embodiment of an optical front-end circuit with a current-to-digital converter circuit is shown;

[0048] Figure 2 An example embodiment of a controlled current source is shown;

[0049] Figure 3 shows a signal diagram for a current-to-digital converter circuit;

[0050] Figure 4 Shows about Figure 2 Signal diagram of the controlled current source;

[0051] Figure 5A and Figure 5B An example signal diagram is shown;

[0052] Figure 6 Another embodiment example of an optical front-end circuit is shown;

[0053] Figure 7 An example implementation of an operational amplifier of an integrating amplifier is shown; and

[0054] Figure 8 An example of an embodiment of a computed tomography apparatus is shown. DETAILED DESCRIPTION

[0055] Figure 1 An example embodiment of an optical front-end circuit with a current-to-digital converter circuit is shown, both based on the proposed concepts. The current-to-digital converter circuit includes an integrating amplifier IAmp, a quantizer circuit Op2, a digital-to-analog converter circuit Dac, and a controlled current source CCS. The integrating amplifier IAmp includes an operational amplifier Op1 and an integrating capacitor Cfb coupled in the operational amplifier's feedback loop between its output 13 and its inverting input 12. Input 12 is adapted to receive a current signal Ip.

[0056] The quantizer circuit Op2 is connected to the output terminal 13 so that it receives the voltage signal Vout as an input. In the example shown, the quantizer circuit Op2 is implemented as a clock comparator that receives the voltage signal Vout at its non-inverting input, the first reference voltage signal Vref1 at its inverting input, and the master clock signal Sclk at its clock input. The quantizer circuit Op2 provides a binary result signal Scmp1 at its output terminal 14 based on a comparison of the voltage signal Vout with at least the first reference voltage signal Vref1.

[0057] The digital-to-analog converter circuit Dac is connected in a switchable manner, i.e., via a plurality of switches, to the input 12 of the integrating amplifier IAmp. In the example shown, the digital-to-analog converter circuit Dac includes a switched capacitor Cdac, which can be connected in series to the input 12 of the integrating amplifier IAmp or to terminals 15 and 16. A third reference voltage Vref3 is supplied between terminals 15 and 16. The switches of the digital-to-analog converter circuit Dac are controlled by a Dac step signal Scmp2 that varies with the binary result signal Scmp1.

[0058] The level of the third reference voltage Vref3 is chosen such that, together with the switched capacitor Cdac of the digital-to-analog converter Dac, a charge is provided that is equal and opposite to the full-scale input current signal Ip.

[0059] The auxiliary current source CCS is connected to the output 13 of the integrating amplifier IAmp by means of a first switch S1. Whenever the first switch S1 is closed, the controlled current source CCS is ready to provide an auxiliary current Iaux to the output 13. The first switch S1 is controlled in dependence on the binary result signal Scmp1.

[0060] In the illustrated example, the current-to-digital converter circuit further includes an output capacitor Ccmp connected to the output 13 of the integrating amplifier IAmp. The output capacitor Ccmp is also connected to the reference potential terminal 10. In the illustrated example, the current-to-digital converter circuit further includes a control unit CTL connected to the output 14 of the quantizer circuit Op2. The control unit CTL is configured to provide a master clock signal Sclk that controls the operation of the quantizer circuit Op2. Furthermore, the control unit CTL receives the binary result signal Scmp1 and, from it, provides a Dac step signal Stmp2 that controls the operation of the switches of the digital-to-analog converter circuit Dac. The control unit CTL provides the Dac step signal based on the binary result signal Scmp1, inserting a short delay to ensure non-overlap between the Dac step signal Scmp2 and the binary result signal Scmp1.

[0061] In the example shown, the photodiode PD is connected to the input terminal 12 of the integrating amplifier IAmp. Specifically, the anode terminal of the photodiode PD is connected to the input terminal 12, while the cathode terminal of the photodiode PD is connected to the reference potential terminal 10, which is also connected to the non-inverting input terminal of the integrating amplifier IAmp.

[0062] The current signal Ip is supplied to the inverting input 12 of the integrating amplifier IAmp. The current signal Ip is integrated by the integrating amplifier IAmp, thereby providing a voltage signal Vout at an output 13. The quantizer circuit Op2 compares the voltage signal Vout with a first reference voltage signal Vref1 and thereby provides a binary result signal Scmp1. The pulses of the binary result signal Scmp1 are also generated based on the master clock signal Sclk. The control unit CTL generates a Dac step signal Scmp2 based on the binary result signal Scmp1, possibly adding some delay to achieve non-overlap between the two signals. The Dac step signal Scmp2 controls the switches Sa, Sb, Sc, and Sd of the digital-to-analog converter circuit Dac. When the switches Sc and Sd are closed, the switched capacitor Cdac is charged to the level of the second reference voltage. Once the output 14 of the quantizer circuit Op2 switches, switches Sc and Sd open, and after a short non-overlap time (not shown in the figure for simplicity), switches Sa and Sb close, allowing the charge accumulated on the switched capacitor Cdac to be provided to the input 12 of the integrating amplifier IAmp. Simultaneously, i.e., when switches Sa and Sb close after the output Scmp1 of the quantizer circuit Op2 switches, the first switch S1 closes with the aid of the charging clock signal Sckp. The controlled current source CCS thus provides the auxiliary current Iaux for a time controlled by the charging clock signal Sckp, which is less than the time constant Tau caused by the integrating amplifier IAmp.

[0063] As another variation, the DAC could consist of two Cdac units that operate in an alternating fashion to allow a 100% duty cycle. Other schemes could also be employed where the second DAC is used only when the first is charging.

[0064] The proposed current-to-digital converter circuit enables faster settling of the output 13 of the integrating amplifier IAmp, improving the settling time by, for example, 4 to 20 times. The optical front-end circuit includes the described current-to-digital converter circuit and a sampling capacitor Cs, an analog-to-digital converter (ADC) circuit Ad, a second switch S2, a third switch S3, and a calculation circuit Cal. A photodiode PD can be connected to the input 12 of the integrating amplifier IAmp. The current signal Ip thus includes the photocurrent of the photodiode PD. The sampling capacitor Cs is coupled to the output 13 of the integrating amplifier IAmp via the second switch S2, which is controlled by a sampling clock signal Scks provided by a control unit CTL. The ADC is coupled to the sampling capacitor Cs via its input via a third switch S3, which is controlled by a conversion clock signal Sckc also provided by the control unit CTL. The output 17 of the ADC circuit Ad and the output 14 of the quantizer circuit Op2 are each coupled to the calculation circuit CAL. A digital signal Sn is provided at the output 17 of the ADC circuit Ad. The digital signal Sn varies with the current signal Ip and comprises N bits, where N is an integer greater than or equal to 1.

[0065] The calculation circuit CAL combines the binary result signal Scmp1 with the digital signal Sn to provide a digital word signal Sw. To this end, the calculation circuit CAL may include a decimation filter DF. This decimation filter is applied to the digital signal Sn and may be advantageous when oversampling the ADC circuit Ad. The calculation circuit CAL also includes a digital function Fx applied to the binary result signal Scmp1. Here, Fx represents an integrator function, which is equivalent to counting the output of the quantizer circuit Op2. The value of the digital word signal Sw provided by the correlated double sampling operation corresponds to the total charge injected at the input 12 of the integrating amplifier IAmp between the current clock edge and the previous clock edge of the sampling clock signal Scks.

[0066] The combination of the bits provided in the binary result signal Scmp1 and the N bits provided in the digital signal Sn is implemented in the combiner component Cmb. The calculation circuit CAL may also include correlated double sampling (CDS) and logic circuit Fcds for correlated double sampling. Correlated double sampling refers to the first-order difference between the digital word at any given rising edge of the sampling clock signal Scks and the digital word at the immediately preceding rising edge of the sampling clock signal Scks.

[0067] At the output of the calculation circuit CAL a digital word signal Sw is provided.

[0068] In the example depicted, the quantizer circuit Op2 is implemented by a comparator amplifier which provides exactly one bit at its output per clock cycle of the master clock signal Sclk.The binary result signal Scmp1 is therefore 1 bit wide.

[0069] The digital signal Sn in the illustrated example has N bits, where N is an integer greater than or equal to 1.

[0070] Reference Figure 3 The detailed function of the current-to-digital converter circuit is explained.

[0071] Under the control of the sampling clock signal Scks, the sampling capacitor Cs samples the output voltage Vout. A voltage follower Vf can be inserted between the second switch S2 and the third switch S3. Once sampling is completed on the sampling capacitor Cs, the sampled result is provided to the input of the ADC circuit Ad under the control of the conversion clock signal Sckc, which closes the third switch S3. The current-to-digital converter circuit provides coarse analog-to-digital conversion of the current signal, while the ADC circuit Ad essentially provides fine analog-to-digital conversion of the current signal. Therefore, in the illustrated example, the most significant bit of the digital word signal Sw provided at the output of the calculation circuit CAL is provided by the binary result signal Scmp1. The remaining bits of the digital word signal Sw are provided by the ADC circuit Ad. Therefore, the clock rates of the sampling clock signal Scks, the conversion clock signal Sckc, and the master clock signal can differ from each other. However, both the sampling clock signal Scks and the conversion clock signal Sckc are derived from the master clock signal Sclk.

[0072] In another exemplary implementation, the sampling and holding function implemented by the third switch S3 in conjunction with the sampling capacitor Cs may be implemented in a different manner than known to those skilled in the art.

[0073] Figure 2 An example of an embodiment of a controlled current source CCS is shown. Figure 2 Shown as Figure 1 An example of implementation of a controlled current source CCS is shown.

[0074] The controlled current source includes a timing generation unit TGU and a current generation unit CGU. The timing generation unit TGU is configured to provide a charging clock signal Sckp. In this example, the timing generation unit TGU includes a first flip-flop FF1, a second flip-flop FF2, an AND gate G, an inverter Inv, a current source for providing a bias current Ibias, and an auxiliary capacitor Caux. The current source for providing the bias current Ibias is coupled between the power supply potential terminal 11 and one plate of the auxiliary capacitor Caux.

[0075] The second plate of the auxiliary capacitor Caux is coupled to the reference potential terminal 10. A connection point 18 between the current source providing the bias current Ibias and the auxiliary capacitor Caux is connected to the non-inverting input of the third operational amplifier Op3. The inverting input of the third operational amplifier Op3 receives the second reference voltage Vref2. The output of the third operational amplifier Op3 is connected to the clock input of the second flip-flop FF2. The first flip-flop FF1 and the second flip-flop FF2 are both implemented as D flip-flops. The D input of the second flip-flop FF2 is connected to the power supply potential terminal 11. The Q output of the second flip-flop FF2 is connected to the first input of the AND gate G. The reset input of the second flip-flop FF2 is connected to the reset input of the first flip-flop FF1 and to the output of the AND gate G. The clock input of the first flip-flop FF1 receives the Dac step signal Scmp2. The D input of the first flip-flop FF1 is connected to the power supply potential terminal 11. The Q output of the first flip-flop FF1 is connected to the second input of the AND gate G.

[0076] The Dac step signal Scmp2 is provided to an inverter Inv, which controls a fourth switch S4, which provides a switchable connection between the connection point 18 and the reference potential terminal 10. The current generating unit CGU in the illustrated example has a current mirror component CM, which mirrors the bias current Ibias to provide an auxiliary current Iaux at its output. The current mirror component includes at least one current mirror. As an alternative, the current generating unit CGU has an adjustable resistor, which is connected to the power supply potential with one terminal and provides the auxiliary current Iaux. In any of these alternatives, whenever the first switch S1 is closed, the auxiliary current Iaux is provided to the output of the integrating amplifier.

[0077] The first level change of the charging clock signal Sckp is generated when the level change of the binary result signal Scmp1 coincides with the level change of the Dac signal Scmp2. Once the auxiliary capacitor Caux is charged to the level of the second reference voltage Vref2 (reflected in the charging end signal Sco) by means of the bias current Ibias (reflected in the charging signal Sci at the connection point 18), the second level change of the charging clock signal Sckp is shown. For detailed functions of the controlled current source, refer to Figure 4 Provide explanation.

[0078] Figure 3Figure 2 shows a signal diagram for the proposed current-to-digital converter circuit. Each row plots a signal versus time t. The first row shows the master clock signal Sclk, the second row shows the current signal Ip, the third row shows the voltage signal Vout, the fourth row plots the binary result signal Scmp1, the fifth row plots the Dac step signal Scmp2, and the sixth row plots the charge clock signal Sckp. VDD represents the supply voltage, which is a high level in the case of binary signals, while zero volts is a low level.

[0079] The current signal Ip is integrated in the integrating amplifier and converted into a voltage signal Vout. This integration is reflected in the falling slope of the voltage signal Vout. At time t1, the voltage signal Vout crosses the level of the first reference voltage signal Vref1. With the arrival of the next pulse of the master clock signal Sclk, the output of the quantizer circuit Op2 switches, changing from low to high, which is reflected in the binary result signal Scmp1. At time t2, the digital-to-analog converter circuit Dac is triggered to inject the charge packet stored on the switched capacitor Cdac into the input of the integrating amplifier IAmp. This charge packet has a polarity opposite to that of the current signal Ip. Simultaneously, at time t2, the charge clock signal Ckp experiences a first level change—in this case, a rising edge. This closes the first switch S1 and causes the auxiliary current Iaux to be supplied to the output terminal 13 of the integrating amplifier IAmp. This causes the voltage signal Vout to quickly assume its starting level. At time t3, the charge clock signal Sckp experiences a second level change—in this case, a falling edge.

[0080] Refer to the following Figure 4 The details of generating the falling edge of the charging clock signal Sckp are explained.

[0081] Figure 4 Shows about Figure 2Signal diagram of a controlled current source. The following signals are plotted, from top to bottom, relative to time t: the Dac step signal Scmp2, the charging signal Sci, the end-of-charge signal Sco, and the charging clock signal Sckp. With the rising edge of the Dac step signal Scmp2 at time t2, the output of the first flip-flop FF1 becomes 1. Switch S4 opens via inverter Inv, and the auxiliary capacitor Caux begins integrating the bias current Ibias, as reflected in the charging signal Sci. Once the charging signal Sci reaches the value of the second reference voltage Vref2, the output of the third operational amplifier Op3 becomes 1, or high, as reflected in the end-of-charge signal Sco. This pulse clocks the second flip-flop FF2, causing its Q output to become 1. This causes the output of the AND gate to also become 1, resetting both the first and second flip-flops FF1 and FF2 via their reset inputs. This means that the charging signal Sckp reaches a falling edge at time t3.

[0082] Therefore, the charging clock signal Sckp is high or turned on for a time amount t, which is the difference between time point t3 and time point t2. The on-time period t can be calculated according to the following equation:

[0083] dT=Vref2*Caux / Ibias (1)

[0084] Wherein, dT represents the on-period t, Vref2 represents the second reference voltage signal Vref2, Caux represents the capacitance of the auxiliary capacitor Caux, and Ibias represents the bias current Ibias.

[0085] Therefore, when the first switch S1 is closed, the following charge amount Qaux is provided to the output terminal 13 of the integrating amplifier IAmp as the auxiliary current Iaux.

[0086] Qaux=Ibias*dT 2)

[0087] Substituting the first equation (1) into the second equation (2) yields:

[0088] Qaux=Vref2*Caux

[0089] It follows that the current-to-digital converter circuit is insensitive to variations in the bias current Ibias across process and temperature. Figure 3 As shown, the voltage step occurring in the voltage signal Vout at time point t2 can be calculated as follows:

[0090] Vstep=Vref2*Cdac / Cfb

[0091] Here, Cdac represents the capacitance of the switching capacitor Cdac, and Cfb represents the capacitance of the feedback capacitor Cfb.

[0092] The so-called capacitor ratio is well controlled, for example, with 0.1% accuracy (6 sigma matching) and reasonable capacitor sizes. This means that Vstep varies with the second reference voltage value Vref2 to first order and is well controlled. The charge at the output terminal 13 of the integrating amplifier IAmp is calculated according to the following equation:

[0093] Qout=Vref2*M*Ccmp

[0094] Where M is the average ratio of capacitances Cdac and Cfb, and Ccmp is the capacitance of the output capacitor Ccmp.

[0095] The auxiliary capacitor Caux is implemented by the same type as the output capacitor Ccmp, which achieves good mutual tracking of process temperature variations of equations 3 and 5. This means that the maximum amount of charge required at the output of the integrating amplifier IAmp is provided by the controlled current source CCS, and therefore the operational amplifier Op1 can be much slower, that is, a larger time constant Tau is achieved. Therefore, the entire proposed front-end circuit is independent of process and temperature variations to first order and is only limited by mismatch, which can usually be made very small. This effect refers to Figure 5A and Figure 5B Explain in more detail.

[0096] Figure 5A and Figure 5B The Dac step signal Scmp2 and the voltage signal Vout are shown respectively. Figure 5A In the example, a prior art implementation is used as the basis without a controlled current source CCS. This means that the voltage signal Vout only slowly recharges to its starting level. The Dac step signal Scmp2 lasts for L seconds. As can be seen, at the end of L seconds, the voltage signal Vout has not yet reached its initial level Vstep. This means that at the end of the Dac step signal Scmp2 cycle, a relatively high error still exists. This is because the operational amplifier must handle the entire settling process of the Dac pulse itself.

[0097] In contrast, Figure 5BThe proposed current-to-digital converter circuit features a controlled current source to help the integrating amplifier stabilize the pulses of the Dac step signal Scmp2. During the on-time of the charging clock signal Sckp, the controlled current source CCS provides an auxiliary current Iaux to charge the output of the integrating amplifier IAmp. Consequently, the voltage step at the voltage signal Vout has a high steepness, which allows the output to recharge quickly. As can be seen from the figure, the time T is very small, for example, only 5% of the time Ls, leaving 95% of the clock cycle to provide the remaining charge to the output terminal 13. Only a small difference d remains between the starting level Vstep and the voltage level reached at time t3. This difference d is determined by the operational amplifier Op1. As can be seen, sufficient time is left for this, and at the end of the pulse of the Dac step signal Scmp2 at time t4, the error is still very low, or even absent.

[0098] The second reference voltage Vref2 and the bias current Ibias are adjusted so that the on-time t of the charging clock signal Sckp is much shorter than the on-time of the Dac step signal Scmp2 between the time points t2 and t4.

[0099] Figure 6 Another embodiment example of the proposed optical front-end circuit is shown. This embodiment is basically the same as Figure 1 The following only explains Figure 1 Examples and Figure 6 The differences between the embodiments. Figure 6 In FIG, quantizer circuit Op2 is implemented as an M-bit clocked quantizer, where M is an integer greater than or equal to 2. A first reference voltage Vref1 having a level of 2 to the power of M minus 1 is supplied for flash memory implementation. Thus, the binary result signal Scmp1 and the Dac step signal Scmp2 are provided with M bits. The operational amplifier Op1 of the integrating amplifier IAmp is implemented by two stages gm1 and gm2. Each stage of gm1 and gm2 includes an operational amplifier. An auxiliary current Iaux from a controlled current source CCS is supplied to the output of the first stage gm1 via a first switch S1. This facilitates faster recharging of the output 13 of the integrating amplifier IAmp. The first switch S1 is controlled by a charging clock signal Sckp, which in this case has M bits. The number of bits of the resulting digital word signal Sw corresponds to the sum of M and N.

[0100] In another exemplary embodiment, Figure 6 The clock quantizer implemented by Op2 in can be implemented in different ways known to those skilled in the art.

[0101] Figure 7An example of an implementation of an operational amplifier for an integrating amplifier is shown. Figure 1 or Figure 6 The embodiment depicted in FIG. 1 is used together to implement an operational amplifier Op1. The depicted circuit shows a folded cascode as defined in the claims. The folded cascode includes transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16. The folded cascode is connected, on the one hand, to a power supply potential terminal 11, at which a power supply potential, such as Vdd, is provided, and, on the other hand, to a reference potential terminal 10, at which a reference potential, such as ground, is provided. In addition to the conventional folded cascode, the depicted circuit includes transistors T9 and T10, each implemented as a PMOS transistor that implements a folded node. Nodes 21 and 22 represent the drain nodes of the input pair of the operational amplifier Op1. The current source itself represents the input pair, which can be viewed as converting a voltage into a current. On the left, the input pair, whose gates are connected to the inverting input of the operational amplifier, is represented by a current source supplying a positive current +I. Connection points 19 and 20 represent the common source node of the input pair, which is at the differential ground potential. On the right, the input pair, with its gate connected to the non-inverting input terminal of operational amplifier Op1, is depicted as a current source providing a negative current -I. Transistors T1 and T2 are connected as a cascode to the drain node 19 of the non-inverting input terminal. Similarly, transistors T4 and T5 are connected as a cascode to the drain terminal 20 of the inverting input terminal. Transistors T6 and T7 are connected as a current mirror for a negative current -I. Similarly, transistors T3 and T8 are connected as a current mirror for a positive current +I. Folding node transistor T9 has its source terminal connected to the drain terminal of transistor T1. The drain terminal of transistor T9 is connected to the drain terminal of transistor T7. The gate terminal of transistor T9 is connected to the gate terminals of transistors T11 and T12. On the right, folding node transistor T10 has its source terminal connected to the drain terminal of transistor T4. The drain terminal of transistor T10 is connected to the drain terminal of transistor T8. The gate terminal of the transistor T10 is connected to the gate terminals of the transistors T14 and T15 .

[0102] The gate terminal of transistor T7 is connected to the gate and drain terminals of transistor T6. The gate terminal of transistor T8 is connected to the gate and drain terminals of transistor T3.

[0103] Transistor T7 biases transistors T9 and T12, while transistor T8 biases transistors T14 and T10. A current with the same polarity from the other branch is used to bias the folding node. For example, the current flowing through transistor T6, which amounts to –I / 2, is mirrored to transistor T7 and used to bias transistors T9 and T12. In low-power and high-performance applications, it is necessary to bias the input pair at very high bias currents while keeping the currents in the other branches of the op amp low. Figure 7 In the example, the maximum values of the positive current +I and the negative current -I can be in the order of hundreds of microamperes to milliamperes to achieve high performance, while the bias currents in the remaining branches may be only a few microamperes. However, without using the above technique, that is, using transistor T7 with its gate connected to transistor T6 to bias the folding node of transistors T12 and T9, and using transistor T8 with its gate connected to transistor T3 to bias the folding node transistors T14 and T10, for the same power, this usually results in poor slewing / linearity performance. Using Figure 7 The proposed circuit achieves low-voltage, low-power, and high-performance operation. For example, four times the saturation voltage is required in transistors T1, T2, T3, and T12 on the left, and one threshold voltage of the gate-source voltage is required in transistor T9. In summary, operating the proposed folded cascode requires one threshold voltage and four times the saturation voltage. Compared to the prior art folded cascode, this saves at least one threshold voltage. Therefore, headroom constraints can be better met.

[0104] Compared with the prior art implementation, the proposed folded cascode is used to implement Figure 1 or Figure 6 When the op amp Opa1 is used, the resulting solution requires at least four times less power to achieve the same noise and linearity for the optical front-end circuit. For example, the proposed solution only requires an analog ground voltage of 0.9V, compared to 1.8V for conventional solutions. This solution thus exceeds the kT / C limit.

[0105] Furthermore, in the described embodiments, power is saved and the chip area required is only about one-quarter or less of conventional implementations if the same noise performance is achieved.

[0106] Figure 8 An embodiment example of a computed tomography apparatus is shown. The computed tomography apparatus CTA includes an optical front-end circuit OFE. The optical front-end circuit OFE is implemented in the form of one of the above-described embodiments.

[0107] It should be understood that any feature described with respect to any embodiment may be used alone or in combination with other features described, and may also be used in combination with one or more features of any other embodiment, or in combination with any other embodiment, unless described as an alternative. In addition, equivalents and modifications not described above may also be employed without departing from the scope of the current-to-digital converter circuit, optical front-end circuit, computed tomography apparatus, and method for providing an output voltage as defined in the appended claims.

[0108] Reference Signs List

[0109] 10 Reference potential terminal

[0110] 11 Power supply potential terminal

[0111] 12 Input terminals

[0112] 13, 14, 17 output terminals

[0113] 15, 16 terminals

[0114] 18, 19, 20, 21, 22 connection points

[0115] PD Photodiode

[0116] IAmp Integrating Amplifier

[0117] Inv Inverter

[0118] Ip current signal

[0119] Cfb, Caux, Cdac, Cs capacitors

[0120] Ccmp capacitor

[0121] Op1, Op3 operational amplifiers

[0122] Op2 quantizer circuit

[0123] Vout voltage signal

[0124] CCS Controlled Current Source

[0125] S1, S2, S3, S4 switches

[0126] Sa, Sb, Sc, Sd switches

[0127] Sclk, Sckp, Scks, Sckc clock signals

[0128] CTL control circuit

[0129] Vre1, Vref1 reference voltage signal

[0130] VF Voltage Follower

[0131] Scmp1, Scmp2, Sn, Sw signals

[0132] Iaux, Ibias currents

[0133] CAL calculation circuit

[0134] Ad ADC circuit

[0135] Dac digital-to-analog converter circuit

[0136] DF decimation filter

[0137] Fx digital function

[0138] Cmb combinator

[0139] Fcds CDS logic circuit

[0140] GM1 and GM2 levels

[0141] G AND gate

[0142] Sci, Sco signal

[0143] FF1, FF2 flip-flops

[0144] CM Current Mirror Component

[0145] Time points t1, t2, t3, and t4

[0146] T1, T2, ...Tx transistors

[0147] CTA Computed Tomography

[0148] OFE optical front-end circuit

Claims

1. A current-to-digital converter circuit comprising: an integrating amplifier (IAmp) having an input (12) adapted to receive a current signal (Ip) and an output (13) adapted to provide a voltage signal (Vout) which is a function of the integral of the current signal (Ip), a quantizer circuit (Op2) having an input coupled to an output (13) of an integrating amplifier (IAmp) and an output (14) adapted to provide a binary result signal (Scmp1) which is a function of a comparison of the voltage signal (Vout) with at least a first reference voltage signal (Vref1), a digital-to-analog converter circuit (Dac) switchably coupled to an input terminal (12) of an integrating amplifier (IAmp) in accordance with the binary result signal (Scmp1), a controlled current source (CCS) coupled to the output terminal (13) of the integrating amplifier (IAmp) via a first switch (S1), the first switch being controlled in accordance with the binary result signal (Scmp1) to supply an auxiliary current (Iaux) to the output terminal (13) of the integrating amplifier (IAmp), and The auxiliary current (Iaux) is supplied when the binary result signal (Scmp1) is pulsed, and for an amount of time that is less than a time constant implemented by the integrating amplifier (IAmp).

2. The current-to-digital converter circuit according to claim 1, wherein: The controlled current source (CCS) comprises a current generating unit (CGU) and a timing generating unit (TGU), wherein the timing generating unit (TGU) is configured to provide a charging clock signal (Sckp), wherein a first level change of the charging clock signal (Sckp) is generated when a level change occurs in the binary result signal (Scmp1), and a second level change of the charging clock signal (Sckp) is generated once charging of an auxiliary capacitor (Caux) included in the timing generating unit (TGU) by means of a bias current (Ibias) reaches the level of a second reference voltage (Vref2), and The current generating unit (CGU) is intended to provide the auxiliary current (Iaux), and comprises a current mirror component (Tx) for mirroring the bias current (Ibias) or an adjustable resistor connected to a power supply potential (11).

3. The current-to-digital converter circuit according to claim 1 or 2, further comprising a control unit (CTL) arranged to provide a master clock signal (Sclk) for controlling the operation of at least the quantizer circuit (Op2).

4. The current-to-digital converter circuit according to claim 1 or 2, wherein: The integrating amplifier (IAmp) comprises an operational amplifier (Op1) and an integrating capacitor (Cfb), wherein the integrating capacitor is coupled in a feedback loop of the operational amplifier (Op1) and is located between an output terminal (13) and an inverting input terminal (12) of the operational amplifier, wherein the operational amplifier (Op1) is implemented by a folded cascode (Ty), wherein each folding node of the folded cascode is implemented by a transistor.

5. The current-to-digital converter circuit according to claim 4, wherein: The operational amplifier (Op1) is implemented by two or more stages (gm1, gm2).

6. The current-to-digital converter circuit according to claim 1 or 2, wherein: The digital-to-analog converter circuit (Dac) is implemented as a single-bit digital-to-analog converter based on switched capacitors (Cdac), which are additionally connected in a switchable manner to respective terminals (15, 16) for supplying a third reference voltage (Vref3).

7. The current-to-digital converter circuit according to claim 1 or 2, wherein: The digital-to-analog converter circuit (Dac) is implemented as an M-bit digital-to-analog converter based on a plurality of capacitors, where M is an integer greater than or equal to 2.

8. The current-to-digital converter circuit according to claim 6, wherein: The quantizer circuit (Op2) is implemented as an exactly one-bit clocked comparator amplifier.

9. The current-to-digital converter circuit according to claim 7, wherein: The quantizer circuit (Op2) is implemented as an M-bit clocked quantizer.

10. An optical front-end circuit, comprising: The current-to-digital converter circuit according to any one of claims 3 to 9, wherein the current signal (Ip) at the input (12) of the integrating amplifier (IAmp) comprises a photocurrent of a photodiode (PD) connectable to said input (12), a sampling capacitor (Cs) coupled to the output terminal (13) of the integrating amplifier (IAmp) via a second switch (S2) controlled by a sampling clock signal (Scks), an analog-to-digital converter (ADC) circuit (Ad) coupled via its input to a sampling capacitor (Cs) via a third switch (S3), the third switch (S3) being controlled by a conversion clock signal (Sckc), the ADC circuit (Ad) having an output (17) at which a digital signal (Sn) is provided, wherein the digital signal (Sn) varies with the current signal (Ip) and comprises N bits, wherein N is an integer greater than or equal to 1, and A calculation circuit (CAL) coupled to an output (17) of the ADC circuit (Ad) and to an output of the quantizer circuit (Op2), said calculation circuit (CAL) being intended to provide a digital word signal (Sw) by combining a binary result signal (Scmp1) with a digital signal (Sn).

11. The optical front-end circuit according to claim 10, wherein: The control unit (CTL) is configured to provide a sampling clock signal (Scks) and a conversion clock signal (Sckc) based on a main clock signal (Sclk), a sampling clock signal (Scks), and a conversion clock signal (Sckc) having different clock rates or substantially equal clock rates.

12. The optical front-end circuit according to claim 10 or 11, wherein: The calculation circuit (CAL) is intended to provide the digital word signal (Sw) as correlated double samples.

13. A computed tomography apparatus (CTA) having the optical front-end circuit (OFE) according to claim 10 or 11.

14. A method for providing an output voltage (Vout), the method comprising at least the following steps: Supply current signal (Ip), The current signal (Ip) is converted into a voltage signal (Vout) by means of charge integration in an integrating amplifier (IAmp), quantizing the voltage signal (Vout) and thereby providing a binary result signal (Scpm1) having at least one bit, providing an auxiliary current (Iaux) to the output of the integrating amplifier (IAmp) substantially simultaneously with the provision of the binary result signal (Scmp1) for recharging said output and adding an additional charge to the current signal (Ip) in accordance with the binary result signal (Scmp1), and The auxiliary current (Iaux) is supplied when the binary result signal (Scmp1) is pulsed, and for an amount of time that is less than a time constant implemented by the integrating amplifier (IAmp).

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