A general-purpose gate-level logic modeling method for aerospace applications for formal verification

Abstract

A general-purpose aerospace gate-level logic modeling method for formal verification analyzes and models the radiation-resistant redundancy characteristics of radiation-hardened logic gate circuits of aerospace-grade large-scale integrated circuits. Based on the model, formal verification-based safety property evaluation and logic integrity check can be performed on aerospace-grade large-scale integrated circuits, solving the problem of safety property evaluation of aerospace large-scale integrated circuits under space radiation environment and high-reliability application conditions of spacecraft. It is easy to operate, highly automated, and highly efficient in evaluation, which reduces the operational links of the evaluation and improves the operability of the evaluation.

Description

Technical Field

[0001] The invention relates to an aerospace general-purpose gate-level logic modeling method for formal verification, and belongs to the field of spacecraft control software evaluation. Background Art

[0002] Logic units are the basic units that make up space-grade VLSI. Through the safety performance evaluation of space-grade VLSI based on logic models, the discovery, evaluation and improvement of incomplete logic design, logic loopholes and even design backdoors can be completed, avoiding the cycle of solving problems after tape-out and the tape-out cost. In order to ensure the safe and reliable on-orbit application of space-grade VLSI, it is necessary to model the logic model and measure and evaluate the device safety attributes based on this model.

[0003] Large-scale integrated circuits used in spacecraft are the core components of spacecraft, and their security threatens the reliable operation of space-based defense facilities. The logic models currently used in formal verification and evaluation in the financial and cryptographic fields cannot fully characterize the radiation resistance and application conditions of aerospace integrated circuits. Summary of the invention

[0004] The technical problem solved by the present invention is: in view of the problem that the traditional logic model used for formal verification in the current prior art cannot meet the evaluation and use requirements of aerospace-grade integrated circuits, a general aerospace gate-level logic modeling method for formal verification is proposed.

[0005] The present invention solves the above technical problems by the following technical solutions:

[0006] A general aerospace gate-level logic modeling method for formal verification, the steps are as follows:

[0007] (1) Sorting out and analyzing the radiation hardening strategies of the space-grade LSIs to be verified, and obtaining the typical characteristics of the logic gates of the space-grade LSIs;

[0008] (2) Based on the typical characteristics of the aerospace-grade large-scale integrated circuit logic gates and the aerospace environmental pollution labels obtained in step (1), a sorting and analysis is performed to obtain a fault truth table;

[0009] (3) Based on the obtained fault truth table, perform logic simplification and perform logic gate modeling based on EDA compatible language;

[0010] (4) Obtain logic gate models and perform simulation tests on the normal functions of commonly used aerospace-grade large-scale integrated circuits;

[0011] (5) judging based on the simulation test results, if the logic gate model has an impact on the normal function of the aerospace-grade large-scale integrated circuit, modifying and modulating the logic gate model until the logic gate model has no impact on the normal function of the aerospace-grade large-scale integrated circuit; otherwise, troubleshooting the aerospace-grade large-scale integrated circuit;

[0012] (6) Use external simulation tools to simulate and traverse the logic gate model and troubleshoot the number of faults, and compare the number of faults with the aerospace-grade large-scale integrated circuit itself;

[0013] (7) Obtaining the fault number comparison result, if the consistency is greater than the specified standard, the logic gate model accuracy meets the requirement, and proceeding to step (8); if the consistency is not greater than the specified standard, modifying and modulating the logic gate model until the fault number comparison result consistency is greater than the specified standard;

[0014] (8) Formal verification-based safety property evaluation of space-grade large-scale integrated circuits based on logic gate models.

[0015] In the step (2), the fault truth table includes logic variables, logic functions, contamination labels, and contamination tracking functions of aerospace-grade large-scale integrated circuits, and the contamination tracking functions are constructed based on fixed fault propagation models, random fault propagation models, or bit flip fault propagation models.

[0016] In the step (3), the logic is simplified to be based on the fault truth table data, and the ABC, SIS, and ESPRESSO tools can be used to complete the simplest logical representation.

[0017] In the step (4), the commonly used aerospace-grade large-scale integrated circuits can be replaced by aerospace-grade integrated circuits of various sizes.

[0018] In step (1), the aerospace environment includes a bit flip failure mode caused by extreme temperature or space radiation conditions.

[0019] In step (7), the specified standard for consistency of the fault number comparison result is 95%.

[0020] The advantages of the present invention compared with the prior art are:

[0021] The present invention provides a general-purpose aerospace gate-level logic modeling method for formal verification. Through the analysis and research on the characteristics of logic gate-level circuits used in aerospace-grade integrated circuits and the aerospace radiation resistance application conditions, the formed logic model can be used for safety attribute analysis of integrated circuits used in spacecraft, fully ensuring its safety and adaptability in the space environment, and fully ensuring the safety and reliability of aerospace-grade large-scale integrated circuits in a system integration environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of aerospace general-purpose gate-level logic modeling flow based on formal verification provided for the invention;

[0023] Figure 2 Binary truth representation of pollution labels for aerospace applications provided for the invention;

[0024] Figure 3 A Verilog-based logic gate-level modeling schematic diagram provided for the invention;

[0025] Figure 4 A schematic diagram of simulation results of typical circuit fault numbers provided for the invention; DETAILED DESCRIPTION

[0026] A general-purpose aerospace gate-level logic modeling method for formal verification is used to solve the problem of integrated circuit safety attribute evaluation under space radiation environment and high-reliability application conditions of spacecraft. The specific method steps are as follows:

[0027] (1) Sorting out and analyzing the radiation hardening strategies of the space-grade LSIs to be verified, and obtaining the typical characteristics of the logic gates of the space-grade LSIs;

[0028] Among them, the aerospace environment includes bit flip failure modes caused by extreme temperatures or space radiation conditions;

[0029] (2) Based on the typical characteristics of the aerospace-grade large-scale integrated circuit logic gates and the aerospace environmental pollution labels obtained in step (1), a sorting and analysis is performed to obtain a fault truth table;

[0030] The fault truth table includes logic variables, logic functions, pollution labels, and pollution tracking functions of aerospace-grade large-scale integrated circuits. The pollution tracking functions should be constructed based on fixed fault propagation models, random fault propagation models, or bit flip fault propagation models, respectively.

[0031] (3) Based on the obtained fault truth table, perform logic simplification and perform logic gate modeling based on EDA compatible language;

[0032] Among them, the logic is simplified to be based on the fault truth table data, and ABC, SIS, and ESPRESSO tools can be used to complete the simplest logical representation.

[0033] (4) Obtain logic gate models and perform simulation tests on the normal functions of commonly used aerospace-grade large-scale integrated circuits;

[0034] Among them, the commonly used aerospace-grade large-scale integrated circuits can be replaced with aerospace-grade integrated circuits of various sizes;

[0035] (5) judging based on the simulation test results, if the logic gate model has an impact on the normal function of the aerospace-grade large-scale integrated circuit, modifying and modulating the logic gate model until the logic gate model has no impact on the normal function of the aerospace-grade large-scale integrated circuit; otherwise, troubleshooting the aerospace-grade large-scale integrated circuit;

[0036] (6) Use external simulation tools to simulate and traverse the logic gate model and troubleshoot the number of faults, and compare the number of faults with the aerospace-grade large-scale integrated circuit itself;

[0037] (7) Obtaining the fault number comparison result, if the consistency is greater than the specified standard, the logic gate model accuracy meets the requirement, and proceeding to step (8); if the consistency is not greater than the specified standard, modifying and modulating the logic gate model until the fault number comparison result consistency is greater than the specified standard;

[0038] Among them, the specified standard for the consistency of the fault number comparison results is 95%;

[0039] (8) Formal verification-based safety property evaluation of space-grade large-scale integrated circuits based on logic gate models.

[0040] The following is further described based on specific embodiments:

[0041] In the current embodiment, if Figure 1 As shown in the figure, the aerospace general gate-level logic modeling method for formal verification has the following specific steps:

[0042] (1) Obtain typical characteristics of space-grade LSI logic gates, specifically:

[0043] Taking the two-input XOR gate logic for aerospace as an example, the two inputs may cause input logic flipping due to threshold voltage offset or single particle upset, which are typical characteristics of aerospace-grade large-scale integrated circuit logic gates;

[0044] (2) Based on the typical characteristics of the space-grade large-scale integrated circuit logic gates obtained in step (1) and the pollution labels that may be caused by the space environment, a fault truth table is formed;

[0045] The fault truth table including the above pollution labels is as follows Figure 2 As shown;

[0046] (3) According to the fault truth table obtained in step (2), the logic is simplified based on the bit flip fault propagation model, and the logic gate modeling is performed based on the Verilog language. The modeling file is as follows: Figure 3 As shown, where:

[0047]

[0048] In the formula, the parameters are added at the end;

[0049] (4) Based on the logic gate model formed in step (3), a simulation test is performed on the normal function of the typical circuit;

[0050] (5) The results show that the circuit functions correctly, proving that the logic model does not affect the normal function of the circuit;

[0051] (6) Select a large-scale typical circuit from the IWIS circuit library, and synthesize it in the Synopsys tool based on the logic gate model obtained in step (3). Use the Modelsim tool to check the number of faults in the synthesized netlist and compare it with the number of faults in the typical circuit itself. The simulation results are as follows: Figure 4 As shown;

[0052] (7) Figure 4 The simulation results shown show that the total number of faults is 32'h832c8a06. Compared with the typical circuit's own fault number 32'585v356h2v0, the comparison accuracy is greater than 98%, indicating that the accuracy of the model can meet the simulation requirements of formal verification safety property troubleshooting.

[0053] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0054] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A general-purpose aerospace gate-level logic modeling method for formal verification, characterized in that Here are the steps: (1) To analyze and sort out the radiation hardening strategies of the space-grade LSIs to be verified, and obtain the typical characteristics of the logic gates of the space-grade LSIs; (2) Based on the typical characteristics of the aerospace-grade large-scale integrated circuit logic gates and the aerospace environmental pollution labels obtained in step (1), a sorting and analysis is performed to obtain a fault truth table; (3) Based on the obtained fault truth table, perform logic simplification and perform logic gate modeling based on EDA compatible language; (4) Obtain logic gate models and perform simulation tests on the normal functions of commonly used aerospace-grade large-scale integrated circuits; (5) judging based on the simulation test results, if the logic gate model has an impact on the normal function of the aerospace-grade large-scale integrated circuit, modifying and modulating the logic gate model until the logic gate model has no impact on the normal function of the aerospace-grade large-scale integrated circuit; otherwise, troubleshooting the aerospace-grade large-scale integrated circuit; (6) Use external simulation tools to simulate and traverse the logic gate model and troubleshoot the number of faults, and compare the number of faults with the aerospace-grade large-scale integrated circuit itself; (7) Obtaining the fault number comparison result, if the consistency is greater than the specified standard, the logic gate model accuracy meets the requirement, and proceeding to step (8); if the consistency is not greater than the specified standard, modifying and modulating the logic gate model until the fault number comparison result consistency is greater than the specified standard; (8) Formal verification-based safety property evaluation of space-grade large-scale integrated circuits based on logic gate models; In step (1), the aerospace environment includes a bit flip failure mode caused by extreme temperature or space radiation conditions; In the step (2), the fault truth table includes logic variables, logic functions, contamination labels, and contamination tracking functions of aerospace-grade large-scale integrated circuits, and the contamination tracking functions are constructed based on a fixed fault propagation model, a random fault propagation model, or a bit flip fault propagation model. In the step (3), the logic is simplified to complete the simplest logical representation based on the fault truth table data by using any one of ABC, SIS, and ESPRESSO tools; In the step (4), the commonly used aerospace-grade large-scale integrated circuits can be replaced with aerospace-grade integrated circuits of various sizes; In step (7), the specified standard for consistency of the fault number comparison result is 95%.

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