A UVM-based FPGA simulation verification system for AOS data processing

Abstract

The present invention provides an AOS data processing FPGA simulation verification system based on UVM. By constructing an AOS data processing FPGA simulation verification system based on UVM, test input randomization and constraint automatic convergence are realized, and at the same time, the EPDU number coverage, header position coverage, tail position coverage, and padding packet and padding frame transmission coverage in the MPDU packet domain are collected in real time, and functional coverage statistics are realized in an all-round way. In addition, the present invention obtains the expected data EXP stack and the measured data ACT stack in real time through a scoreboard group, and performs automatic consistency matching, and gives the error frame reception and missing frame situation, which greatly facilitates the designer to locate the fault. Finally, the present invention also provides versatility by maximizing the number of channels n. By changing the number of channels n and changing the MPDU proportion of the corresponding channel according to the rate modification constraint, the AOS data processing FPGA simulation verification of any multiple channels can be realized, and the FPGA ground simulation verification of the AOS data processing system of various aerospace models can be expanded and applied.

Description

Technical Field

[0001] The present invention discloses a full digital simulation verification system of an AOS data processing FPGA built based on UVM verification methodology. Background Art

[0002] The AOS data processing FPGA is used to receive the transmission frames sent by the relay terminal, synchronize, derandomize, and RS decode the transmission frames, unpack the data stream according to the CCSDS AOS protocol and the IP OVER CCSDS protocol, and finally send the remote control data, video and voice data, and network data to the designated user through their respective output interfaces according to the established transmission protocol based on the identifier in the transmission frame.

[0003] First of all, AOS data processing FPGA is widely used as a data processing and forwarding device for space stations, free-flying vehicles, deep space probes and space transmission systems. It realizes multiple types of data transmission at different rates in the entire space link (star-to-ground, ground-to-star, star-to-star). The CCSDS protocol transmission frame generation method includes periodic generation and burst generation. The channel data rate forwarded by AOS data processing FPGA to each user varies from hundreds of Kbps to several Gbps. Therefore, when various types of data are interspersed in the same channel, AOS data processing FPGA should be able to effectively and timely process the forwarded data without causing AOS to crash.

[0004] Secondly, the CCSDS protocol transmission frame protocol is relatively complex. A complete CCSDS protocol transmission frame includes synchronization word + version number + spacecraft identifier SCID + virtual channel identifier VCID + virtual channel frame count + signaling field + transmission frame data field (886Byte) + RS check (128Byte). The spacecraft identifier SCID + virtual channel identifier VCID is used to distinguish which channel the data belongs to, so as to determine which user it should be forwarded to. The transmission frame data field uses multi-channel protocol data unit (MPDU) to transmit IP packets, and its frame format is: MPDU header pointer + MPDU packet field. The MPDU packet field is composed of any valid protocol data subunit (EPDU) packets. The header pointer directly points to the starting position of the first EPDU packet. The EPDU packet is divided into valid data frame EPDU and padding frame EPDU. The format of valid data frame EPDU is valid data frame EPDU frame header (6 bytes) + packet length (2 bytes) + data, and the format of padding frame EPDU is padding frame EPDU frame header (1 byte) + data (indefinite length). The data length of the valid data frame EPDU and the padding frame EPDU is uncertain, and may exceed one or even several MPDU packet fields. It is also possible that one MPDU packet field has multiple EPDUs. The second half of the last EPDU may be in the next MPDU packet field, or the second half of the EPDU frame header may be in the next MPDU packet field, or the second byte of the EPDU packet length may be in the next MPDU packet field.

[0005] Traditional ground hardware joint testing can only periodically generate certain specific expected CCSDS protocol data, and cannot randomly generate bursts of EPDU data packets of indefinite length, let alone ensure coverage of various MPDU packet domains. This often leads to missed design defects and changes in system indicators or overall system concessions to reception, which may seriously lead to system mission failure.

[0006] Finally, the transmission frame formats of the MPDU packet fields of each channel are different, which leads to different formats of the corresponding sub-packets EPDU. For example, the forwarding speed of the remote control data packet is much slower than that of the Ethernet master control data packet. The traditional test method can only rely on manual or periodic control of the sending interval of the MPDU frames of each channel, which cannot effectively guarantee the continuity of the test data and the test pressure. Summary of the invention

[0007] The object of the present invention is to provide a fully digital simulation verification system of AOS data processing FPGA built based on UVM verification methodology, so as to solve the problem that the packet service, bit stream service, virtual channel access service, virtual channel frame service, main channel service, main channel frame service and insertion service of the payload in the existing large-scale spacecraft product engineering only adopt one main channel data processing mechanism on the same space physical channel. In addition, the simulation system also includes a data model automatic comparison module and a data structure feature monitoring module. In particular, it is necessary to solve the data type structure that is difficult to generate randomness in hardware joint testing and the coverage statistics that cannot be performed on the EPDU data packet length in the frame structure, the location of the header and tail pointer.

[0008] To achieve the above object, the present invention provides a fully digital simulation verification system for AOS data processing FPGA built based on UVM verification methodology, which is used to provide a closed-loop working environment for AOS data processing FPGA, and the indefinite working conditions of EPDU data packet length, header and tail position in MPDU that cannot be achieved by AOS data processor in ground hardware joint testing, specifically including:

[0009] The AOS data generation module is used to generate EPDU subframes according to the EPDU frame format from the EPDU transactions epdu_transaction of n channels, where the packet length and data are random values, and send them to the mpdu_transaction queue. The mpdu_transaction combines the MPDU packet domain according to the remaining packet length of the previous insertion and the current packet length, and randomly inserts the data packets and random arrays generated by the queue into the AOS data agent module Aos_agent through the AOS transaction module Aos_Transaction. In the AOS data agent module Aos_agent, the AOS data queue generator Aos_sequencer generates a random queue, and transmits the data to the RS interleaving encoding module through the AOS data input driver Aos_driver; at the same time, mpdu_transaction processes the epdu_transaction according to the forwarding data format to obtain the data length and data, and converts them into the expected ip_transaction_r stack.

[0010] The RS interleaving encoding module uses the RS (255, 223) format for encoding, with an interleaving depth of 4. The RS encoding IP core that comes with XILINX is called to interleave the data transmitted by Aos_driver;

[0011] The scrambling C program scrambles the array generated after RS ​​interleaving encoding in C code through the DPI interface provided by the simulator;

[0012] The relay data generation module is used to add the scrambled data to the synchronization frame header, and convert the parallel data into serial data on the rising edge of the forward clock and output it to the FPGA as input stimulus;

[0013] A monitoring module group is used to receive data, clock and gating signals output by the AOS data processing FPGA to obtain a measured ip_transaction_r data stack;

[0014] The scoreboard group is used to compare the data packets of the ip_transaction_r data stack of the corresponding channel actually received and measured with the data packets of the ip_transaction_r data stack of the expected channel in real time for consistency matching. If the match is successful, the matching consistency information is given and the number is compared. If the number is inconsistent, the missing frame information is given; if the match is inconsistent, the expected and actually received data packets are printed out to the user for fault location;

[0015] Preferably, in order to quickly realize automatic comparison of data, the ip_transaction_r structure is defined as 16-bit packet length + data according to the AOS data processing FPGA forwarding data format.

[0016] Preferably, in order to cover various working conditions where the number of valid data packets, data packet length, header position and tail position of EPDU in MPDU are uncertain, the AOS-like data generation module applies UVM advanced verification methodology, first defines the format of valid data frame EPDU as valid data frame EPDU header (6 bytes) + packet length (2 bytes) + data, designs constraints for the packet length, and then sets the length of the data area data according to the constrained packet length. Then the data and data length of EPDU are transferred to ip_transaction_r and put into the expected data stack. Then the parameters defined by MPDU generation include synchronization word, first header pointer First_frame_pointer, data pre_end remaining in the previous EPDU, and number of data pre_leave_size remaining in the previous packet. Each time a new MPDU is created, pre_leave_size is first determined. If it is equal to 0, the first header pointer First_frame_pointer=0; if pre_leave_size is greater than 883, the first header pointer First_frame_pointer=11'h7ff; otherwise, the first header pointer First_frame_pointer=pre_leave_size. By collecting First_frame_pointer at the end of MPDU generation, the header position of the first EPDU of each MPDU can be known. In this way, all situations of EPDU header position can be covered at the end of MPDU generation. When the first header pointer coverage is "11'h7ff" (excluding header), "11'h7fe" (excluding valid data), 0, 1, 2, 3~50, 50~100, 100~150, 150~200, 200~208, 209, 210, 211, 212, 213, 214 (where 209~214 belong to the case of EPDU header segmentation), it is considered that all possible header positions are covered, reaching 100% coverage of the header position. Similarly, every time an EPDU function less than one frame is generated, the current EPDU tail pointer ip_tail_pointer_beat_g = pre_leave_size will be recorded after processing. At this time, it indicates the number of bytes that have been processed.At the end of MPDU generation, by collecting ip_tail_pointer_beat_g, all situations of the EPDU tail position can be covered. When the tail pointer covers 0, 1, 2, 3~50, 50~100, 100~150, 150~200, 200~250, 250~300, 350~400, 400~450, 450~500, 550~600, 600~650, 700~750, 750~800, 800~850, 850~877, 878~883, 884 respectively, it is considered that all possible positions of the tail are covered, reaching 100% coverage of the tail position.

[0017] Preferably, in order to detect how many EPDU packets are contained in an MPDU packet, the AOS-like data generation module sets and records the normal EPDU counter ip_num_epdu_beat_g, and the initial value is 0 when generating an MPDU packet. Whenever a new EPDU is created, ip_num_epdu_beat_g is counted. At the end of MPDU generation, by collecting ip_num_epdu_beat_g, a MPDU can be included in several EPDU function coverage statistics. When the number of EPDUs covers 0, 1, 2, 3, [4, +∞) 5 cases, it is considered that the number of EPDUs covers all cases.

[0018] Preferably, in order to cover the padding data contained in the MPDU packet and the non-padding data, the AOS-like data generation module sets the padding data identifier redundant_flag, and the power-on reset initial value is 0. When it is determined that the number of remaining data is less than 884, that is, when the current MPDU can fit the remaining data of the previous EPDU, a random number is generated, and the random number is taken as a remainder of 6. When the remainder is 0, the padding data packet is inserted, and the padding data identifier redundant_flag is set to 1. Collecting the value of redundant_flag can cover whether the padding data is inserted. Similarly, in order to cover the padding frame and data valid frame coverage, a call padding frame identifier is set, and the power-on reset initial value is 0. When the padding frame function is called, is_ip_redunt_frame_g is inverted. Collecting the value of is_ip_redunt_frame_g can cover whether the padding frame is generated, covering the MPDU padding frame and MPDU data valid frame.

[0019] Preferably, since the clock rates output to each channel after the AOS data processing FPGA is parsed are different, but the internal processing methods are completely consistent, according to the equivalence principle, as long as there is a channel with comprehensive coverage, all hidden dangers can be discovered. In order to achieve automatic constraint convergence, the AOS-like data generation module imposes specific constraints on the virtual channel identifier VCID, and constrains it according to the speed. The faster the rate, the greater the proportion of the channel, the filler frame VCID and the faster rate channel have the same proportion, and the slower the rate, the lower the proportion of the channel. This can improve the test efficiency, so that the functional coverage reaches 100% as soon as possible, and the simulation test will not diverge endlessly.

[0020] Preferably, the monitoring module group sets a global port ap_ip of ip_transaction_r for each channel, and when a complete data frame is received according to the number of data when the gating is effective, it is packaged into ip_transaction_r and written into port ap_ip.

[0021] Preferably, when the AOS-like data generation module calls the function to generate a new EPDU, each time an EPDU packet is passed, it triggers the one-time transmission of multiple epdu packets in epdu_ip_inst_g to the event event_epdu_ip_g. In the scoreboard group, when event_epdu_ip_g is triggered, the EPDU packet generated by the corresponding channel is converted into ip_transaction_r and pushed into the expected stack of the corresponding channel, and the expected number is counted at the same time. In addition, the scoreboard group designs a comparison data function, obtains the measured ip_transaction_r from the global port ap_ip, counts the actual number of receptions, obtains the current expected ip_transaction_r in order in the expected stack, and then performs consistency matching. When a matching expected ip_transaction_r is found, comparison consistency information is given, and the expected ip_transaction_r in the expected stack is deleted. If the match is not the first ip_transaction_r in the stack, it means that there is a missing frame, and an error alarm of lost epdu data packets is printed, and the result of lost epdu data packets is given; if a matching expected ip_transaction_r cannot be found, an error alarm is issued, and the expected result and the measured result are given respectively.

[0022] The present invention has the following beneficial effects:

[0023] 1) AOS data processing FPGA has uncertain EPDU number in MPDU packet domain, and uncertain header position and tail position. It is difficult to consider various situations manually and manually design test cases to cover various MPDU packet domain situations. To achieve functional coverage statistics of various situations in MPDU packet domain and avoid design risks. The present invention constructs an AOS data processing FPGA simulation verification system based on UVM to achieve test input randomization, collect the EPDU number coverage, header position coverage, tail position coverage, padding packet and padding frame sending coverage in real time in the MPDU packet domain, realize functional coverage statistics in all directions, and give uncovered situations, so as to get rid of the dilemma that traditional FPGA simulation verification can only perform code coverage statistics but cannot achieve functional coverage statistics.

[0024] 2) Automatic test comparison is realized. The expected data EXP stack and the measured data ACT stack are collected in real time through the scoreboard group, and consistency matching is performed. The error frame reception and missed frame conditions are given in real time, which is convenient for designers and evaluators to locate faults.

[0025] 3) Strong channel tolerance. The present invention provides universality by arranging the frame structure and maximizing the number of channels n. By changing the number of channels n and changing the MPDU ratio of the corresponding channels according to the rate modification constraint, FPGA simulation verification of AOS data processing of any number of channels can be achieved. The applicability is extended to AOS data processing systems in different aerospace models, promoting the construction of aerospace product spectrum. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a system block diagram of a preferred embodiment of the present invention;

[0027] Figure 2 This is a flow chart of the MPDU packet generation function according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will clearly and completely describe and discuss the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings of the present invention. Obviously, what is described here is only a part of the examples of the present invention, not all the examples. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0029] In order to facilitate the understanding of the embodiments of the present invention, the following will be further explained by taking specific embodiments as examples in conjunction with the drawings, and each embodiment does not constitute a limitation on the embodiments of the present invention.

[0030] The present invention can be applied to the technical field related to the design of an AOS multi-type payload data communication receiving terminal using the CCSDS (Consultative Committee for Space Data Systems) standard.

[0031] The present embodiment provides an AOS data processing FPGA simulation verification system based on UVM, which is used to provide a closed-loop real-time simulation working environment for the AOS data processing FPGA, realize random generation of test stimuli, and automatic convergence of constraints. In particular, it can overcome the difficulties that the existing simulation technology is difficult to ensure various MPDU packet domain conditions, the design of test cases is complex, and a large amount of manpower and material resources are wasted, but the complete functional coverage statistics cannot be guaranteed. At the same time, it can realize automatic comparison of multiple channels and discover the hidden dangers of frame leakage in real time.

[0032] like Figure 1 As shown, the system specifically includes:

[0033] AOS data generation module 1 uses UVM advanced verification methodology to simulate various random CCSDS protocol data of different types and rates, and triggers the expected ip_transaction_r transmission event. At the same time, it monitors the location of various data packet lengths, headers, and tail pointers to transmit data to the RS interleaving encoding module, thereby ensuring the test function coverage of the AOS data processing FPGA;

[0034] RS interleaving encoding module 2, interleaving and encoding the data transmitted from AOS data generating module 1 using RS (255, 223) format to generate an array;

[0035] The scrambling C program 3 scrambles the array generated after the RS interleaving encoding in the C code to obtain the scrambled data;

[0036] The relay data generation module 4 is used to add the scrambled data to the synchronization frame header, and perform parallel-to-serial conversion and output to the FPGA as input stimulus at the rising edge of the forward clock;

[0037] Monitoring module group 5, used to receive data, clock and gating signals output by the AOS data processing FPGA, and obtain the measured ip_transaction_r data stack;

[0038] The scoreboard group 6 is used to perform data packet consistency matching between the ip_transaction_r of the corresponding channel under test and the ip_transaction_r data stack of the expected channel.

[0039] The present invention provides an AOS data processing FPGA simulation verification system to simulate various randomly generated CCSDS protocol data of different types and rates, and can automatically compare the consistency of received and forwarded data packets in real time, and can monitor the positions of various data packet lengths, headers and tails, so as to ensure the test function coverage of the AOS data processing FPGA. To this end, the present invention proposes a fully digital simulation verification system for AOS data processing FPGA built based on UVM verification methodology.

[0040] The present invention includes: an AOS data generation module, an RS interleaving encoding module, a scrambling C program, a relay generation module, a monitoring module group and a scoreboard group. The present invention is suitable for ground simulation verification of AOS multi-type payload data communication FPGA using the CCSDS (Consultative Committee for Space Data Systems) standard. The present invention realizes test input randomization and constraint automatic convergence by constructing a UVM-based AOS data processing FPGA simulation verification system, and collects the EPDU number coverage, header position coverage, tail position coverage, filling packet and filling frame transmission coverage in the MPDU packet domain in real time, and realizes functional coverage statistics in an all-round way. In addition, the present invention obtains the expected data EXP stack and the measured data ACT stack in real time through the scoreboard group, and performs automatic consistency matching, and gives the error frame reception and missing frame situation, which greatly facilitates the designer to locate the fault. Finally, the present invention also provides the maximization of the number of channels n to achieve universality. By changing the number of channels n and changing the MPDU proportion of the corresponding channel according to the rate modification constraint, the AOS data processing FPGA simulation verification of any multiple channels can be realized, and it can be extended to be applied to the FPGA ground simulation verification of various aerospace models of AOS data processing systems.

[0041] Furthermore, the above-mentioned UVM-based AOS data processing FPGA simulation verification system can configure the environment by configuring the number of channels n, thereby improving the versatility of the AOS data processing FPGA simulation system. By randomly generating EPDUs, padding packets, and padding frames of different packet lengths, and by monitoring the positions of various data packet lengths, packet headers, and packet tail pointers, the test function coverage of the AOS data processing FPGA is achieved.

[0042] In a further preferred embodiment, the AOS data generating module 1 further converts the sent EPDU into ip_transaciton_r, and by triggering the EPDU transfer event, starts the scoreboard group 6 to collect ip_transaciton_r for generating the EXP data stack.

[0043] In a further preferred embodiment, the monitoring module group 5 is specifically used to receive three-wire data, receive the packet length when the gating is effective, receive data when the gating is invalid according to the packet length, and write the received ip_transaciton_r into the public measurement port ap_ip.

[0044] In a further preferred embodiment, the scoreboard group 6 obtains the measured ip_transaciton_r of the measured port ap_ip and the expected ip_transaciton_r of the EXP data stack for consistency matching, and checks whether there is a frame leakage when the matching is consistent.

[0045] The system is written in System Verilog code and uses the VCS simulation verification tool from Synopsys, which provides a closed-loop working environment for the AOS data processing FPGA.

[0046] The idea of ​​the system for implementing the above-mentioned embodiment is: using UVM advanced verification methodology to construct an AOS data generation module 1 to randomly generate source EPDU packets according to the proportion of constraint settings, and each EPDU packet is cleared and inserted into the MPDU packet domain according to the randomly generated packet length, and then in the MPDU data packet domain that conforms to the CCSDS protocol, RS (255, 223) interleaving encoding is performed by the RS interleaving encoding module 2, and then the scrambling C program 3 is called through the DPI interface for scrambling, and then the scrambled data is output to the relay data generation module 4 through the DPI interface, a frame header is added in front, and then the data is serially output to the AOS data processing FPGA7, and the corresponding channel data is received through the monitoring module group 5 to form ip_transaciton_r and written into the actual measurement port, and the source remote control IP packet generated by the AOS data generation module 1 is received through the scoreboard group 6 for comparison, thereby realizing an automatic comparison closed-loop simulation system.

[0047] To achieve the above object, the method of the present invention mainly comprises the following steps:

[0048] Step 1: First build Figure 1 The shown modules include an AOS data generation module 1, an RS interleaving encoding module 2, a scrambling C program 3, a relay generation module 4, a monitoring module group 5, and a scoreboard group 6.

[0049] Step 2: Secondly, if Figure 1The AOS data generation module 1 described in the figure uses the UVM advanced verification methodology to construct the AOS data generation module 1, and n can be configured by parameters according to the actual number of channels, indicating that there are n channels. Each channel first generates an EPDU frame in epdu_ip_transaction according to the EPDU frame format frame header + packet length + data, where the packet length and data are both random values, and sends it to the EPDU queue. The current EPDU frame in the EPDU queue is generated according to the epdu frame format epdu_ip_transaction and transmitted to mpdu_transaction. mpdu_transaction combines the MPDU packet domain according to the remaining packet length of the previously inserted epdu_ip_transaction and the current epdu_ip_transaction packet length. After the MPDU packet domain is combined, the MPDU frame header is added to form an MPDU frame to generate mpdu_transaction and transmit it to aos_transaction. At the same time, the bytes and byte counts of the epdu_ip_transaction packaged in the queue are converted into ip_transaction_r as expected values ​​and transmitted to the scoreboard rc_scoreboard of the corresponding channel in the scoreboard group 6 for consistency matching with the rc_monitor corresponding to the monitoring module group 5. aos_transaction designs the channel duty cycle according to the channel reverse rate, selects the MPDU frame mpdu_transaction of the corresponding channel according to the current VCID number for framing, and forms a complete CCSDS protocol frame for transmission to the aos_driver driver module. The aos_driver driver module byte-packs the CCSDS protocol frame data after mpdu_transaction framing, and cross-divides the data into 4 groups (0, 4, 8...888 are divided into the first group, 1, 5, 9...889 are divided into the second group, 2, 6, 10...890 are divided into the third group, and 3, 7, 11...891 are divided into the fourth group), and then strictly transmits it to the RS interleaving coding module 2 according to the input timing of the RS coding.

[0050] Step 3: If Figure 2As shown, mpdu_transaction constructs an 886-byte mpdu data packet domain, frame header + header pointer + previous EPDU packet tail + n EPDU packets, defines the starting position of the next packet as next_start, the number of remaining data of the previous EPDU packet as pre_leave_size, and the remaining data of the previous EPDU packet as pre_end. In addition, 6 functions are designed: Create a new MPDU data packet domain function 1, create a new padding packet function 6, the previous packet is less than one frame function 2, the previous packet is greater than one frame function 3, generate a new EPDU packet function 4 and generate a padding frame function 5. Reference Figure 2 As shown, the MPDU data packet domain generation process is constructed. The six functions are described as follows:

[0051] 1) Create a new MPDU data packet domain function 1. An MPDU data packet domain has 886 bytes. First determine the number of data left in the previous packet, pre_leave_size. If pre_leave_size is 0, it means that the first byte of the MPDU packet domain is the first byte of the source packet header, then set the first header pointer to 0, and then determine whether to insert the transmission frame based on whether the random number modulus 6 is 0. If it is 0, call the padding frame generation function 5 to insert the padding frame, otherwise call the previous packet less than one frame function 2 for transmission, and collect the padding frame transmission coverage at the same time; if the number of data left in the previous packet is greater than 883, it means that the amount of data in the previous packet is greater than one frame, and the MPDU packet domain does not contain the epdu packet header. Set the first header pointer to all 1, that is, 16'h7ff, and use the previous packet greater than one frame function 3 for transmission. If the number of data left in the previous packet is less than or equal to 883. It means that the amount of data in the previous packet is less than one frame. Set the first header pointer to the amount of data in the previous packet, and use the previous packet less than one frame function 2 for transmission. Collect the first header pointer coverage at the same time.

[0052] 2) Generate a padding frame function 5 to set the first 2 bytes of the current MPDU frame as a padding frame header, and set the remaining 884 bytes of data to be filled as padding data.

[0053] 3) The previous packet is larger than one frame. Function 3 sets the frame header + leader pointer, and compresses the remaining data of the previous epdu packet into the data stack, and then stores the excess data into the remaining data of the next packet, resets Pre_end, and subtracts 884 from the number of remaining data of the previous epdu packet to obtain the new number of remaining data of the previous epdu packet Pre_leave_size = Pre_leave_size-884.

[0054] 4) Call the previous packet less than one frame function 2 to set the frame header + header pointer, and compress the remaining data of the previous epdu packet into the data stack. Record i = the number of remaining bytes after processing the current packet Pre_leave_size, then clear the epdu queue and call the new EPDU packet function 4 to generate a new edpu packet.

[0055] 5) Generate a new EPDU packet. Function 4 loops to determine i. 1) If i is less than 884, then determine that the number of bytes remaining after processing the current packet is not equal to 0 and use a random number to take the remainder 6. When the remainder is 0, call the fill packet frame function to insert the fill packet and collect the insert fill packet identifier. When the remainder is not 0, record the remaining number of writable data and randomly generate a new EPDU packet. Obtain the number and data of this new EPDU packet according to the Ethernet receiving frame structure IP data length + ip data format, push it into the expected stack and notify the scoreboard, then pack the EPDU packet in byte mode, record i = the current number of processed + the length of the packed data (i = i + data_size). When i is less than 884, that is, the remaining position is enough to write a new EPDU packet, then write the packed data to the MPDU in a byte-by-byte manner, and pass the multiple epdu packets generated in the stack at one time. 2) If i is greater than or equal to 884, first pass the multiple epdu packets generated in the stack at one time. Then determine whether to fill the padding packet. If not, generate the next cross-MPDU EPDU packet, calculate the remaining writable data, write the data to the remaining position of the MPDU, and record the starting part next_start and the remaining part pre_end of the cross-domain EPDU packet, as well as the number of remaining data to be written for use by the next MPDU generation function.

[0056] 6) Create a new filling packet function 6. Put all the remaining area of ​​the MPDU packet field into the filling data 8'he0, clear the remaining part Pre_end = new[0] without matching space pre_leave_size = 0. Then pass the multiple epdu packets generated in the stack at one time.

[0057] Step 4: Figure 1 As shown, RS interleaving encoding module 2 is constructed, the IP core rs_encoder_v5_0 in the XilinxCoreLib library of Xilinx is called, the parameters c_n=255, c_k=223 are set, and RS (255, 223) 4 groups of 223 bytes of interleaving encoding are performed. After RS ​​interleaving encoding, the number of data bytes increases from 892 bytes to 1020 bytes.

[0058] Step 5: Figure 1As shown, construct the scrambling C program 3, which is specifically implemented as the encrypt function, to achieve the random scrambling of a specific formula of the 1020-byte array. The initial scrambling value is 255. The scrambling code is generated according to the formula, the scrambling value is shifted right by one bit, and the scrambling code is placed in the highest bit to generate a new scrambling value. The lowest bit of the scrambling value is used in turn to perform XOR on each bit of the 1020-byte data to complete the scrambling.

[0059] Step 6: Figure 1 As shown, a relay data generation module 4 is constructed. A 32-bit frame header is added to the scrambled data to form a 1024-byte array, and then single-bit data is sequentially taken from the 1024-byte array at the rising edge of the clock input to the AOS data processing FPGA7 as data input to the AOS data processing FPGA7.

[0060] Step 7: Figure 1 As shown, a monitoring module group 5 is constructed. The AOS data processing FPGA 7 is parsed to obtain the corresponding n output channels, and each channel has a corresponding Rc_monitor module. At the rising edge of the clock of the output channel, if the gate control is valid, the first 2 bytes are the number of data. The data is received according to the number of data and put into the stack to form ip_transaction_r.

[0061] Step 8: Figure 1 As shown, construct the scoreboard group 6. Compare the expected ip_transaction_r stack output by epdu_ip_transaction to the output of ip_transaction and the ACT array obtained by the ip_transaction_r output by the monitoring module group 5, find the consistent ip_transaction_r in the expected stack in turn according to the measured ip_transaction_r, and give correct information if the consistent one is found. If the matching ip_transaction_r found in the expected stack is not the first ip_transaction_r in the stack, a missing frame warning is issued and the lost EPDU data packet result is printed; if no matching expected ip_transaction_r is found, a no error warning is given, and all expected frames and the current measured frame results are given.

[0062] The method of the above embodiment is to assist in explaining the composition and function of the system. Any improvements made to the system by those skilled in the art based on the above method are also included in the scope of the present invention.

[0063] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any modification or replacement made by a person skilled in the art within the technical scope disclosed by the present invention shall be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A UVM-based AOS data processing FPGA simulation verification system, characterized in that: include: The AOS data generation module is used to simulate various random CCSDS protocol data of different types and rates using UVM advanced verification methodology, and trigger the expected ip_transaction_r transmission event, while monitoring the location of various data packet lengths, headers and tail pointers to transmit data to the RS interleaving encoding module; A RS interleaving encoding module, used for performing interleaving encoding with a depth of 4 on the data transmitted from the AOS data generating module in RS (255, 223) format to generate an array; The scrambling C program is used to scramble the array generated by the RS interleaving encoding module in the C code to obtain the scrambled data; The relay data generation module is used to add the scrambled data to the synchronization frame header, and convert the parallel data into serial data on the rising edge of the forward clock and output it to the FPGA as input stimulus; The monitoring module group is used to monitor the data, clock and gating signals output by the AOS data processing FPGA to obtain the measured ip_transaction_r data stack; The scoreboard group is used to match the data packets of the ip_transaction_r data stack of the corresponding channel under actual measurement with the ip_transaction_r data stack of the expected channel.

2. The AOS data processing FPGA simulation verification system based on UVM according to claim 1, characterized in that, The AOS data generation module is used to configure the environment by configuring the number of channels n, thereby improving the versatility of the AOS data processing FPGA simulation system, and achieving test function coverage of the AOS data processing FPGA by randomly generating EPDUs, padding packets and padding frames with different packet lengths, and by monitoring the lengths of various data packets, the locations of packet headers and packet tail pointers, and the number of valid EPDUs in an MPDU packet.

3. According to the AOS data processing FPGA simulation verification system based on UVM of claim 2, it is characterized in that, The AOS data generation module includes: an EPDU generation queue epdu_ip_transaction, an MPDU packet domain generation queue mpdu_transaction, a CCSDS protocol data generation queue aos_transaction and an interface driver module aos_driver, wherein: epdu_ip_transaction generates EPDU frames according to the EPDU frame format frame header + packet length + data, sends them to the epdu_ip_transaction queue and transmits them to the MPDU packet domain to generate the queue mpdu_transaction; mpdu_transaction combines the MPDU packet fields according to the remaining packet length of the previously inserted epdu_ip_transaction and the current epdu_ip_transaction packet length. After the MPDU packet fields are combined, the MPDU frame header is added to form an MPDU frame to generate the mpdu_transaction queue and transmit it to the CCSDS protocol data generation queue aos_transaction for framing. A complete CCSDS protocol frame is formed and transmitted to the interface driver module aos_drive. The interface driver module aos_driver byte-packs the CCSDS protocol frame data after aos_transaction framing, divides the data into 4 groups crosswise, and then transmits it to the RS interleaving coding module strictly according to the input timing of the RS interleaving coding with a depth of 4.

4. The AOS data processing FPGA simulation verification system based on UVM according to claim 3, characterized in that, The MPDU packet domain generates the queue mpdu_transaction and converts the sent EPDU into the output comparable queue ip_transaction_r according to the byte number + data. By triggering the EPDU transmission event, the scoreboard group is started to collect ip_transaciton_r for generating the expected value EXP data stack.

5. The AOS data processing FPGA simulation verification system based on UVM according to claim 4, characterized in that, The MPDU packet domain generation queue mpdu_transaction includes 6 key functions: a function for creating a new MPDU data packet domain, a function for creating a new filling packet, a function for the previous packet being less than one frame, a function for the previous packet being greater than one frame, a function for generating a new EPDU packet, and a function for generating a filling frame; the 6 functions are randomly called according to the number of data remaining in the previous EPDU packet pre_leave_size, the remaining data of the previous EPDU packet data pre_end, and the result of taking the remainder of a random value as 6 to achieve test stimulus randomization.

6. The AOS data processing FPGA simulation verification system based on UVM according to claim 1, characterized in that, The monitoring module group is used to receive three-wire data, receive the packet length when the gate control is effective, receive data when the gate control is invalid according to the packet length, and write the received measured ip_transaciton_r into the public measured port ap_ip.

7. The AOS data processing FPGA simulation verification system based on UVM according to claim 1, characterized in that, The scoreboard group is used to obtain the measured ip_transaciton_r of the measured port ap_ip and the expected ip_transaciton_r in the EXP data stack generated by the AOS data generation module triggering the transmission of the EPDU event for automatic consistency matching. If the match is consistent, check whether there is a missing frame and give the missing frame information; if the match is inconsistent, print out all ip_transaciton_r and measured ip_transaciton_r results of the expected EXP data stack.

8. The AOS data processing FPGA simulation verification system based on UVM according to claim 1, characterized in that, The AOS data generation module is used to achieve the consistency matching of sending and forwarding reception of EPDU packets of multiple channels by configuring the channel parameter n; by constraining the number of occurrences of the virtual channel identifier VCID, the sending frequency of the CCSDS protocol of each channel is constrained. According to the principle of equivalence, the VCID corresponding to the channel with the fastest forwarding rate is set to be 3 times the number of occurrences of other channels, so as to achieve the functional coverage statistics of the number of EPDU valid data packets, packet length, and the location of the header and tail pointers in the frame structure of the fastest channel.

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