A semiconductor structure and a method of forming the same

Abstract

Embodiments of the present application disclose a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a substrate; a transistor structure on the substrate; an isolation structure formed in the substrate and located between adjacent transistor structures for electrically isolating the adjacent transistor structures; the isolation structure comprises: a first shallow isolation structure located on one side of one of the adjacent transistor structures, a second shallow isolation structure located on one side of the other of the adjacent transistor structures, and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure, wherein the deep isolation region comprises a first active region and a counter-doped region located below the first active region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of semiconductor technology, the performance requirements for high-voltage metal-oxide-semiconductor (HVMOS) devices are becoming increasingly stringent. Breakdown voltage (BV) is a key characteristic affecting the application of HVMOS devices. HVMOS devices are used to form the driving circuits of 3D NAND flash memory, and they must have sufficiently high breakdown voltages during read, write, and erase operations on memory cells. As semiconductor processes continue to evolve and the number of product layers increases, the requirements for the breakdown voltage of HVMOS devices become increasingly stringent. Therefore, improving the breakdown voltage of HVMOS devices has become a pressing problem in this technical field. Summary of the Invention

[0003] In view of this, the main objective of this application is to provide a semiconductor structure and a method for forming the same.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] This application provides a semiconductor structure, including:

[0006] Substrate;

[0007] The transistor structure on the substrate;

[0008] An isolation structure formed within the substrate is located between adjacent transistor structures for electrically isolating the adjacent transistor structures. The isolation structure includes: a first shallow isolation structure located on the side of one of the adjacent transistor structures, a second shallow isolation structure located on the side of the other of the adjacent transistor structures, and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure. The deep isolation region includes a first active region and an anti-doped region located below the first active region.

[0009] In the above scheme, the transistor structure is arranged in an array along the row and column directions, and the isolation structure is formed between adjacent rows and adjacent columns of the transistor structure.

[0010] In the above scheme, the transistor structure includes an N-type doped region that extends along the row direction; the distance between adjacent transistor structures along the row direction is smaller than the distance between adjacent transistor structures along the column direction.

[0011] In the above scheme, the depth of the deep isolation zone is greater than the depth of the first shallow isolation structure and the second shallow isolation structure.

[0012] In the above scheme, the depth of the first active region is the same as the depth of the first shallow isolation structure and the second shallow isolation structure.

[0013] In the above scheme, the first active region and the anti-doped region have different doping types.

[0014] In the above scheme, the transistor structure is a high-voltage NMOS transistor, and the bias voltage between adjacent transistor structures differs by 25V.

[0015] This application embodiment also provides a method for forming a semiconductor structure, the method comprising:

[0016] A substrate is provided; an isolation structure is formed within the substrate, and the region between adjacent isolation structures is a second active region;

[0017] A transistor structure is formed in the second active region; wherein the isolation structure is located between adjacent transistor structures for electrically isolating adjacent transistor structures; the isolation structure includes: a first shallow isolation structure located on the side of one transistor structure in the adjacent transistor structures, a second shallow isolation structure located on the side of the other transistor structure in the adjacent transistor structures, and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure, the deep isolation region including a first active region and an anti-doped region located below the first active region.

[0018] In the above scheme, forming an isolation structure within the substrate includes:

[0019] A first shallow isolation structure located on one side of the adjacent transistor structure, a second shallow isolation structure located on the side of the adjacent transistor structure, and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure are sequentially formed in the substrate.

[0020] In the above scheme, forming the deep isolation region located between the first shallow isolation structure and the second shallow isolation structure includes:

[0021] A first active region is formed between the first shallow isolation structure and the second shallow isolation structure using a first ion implantation process.

[0022] In the above scheme, forming the deep isolation region located between the first shallow isolation structure and the second shallow isolation structure further includes:

[0023] An anti-doped region is formed under the first active region by a second ion implantation process.

[0024] In the above scheme, the depth of the deep isolation zone is greater than the depth of the first shallow isolation structure and the second shallow isolation structure.

[0025] In the above scheme, the depth of the first active region is the same as the depth of the first shallow isolation structure and the second shallow isolation structure.

[0026] In the above scheme, the first active region and the second active region have the same doping type; the first active region and the anti-doped region have different doping types.

[0027] The semiconductor structure provided in this application includes: a substrate; transistor structures on the substrate; and an isolation structure formed within the substrate, located between adjacent transistor structures for electrically isolating the adjacent transistor structures. The isolation structure includes: a first shallow isolation structure located on the side of one of the adjacent transistor structures; a second shallow isolation structure located on the side of the other of the adjacent transistor structures; and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure. The deep isolation region includes a first active region and an anti-doped region located below the first active region. The semiconductor structure provided in this application, by providing an isolation structure with a first shallow isolation structure, a second shallow isolation structure, a first active region, and an anti-doped region between adjacent transistor structures, wherein the anti-doped region is formed below the first active region, facilitates the reduction of the anti-doped region size. Without increasing the device size, the distance between the anti-doped region and the transistor structure can be increased, thereby improving the device's breakdown voltage to a certain extent. Attached Figure Description

[0028] Figure 1 This is a top view of a semiconductor structure in the relevant technology;

[0029] Figure 2 for Figure 1 A magnified view of the area within the dashed box;

[0030] Figure 3 This is a cross-sectional view of the isolation structure in a semiconductor structure in related technologies;

[0031] Figure 4 A top view of a semiconductor structure provided in an embodiment of this application;

[0032] Figure 5 A cross-sectional view of a semiconductor structure provided in an embodiment of this application;

[0033] Figure 6 for Figure 4 A magnified view of the area within the dashed box;

[0034] Figure 7 This is a schematic diagram illustrating the implementation process of the semiconductor structure formation method provided in the embodiments of this application.

[0035] The above figures include the following reference numerals:

[0036] 10-Transistor structure; 11-N-type doped region; 20-Isolation structure; 21-Deep isolation structure; 22-Shallow trench isolation structure; 23-Source; 24-Drain; 25-Gate; 26-Substrate; 30-Substrate; 40-Transistor structure; 41-N-type doped region; 50-Isolation structure; 51-First shallow isolation structure; 52-Second shallow isolation structure; 53-First active region; 54-Dedoped region; 55-Source; 56-Drain; 57-Gate. Detailed Implementation

[0037] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0038] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0039] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0040] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal planes at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces.

[0041] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0042] In some applications of HVMOS devices, sufficiently high breakdown voltages are required. With the continuous development of semiconductor processes and the increasing number of product layers, the requirements for the operating voltage of memory cells are constantly rising, placing even higher demands on the breakdown voltage of HVMOS devices. The inventors conducted research and analysis on the problem of the urgent need to improve the breakdown voltage of word line drivers—an example of HVMOS devices used in the driving circuit of 3D NAND memory—and discovered that:

[0043] Reference Figure 1 and Figure 2 The breakdown voltage of the current word line driver is mainly limited by the distance in the Y direction between the N-type doped region 11 in the transistor structure 10 and the deep isolation structure 21 in the isolation structure 20. Here, D1 is the distance of adjacent transistor structures 10 along the Y direction, and D3 is the distance of adjacent transistor structures 10 along the X direction. D1 and D3 are usually equal.

[0044] Figure 3 for Figure 2 The cross-sectional view of the isolation structure along the AA' direction in the semiconductor structure shown is as follows. Figure 3 As shown, the transistor structures 10 on both sides of the isolation structure 20 include a gate 25 located on the substrate 26, and a source 23 and a drain 24 located on both sides of the gate 25 in the substrate. The isolation structure 20 includes a shallow trench isolation structure 22 and a deep isolation structure 21, the deep isolation structure 21 being formed by ion implantation. Since the distance D1 between the transistor structures 10 is determined by the height of the array block and cannot be increased further, the distance between the N-type doped region 11 and the deep isolation structure 21 in the Y direction can only be increased by reducing the width D2 of the deep isolation structure 21, thereby improving the breakdown voltage of the word line driver. It should be noted that the transistor structures 10 in the word line driver are arranged in an array along the row and column directions, and the isolation structure 20 is formed between adjacent rows and adjacent columns of the transistor structures 10. Here, the direction of the row is the X direction, and the direction of the column is the Y direction.

[0045] Based on this, embodiments of this application provide a semiconductor structure. Figure 4 This is a top view of the semiconductor structure provided in an embodiment of this application. Figure 5 A cross-sectional view of the semiconductor structure provided in the embodiments of this application, such as Figure 4 and Figure 5 As shown, the semiconductor structure includes:

[0046] Substrate 30;

[0047] The transistor structure 40 on the substrate 30;

[0048] An isolation structure 50 is formed in the substrate 30 and is located between adjacent transistor structures 40 for electrically isolating adjacent transistor structures 40.

[0049] The isolation structure 50 includes: a first shallow isolation structure 51 located on the side of one transistor structure in the adjacent transistor structures, a second shallow isolation structure 52 located on the side of the other transistor structure in the adjacent transistor structures, and a deep isolation region located between the first shallow isolation structure 51 and the second shallow isolation structure 52, wherein the deep isolation region includes a first active region 53 and an anti-doped region 54 located under the first active region 53.

[0050] Please see Figure 5 In this application, the transistor structure 40 on both sides of the isolation structure 50 includes a gate 57 on the substrate 30, a source 55 and a drain 56 located on both sides of the gate 57 in the substrate, and the source and the drain may have a first doping type.

[0051] In this application, the first active region 53 is formed by ion implantation of a first doping type in the region located between the first shallow isolation structure 51 and the second shallow isolation structure 52.

[0052] In this embodiment, the first active region 53 can be formed together with the source 55 and drain 56 of the transistor structure 40, so that no new mask and process steps are needed for the first active region, and the first active region can be realized using the existing process, thereby reducing process costs.

[0053] In this application, the undoped region 54 is formed by ion implantation of a second type of doping into the region below the first active region 53. Specifically, depending on the device type, N-type or P-type dopant particles can be implanted. N-type dopant particles can be, for example, N, P, As, S, etc., while P-type dopant particles can be, for example, B, Al, Ga, or In, etc. Compared to... Figure 3 In the related technologies shown, a deep isolation structure 21 is formed by ion implantation of an insulating material structure such as a shallow trench isolation structure 22. In this application, the energy required for ion implantation of a semiconductor material structure such as the first active region 53 when forming the anti-doped region 54 is less, thereby reducing the thickness of the photoresist during ion implantation and thus reducing the size of the anti-doped region 54. In specific applications, in the embodiments of this application, the region below the first active region can also be ion implanted with a first doping type to form an anti-doped region.

[0054] Here, the first doping type and the second doping type are different. In some embodiments, the substrate can be a semiconductor substrate. The semiconductor substrate can be a single-element semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0055] In this embodiment, the transistor structures 40 are arranged in an array along the row and column directions, and the isolation structures 50 are formed between adjacent rows and adjacent columns of the transistor structures 40. Here, the direction of the row is the X direction, and the direction of the column is the Y direction.

[0056] In this embodiment of the application, the transistor structure 40 is a high-voltage NMOS transistor, and the bias voltage between adjacent transistor structures 40 differs by 25V.

[0057] In the embodiments of this application, such as Figure 5 As shown, the depth of the deep isolation zone is greater than the depth of the first shallow isolation structure 51, and the depth of the deep isolation zone is greater than the depth of the second shallow isolation structure 52.

[0058] In the embodiments of this application, such as Figure 5 As shown, the depth of the first active region 53 is the same as the depth of the first shallow isolation structure 51, and the depth of the first active region 53 is the same as the depth of the second shallow isolation structure 52.

[0059] In practical applications, an anisotropic dry etching process can be used to first form a first shallow trench and a second shallow trench in the substrate, and then fill the first shallow trench and the second shallow trench with insulating material to form a first shallow isolation structure 51 and a second shallow isolation structure 52.

[0060] In this embodiment, the first active region 53 and the anti-doped region 54 have different doping types. In some embodiments, the first active region 53 may also be an undoped region.

[0061] In some embodiments, the first active region 53 and the anti-doped region 54 have different doping types. That is, when the doping type of the first active region 53 is N-type, the doping type of the anti-doped region 54 is P-type; similarly, when the doping type of the first active region 53 is P-type, the doping type of the anti-doped region 54 is N-type. Depending on the doping type requirements, N-type or P-type dopant particles can be implanted using ion implantation. For example, N-type dopant particles can be N, P, As, S, etc., and P-type dopant particles can be for example B, Al, Ga, or In.

[0062] In this application embodiment, a deep isolation region including an anti-doped region is used to improve the isolation effect between devices. This deep isolation region can also be used to improve the isolation effect of high-voltage devices. The semiconductor structure including a deep isolation region provided in this application embodiment not only improves the device isolation effect but also helps to further reduce the size between devices and improve device integration.

[0063] In some embodiments, when the transistor structure 40 is a high-voltage NMOS transistor, the doping type of the first active region 53 is N-type, and the doping type of the anti-doped region 54 is P-type.

[0064] In this embodiment, the width of the anti-doped region 54 is less than 0.3 μm. It should be noted that when the isolation structure 50 extends along the X direction, the width of the anti-doped region 54 is the same as the width of the anti-doped region 54 along the Y direction; when the isolation structure 50 extends along the Y direction, the width of the anti-doped region 54 is the same as the width of the anti-doped region 54 along the X direction.

[0065] Figure 6 for Figure 4 A magnified view of the area within the dashed box, as shown below. Figure 6 As shown, the transistor structure 40 includes an N-type doped region 41, which extends along the row direction (X direction).

[0066] In a preferred embodiment, the distance between adjacent transistor structures 40 along the row direction (X direction) is less than the distance between adjacent transistor structures 40 along the column direction (Y direction).

[0067] Although ion implantation to form an anti-doped region in the region below the first active region in this embodiment helps reduce the size of the anti-doped region, thereby reducing the size of the isolation structure, to ensure sufficient breakdown voltage for the word line driver, the width of the isolation structure in the Y direction is not significantly altered. Instead, the distance between the N-type doped region and the anti-doped region in the Y direction is increased by reducing the width of the anti-doped region. Thus, by reducing the size of the anti-doped region through ion implantation in the region below the first active region, the distance between the N-type doped region and the anti-doped region in the transistor structure can be increased without increasing the device size, thereby improving the breakdown voltage.

[0068] However, since the breakdown voltage is not affected by the distance between the N-type doped region and the anti-doped region in the X direction in the transistor structure, the width of the isolation structure in the X direction can be reduced, thereby reducing the overall device size in the X direction. This allows for further reduction in device size.

[0069] In some embodiments, the widths of the first shallow isolation structure 51 and the second shallow isolation structure 52 can be the same. In practical applications, the width of the first active region 53 can be set according to the widths of the first shallow isolation structure 51 and the second shallow isolation structure 52. Therefore, when the first shallow isolation structure 51 and the second shallow isolation structure 52 are wider, the first active region 53 can be set to be narrower; and when the first active region 53 is wider, the first shallow isolation structure 51 and the second shallow isolation structure 52 can be set to be narrower, so as to minimize the total width of the isolation structure, thereby making the distance between adjacent transistors 10 along the X direction less than 0.6 μm. Therefore, the distance between adjacent transistors along the row direction is less than the distance between adjacent transistor structures along the column direction, which is beneficial to further reduce the size between devices and improve the integration density of devices.

[0070] In some embodiments, when the isolation structure 50 extends along the X direction, the width of the anti-doped region 54 along the Y direction is less than or equal to the width of the first active region 53 along the Y direction; and when the isolation structure 50 extends along the Y direction, the width of the anti-doped region 54 along the X direction is less than or equal to the width of the first active region 53 along the X direction. In practical applications, the width of the first active region can be set according to the width of the anti-doped region, thereby minimizing the size of the isolation structure as much as possible.

[0071] The semiconductor structure provided in this application includes: a substrate; transistor structures on the substrate; and an isolation structure formed within the substrate, located between adjacent transistor structures for electrically isolating the adjacent transistor structures. The isolation structure includes: a first shallow isolation structure located on the side of one of the adjacent transistor structures; a second shallow isolation structure located on the side of the other of the adjacent transistor structures; and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure. The deep isolation region includes a first active region and an anti-doped region located below the first active region. The semiconductor structure provided in this application, by providing an isolation structure with a first shallow isolation structure, a second shallow isolation structure, a first active region, and an anti-doped region between adjacent transistor structures, wherein the anti-doped region is formed in the region below the first active region, facilitates the reduction of the anti-doped region size. Without increasing the device size, the distance between the anti-doped region and the transistor structure can be increased, thereby improving the device's breakdown voltage to a certain extent.

[0072] This application also provides a method for forming a semiconductor structure. Figure 7 This is a schematic diagram illustrating the implementation flow of the semiconductor structure formation method provided in the embodiments of this application. The semiconductor structure formation method is coordinated with... Figure 4 as well as Figure 5 Please provide an explanation.

[0073] like Figure 4 , Figure 5 as well as Figure 7 As shown, the specific steps of the method for forming this semiconductor structure include:

[0074] Step S701: Provide substrate 30;

[0075] Step S702: An isolation structure 50 is formed in the substrate, and the region between adjacent isolation structures is a second active region;

[0076] Step S703: Form a transistor structure 40 in the second active region; wherein, the isolation structure 50 is located between adjacent transistor structures 40 for electrically isolating adjacent transistor structures 40; the isolation structure 50 includes: a first shallow isolation structure 51 located on the side of one transistor structure in the adjacent transistor structures, a second shallow isolation structure 52 located on the side of the other transistor structure in the adjacent transistor structures, and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure, the deep isolation region including a first active region 53 and an anti-doped region 54 located under the first active region.

[0077] The semiconductor structure formation method provided in this application forms a first shallow isolation structure 51 and a second shallow isolation structure 52 through a shallow trench isolation structure formation process. The first shallow isolation structure 51 and the second shallow isolation structure 52 define a first active region. Then, an anti-doped region 54 is formed in the region below the first active region through an ion implantation process, thereby forming an isolation structure. In the embodiments of this application, the above-mentioned isolation structure can be formed without adding any additional processes. By forming an anti-doped region through ion implantation in the region below the first active region, the size of the anti-doped region is reduced. That is, without increasing the device size, the distance between the N-type doped region and the anti-doped region in the transistor structure can be increased to improve the breakdown voltage. Furthermore, since the breakdown voltage is not affected by the distance between the N-type doped region and the anti-doped region in the X direction in the transistor structure, the width of the isolation structure in the X direction can be reduced, thereby reducing the overall device size in the X direction. Thus, the device size can be further reduced, and the device integration density can be improved.

[0078] Specifically, the step S702 of forming the isolation structure 50 includes: sequentially forming a first shallow isolation structure 51 located on the side of one transistor structure in the adjacent transistor structures, a second shallow isolation structure 52 located on the side of the other transistor structure in the adjacent transistor structures, and a deep isolation region located between the first shallow isolation structure 51 and the second shallow isolation structure 52 in the substrate 30.

[0079] In some embodiments, the first shallow isolation structure 51 and the second shallow isolation structure 52 may include one or more layers of insulating material, such as silicon nitride, silicon oxynitride, silicon carbonitride or other suitable insulating material, and the first shallow isolation structure 51 and the second shallow isolation structure 52 may be shallow trench isolation (STI) structures.

[0080] In this embodiment, the region between the first shallow isolation structure and the second shallow isolation structure is the first active region 53. The formation of the deep isolation region located between the first shallow isolation structure 51 and the second shallow isolation structure 52 includes: forming an anti-doped region 54 in the region below the first active region 53 by an ion implantation process of the second doping type.

[0081] Specifically, depending on the device type, the ion implantation process can involve implanting N-type or P-type doped particles. For example, N-type doped particles can be N, P, As, S, etc., while P-type doped particles can be B, Al, Ga, or In, etc.

[0082] In this embodiment, the first active region 53 and the second active region have the same doping type; the first active region 53 and the dedoped region 54 have different doping types, that is, when the doping type of the first active region 53 is N-type, the doping type of the second active region is N-type, and the doping type of the dedoped region 54 is P-type; similarly, when the doping type of the first active region 53 is P-type, the doping type of the second active region is P-type, and the doping type of the dedoped region 54 is N-type. In some embodiments, the first active region 53 may also be an undoped region.

[0083] In some embodiments, when the transistor structure 40 is a high-voltage NMOS transistor, the doping type of the second active region is N-type, the doping type of the first active region 53 is N-type, and the doping type of the anti-doped region 54 is P-type.

[0084] In the embodiments of this application, such as Figure 5 As shown, the depth of the deep isolation zone is greater than the depth of the first shallow isolation structure 51, and the depth of the deep isolation zone is greater than the depth of the second shallow isolation structure 52.

[0085] In the embodiments of this application, such as Figure 5 As shown, the depth of the first active region 53 is the same as the depth of the first shallow isolation structure 51, and the depth of the first active region 53 is the same as the depth of the second shallow isolation structure 52.

[0086] In practical applications, an anisotropic dry etching process can be used to first form a first shallow trench and a second shallow trench in the substrate, and then fill the first shallow trench and the second shallow trench with insulating material to form a first shallow isolation structure 51 and a second shallow isolation structure 52.

[0087] After the semiconductor structure of the embodiments of this application is formed, other device structures, such as contact and interconnect structures, can be formed.

[0088] It should be understood that the phrases "an embodiment" or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0089] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The transistor structure on the substrate; An isolation structure formed within the substrate is located between adjacent transistor structures for electrically isolating adjacent transistor structures; The isolation structure includes: a first shallow isolation structure located on the side of one transistor structure in the adjacent transistor structures, a second shallow isolation structure located on the side of the other transistor structure in the adjacent transistor structures, and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure, wherein the deep isolation region includes a first active region and an anti-doped region located below the first active region.

2. The structure as described in claim 1, characterized in that, The transistor structures are arranged in an array along the row and column directions, and the isolation structures are formed between adjacent rows and adjacent columns of the transistor structures.

3. The structure as described in claim 2, characterized in that, The transistor structure includes an N-type doped region extending along the row direction; the distance between adjacent transistor structures along the row direction is smaller than the distance between adjacent transistor structures along the column direction.

4. The structure as described in claim 1, characterized in that, The depth of the deep isolation zone is greater than the depth of the first shallow isolation structure and the second shallow isolation structure.

5. The structure as described in claim 1, characterized in that, The depth of the first active region is the same as the depth of the first shallow isolation structure and the second shallow isolation structure.

6. The structure as described in claim 1, characterized in that, The first active region has a different doping type than the anti-doped region.

7. The structure according to claim 1, characterized in that, The transistor structure is a high-voltage NMOS transistor, and the bias voltage between adjacent transistor structures differs by 25V.

8. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided; an isolation structure is formed within the substrate, and the region between adjacent isolation structures is a second active region; A transistor structure is formed in the second active region; wherein the isolation structure is located between adjacent transistor structures for electrically isolating adjacent transistor structures; the isolation structure includes: a first shallow isolation structure located on the side of one transistor structure in the adjacent transistor structures, a second shallow isolation structure located on the side of the other transistor structure in the adjacent transistor structures, and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure, the deep isolation region including a first active region and an anti-doped region located below the first active region.

9. The method as described in claim 8, characterized in that, The formation of the isolation structure within the substrate includes: A first shallow isolation structure located on one side of the adjacent transistor structure, a second shallow isolation structure located on the side of the adjacent transistor structure, and a deep isolation region located between the first shallow isolation structure and the second shallow isolation structure are sequentially formed in the substrate.

10. The method as described in claim 8, characterized in that, Forming the deep isolation region located between the first shallow isolation structure and the second shallow isolation structure includes: A first active region is formed between the first shallow isolation structure and the second shallow isolation structure using a first ion implantation process.

11. The method as described in claim 10, characterized in that, Forming the deep isolation region located between the first shallow isolation structure and the second shallow isolation structure further includes: An anti-doped region is formed under the first active region by a second ion implantation process.

12. The method as described in claim 9 or 10, characterized in that, The depth of the deep isolation zone is greater than the depth of the first shallow isolation structure and the second shallow isolation structure.

13. The method as described in claim 10, characterized in that, The depth of the first active region is the same as the depth of the first shallow isolation structure and the second shallow isolation structure.

14. The method as described in claim 11, characterized in that, The first active region and the second active region have the same doping type; The first active region has a different doping type than the anti-doped region.

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