Memory and method of making the same

Abstract

The application provides a memory and a manufacturing method thereof. The memory comprises a stack structure, a storage channel hole penetrating through the stack structure, and a charge trapping layer located on a sidewall of the storage channel hole. The charge trapping layer comprises a first part and a second part which are sequentially and radially arranged along the storage channel hole. The content of a first element in the second part is greater than that in the first part.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a memory and its manufacturing method. Background Technology

[0002] Memory, such as charge-trapping memory, is an emerging type of flash memory. As a candidate for next-generation high-density memory, it has been a focus of basic research and industrial development in the semiconductor technology field. In related technologies, as the size of memory devices shrinks, the size of each functional layer of the memory also decreases.

[0003] However, as the size of each functional layer of the memory decreases, the reliability of the device decreases. Summary of the Invention

[0004] To address one or more problems existing in related technologies, embodiments of the present invention propose a memory and a method for manufacturing the same.

[0005] One embodiment of the present invention provides a memory, comprising:

[0006] Stacked structure;

[0007] Storage channel holes penetrating the stacked structure;

[0008] Charge trapping layer located on the sidewall of the storage channel aperture;

[0009] The charge trapping layer comprises a first part and a second part that are sequentially stacked along the radial direction of the storage channel hole; the content of the first element in the second part is greater than the content of the first element in the first part.

[0010] In the above scheme, the material of the charge trapping layer includes hydrogen-containing silicon nitride; the first element includes hydrogen.

[0011] In the above scheme, the thickness of the second part is less than the thickness of the first part; the second part is not used for charge storage.

[0012] In the above scheme, during the annealing process of the memory,

[0013] The amount of the first element diffused from the second part to the first part is greater than the amount of the first element diffused from the first part to the second part.

[0014] And / or,

[0015] The first element that diffuses from the first part to the second part is repelled by the first element in the second part and returns to the first part.

[0016] In the above scheme, the memory further includes: a barrier dielectric layer, a tunneling dielectric layer, and a channel layer;

[0017] The barrier dielectric layer is located between the storage channel via sidewall and the charge trapping layer; the tunneling dielectric layer covers the charge trapping layer; and the channel layer covers the tunneling dielectric layer.

[0018] In the above scheme, the material of the barrier dielectric layer includes oxides; the material of the tunneling dielectric layer includes nitrogen-doped oxides.

[0019] In the above scheme, the memory includes a three-dimensional (3D) NAND type memory.

[0020] Another aspect of this invention provides a method for manufacturing a memory, comprising:

[0021] Provide a stacking structure;

[0022] Forming storage channel holes that penetrate the stacked structure;

[0023] A charge trapping layer is formed on the sidewall of the storage channel hole;

[0024] The charge trapping layer comprises a first part and a second part that are sequentially stacked along the radial direction of the storage channel hole; the content of the first element in the second part is greater than the content of the first element in the first part.

[0025] In the above scheme, the material of the charge trapping layer includes hydrogen-containing silicon nitride; the first element includes hydrogen.

[0026] In the above scheme, forming a charge trapping layer on the sidewall of the storage channel aperture includes:

[0027] A charge-capturing material layer is formed on the sidewall of the storage channel hole;

[0028] The surface of the charge-trapping material layer is passivated to form a second portion of the charge-trapping layer; wherein the charge-trapping material layer that has not undergone the passivation treatment forms a first portion of the charge-trapping layer.

[0029] In the above scheme, forming a charge trapping layer on the sidewall of the storage channel aperture includes:

[0030] A first portion of the charge trapping layer is formed on the sidewall of the storage channel hole using a first deposition process;

[0031] A second deposition process is used to form a second portion covering the first portion; wherein the content of the source material containing the first element provided in the second deposition process is greater than the content of the source material containing the first element provided in the first deposition process.

[0032] The method in the above scheme further includes:

[0033] The memory is subjected to annealing; wherein, during the annealing process, the amount of the first element diffused from the second part to the first part is greater than the amount of the first element diffused from the first part to the second part.

[0034] And / or,

[0035] The first element that diffuses from the first part to the second part is repelled by the first element in the second part and returns to the first part.

[0036] The method in the above scheme further includes:

[0037] Before forming the charge trapping layer, a barrier dielectric layer is formed on the sidewall of the storage channel hole;

[0038] The formation of a charge trapping layer on the sidewall of the storage channel aperture includes:

[0039] A charge trapping layer is formed covering the barrier dielectric layer;

[0040] Form a tunneling dielectric layer covering the charge trapping layer;

[0041] A channel layer is formed covering the tunneling dielectric layer.

[0042] In the above scheme, the material of the barrier dielectric layer includes oxides; the material of the tunneling dielectric layer includes nitrogen-doped oxides.

[0043] In the above scheme, the memory includes a 3D NAND type memory.

[0044] This invention provides a memory and a method for manufacturing the same, wherein the memory includes: a stacked structure; a storage channel hole penetrating the stacked structure; and a charge trapping layer located on the sidewall of the storage channel hole; wherein the charge trapping layer includes a first portion and a second portion sequentially stacked radially along the storage channel hole; the content of a first element in the second portion is greater than the content of a first element in the first portion. In this invention, by setting the content of the first element in the second portion of the charge trapping layer to be greater than the content of the first element in the first portion of the charge trapping layer, the first element contained in the second portion of the charge trapping layer can compensate for the loss of the first element in the first portion of the charge trapping layer during heat treatment, or can be used to block the diffusion of the first element from the first portion of the charge trapping layer to the second portion of the charge trapping layer, thereby reducing the loss of the first element in the first portion of the charge trapping layer; thus enhancing the data retention time of the first portion of the charge trapping layer, thereby improving the reliability of the electrical performance of the memory. Attached Figure Description

[0045] Figure 1a This is a schematic diagram of the structure of a memory provided in related technologies;

[0046] Figure 1b for Figure 1a A schematic diagram of the structure of the memory material layer;

[0047] Figure 2 A schematic flowchart illustrating a method for manufacturing a memory according to an embodiment of the present invention;

[0048] Figures 3a-3d A cross-sectional schematic diagram of the fabrication process of a memory provided in an embodiment of the present invention;

[0049] Figures 4a-4b This is a schematic diagram of a process for forming a charge trapping layer according to an embodiment of the present invention;

[0050] Figures 5a-5b This is a schematic diagram of another process for forming a charge trapping layer provided in an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the diffusion of a first element in a charge trapping layer provided in an embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of the diffusion of the first element in another charge trapping layer provided in an embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram of a memory material layer provided in an embodiment of the present invention. Detailed Implementation

[0054] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0055] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0056] It is understood that the meanings of “on”, “above” and “over” in this invention should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0057] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0058] In embodiments of the invention, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0059] In embodiments of the invention, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0060] In this embodiment of the invention, the terms "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0061] The memory described in this embodiment of the invention can be applied to charge-trap flash memory (CTF). Here, charge-trap flash memory has been widely studied due to its advantages such as high stability, low power consumption, strong radiation resistance, and compatibility with standard complementary metal-oxide-semiconductor (CMOS) processes.

[0062] In practical applications, with the development of semiconductor technology, memory devices are trending towards miniaturization, and the dimensions of each functional layer in charge-trapping memory are also decreasing. However, as the dimensions of each functional layer of the memory decrease, the reliability of the memory device will decrease.

[0063] As the necessary cell size scaling or the application of larger programming voltages to the cells become necessary, lateral charge diffusion in the charge trapping layer will become increasingly severe, and this problem will become a critical point for the robustness and reliability of charge trapping memories.

[0064] It should be noted that in charge-trapping memory, insulating materials with high charge trapping density are typically used to trap and store electrons.

[0065] Based on the above considerations, in some specific embodiments, silicon nitride (Si3N4) or hydrogen-containing silicon nitride (Si) is used. x N y H zSilicon nitride (SiN) is commonly used as a material to form charge trapping layers due to its ultra-high storage density, lower manufacturing cost, and higher reliability. Furthermore, using SiN as a charge trapping layer (i.e., a charge storage layer) can overcome many problems present in traditional flash memory (such as charge leakage) in some charge trapping memories.

[0066] In some specific embodiments, Si x N y H z The reason why Si is a preferred material for forming a charge trapping layer is also due to... x N y H z Hydrogen (H) atoms in the layer help eliminate shallow energy level traps and improve electron storage properties. Specifically, when electronic impurities (such as dangling bonds of N) are unavoidably present in the charge trapping layer (i.e., nitride), hydrogen atoms couple with the dangling bonds of N, thereby removing the electronic impurities of N. Alternatively, when oxygen impurities are present in the charge trapping layer (i.e., nitride), the reducing properties of hydrogen can be used to remove the oxygen impurities during the annealing process of the material layer.

[0067] To facilitate a clear and concise explanation of the invention's intent, this invention uses a 3D NAND type memory as an example for illustration; however, it should be understood that the memory in various embodiments of this invention includes, but is not limited to, a 3D NAND type memory.

[0068] For example, such as Figure 1a As shown, in the fabrication process of 3D NAND memory, a memory material layer 20 (i.e., an ONOP structure) needs to be formed in the memory channel via 10. Here, the ONOP structure includes four thin films, specifically a barrier dielectric layer 201, a charge trapping layer 202, a tunneling dielectric layer 203, and a channel layer 204, which are sequentially stacked along the radial direction of the memory channel via. The distribution of the thin films in the ONOP structure 20 is as follows... Figure 1b As shown.

[0069] It should be noted that, Figure 1a This is a schematic diagram of the structure of a 3D NAND flash memory. Figure 1b for Figure 1a A schematic diagram of the structure of the memory material layer.

[0070] In practical applications, the charge trapping layer in the ONOP thin film structure is deposited on the sidewall of the storage channel hole (CH) using an atomic layer deposition (ALD) process, which involves the reaction of dichlorosilane (SiH2Cl2) and ammonia (NH3). The chemical equation for the reaction is: SiH2Cl2 + NH3 → Si x N y Hz +HCl+H2. It is understandable that due to the structural properties of memory material layers, such as multiple vertically stacked memory cells sharing a single charge trapping layer, lateral charge diffusion within the charge trapping layer leads to severe degradation of data retention characteristics.

[0071] Specifically, lateral charge diffusion in the charge trap (CT) layer of 3D NAND flash memory results in a data retention time of 10 seconds for the data stored in the charge trap layer. 0 s~10 4 The difference in the retention time of stored data in the charge trapping layer is significant, resulting in non-uniformity in data storage time across different storage cells.

[0072] However, in related technologies, when the material is Si... x N y H z When high temperatures are applied to the charge trapping layer, hydrogen atoms become unstable, which weakens their ability to eliminate shallow energy level traps, undoubtedly affecting the electrical characteristics of the device.

[0073] Based on this, various embodiments of the present invention provide a memory and a method for manufacturing the same. By setting the content of the first element in the second part of the charge trapping layer to be greater than the content of the first element in the first part of the charge trapping layer, the first element contained in the second part of the charge trapping layer can compensate for the loss of the first element in the first part of the charge trapping layer during heat treatment, or can be used to block the diffusion of the first element in the first part of the charge trapping layer to the second part of the charge trapping layer, thereby reducing the loss of the first element in the first part of the charge trapping layer; thus enhancing the data retention time of the first part of the charge trapping layer, thereby improving the reliability of the electrical performance of the memory. Specifically,

[0074] This invention provides a method for manufacturing a memory. Figure 2 A flowchart illustrating the implementation of the manufacturing method provided in the embodiments of the present invention is shown below. Figure 2 As shown, the method includes the following steps:

[0075] Step 201: Provide a stacking structure;

[0076] Step 202: Form a storage channel hole (CH, Channel Hole) through the stacked structure;

[0077] Step 203: Form a charge trapping layer on the sidewall of the storage channel aperture;

[0078] The charge trapping layer comprises a first part and a second part that are sequentially stacked along the radial direction of the storage channel hole; the content of the first element in the second part is greater than the content of the first element in the first part.

[0079] Figures 3a-3d This is an example of a cross-sectional view illustrating the fabrication process of a memory according to an embodiment of the present invention. It should be understood that... Figure 2 The operations shown are not exclusive; other operations can be performed before, after, or between any of the operations shown. The following is in conjunction with... Figure 2 , Figures 3a-3d The method for forming the memory in this embodiment is described.

[0080] In practical applications, in step 201, such as Figure 3a As shown, a stacking structure is provided.

[0081] Here, methods for providing a stacked structure include: providing a substrate ( Figure 3a (not shown in the image); a stacked structure is formed on the substrate.

[0082] Here, the substrate may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0083] In practical applications, the stacked structure may include several sacrificial layers 301 (e.g., nitride layers) and insulating layers 302 (e.g., oxide layers) stacked at intervals. Here, the stacked structure is a NO Stack.

[0084] In practical applications, the sacrificial layer 301 and the insulating layer 302 (oxide layer and nitride layer) can be formed through deposition processes; for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or ALD. In some embodiments, the deposition process also includes plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), etc.

[0085] In step 202, as Figure 3b As shown, a storage channel hole 303 is formed that penetrates the stacked structure.

[0086] In practical applications, a memory may include multiple memory channel holes; the memory channel holes 303 are typically formed using a deep hole etching process. In some specific embodiments, the cross-section of the memory channel holes 303 may be circular.

[0087] In step 203, as Figure 3c , 3d As shown, a charge trapping layer 305 is formed on the sidewall of the storage channel hole 303.

[0088] In practical applications, a barrier dielectric layer 304 is formed on the sidewall of the storage channel hole 303 before the charge trapping layer 305 is formed.

[0089] In practical applications, a barrier dielectric layer 304 covers the sidewall surface of the storage channel via 303 to reduce the probability of charge moving from the storage cell to the gate of the storage cell. The material of the barrier dielectric layer 304 may include oxide (OX).

[0090] Methods for forming a barrier dielectric layer include, but are not limited to, CVD, PVD, or ALD.

[0091] It should be noted that, in Figure 3c In the schematic cross-sectional view of the memory shown, the solid line represents one side 30-1 of the memory, and the dashed line represents the other side 30-2 of the memory. Here, for the sake of clearer and more concise description of the intent of the present invention, only one side 30-1 of the memory will be used as an example for explanation in the following figures.

[0092] Next, as Figure 3d As shown, a charge trapping layer 305 is formed on the sidewall of the barrier dielectric layer 304.

[0093] In practical applications, the charge trapping layer 305 is used to trap charges; the material of the charge trapping layer 305 may include hydrogen-containing silicon nitride (SiNH).

[0094] Here, the charge trapping layer 305 includes a first portion 3051 and a second portion 3052 that are sequentially stacked along the radial direction of the storage channel hole.

[0095] In practical applications, the materials of the first portion 3051 and the second portion 3052 forming the charge trapping layer 305 contain the same substances, wherein the content of the first element in the second portion 3052 is greater than the content of the first element in the first portion; here, the second portion 3052 is used to reduce the loss of the first element in the first portion. Specifically,

[0096] During heat treatment (e.g., annealing), for example, when the ambient temperature is between 800°C and 900°C, the first element in the second part 3052 of the charge trapping layer and the first element in the first part 3051 of the charge trapping layer can diffuse into each other. At this time, the first element in the second part 3052 of the charge trapping layer can provide a source of first element for the first part 3051 of the charge trapping layer. In addition, when the ambient temperature is between 400°C and 500°C, the first element in the second part 3052 of the charge trapping layer can block the diffusion of the first part 3051 of the charge trapping layer, thereby reducing the loss of the first element in the first part 3051.

[0097] In some embodiments, the first element includes hydrogen.

[0098] For example, the first portion 3051 of the charge trapping layer is made of Si material. x N y H z The material of the second portion 3052 of the charge trapping layer 305 includes Si. x N y H z’ In the second part 3052, the hydrogen content is greater than that in the first part, that is, Z' is greater than Z.

[0099] It should be noted that the thickness of the second part 3052 of the charge trapping layer is less than the thickness of the first part 3051 of the charge trapping layer. In practical applications, the thickness of the second part 3052 of the charge trapping layer is about 5-6 angstroms, which is less than the thickness of the first part 3051 of the charge trapping layer (about tens of angstroms). Based on this, the second part 3052 of the charge trapping layer is not used for charge storage.

[0100] In practical applications, it can be obtained in a variety of ways. Figure 3d The charge trapping layer 305 shown has a first portion 3051 and a second portion 3052, two of which are described below.

[0101] Method 1

[0102] In some embodiments, such as Figure 4a , 4b As shown, the formation of the charge trapping layer 305 on the sidewall of the storage channel aperture includes:

[0103] A charge trapping material layer 305 is formed on the sidewall of the storage channel hole;

[0104] The surface of the charge-trapping material layer 305 is passivated to form a second portion 3052 of the charge-trapping layer; wherein the charge-trapping material layer that has not undergone the passivation treatment forms a first portion 3051 of the charge-trapping layer.

[0105] In practical applications, a charge trapping material layer 305 is formed on the sidewall of the barrier dielectric layer 304; the surface of the charge trapping material layer 305 is passivated, and the passivated part is the second part 3052 of the charge trapping layer; the unpassivated part is the first part 3051 of the charge trapping layer.

[0106] Here, passivation treatment may include ion implantation on the surface of charge trapping material layer 305, wherein the implanted ions include hydrogen ions; after ion implantation, the hydrogen content in the second part 3052 of the charge trapping layer is greater than the hydrogen content in the first part 3051 of the charge trapping layer.

[0107] Method 2

[0108] In some embodiments, such as Figure 5a , 5b As shown, the formation of the charge trapping layer 305 on the sidewall of the storage channel aperture includes:

[0109] A first portion 3051 of the charge trapping layer is formed on the sidewall of the storage channel hole using a first deposition process;

[0110] A second deposition process is used to form a second portion covering the first portion; wherein the content of the source material containing the first element provided in the second deposition process is greater than the content of the source material containing the first element provided in the first deposition process.

[0111] It should be noted that the first and second deposition processes in Method 2 are similar, but their deposition conditions or environments differ. In practical applications, by changing the deposition conditions of the first and second deposition processes, the content of the first element in the second part 3052 of the charge trapping layer can be made greater than the content of the first element in the first part 3051 of the charge trapping layer.

[0112] For example, under the same deposition conditions (or reaction conditions), the concentration of the reaction source of the first element can be increased during the second deposition process; or the reaction temperature can be increased, the reaction time can be increased, etc., during the second deposition process, all of which can increase the content of the first element in the second part 3052 of the charge trapping layer.

[0113] It should be noted that methods for increasing the content of the first element in the second part 3052 of the charge trapping layer include, but are not limited to, this.

[0114] The present invention will be further described in detail below with reference to specific embodiments.

[0115] For example, during the first deposition process, at a certain reaction temperature, such as 680°C, dichlorosilane (DCS) reacts with NH3 to form the first portion of the charge trapping layer covering the sidewalls of the storage channel apertures, 3051 (Si). x N y H z The first deposition process includes, but is not limited to, CVD, PVD, or ALD.

[0116] The second deposition process is similar to the first deposition process, except that the concentration of hydrogen in the reaction source differs in the second deposition process. Here, by increasing the proportion of hydrogen in DCS and NH3, or by adding other hydrogen-containing substances (i.e., increasing the hydrogen reaction concentration) based on the first deposition process, the second part of the charge trapping layer, 3052 (Si), is formed. x N y H z’ The hydrogen content in the second deposition process is greater than the hydrogen content in the first part 3051 of the charge trapping layer. Here, other hydrogen-containing substances mentioned in the second deposition process may include, but are not limited to, hydrogen gas, deuterium gas, etc.

[0117] For example, the deposition conditions of the second deposition process are based on the deposition conditions of the first deposition process, by increasing the reaction temperature and adjusting the reaction time of DCS and NH3, for example, by increasing the reaction time, to increase the reactivity of hydrogen, thereby making the second part of the charge trapping layer 3052 (Si) more effective. x N y H z’ The hydrogen content in the first part 3051 of the charge trapping layer is greater than the hydrogen content in the second part 3051 of the charge trapping layer.

[0118] Understandably, due to Si x N y H z’ The hydrogen content in the layer is greater than that in Si. x N y H z The hydrogen content in the layer, therefore, Si x N y H z’ The layer can also be understood as hydrogen-rich Si. x N y H z Layer (H-rich Si) x N y H z ).

[0119] The following section will explain hydrogen-rich Si in conjunction with the high-temperature environment of annealing. x N y H zWhy can the layer reduce the loss of the first element in the first part of the charge trapping layer?

[0120] In some embodiments, the method further includes:

[0121] The memory is subjected to annealing; wherein, during the annealing process, the amount of the first element diffused from the second part to the first part is greater than the amount of the first element diffused from the first part to the second part.

[0122] And / or,

[0123] The first element that diffuses from the first part to the second part is repelled by the first element in the second part and returns to the first part.

[0124] In some embodiments, such as Figure 6 As shown, the method further includes:

[0125] After the charge trapping layer is formed, the memory is subjected to a first annealing process under a first temperature condition;

[0126] In the first annealing process, the amount of the first element diffused from the second part to the first part is greater than the amount of the first element diffused from the first part to the second part.

[0127] In practical applications, the temperature of the first annealing treatment is greater than the first temperature; the first temperature is greater than 800℃; preferably, the temperature of the first annealing treatment is 800℃-900℃.

[0128] In practical applications, at the first annealing temperature, the chemical bonds between the atoms of the first element in the charge trapping layer are broken, allowing the first element with suspending bonds to diffuse between the first part 3051 and the second part 3052 of the charge trapping layer.

[0129] Since the content of the first element in the second part 3052 of the charge trapping layer is greater than the content of the first element in the first part 3051 of the charge trapping layer, in the same annealing environment, the diffusion amount of the first element in the second part 3052 of the charge trapping layer into the first part 3051 of the charge trapping layer is greater than the diffusion amount of the first element in the first part 3051 of the charge trapping layer into the second part 3052 of the charge trapping layer.

[0130] For example, during the first annealing process, at a relatively high annealing temperature, such as 800°C-900°C, the hydrogen bonds of the hydrogen elements in the charge trapping layer break, causing Si to... x N y H z’ Layer (i.e., hydrogen-rich Si)x N y H z Hydrogen atoms with suspending bonds in the layer and Si x N y H z Hydrogen atoms with suspending bonds diffuse into each other within the layer.

[0131] Understandably, due to Si x N y H z’ The hydrogen content in the layer is greater than that in Si. x N y H z The hydrogen content in the layer, therefore, Si x N y H z’ Layered Si x N y H z The amount of hydrogen diffused in the layer is greater than that in Si. x N y H z Layered Si x N y H z’ The amount of hydrogen diffused in the layer.

[0132] Based on this, in this embodiment of the invention, by setting the second part 3052 of the charge trapping layer to contain a higher hydrogen content than the first part 3051 of the charge trapping layer, the hydrogen content in the second part of the charge trapping layer can be interchanged with that in the first part of the charge trapping layer under high-temperature heat treatment conditions, or the second part 3052 of the charge trapping layer can serve as a source of hydrogen for the first part 3051 of the charge trapping layer, thereby reducing the loss of hydrogen content in the first part 3051 of the charge trapping layer; thus enhancing the data retention time of the first part 3051 of the charge trapping layer and improving the reliability of the electrical performance of the memory.

[0133] In some embodiments, such as Figure 7 As shown, the method further includes:

[0134] After the charge trapping layer is formed, the memory is subjected to a second annealing process under a second temperature condition;

[0135] During the second annealing process, the first element that diffuses from the first part to the second part is repelled by the first element in the second part and returns to the first part.

[0136] In practical applications, the temperature of the second annealing treatment is lower than the second temperature; the second temperature is less than 500℃; preferably, the temperature of the second annealing treatment is 400℃-500℃.

[0137] In practical applications, at the second annealing temperature, the first element in the charge trapping layer remains relatively active and diffuses outward. However, at this lower temperature (the second annealing temperature), the atomic bond energy of the first element in the charge trapping layer is not broken. Based on this, the first element in the charge trapping layer still diffuses between the first part 3051 and the second part 3052 of the charge trapping layer in atomic form.

[0138] It is understandable that due to the interaction of charges between atoms, a repulsive force is generated between the two atoms (i.e., the principle of attraction between atoms of the same direction and repulsion between atoms of opposite directions). As a result, the first element in the first part 3051 of the charge trapping layer diffuses into the second part 3052 of the charge trapping layer, is repelled by the first element in the second part 3052 of the charge trapping layer, and returns to the first part 3051 of the charge trapping layer.

[0139] For example, during the second annealing process, at a lower annealing temperature, such as 400°C-500°C, Si x N y H z Layered Si x N y H z’ Layer (i.e., hydrogen-rich Si) x N y H z When hydrogen atoms diffuse in the layer, they are reacted with Si. x N y H z’ Layer (i.e., hydrogen-rich Si) x N y H z Hydrogen atoms in the layer are repelled and return to Si. x N y H z layer.

[0140] Based on this, in this embodiment of the invention, by setting the second part 3052 of the charge trapping layer to contain a higher hydrogen content than the first part 3051 of the charge trapping layer, the second part 3052 of the charge trapping layer can act as a barrier layer for hydrogen in the first part 3051 of the charge trapping layer under lower temperature conditions, preventing the leakage of hydrogen from the first part 3051 of the charge trapping layer, thereby reducing the loss of hydrogen in the first part 3051 of the charge trapping layer; thus enhancing the data retention time of the first part 3051 of the charge trapping layer and improving the reliability of the electrical performance of the memory.

[0141] In some embodiments, the method further includes:

[0142] After the charge trapping layer is formed, the memory is subjected to a third annealing process under a third temperature condition;

[0143] During the third annealing process, the amount of the first element diffused from the second part to the first part is greater than the amount of the first element diffused from the first part to the second part; at the same time, the first element diffused from the first part to the second part is repelled by the first element in the second part and returns to the first part.

[0144] In practical applications, the temperature of the third annealing treatment is within the third temperature range; the third temperature is 500℃-800℃.

[0145] During the third annealing process, the first element in the first part 3051 and the second part 3052 of the charge trapping layer may have two situations: the atomic bonds between the atoms of the first element in a portion of the charge trapping layer are broken, causing the first element with dangling bonds to diffuse between the first part 3051 and the second part 3052 of the charge trapping layer; at this time, the amount of the first element diffused from the second part 3052 to the first part 3051 of the charge trapping layer is greater than the amount of the first element diffused from the first part 3051 to the second part 3052 of the charge trapping layer.

[0146] Meanwhile, the atomic bonds of the first element in another part of the charge trapping layer are not broken, and they still diffuse between the first part 3051 and the second part 3052 of the charge trapping layer in atomic form. At this time, the first element that diffuses from the first part 3051 to the second part 3052 of the charge trapping layer is repelled by the first element in the second part 3052 of the charge trapping layer and returns to the first part 3051 of the charge trapping layer.

[0147] Based on this, in this embodiment of the invention, by setting the second part 3052 of the charge trapping layer to contain a higher content of hydrogen than the first part 3051 of the charge trapping layer, the hydrogen in the second part of the charge trapping layer can be interchanged with the hydrogen in the first part of the charge trapping layer under certain temperature conditions, or the hydrogen in the first part of the charge trapping layer can be prevented from diffusing to the second part of the charge trapping layer, thereby reducing the loss of hydrogen in the first part 3051 of the charge trapping layer; thus enhancing the data retention time of the first part 3051 of the charge trapping layer, thereby improving the reliability of the electrical performance of the memory.

[0148] In some embodiments, such as Figure 8 As shown, the method further includes:

[0149] Before forming the charge trapping layer, a barrier dielectric layer 304 is formed on the sidewall of the storage channel hole;

[0150] The formation of the charge trapping layer 305 on the sidewall of the storage channel aperture includes:

[0151] A charge trapping layer 305 is formed covering the barrier dielectric layer 304;

[0152] A tunneling dielectric layer 306 is formed covering the charge trapping layer 305;

[0153] A channel layer 307 is formed covering the tunneling dielectric layer 306.

[0154] In practical applications, a barrier dielectric layer covering the sidewall surface of the memory channel via is used to reduce the probability of charge moving from the memory cell to the gate of the memory cell. The material of the barrier dielectric layer can include oxide (OX). A charge trapping layer covering the surface of the barrier dielectric layer is used to trap charge. The material of the charge trapping layer can include hydrogen-containing silicon nitride (Si). x N y H z The tunneling dielectric layer covering the surface of the charge trapping layer is used to allow charge to tunnel between the storage channel region and the charge trapping layer under the action of an applied voltage. The material of the tunneling dielectric layer may include oxide (OX). The channel layer covering the surface of the tunneling dielectric layer is used to provide support. The material of the channel layer may include polysilicon (Poly).

[0155] In some embodiments, the material of the barrier dielectric layer includes oxides; the material of the tunneling dielectric layer includes nitrogen-doped oxides.

[0156] In practical applications, nitrogen-doped oxides can also be used to adjust the energy levels of tunneling dielectric layers.

[0157] It should be noted that the oxides (such as silicon dioxide) contained in the barrier dielectric layer have fewer defects, thus effectively preventing the diffusion of the first element from the charge trapping layer into the barrier dielectric layer. On the other hand, the tunneling dielectric layer, located on the other side of the charge trapping layer, generally includes nitrogen-doped oxides with more defects, mostly shallow-level defects. Therefore, the first element in the charge trapping layer can easily diffuse into the tunneling dielectric layer.

[0158] Based on this, in various embodiments of the present invention, the content of the first element is increased only on the surface side where the charge trapping layer and the tunneling dielectric layer are in contact, in order to prevent the loss of the first element in the charge trapping layer.

[0159] In some embodiments, the memory includes 3D NAND type memory.

[0160] It should be noted that the memory in the embodiments of the present invention includes, but is not limited to, 3D NAND memory.

[0161] Based on the above-mentioned method for manufacturing memory, combined with Figure 3c , 3d as well as Figure 8 The present invention also provides a memory, comprising:

[0162] Stacked structure;

[0163] Storage channel holes penetrating the stacked structure;

[0164] Charge trapping layer located on the sidewall of the storage channel aperture;

[0165] The charge trapping layer comprises a first part and a second part that are sequentially stacked along the radial direction of the storage channel hole; the content of the first element in the second part is greater than the content of the first element in the first part.

[0166] In some embodiments, the material of the charge trapping layer includes hydrogen-containing silicon nitride; the first element includes hydrogen.

[0167] In some embodiments, the thickness of the second portion is less than the thickness of the first portion; the second portion is not used for storing charge.

[0168] In some embodiments, during the annealing process of the memory...

[0169] The amount of the first element diffused from the second part to the first part is greater than the amount of the first element diffused from the first part to the second part.

[0170] And / or,

[0171] The first element that diffuses from the first part to the second part is repelled by the first element in the second part and returns to the first part.

[0172] In some embodiments, the memory further includes: a barrier dielectric layer, a tunneling dielectric layer, and a channel layer; wherein the barrier dielectric layer is located between the storage channel via sidewall and the charge trapping layer; the tunneling dielectric layer covers the charge trapping layer; and the channel layer covers the tunneling dielectric layer.

[0173] In some embodiments, the material of the barrier dielectric layer includes oxides; the material of the tunneling dielectric layer includes nitrogen-doped oxides.

[0174] In some embodiments, the memory includes 3D NAND type memory.

[0175] It should be noted that the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.

[0176] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A memory, characterized in that, include: Stacked structure; Storage channel holes penetrating the stacked structure; Charge trapping layer located on the sidewall of the storage channel aperture; The charge trapping layer comprises a first portion and a second portion sequentially stacked radially along the storage channel aperture; the content of a first element in the second portion is greater than the content of a first element in the first portion; the material of the charge trapping layer comprises hydrogen-containing silicon nitride; and the first element comprises hydrogen.

2. The memory according to claim 1, characterized in that, The thickness of the second part is less than that of the first part; the second part is not used for charge storage.

3. The memory according to claim 1, characterized in that, During the annealing process of the memory... The amount of the first element diffused from the second part to the first part is greater than the amount of the first element diffused from the first part to the second part. And / or, The first element that diffuses from the first part to the second part is repelled by the first element in the second part and returns to the first part.

4. The memory according to claim 1, characterized in that, The memory also includes: a barrier dielectric layer, a tunneling dielectric layer, and a channel layer; The barrier dielectric layer is located between the storage channel via sidewall and the charge trapping layer; the tunneling dielectric layer covers the charge trapping layer; and the channel layer covers the tunneling dielectric layer.

5. The memory according to claim 4, characterized in that, The material of the barrier dielectric layer includes oxides; the material of the tunneling dielectric layer includes nitrogen-doped oxides.

6. The memory according to claim 1, characterized in that, The memory includes a three-dimensional NAND type memory.

7. A method for manufacturing a memory, characterized in that, include: Provide a stacking structure; Forming storage channel holes that penetrate the stacked structure; A charge trapping layer is formed on the sidewall of the storage channel hole; The charge trapping layer comprises a first portion and a second portion sequentially stacked radially along the storage channel aperture; the content of a first element in the second portion is greater than the content of a first element in the first portion; the material of the charge trapping layer comprises hydrogen-containing silicon nitride; and the first element comprises hydrogen.

8. The manufacturing method according to claim 7, characterized in that, The formation of a charge trapping layer on the sidewall of the storage channel aperture includes: A charge-capturing material layer is formed on the sidewall of the storage channel hole; The surface of the charge-trapping material layer is passivated to form a second portion of the charge-trapping layer; wherein the charge-trapping material layer that has not undergone the passivation treatment forms a first portion of the charge-trapping layer.

9. The manufacturing method according to claim 7, characterized in that, The formation of a charge trapping layer on the sidewall of the storage channel aperture includes: A first portion of the charge trapping layer is formed on the sidewall of the storage channel hole using a first deposition process; A second deposition process is used to form a second portion covering the first portion; wherein the content of the source material containing the first element provided in the second deposition process is greater than the content of the source material containing the first element provided in the first deposition process.

10. The manufacturing method according to claim 7, characterized in that, The method further includes: The memory is subjected to annealing; wherein, during the annealing process, the amount of the first element diffused from the second part to the first part is greater than the amount of the first element diffused from the first part to the second part. And / or, The first element that diffuses from the first part to the second part is repelled by the first element in the second part and returns to the first part.

11. The manufacturing method according to claim 7, characterized in that, The method further includes: Before forming the charge trapping layer, a barrier dielectric layer is formed on the sidewall of the storage channel hole; The formation of a charge trapping layer on the sidewall of the storage channel aperture includes: A charge trapping layer is formed covering the barrier dielectric layer; Form a tunneling dielectric layer covering the charge trapping layer; A channel layer is formed covering the tunneling dielectric layer.

12. The manufacturing method according to claim 11, characterized in that, The material of the barrier dielectric layer includes oxides; the material of the tunneling dielectric layer includes nitrogen-doped oxides.

13. The manufacturing method according to claim 7, characterized in that, The memory includes a three-dimensional NAND type memory.

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