A reverse conducting insulated gate bipolar transistor and a method for manufacturing the same

Abstract

The present application provides a reverse-conducting insulated gate bipolar transistor and a method for manufacturing the same, wherein the transistor comprises: a silicon SOI wafer on an insulating substrate, the SOI wafer comprising a first epitaxial layer, a second epitaxial layer, and a first oxide layer arranged in sequence; a collector region and a short-circuit region arranged in the first oxide layer at intervals, and a first metal layer arranged on a side of the first oxide layer that is not in contact with the second epitaxial layer, forming a collector structure of the reverse-conducting insulated gate bipolar transistor. Through the present application, the technical problems of complex process and large leakage current existing in the conventional reverse-conducting IGBT in the prior art are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. Background Art

[0002] A reverse-conducting insulated gate bipolar transistor (IGBT) is an IGBT that has a fast recovery diode (FRD) integrated inside and has the capability of conducting reverse current. Conventional reverse-conducting IGBTs in the prior art have technical problems of complex process and large leakage current. Summary of the invention

[0003] The purpose of the embodiment of the present application is to provide a reverse conducting insulated gate bipolar transistor and a method for manufacturing the same, which solves the technical problems of complex process and large leakage current of the conventional reverse conducting IGBT in the prior art. The specific technical solution is as follows:

[0004] In the first aspect of the implementation of the present application, a reverse conducting insulated gate bipolar transistor is first provided, and the transistor includes: a silicon SOI wafer on an insulating substrate, the SOI wafer includes a first epitaxial layer, a second epitaxial layer, and a first oxide layer arranged in sequence; a collector region and a short-circuit region arranged at intervals in the first oxide layer, and a first metal layer arranged on a side of the first oxide layer that is not in contact with the second epitaxial layer, to form a collector structure of the reverse conducting insulated gate bipolar transistor.

[0005] In the second aspect of the implementation of the present application, a method for manufacturing a reverse conducting insulated gate bipolar transistor is also provided, the method comprising: thinning the substrate of an unprocessed SOI wafer to a first oxide layer to obtain an SOI wafer; exposing and developing the SOI wafer based on a first photomask; etching the first oxide layer of the processed SOI wafer to obtain a short-circuit area; exposing and developing the SOI wafer based on a second photomask; etching the first oxide layer of the processed SOI wafer to obtain a collector area.

[0006] The reverse conducting insulated gate bipolar transistor and its manufacturing method provided in the embodiment of the present application are based on the reverse conducting insulated gate bipolar transistor including a silicon SOI wafer on an insulating substrate and a collector structure, and the substrate of the unprocessed SOI wafer is thinned to the first oxide layer to obtain the SOI wafer; the SOI wafer is exposed and developed based on the first photolithography; the first oxide layer of the processed SOI wafer is etched to obtain the short-circuit area; the SOI wafer is exposed and developed based on the second photolithography; the first oxide layer of the processed SOI wafer is etched to obtain the collector area; the reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application is manufactured based on the SOI wafer, and the collector area and the short-circuit area are arranged in the oxide layer at intervals, thereby solving the technical problems of complex process and large leakage current existing in the traditional reverse conducting IGBT in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0008] Figure 1 This is one of the cross-sectional schematic diagrams of a reverse conducting insulated gate bipolar transistor in an embodiment of the present application;

[0009] Figure 2 This is the second cross-sectional schematic diagram of the reverse conducting insulated gate bipolar transistor in the embodiment of the present application;

[0010] Figure 3 This is one of the flow charts of the method for manufacturing a reverse conducting insulated gate bipolar transistor in an embodiment of the present application;

[0011] Figure 4 This is a schematic diagram of the superposition of the first photoresist plate and the second photoresist plate in an embodiment of the present application;

[0012] Figure 5 This is the second flow chart of the method for manufacturing a reverse conducting insulated gate bipolar transistor in an embodiment of the present application;

[0013] Figure 6 This is the third flow chart of the method for manufacturing a reverse conducting insulated gate bipolar transistor in an embodiment of the present application;

[0014] Figure 7 This is a fourth flow chart of a method for manufacturing a reverse conducting insulated gate bipolar transistor in an embodiment of the present application;

[0015] Figure 8 This is the fifth flow chart of the method for manufacturing a reverse conducting insulated gate bipolar transistor in the embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0017] In the following description, the suffixes such as "module" and "unit" used to represent elements are only used to facilitate the description of the present application, and they themselves have no specific meaning. Therefore, "module" and "component" can be used interchangeably.

[0018] The technical solution in the embodiment of the present application will be described below in conjunction with the accompanying drawings in the embodiment of the present application. The embodiment of the present application provides a reverse conducting insulated gate bipolar transistor, such as Figure 1 As shown, the transistor includes: a silicon on insulating substrate (Silicon On Insulator, referred to as SOI) wafer, the SOI wafer includes a first epitaxial layer, a second epitaxial layer, and a first oxide layer arranged in sequence;

[0019] The collector region and the short-circuit region are arranged in the first oxide layer at intervals, and the first metal layer is arranged on the side of the first oxide layer that is not in contact with the second epitaxial layer, forming the collector structure of the reverse conducting insulated gate bipolar transistor.

[0020] Among them, it should be noted that the SOI wafer has undergone substrate thinning treatment and has been thinned to the first oxide layer; the first epitaxial layer is a low-doped N-type epitaxial layer; the second epitaxial layer is a highly doped N-type epitaxial layer; the collector region can be a highly doped P-type collector region; and the short-circuit region can be a highly doped N-type diode.

[0021] Through the above-mentioned structure of the embodiment of the present application, the transistor includes an SOI wafer, the SOI wafer includes a first epitaxial layer, a second epitaxial layer, and a first oxide layer arranged in sequence; a collector region and a short-circuit region are spaced apart in the first oxide layer, and a first metal layer is arranged on a side of the first oxide layer that is not in contact with the second epitaxial layer, forming a collector structure of a reverse conducting insulated gate bipolar transistor; the reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application is made based on an SOI wafer and the collector region and the short-circuit region are spaced apart in the oxide layer, thereby solving the technical problems of complex process and large leakage current existing in the traditional reverse conducting IGBT in the prior art.

[0022] In an optional implementation of the embodiment of the present application, the reverse conducting insulated gate bipolar transistor provided in the present application includes: a second oxide layer and a polysilicon gate;

[0023] The polysilicon gate is built into a groove obtained by groove etching in the first epitaxial layer, and a second oxide layer is arranged on the surface of the polysilicon gate and on a side of the first epitaxial layer that is not in contact with the second epitaxial layer.

[0024] It should be noted that the second oxide layer refers to the gate oxide layer.

[0025] It can be seen that the surface of the polysilicon gate of the reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application has a gate oxide layer which plays an insulating effect.

[0026] In an optional implementation of the embodiment of the present application, the reverse conducting insulated gate bipolar transistor provided by the present application is as follows: Figure 2 As shown, it includes: a base region, an emitter region and a second metal layer;

[0027] The base region is located between the first epitaxial layer and the second oxide layer on both sides of the trench; the emitter region is located in the base region on both sides of the trench, and the side of the emitter region not in contact with the base region is in contact with the second metal layer and the second oxide layer; the second metal layer is in partial contact with the base region.

[0028] Among them, it should be noted that the base region can be a P-type base region, preferably a P-type base region formed by injecting boron ions; the emitter region can be a highly doped N-type emitter region, or it can be a highly doped N-type emitter region formed by injecting phosphorus ions, preferably a highly doped N-type emitter region formed by injecting arsenic ions.

[0029] In an optional implementation manner of the embodiment of the present application, the reverse conducting insulated gate bipolar transistor provided in the present application includes:

[0030] The first epitaxial layer is a low-doped N-type epitaxial layer, and the second epitaxial layer is a high-doped N-type epitaxial layer.

[0031] The present invention provides a method for manufacturing a reverse-conducting insulated gate bipolar transistor. Figure 3 As shown, the method includes:

[0032] Step 302: thinning the substrate of the unprocessed SOI wafer to the first oxide layer to obtain an SOI wafer;

[0033] Step 304: exposing and developing the SOI wafer based on the first photoresist;

[0034] Step 306: etching the first oxide layer of the processed SOI wafer to obtain a short-circuit area;

[0035] Step 308: exposing and developing the SOI wafer based on the second photomask;

[0036] Step 310: Etching the first oxide layer of the processed SOI wafer to obtain a collector region.

[0037] It should be noted that the unprocessed SOI wafer includes a first epitaxial layer, a second epitaxial layer, a first oxide layer, and a substrate arranged in sequence; the exposure area of ​​the first photoresist is a plurality of parallel and staggered rectangles, and the exposure area of ​​the second photoresist is a plurality of parallel and staggered rectangles that do not overlap with the exposure area of ​​the first photoresist. The schematic diagram of the superposition of the first photoresist and the second photoresist is as shown in FIG. Figure 4 As shown; the collector region can be a highly doped P-type collector region, and the short-circuit region can be a highly doped N-type diode.

[0038] The method for manufacturing a reverse conducting insulated gate bipolar transistor in an embodiment of the present application is to obtain an SOI wafer by thinning the substrate of an unprocessed SOI wafer to a first oxide layer; exposing and developing the SOI wafer on a first photomask; etching the first oxide layer of the processed SOI wafer to obtain a short-circuit region; exposing and developing the SOI wafer based on a second photomask; etching the first oxide layer of the processed SOI wafer to obtain a collector region; the method for manufacturing a reverse conducting insulated gate bipolar transistor provided in an embodiment of the present application manufactures a reverse conducting insulated gate bipolar transistor in which a collector region and a short-circuit region are spaced apart and arranged in an oxide layer based on an SOI wafer, thereby solving the technical problems of complex process and large leakage current of traditional reverse conducting IGBTs in the prior art.

[0039] In an optional implementation of the embodiment of the present application, the method for manufacturing a reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application, before step 302, as Figure 5 As shown, including:

[0040] Step 502: depositing an oxide layer on the first epitaxial layer, and applying glue to the deposited oxide layer;

[0041] It should be noted that the first epitaxial layer is a low-doped N-type epitaxial layer.

[0042] Step 504: exposing and developing the SOI wafer based on the third photomask;

[0043] It should be noted that the third photoresist plate refers to a trench photoresist plate.

[0044] Step 506: etching the oxide layer of the first epitaxial layer of the processed SOI wafer, and performing trench etching based on the etched oxide layer;

[0045] Step 508: removing the oxide layer in the trench after the trench etching is completed, and growing the gate oxide layer after the removal.

[0046] It should be noted that the gate oxide layer plays an insulating role.

[0047] It can be seen that the method for manufacturing the reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application performs trench etching through a Trench photomask and grows a gate oxide layer in the trench to prevent the polysilicon gate from directly contacting the first epitaxial layer.

[0048] In an optional implementation of the embodiment of the present application, the method for manufacturing a reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application, before step 302, as Figure 6 As shown, including:

[0049] Step 602: exposing and developing the SOI wafer based on a fourth photomask;

[0050] It should be noted that the fourth photoresist plate refers to a polysilicon (Poly) photoresist plate.

[0051] Step 604: performing polysilicon etching on the trenches of the first epitaxial layer of the processed SOI wafer.

[0052] In an optional implementation of the embodiment of the present application, the method for manufacturing a reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application, before step 302, as Figure 7 As shown, including:

[0053] Step 702: implanting P-type semiconductor ions on both sides of the trench to form a base region;

[0054] It should be noted that the ions of the P-type semiconductor are preferably boron ions.

[0055] Step 704: Implant ions that form an N-type semiconductor into the base region to form an emitter region.

[0056] It should be noted that the ions of the N-type semiconductor are preferably arsenic ions, but may also be phosphorus ions.

[0057] In an optional implementation manner of an embodiment of the present application, the method for manufacturing a reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application, before step 302, includes: depositing and growing a gate oxide layer on a side of the polysilicon gate that is not in the trench and on a side of the emitter region that is not in contact with the base region, to form a second oxide layer together with the gate oxide layer in the trench.

[0058] It should be noted that the second oxide layer is a gate oxide layer, which plays an insulating role.

[0059] In an optional implementation of the embodiment of the present application, the method for manufacturing a reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application, after step 310, as Figure 8 As shown, including:

[0060] Step 802: performing exposure and development processing on the SOI wafer based on the fifth photoresist;

[0061] It should be noted that the fifth photoresist plate refers to a contact photoresist plate.

[0062] Step 804: etching the oxide layer of the processed SOI wafer;

[0063] It should be noted that after etching, the oxide layer forms a second oxide layer together with the gate oxide layer in the trench, the base region does not contact the oxide layer, part of the emitter does not contact the oxide layer, and the surface of the polysilicon gate contacts the oxide layer.

[0064] Step 806: depositing a metal layer and applying glue to the etched area;

[0065] Step 808: performing exposure and development processing on the SOI wafer based on the sixth photoresist;

[0066] It should be noted that the sixth photoresist plate refers to a metal photoresist plate.

[0067] Step 810: Perform metal etching on the processed SOI wafer.

[0068] It should be noted that the second metal layer is obtained after metal etching.

[0069] An exemplary method for manufacturing a reverse conducting insulated gate bipolar transistor provided in an embodiment of the present application is based on a SOI wafer having a first epitaxial layer, a second epitaxial layer, a first oxide layer and a substrate sequentially provided thereon, and the manufacturing process includes:

[0070] Step 902: depositing an oxide layer on the low-doped N-type epitaxial layer, and applying glue to the deposited oxide layer;

[0071] Step 904: exposing and developing the SOI wafer based on the Trench photomask;

[0072] Step 906: etching the oxide layer of the low-doped N-type epitaxial layer of the processed SOI wafer, and performing trench etching based on the etched oxide layer;

[0073] Step 908: removing the oxide layer in the trench after the trench etching is completed, and growing the gate oxide layer after the removal;

[0074] Step 910: exposing and developing the SOI wafer based on the Poly photomask;

[0075] Step 912: etching the trench with polysilicon;

[0076] Step 914: implanting boron ions on both sides of the trench to form a P-type base region;

[0077] Step 916: implanting arsenic ions into the base region to form an N-type emitter region;

[0078] Step 918: depositing and growing a gate oxide layer on a side of the polysilicon gate that is not in the trench and a side of the N-type emitter region that is not in contact with the P-type base region, to form a second oxide layer together with the gate oxide layer in the trench;

[0079] Step 920: thinning the substrate to a first oxide layer;

[0080] Step 922: exposing and developing the SOI wafer based on the first photoresist;

[0081] Step 924: Etching the first oxide layer of the processed SOI wafer to obtain a highly doped N-type diode;

[0082] Step 926: exposing and developing the SOI wafer based on the second photomask;

[0083] Step 928: Etching the first oxide layer of the processed SOI wafer to obtain a highly doped P-type collector region;

[0084] Step 930: performing exposure and development processing on the SOI wafer based on the Contact photoresist;

[0085] Step 932: etching the second oxide layer of the processed SOI wafer;

[0086] Step 934: depositing a metal layer and applying glue to the etched area;

[0087] Step 936: performing exposure and development processing on the SOI wafer based on the Metal photomask;

[0088] Step 938: Perform metal etching on the processed SOI wafer to obtain a second metal layer.

[0089] It can be seen that the method for manufacturing a reverse conducting insulated gate bipolar transistor provided in the embodiment of the present application is based on an SOI wafer to manufacture a reverse conducting insulated gate bipolar transistor in which a collector region and a short circuit region are separated and arranged in an oxide layer, thereby solving the technical problems of complex process and large leakage current existing in traditional reverse conducting IGBTs in the prior art.

[0090] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0091] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0092] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A reverse conducting insulated gate bipolar transistor, characterized in that: include: A silicon SOI wafer on an insulating substrate, wherein the SOI wafer comprises a first epitaxial layer, a second epitaxial layer, and a first oxide layer arranged in sequence; The collector region and the short-circuit region are arranged in the first oxide layer at intervals, and the first metal layer is arranged on the side of the first oxide layer that is not in contact with the second epitaxial layer, forming the collector structure of the reverse conducting insulated gate bipolar transistor; wherein the collector region and the short-circuit region are arranged in the first oxide layer at intervals, which means that the collector regions are arranged on both sides of the short-circuit region, and the first oxide layer is between the short-circuit region and the collector region; Wherein, the reverse conducting insulated gate bipolar transistor comprises: a second oxide layer and a polysilicon gate; The polysilicon gate is built into a groove obtained by trench etching in the first epitaxial layer, and the second oxide layer is provided on the surface of the polysilicon gate and on a side of the first epitaxial layer not in contact with the second epitaxial layer. The second oxide layer is a gate oxide layer.

2. The reverse conducting insulated gate bipolar transistor according to claim 1, characterized in that: include: A base region, an emitter region, and a second metal layer; The base region is located between the first epitaxial layer and the second oxide layer on both sides of the trench; The emitter region is located in the base region on both sides of the groove, and a side of the emitter region not in contact with the base region is in contact with the second metal layer and the second oxide layer; the second metal layer is in partial contact with the base region. 3 . The reverse conducting insulated gate bipolar transistor according to claim 1 , wherein the first epitaxial layer is a low-doped N-type epitaxial layer, and the second epitaxial layer is a high-doped N-type epitaxial layer.

4. A method for manufacturing a reverse conducting insulated gate bipolar transistor according to any one of claims 1 to 3, characterized in that: include: Thinning the substrate of an untreated SOI wafer to the first oxide layer to obtain the SOI wafer; Expose and develop the SOI wafer based on a first photoresist; Etching the first oxide layer of the processed SOI wafer to obtain the short-circuit area; Expose and develop the SOI wafer based on a second photoresist; The collector region is obtained by etching the first oxide layer of the processed SOI wafer; wherein the collector region and the short-circuit region are arranged in the first oxide layer at intervals, and the collector region is arranged on both sides of the short-circuit region; Before the SOI wafer is exposed and developed based on the first photomask, the method includes: depositing an oxide layer on the first epitaxial layer and applying glue to the deposited oxide layer; exposing and developing the SOI wafer based on the third photomask; etching the oxide layer of the first epitaxial layer of the processed SOI wafer, and performing groove etching based on the etched oxide layer; removing the oxide layer in the groove after the groove etching is completed, and growing a gate oxide layer after the removal; Before exposing and developing the SOI wafer based on the first photomask, the method further includes: exposing and developing the SOI wafer based on a fourth photomask; and performing polysilicon etching on the grooves of the first epitaxial layer of the processed SOI wafer; Before the SOI wafer is exposed and developed based on the first photomask, the method further comprises: injecting ions of a P-type semiconductor on both sides of the groove to form a base region; and injecting ions of an N-type semiconductor into the base region to form an emitter region; Among them, before the SOI wafer is exposed and developed based on the first photolithography, the method also includes: depositing and growing a gate oxide layer on a side of the polysilicon gate that is not in the groove and on a side of the emitter region that is not in contact with the base region, to form a second oxide layer together with the gate oxide layer in the groove; the second oxide layer is a gate oxide layer.

5. The method according to claim 4, characterized in that After etching the first oxide layer of the processed SOI wafer to obtain the collector region, the method further includes: Performing exposure and development processing on the SOI wafer based on a fifth photoresist; Etching the oxide layer of the processed SOI wafer; Depositing a metal layer and applying glue to the etched area; Performing exposure and development processing on the SOI wafer based on a sixth photoresist; The processed SOI wafer is subjected to metal etching.

Images