Memory based on charge injection mechanism and preparation method thereof

Abstract

The present invention discloses a memory based on a charge injection mechanism and a preparation method thereof, which can be applied to the field of memory technology. The memory of the present invention comprises: a substrate; a control gate layer, the control gate layer comprising tungsten selenide, which is located on the substrate, and a gate electrode is provided on the first end of the control gate layer for connecting to an external applied voltage; a threshold switching layer, the threshold switching layer comprising oxidized graphene with threshold conversion characteristics, the first end of which is located on the substrate, and the second end of which is located on the first end of the control gate layer; a charge storage layer, the charge storage layer comprising molybdenum sulfide, which is located on the threshold switching layer; a blocking layer, which is located on the charge storage layer; a channel layer, which is located on the blocking layer, a source electrode is provided on the first end of the channel layer, and a drain electrode is provided on the second end of the channel layer. The present invention can achieve ultra-fast write or erase operations.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory based on a charge injection mechanism and a preparation method thereof. Background Art

[0002] Continuous innovation in memory technologies, including random access memory (RAM) and flash memory (Flash), has fueled the rapid development of the information age. With the advent of the big data era, data is exponentially increasing. Currently, mainstream commercial silicon-based memory suffers from shortcomings such as slow operation, low storage capacity, complex structure, and high energy consumption, making it unable to meet the demands of big data storage and access. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a memory based on a charge injection mechanism and a method for preparing the same, which can achieve ultrafast injection and achieve high-speed, low-power non-volatile storage.

[0004] In one aspect, an embodiment of the present invention provides a memory based on a charge injection mechanism, comprising:

[0005] substrate;

[0006] a control gate layer, the control gate layer comprising tungsten selenide, the control gate layer being located on the substrate, a gate electrode being provided on a first end of the control gate layer for connecting to an externally applied voltage;

[0007] a threshold switching layer, the threshold switching layer comprising GO having a threshold switching characteristic, wherein a first end of the threshold switching layer is located above the substrate, and a second end of the threshold switching layer is located above the first end of the control gate layer;

[0008] a charge storage layer, the charge storage layer comprising molybdenum sulfide, the charge storage layer being located above the threshold switch layer;

[0009] a blocking layer, the blocking layer being located on the charge storage layer;

[0010] A channel layer is located on the barrier layer, a source electrode is provided on a first end of the channel layer, and a drain electrode is provided on a second end of the channel layer.

[0011] The memory based on the charge injection mechanism provided in this embodiment has the following beneficial effects:

[0012] In this embodiment, a control gate layer, a threshold switching layer, a charge storage layer, a blocking layer, and a channel layer are stacked in sequence on a substrate. At the same time, the first end of the threshold switching layer is located above the substrate, and the second end of the threshold switching layer is located above the first end of the control gate layer. A gate electrode for connecting to an externally applied voltage is provided on the first end of the control gate layer, and a source electrode and a drain electrode are provided on the channel layer. The control gate and the charge storage layer are connected through GO with threshold conversion characteristics to achieve low-voltage ultrafast non-volatile storage, while achieving the characteristic of direct charge injection into the charge storage layer, thereby achieving ultrafast write or erase operations.

[0013] In some embodiments, the channel layer includes molybdenum sulfide.

[0014] In some embodiments, the substrate comprises a silicon substrate.

[0015] In some embodiments, the barrier layer includes boron nitride.

[0016] In some embodiments, the gate electrode, the source electrode, and the drain electrode include chromium and gold materials.

[0017] On the other hand, an embodiment of the present invention provides a method for preparing a memory based on a charge injection mechanism, comprising the following steps:

[0018] The Graphyne film is treated with ozone to obtain Graphyne oxide as the threshold switching layer;

[0019] A charge storage layer, a channel layer, a barrier layer and a control gate layer containing tungsten selenide are prepared by mechanical stripping;

[0020] stacking the control gate layer, the threshold switch layer, the charge storage layer, the blocking layer and the channel layer on a substrate in sequence;

[0021] A gate electrode is formed on the control gate layer by photolithography and thermal evaporation, and a source electrode and a drain electrode are formed on the channel layer respectively;

[0022] The control gate layer and the charge storage layer are connected via graphene oxide having a threshold switching characteristic.

[0023] In some embodiments, stacking the control gate layer, the threshold switch layer, the charge storage layer, the blocking layer, and the channel layer on the substrate in sequence includes:

[0024] The control gate layer, the threshold switch layer, the charge storage layer, the blocking layer and the channel layer are stacked in sequence on a substrate by using a van der Waals stacking method.

[0025] In some embodiments, the method of forming a gate electrode on the control gate layer and a source electrode and a drain electrode on the channel layer by photolithography and thermal evaporation includes:

[0026] Electrodes composed of chromium and gold materials are prepared on the control gate layer as a gate electrode by photolithography and thermal evaporation, and electrodes composed of chromium and gold materials are respectively prepared on the channel layer as a source electrode and a drain electrode.

[0027] In some embodiments, the channel layer includes molybdenum sulfide.

[0028] In some embodiments, the barrier layer includes boron nitride.

[0029] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0031] Figure 1 Schematic diagram of the structure of a memory based on a charge injection mechanism according to an embodiment of the present invention;

[0032] Figure 2 This is a flow chart of a method for preparing a memory based on a charge injection mechanism according to an embodiment of the present invention;

[0033] Figure 3 is a current-voltage curve diagram for the positive voltage segment 2a according to an embodiment of the present invention;

[0034] Figure 4 is a current-voltage curve diagram for the negative voltage segment 2b according to an embodiment of the present invention;

[0035] Figure 5 This is a test chart of the write and erase capability according to an embodiment of the present invention;

[0036] Figure 6 A test chart of the reading speed of an embodiment of the present invention;

[0037] Figure 7 This is a durability test diagram of an embodiment of the present invention;

[0038] Figure 8 This is a stability test diagram of an embodiment of the present invention;

[0039] Figure 9 Schematic diagram of the mechanism when a nanosecond negative pulse voltage is applied to the control gate terminal according to an embodiment of the present invention;

[0040] Figure 10Schematic diagram of the mechanism of the embodiment of the present invention after the negative voltage pulse is removed;

[0041] Figure 11 Schematic diagram of the mechanism when a symmetrical nanosecond-level positive voltage is applied to the control gate according to an embodiment of the present invention;

[0042] Figure 12 Schematic diagram of the mechanism of the embodiment of the present invention after the positive voltage pulse is removed;

[0043] Figure 13 is a diagram showing the robustness characteristics of an embodiment of the present invention within a temperature range;

[0044] Figure 14 This is a diagram showing the robustness of the embodiment of the present invention within a range of days of placement;

[0045] Figure 15 This is a multi-bit storage capacity test diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0047] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0048] In the description of the present invention, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0049] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0050] In the description of the present invention, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0051] Currently, mainstream commercial silicon-based memory has disadvantages such as slow operation speed, low storage capacity, complex structure and high energy consumption, which is not conducive to the development of new low-energy chips in the post-Moore era. Therefore, there is an urgent need for a processor and memory that combines ultra-fast response, ultra-low voltage, ultra-long retention, ultra-high capacity and ultra-low energy consumption to meet the growing data demand.

[0052] Among related technologies, resistive switching memories based on two-dimensional materials have been extensively studied by researchers. Due to its excellent properties such as fast switching and high on / off ratio, resistive switching memories based on threshold switching are widely used in the fields of volatile storage and short-term plasticity artificial synapses. The working mechanism of threshold switching memories is that under the action of an electric field, ions are driven to form a conductive path within the threshold characteristic material, which quickly returns to its initial state after the power is cut off, thus achieving a rapid switching process. Therefore, the selection of materials that are prone to the formation of oxygen vacancies and defect vacancies is conducive to the formation of conductive filaments, thereby facilitating the realization of threshold switching.

[0053] Van der Waals stacking greatly facilitates the construction of multifunctional heterojunctions and provides a strategy for developing new ultrafast, low-power memories. Floating-gate memories based on van der Waals stacking can achieve ultrafast non-volatile storage. Due to the atomically sharp interfaces between the layers, they enable ultrafast tunneling based on the Fowler–Nordheim tunneling mechanism, breaking the limitations of the "memory wall." However, conventional floating-gate memories often require high operating voltages (tens of volts), which results in higher energy consumption for memory devices based on the Fowler–Nordheim tunneling mechanism and limits their application in complementary metal oxide semiconductors (CMOS). To overcome the limitations of the Fowler–Nordheim tunneling mechanism, it is urgently necessary to design a new device structure to achieve ultrafast charge injection at low voltages.

[0054] Based on this, refer to Figure 1An embodiment of the present invention provides a memory device based on a charge injection mechanism, comprising a substrate 110, a control gate layer 120, a threshold switching layer 130, a charge storage layer 140, a barrier layer 150, and a channel layer 160. Specifically, the substrate 110 can be a silicon substrate. The control gate layer 120 comprises tungsten selenide (WSe2), which is located above the substrate 110. A gate electrode 170 is provided on the first end of the control gate layer 120 for connecting to an externally applied voltage. The threshold switching layer 130 comprises graphene oxide (GDYO) having threshold switching characteristics. The graphene oxide (GDYO) is a material with known threshold characteristics, with a first end located above the substrate 110 and a second end located above the first end of the control gate layer 120. The control gate layer 120 and the charge storage layer 140 are connected via the graphene oxide (GDYO) having threshold switching characteristics, enabling ultrafast write or erase operations by directly injecting charge into the charge storage layer 140, thereby realizing low-voltage ultrafast non-volatile storage. The charge storage layer 140, comprising molybdenum sulfide (MoS2), is located above the threshold switching layer 130. A barrier layer 150 is located above the charge storage layer 140. A channel layer 160 is located above the barrier layer 150. A source electrode 180 is located on a first end of the channel layer 160, and a drain electrode 190 is located on a second end of the channel layer 160. The gate electrode 170, source electrode 180, and drain electrode 190 are all composed of chromium and gold. The chromium (Cr) is 5 nm thick, and the gold (Au) is 50 nm thick.

[0055] In this embodiment, the channel layer also includes molybdenum sulfide (MoS2), and the barrier layer includes boron nitride (hBN). A charge storage layer composed of the bottom molybdenum sulfide (MoS2) is located above the threshold switching layer and is used to store charge injected from the control gate composed of tungsten selenide (WSe2). A barrier layer composed of boron nitride (hBN) is located between the charge storage layer and the channel layer and is used to block charge from the charge storage layer from being injected into the top channel layer composed of molybdenum sulfide (MoS2). The top channel layer composed of molybdenum sulfide (MoS2) is located on the boron nitride (hBN) and is affected by the charge stored in the bottom molybdenum sulfide (MoS2), exhibiting different conductivity states.

[0056] The memory of this embodiment uses a threshold switch layer RS to connect a control gate and a charge storage layer to achieve low-voltage ultra-fast non-volatile storage. The threshold switch layer allows the control gate layer to directly inject charge into the charge storage layer to perform ultra-fast write / erase operations, and the write / erase operation can be completed in about 20ns; the injected charge is confined in the charge storage layer, which can also be understood as being confined in the floating gate and can be retained for a long time, for about 10 years. In particular, compared with traditional floating gate memory, the memory of this embodiment can be driven by a low voltage (about 2V) and can achieve ultra-low energy consumption of 10fJ. In addition, the high on / off ratio (10 7) and nanosecond operation speed enable the memory to achieve 3-bit storage with a write pulse of a few nanoseconds, meeting the requirements of ultra-high speed, ultra-long retention, ultra-high capacity and ultra-low energy consumption.

[0057] In this embodiment, graphyne has abundant π electrons and inherent defects, and can be used as a new type of threshold switching characteristic material. The oxygen vacancy concentration on the surface of graphyne can be increased by ozone treatment, and then a conductive path of oxygen vacancies and defect vacancies can be formed by electrical induction, thereby realizing threshold switching.

[0058] Based on this, Figure 2 As shown, an embodiment of the present invention provides a method for preparing a memory based on a charge injection mechanism, comprising the following steps:

[0059] S210, treating the graphyne film with ozone to obtain graphyne oxide as a threshold switch layer;

[0060] S220, preparing a charge storage layer, a channel layer, a barrier layer, and a control gate layer containing tungsten selenide by mechanical stripping;

[0061] S230: Stacking a control gate layer, a threshold switching layer, a charge storage layer, a barrier layer, and a channel layer sequentially on a substrate, wherein the control gate layer and the charge storage layer are connected via GO having threshold switching characteristics. Specifically, the control gate layer, the threshold switching layer, the charge storage layer, the barrier layer, and the channel layer can be stacked sequentially on the substrate using a van der Waals stacking method. The charge storage layer and the channel layer both include molybdenum sulfide, and the barrier layer includes boron nitride.

[0062] S240: A gate electrode is formed on the control gate layer, and a source electrode and a drain electrode are formed on the channel layer using photolithography and thermal evaporation. Specifically, the gate electrode, source electrode, and drain electrode are all composed of chromium and gold. The chromium (Cr) is 5 nm thick, and the gold (Au) is 50 nm thick.

[0063] In this embodiment, because current Fowler–Nordheim tunneling memories utilize a band-tilted tunneling mechanism, they require a relatively high operating voltage. Compared to current tunneling memories, the direct charge injection memory of this embodiment has advantages such as low operating voltage and low energy consumption.

[0064] against Figure 3 The prepared memory was tested in the following manner:

[0065] The write / erase capability of the device is studied by applying a voltage pulse of -2V (20ns) / 2V (20ns) on the control gate, that is, inputting -2V for 20ns and then inputting 2V for 20ns, and at the same time detecting the delay time between the input pulse and the output pulse to measure the read speed of the device.

[0066] The cyclic durability of the device was investigated by cyclically applying voltage pulses of -2V (20ns) and 2V (20ns) on the control gate, that is, cyclically inputting voltages of -2V and 2V for 20ns. The stability of the device was investigated by inputting voltage pulses of -2V / 2V (20ns) on the control gate and using a source-drain voltage of 0.1V to read the current state of the device.

[0067] By changing the ambient temperature of the device and detecting the changes in the source and drain current states of the device, the stability of the device's temperature dependence is explored, and by changing the control gate input voltage, the multi-bit storage capability of the device is explored.

[0068] By exploring the relationship between the thickness of the threshold switching layer and the write-erase performance of the device, the thickness of the threshold switching layer is controlled at around 10nm, enabling the device to exhibit optimal performance. The ambient temperature is set within the range of 220K-350K to explore the temperature stability of the device. A patterned threshold conversion characteristic material layer is used to reduce the interference of the large-area threshold switching layer on the electrical performance of the device.

[0069] In general, the high-speed non-volatile memory based on the direct charge injection mechanism provided by this embodiment has the following advantages over existing floating gate memories:

[0070] First, the traditional floating gate memory uses the FN tunneling mechanism. Since the process of implementing the band-tilted charge injection requires a large voltage, it will generate a large energy consumption. This embodiment uses a direct charge injection mechanism, so the voltage used is small, which can significantly reduce energy consumption.

[0071] Second, the tunnel dielectric layer of traditional floating gate memories often uses materials with high dielectric constants, which results in a large barrier to charge injection. The present invention utilizes the conductive path formed by oxygen vacancies and defect vacancies in the threshold switching layer, resulting in fast switching speed and strong responsiveness.

[0072] In other embodiments, the memory provided in this embodiment is tested for performance in multiple aspects in the following manner:

[0073] Figure 3 and Figure 4 The current-voltage curve of the tungsten selenide / graphene oxide / molybdenum disulfide threshold resistive switch of the memory of this embodiment. Figure 3 The positive voltage segment 2a and Figure 4Performing a current-voltage (IV) scan on the negative voltage segment 2b shows that the device of this embodiment has a threshold switching characteristic. Meanwhile, the steep IV curve at ±1V indicates that the device has an extremely fast switching speed.

[0074] Figure 5 This is a test diagram of the write and erase capability of the memory of this embodiment. Figure 5 It can be seen that by applying voltage pulses of -2V (20ns) and 2V (20ns) on the control gate, the memory of this embodiment can be switched to the off state and the on state, respectively, indicating that the memory has nanosecond write and erase capabilities.

[0075] Figure 6 This is a test chart of the reading speed of the memory of this embodiment. Figure 6 It can be seen that this embodiment cyclically applies a pulse group with a pulse width of 20ns and a pulse interval of 200ns, and simultaneously detects the input pulse and the output pulse. Figure 6 It can be seen that the delay between the input signal and the output signal is extremely short, indicating that the device has an extremely fast response speed.

[0076] Figure 7 This is the endurance test of the memory of this embodiment. This embodiment applies -2V (20ns) and 2V (20ns) 1000 times in a cycle and monitors the change of the current state. Figure 7 It is known that the switching current has almost no obvious change, indicating that the device has good durability.

[0077] Figure 8 This is a stability test of the memory of this embodiment. This embodiment applies a voltage pulse of -2V / 2V (20ns) and monitors the change of current at a source-drain voltage of 0.1V. Figure 8 It can be seen that there is no obvious change in the switching current, indicating that the device has good stability.

[0078] Figure 9 、 Figure 10 、 Figure 11 and Figure 12 This is an explanation of the memory mechanism of this embodiment. When a nanosecond negative pulse voltage is applied to the control gate, the threshold switching layer GO is converted to the on state, and electrons are injected into the bottom molybdenum sulfide through tungsten selenide, as shown in FIG. Figure 9 As shown in the figure; after the voltage pulse is removed, the threshold switching layer GO switches to the off state. At this time, the electrons entering the bottom MoS2 are stored in it, and the top MoS2 channel is depleted. At this time, the device is in the off state (writing process), as shown in the figure. Figure 10 As shown; On the contrary, when a symmetrical nanosecond positive voltage is applied to the control gate, the electrons stored in the bottom MoS2 return to the WSe through the threshold switching layer to complete the erase process, as shown Figure 11As shown; after removing the voltage pulse, the MoS2 channel returns to its initial state, as shown Figure 12 shown.

[0079] Figure 13 and Figure 14 This is the robustness characteristic of the memory in this embodiment. Figure 13 The on and off states of the test device are shown in the temperature range of 220K-350K, and Figure 14 As shown in the on-state and off-state tests of the device under the conditions of 0-60 days, it can be seen that the device has good robustness.

[0080] Figure 15 This is a test of the multi-bit storage capability of the memory of this embodiment. Figure 15 It can be seen that by applying different pulse voltages on the control gate, 8 different current levels are presented, indicating its multi-bit storage capability.

[0081] While the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited to the embodiments described above. Various modifications may be made within the scope of knowledge possessed by a person skilled in the art without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof may be combined with one another unless there is a conflict.

Claims

1. A memory based on a charge injection mechanism, characterized in that: include: substrate; a control gate layer, the control gate layer comprising tungsten selenide, the control gate layer being located on the substrate, a gate electrode being provided on a first end of the control gate layer for connecting to an externally applied voltage; a threshold switching layer, the threshold switching layer comprising graphene oxide having threshold switching characteristics, the second end of the threshold switching layer being located above the substrate, the first end of the threshold switching layer being located above the second end of the control gate layer, and the side surface of the first end of the threshold switching layer being in close contact with the side surface of the gate electrode; a charge storage layer, the charge storage layer comprising molybdenum sulfide, the charge storage layer being located above the threshold switch layer; a blocking layer, the blocking layer being located on the charge storage layer; a channel layer, the channel layer being located on the barrier layer, a source electrode being provided on a first end of the channel layer, and a drain electrode being provided on a second end of the channel layer; The gate electrode, the source electrode and the drain electrode all include chromium and gold materials.

2. The memory based on the charge injection mechanism according to claim 1, characterized in that: The channel layer includes molybdenum sulfide.

3. The memory based on the charge injection mechanism according to claim 1, characterized in that: The substrate includes a silicon substrate.

4. The memory based on the charge injection mechanism according to claim 1, characterized in that: The barrier layer includes boron nitride.

5. A method for preparing a memory based on a charge injection mechanism, characterized in that: The following steps are involved: The Graphyne film is treated with ozone to obtain Graphyne oxide as the threshold switching layer; A charge storage layer, a channel layer, a barrier layer and a control gate layer containing tungsten selenide are prepared by mechanical stripping; stacking the control gate layer, the threshold switch layer, the charge storage layer, the blocking layer and the channel layer on a substrate in sequence; A gate electrode is formed on the control gate layer by photolithography and thermal evaporation, and a source electrode and a drain electrode are formed on the channel layer respectively; The control gate layer and the charge storage layer are connected via graphene oxide having a threshold switching characteristic.

6. The method for preparing a memory based on a charge injection mechanism according to claim 5, characterized in that: The step of sequentially stacking the control gate layer, the threshold switch layer, the charge storage layer, the blocking layer, and the channel layer on the substrate comprises: The control gate layer, the threshold switch layer, the charge storage layer, the blocking layer and the channel layer are stacked in sequence on a substrate by using a van der Waals stacking method.

7. The method for preparing a memory based on a charge injection mechanism according to claim 5, characterized in that: The method of preparing a gate electrode on the control gate layer and a source electrode and a drain electrode on the channel layer by photolithography and thermal evaporation includes: Electrodes composed of chromium and gold materials are prepared on the control gate layer as a gate electrode by photolithography and thermal evaporation, and electrodes composed of chromium and gold materials are respectively prepared on the channel layer as a source electrode and a drain electrode.

8. The method for preparing a memory based on a charge injection mechanism according to claim 5, characterized in that: The channel layer includes molybdenum sulfide.

9. The method for preparing a memory based on a charge injection mechanism according to claim 5, characterized in that: The barrier layer includes boron nitride.

Images