Method for improving read-write operation reliability of ferroelectric memory through electrostatic shielding

Abstract

The invention belongs to the technical field of ferroelectric memory devices, and particularly relates to a method for improving read-write operation reliability of a ferroelectric memory through electrostatic shielding. An electrostatic shielding conductive structure is introduced into a ferroelectric material of the ferroelectric memory and an electrode interface region, so that the charge injection speed of an interface layer is increased, a ferroelectric depolarization field is reduced, and the symmetry of positive and negative write voltages in a rapid operation process of the ferroelectric memory is realized; therefore, the read-write operation reliability of the high-density ferroelectric memory during high-speed operation is improved, and a ferroelectric memory with an electrostatic shielding structure is called as an electrostatic shielding ferroelectric memory. The invention is suitable for the ferroelectric memory cell, the plane crossing bar array and the three-dimensional stacking structure. According to the invention, a depolarization field can be effectively inhibited, the imprinting time is greatly shortened, the symmetry of a ferroelectric hysteresis loop is improved, the read-write speed of a memory is improved, and the method is compatible with a semiconductor process. Effective technical support is provided for large-scale manufacturing and application of high-speed, high-density and high-reliability ferroelectric memories.

Description

Technical Field

[0001] This invention belongs to the field of ferroelectric storage device technology, and specifically relates to a method for improving the reliability of read and write operations of ferroelectric storage devices. Background Technology

[0002] Ferroelectric memories, as a representative of next-generation non-volatile memory technology, rely on the core characteristic of ferroelectric materials—the reversible change of their spontaneous polarization direction with the direction of an applied electric field—to non-volatilely store the "1" and "0" states in binary logic. However, in practical operation, ferroelectric memory cells and their electrode interfaces commonly exhibit uneven ferroelectric polarization distribution and various incompletely shielded charges, including ferroelectric domain polarization charges, electrode-injected carriers, charged defects such as oxygen vacancies, and doping centers. The localized accumulation of these charges triggers a significant microscopic depolarization field. If not shielded, this leads to a severe asymmetry in the positive and negative write voltages of the memory, resulting in an imprinting effect. This severely restricts the device's performance stability and the reliability of read / write operations, directly reducing information retention time and read / write speed.

[0003] Depolarization electric field originates from an electrostatic field generated when the polarization charge of ferroelectric domains within a memory cell cannot be completely shielded. Its direct effects include inducing all or part of the ferroelectric domains to undergo a "reverse flip" phenomenon, causing the residual ferroelectric polarization to decay with prolonged retention time, and ultimately causing the "1" or "0" logic state originally written to the device to reverse, severely affecting the long-term retention capability of information.

[0004] Imprinting effects generally originate from the injection of opposite-polarity shielding charges or the accumulation of charged defects at the ferroelectric domain interfaces. Once the domains reverse, the polarity of these shielding charges cannot change in time, establishing a depolarization field. Its direct effects include: causing asymmetric pinning of the ferroelectric domain polarization direction, resulting in unequal absolute values ​​of the positive coercive voltage (the voltage required to write to the "1" state) and the negative coercive voltage (the voltage required to write to the "0" state) of the memory cell, reducing the consistency of read and write operations in the array device; easily inducing ferroelectric polarization fatigue and ferroelectric aging, causing the read and write performance of the memory device to gradually degrade after multiple cycles; and also accelerating the decay of data retention capability, affecting the reliability of long-term use.

[0005] Traditionally, depolarization fields generated by interfacial layers are often reduced by optimizing electrode materials or introducing interfacial buffer layers. However, these methods rely heavily on interface engineering, making it difficult to address the problem at the intrinsic material level. Furthermore, they often lack universality across ferroelectric material systems, leading to high research costs and implementation difficulties. Especially with the current trend of continuously shrinking the size of high-density ferroelectric memory devices and advancing domain structures to the nanoscale, read / write times have entered the sub-nanosecond range. The depolarization fields generated by these interfacial layers severely impact the read / write speeds of memory. Traditional improvement techniques are no longer sufficient to meet these demands. Therefore, there is an urgent need to develop a low-cost, engineerable, and universal implementation method that can effectively suppress microscopic depolarization field effects across all ferroelectric material systems. This would improve the overall performance of ferroelectric memory in terms of high-speed read / write, high-density storage, and low-power operation, accelerating its application. Summary of the Invention

[0006] The purpose of this invention is to propose a method to improve the reliability of ferroelectric memory read and write operations through electrostatic shielding, so as to improve the overall performance of ferroelectric memory in terms of high-speed read and write, high-density storage, and low-power operation.

[0007] The method for improving the read / write reliability of ferroelectric memory through electrostatic shielding proposed in this invention involves introducing an electrostatic shielding conductive structure at the interface between the ferroelectric material and the electrode in the ferroelectric memory, such as... Figure 1 As shown, in order to accelerate the charge injection speed of the interface layer, reduce the ferroelectric depolarization field, and realize the symmetry of positive and negative write voltages in the ferroelectric memory during fast operation, thereby improving the reliability of read and write operations of high-density ferroelectric memory during high-speed operation, the ferroelectric memory with the introduction of electrostatic shielding structure is called electrostatic shielded ferroelectric memory.

[0008] For the ferroelectric memory, which is a ferroelectric storage cell structure, the electrostatic shielding structure and the layout of the ferroelectric memory are as follows: The ferroelectric memory consists of a ferroelectric body and a first electrode and a second electrode respectively disposed on both sides of the ferroelectric body; wherein, at least one of the first electrode and the second electrode is provided with a conductive shielding structure integrally formed or electrically connected thereto; and the conductive shielding structure at least partially covers the ferroelectric storage cell, including the end face of the corresponding side and the adjacent side face, forming a conductive enclosure of the interface layer region formed between the ferroelectric body and the electrode end face; the conductive shielding structure is physically isolated from the other electrode through a gap or an insulating dielectric layer.

[0009] The conductive shielding structure, when the ferroelectric memory is in the holding state, is used to shield the depolarization field generated by the failure to compensate the ferroelectric polarization charge in the interface layer in time, so as to prevent the logic reversal of the "1" or "0" logic state recorded in the memory cell due to the interference of the depolarization field or other stray electric fields, thereby improving the information non-volatile retention capability.

[0010] The conductive shielding structure significantly shortens the space charge injection time (i.e., imprinting time) within the interface layer when the ferroelectric memory is in write operation mode. The injected charge can be captured by interface defect states, promptly compensating for ferroelectric polarization charges, reducing the depolarization field, and improving the memory read / write speed. This ensures that the coercive voltage required to write a "1" state to the coercive voltage required to write a "0" state remains symmetrical, thereby improving the consistency and reliability of write operations.

[0011] The imprinting time refers to the asymmetry phenomenon that occurs in ferroelectric memory due to the presence of injected charge. The asymmetry phenomenon means that when the memory write operation time is less than the imprinting time, the positive and negative coercive voltages of the electric domains in the ferroelectric memory cell are asymmetrical when information is written quickly due to the presence of the depolarization field, that is, the imprinting effect occurs.

[0012] Furthermore, the conductive shielding structure covers a portion of the ferroelectric memory cell, particularly the region where an interface layer is easily formed in contact with the electrodes. The ferroelectric polarization intensity within this interface layer is relatively weak, making it prone to depolarization and resulting in space charge injection. The conductive layer (conductive shielding structure) covers the end face and side face of the ferroelectric memory cell, with a continuous length along the side face not less than 1 nm and not greater than 10 μm.

[0013] Furthermore, the continuous length of the conductive shielding structure along the side of the ferroelectric memory cell is related to the electrostatic shielding effect, and includes all or part of the four sides: top, bottom, left, and right. The shape of the ferroelectric memory cell is not limited, and can be, for example, a cube, cuboid, cylinder, ellipsoid, or polygon.

[0014] Furthermore, the ferroelectric storage unit uses ferroelectric materials including, but not limited to, lithium niobate, lithium tantalate, bismuth ferrite, and lead zirconate titanate; wherein the lithium niobate, lithium tantalate, bismuth ferrite, and lead zirconate are single crystals or thin films, lithium niobate salts, lithium tantalate salts, or bismuth ferrite salts doped with MgO, Mn2O5, or Fe2O3, or blackened lithium niobate salts and blackened lithium tantalate salts; the crystal orientations of lithium niobate and lithium tantalate include: X-cut, Z-cut, Y-cut, and oblique-cut crystals.

[0015] Furthermore, the materials of the electrodes and conductive shielding structures include, but are not limited to: metal electrodes, such as tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, silver, and gold; inorganic non-metallic conductive materials, such as tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and tantalum nitride; and conductive structures formed within the ferroelectric material, including conductive domain walls, conductive defects, conductive doped regions, and injected charge pathways.

[0016] This invention provides a method for improving the read / write reliability of ferroelectric memory through electrostatic shielding. The ferroelectric memory employs a crossbar storage two-dimensional array structure, specifically including multiple ferroelectric memory cells with electrostatic shielding structures arranged in an orthogonal grid pattern in a two-dimensional plane. Each ferroelectric memory cell includes a ferroelectric material, word line electrodes, bit line electrodes, and a conductive shielding structure. Specifically, in the crossbar storage array, multiple word line electrodes are arranged parallel along a first direction (corresponding to the initial polarization direction of the ferroelectric material), and multiple bit line electrodes are arranged parallel along a second direction perpendicular to the first direction. The word line electrodes and bit line electrodes are electrically isolated and mechanically supported by an interlayer dielectric layer or gap. Each ferroelectric memory cell is located near the intersection of a word line electrode and a bit line electrode, and is connected to the corresponding word line electrode and bit line electrode.

[0017] In this embodiment, at least one of the word line electrodes and bit line electrodes is provided with a conductive shielding structure integrally formed or electrically connected thereto; adjacent ferroelectric memory cells are provided with a shared or independent conductive shielding structure; the conductive shielding structure at least partially covers the ferroelectric memory cell, including the end face of the corresponding side and the adjacent side face, forming a conductive enclosure of the interface layer region formed between the ferroelectric body and the electrode end face; a gap or insulating dielectric layer is provided between the conductive shielding structure and the other electrode of the ferroelectric memory cell to achieve physical isolation and avoid electrical short circuit.

[0018] When the memory cell is in the hold state, the conductive shielding structure can shield the depolarization field or other stray electric fields generated by the uncompensated ferroelectric polarization charge in the interface layer region between the ferroelectric and the electrode, preventing the "1" or "0" state reversal. When the memory cell is in the write operation, the conductive shielding structure can significantly shorten the space charge injection time in the interface layer region, i.e. the imprinting time. This space charge can shield the ferroelectric polarization charge, reduce the depolarization field, and ensure that the domain reversal process from "0" to "1" and from "1" to "0" has equal absolute coercive voltage, thereby improving the read and write operation reliability of the entire stacked array, and improving the memory read and write speed and information retention time.

[0019] Furthermore, in the ferroelectric memory cell, the conductive layer (conductive shielding structure) covers the end face and side face of the ferroelectric memory cell, and the continuous length along the side face direction, the shape of the ferroelectric memory cell, the ferroelectric material, the materials of the electrodes and the conductive shielding structure are as described above.

[0020] Furthermore, the materials of the interlayer dielectric layer include, but are not limited to, the ferroelectric storage medium itself, alumina, hafnium oxide, silicon oxynitride, silicon nitride, or silicon oxide.

[0021] Furthermore, the materials of the word line electrode, bit line electrode, and others include, but are not limited to, tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, silver, gold, tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and tantalum nitride.

[0022] The present invention provides a method for improving the read and write reliability of ferroelectric memory through electrostatic shielding. The ferroelectric memory adopts a three-dimensional array stacked structure. The three-dimensional array includes multiple word line layers and multiple interlayer dielectric layers that are alternately stacked in the vertical direction, and bit line electrodes composed of several conductive vias penetrating each stacked layer, thereby forming a vertical extension structure of a multilayer crossbar memory array.

[0023] Each word line layer includes a plurality of strip word line electrodes arranged in parallel along a first direction (corresponding to the initial polarization direction of the ferroelectric material), and a bit line electrode array arranged between two adjacent word lines along a second direction perpendicular to the first direction; each word line electrode and the adjacent bit line electrode form a ferroelectric memory cell near the intersection, and the ferroelectric body of the cell is connected to the corresponding word line electrode and bit line electrode respectively.

[0024] In this design, at least one of the word line electrodes and bit line electrodes is provided with a conductive shielding structure integrally formed or electrically connected thereto. The conductive shielding structure is independently provided within each ferroelectric memory layer, or forms a shared or partially shared structure between adjacent memory cells or adjacent stacked layers. The conductive shielding structure at least partially covers the ferroelectric memory cell, including the corresponding end face and adjacent side faces, forming a conductive enclosure of the interface layer region formed between the ferroelectric material and the electrode end face. A gap or insulating dielectric layer is provided between the conductive shielding structure and the other electrode of the ferroelectric memory cell to achieve physical isolation and prevent electrical short circuits.

[0025] When the memory cell is in the hold state, the conductive shielding structure can shield the depolarization field or other stray electric fields generated by the uncompensated ferroelectric polarization charge in the interface layer region between the ferroelectric and the electrode, preventing the "1" or "0" state reversal. When the memory cell is in the write operation, the conductive shielding structure can significantly shorten the space charge injection time in the interface layer region, i.e. the imprinting time. This space charge can shield the ferroelectric polarization charge, reduce the depolarization field, and ensure that the domain reversal process from "0" to "1" and from "1" to "0" has equal absolute coercive voltage, thereby improving the read and write operation reliability of the entire stacked array, and improving the memory read and write speed and information retention time.

[0026] Furthermore, in the ferroelectric memory cell, the conductive layer (conductive shielding structure) covers the end face and side face of the ferroelectric memory cell, and the continuous length along the side face direction, the shape of the ferroelectric memory cell, the ferroelectric material, the materials of the electrodes and the conductive shielding structure are as described above.

[0027] Furthermore, the materials of the interlayer dielectric layer and the insulating dielectric layer include, but are not limited to, ferroelectric material itself, alumina, hafnium oxide, silicon oxynitride, silicon nitride, or silicon oxide.

[0028] Furthermore, the materials of the word line electrodes and bit line electrodes include, but are not limited to, tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, silver, gold, tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and tantalum nitride.

[0029] The present invention also provides an electrostatically shielded ferroelectric memory constructed in the above method, specifically including: the ferroelectric memory being a ferroelectric memory cell structure; the ferroelectric memory being a crossbar storage two-dimensional array structure; and the ferroelectric memory being a three-dimensional array stack structure. Attached Figure Description

[0030] Figure 1 This image compares the structure of a traditional ferroelectric memory with that of an electrostatically shielded ferroelectric memory. In the image, 'a' represents the traditional ferroelectric memory structure, and 'b' represents the electrostatically shielded ferroelectric memory structure. For both 'a' and 'b', the left side is a top view, and the right side is a cross-sectional view.

[0031] Figure 2 This is a schematic diagram of the finite element calculation model.

[0032] Figure 3 A comparison of finite element simulation results showing the impact of electrostatic shielding structures on the information retention performance of ferroelectric memory.

[0033] Figure 4 A comparison of finite element simulation results showing the impact of electrostatic shielding structures on the write operation performance of ferroelectric memories.

[0034] Figure 5 It is a single-sided, single-end electrostatically shielded ferroelectric storage cell structure.

[0035] Figure 6 This is a scanning electron microscope image of a single-sided, single-end electrostatically shielded ferroelectric storage cell structure.

[0036] Figure 7 This refers to the domain reversal hysteresis loops with different coverage lengths in a single-sided, single-ended electrostatically shielded ferroelectric storage cell structure.

[0037] Figure 8 It is a three-sided, single-ended electrostatically shielded ferroelectric storage cell structure.

[0038] Figure 9 This is a scanning electron microscope image of a three-sided, single-ended electrostatically shielded ferroelectric storage cell structure.

[0039] Figure 10The domain reversal hysteresis loops of different coverage lengths are for a three-sided single-ended electrostatically shielded ferroelectric storage cell structure.

[0040] Figure 11 It is a four-sided, single-end electrostatically shielded ferroelectric storage cell structure.

[0041] Figure 12 It is a toroidal single-end electrostatically shielded ferroelectric storage cell structure.

[0042] Figure 13 It is a three-sided electrostatically shielded ferroelectric storage cell structure.

[0043] Figure 14 It is a ferroelectric storage cell structure with electrostatic shielding on both sides.

[0044] Figure 15 It is a ferroelectric memory structure with single-ended electrostatic shielding on two sides.

[0045] Figure 16 It is a ferroelectric storage cell structure with electrostatic shielding on one side.

[0046] Figure 17 It is a ferroelectric storage cell structure with a groove for electrostatic shielding on one side.

[0047] Figure 18 It is a single-sided, single-end electrostatically shielded grooved ferroelectric storage cell structure.

[0048] Figure 19 This is a ferroelectric memory cell structure with one side single-end electrostatic shielding based on the conductive ferroelectric domain wall.

[0049] Figure 20 This is a ferroelectric memory cell structure with double-sided single-end electrostatic shielding based on conductive ferroelectric domain walls.

[0050] Figure 21 This is a top view of an electrostatically shielded ferroelectric storage planar array.

[0051] Figure 22 This is a cross-sectional view of an electrostatically shielded ferroelectric storage planar array.

[0052] Figure 23 This is a top view of an electrostatically shielded ferroelectric storage planar array based on ferroelectric conductive domain walls.

[0053] Figure 24 This is a cross-sectional view of an electrostatically shielded ferroelectric storage planar array based on ferroelectric conductive domain walls.

[0054] Figure 25 This is a schematic diagram of a three-dimensional stacked array of electrostatically shielded ferroelectric storage cells.

[0055] Figure 26 Top view of a three-dimensional stacked array of electrostatically shielded ferroelectric storage cells.

[0056] Figure 27 A cross-sectional view of a three-dimensional stacked array of electrostatically shielded ferroelectric storage cells.

[0057] In the diagram, the following labels are used: 1011 is the first electrode, 1012 is the second electrode, 102 is the ferroelectric material, 1031 is the interface layer formed between the ferroelectric material and the first electrode, 1032 is the interface layer formed between the ferroelectric material and the second electrode, 104 is the substrate, and 105, 1051, and 1052 are conductive shielding structures formed by domain wall conductive layers. 2012 is the conductive plug, 202 is the ferroelectric memory cell, 204 is the substrate, 205 is the conductive shielding structure, 2051 and 2052 are conductive shielding structures formed by domain wall conductive layers, WL1-3 is the planar array, and BL1-6 is the bit line in the planar array. 3012 is the bit line electrode, 302 is the ferroelectric memory cell, 304 is the substrate, 306 is the interlayer insulating layer, WL1-1-3, WL2-1-3, and WL3-1-3 are word lines in the three-dimensional stacked array, and BL1-5 is the bit line in the three-dimensional stacked array. Detailed Implementation

[0058] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of some implementations of the present invention and do not constitute a limitation thereof.

[0059] In the description of the embodiments, the terms "first electrode" and "second electrode" are used to clearly illustrate the basic principles. These terms are for structural illustration only and do not represent any orientational limitation in the actual device. Furthermore, the two-electrode structure shown in the embodiments of this application is a basic model, possessing good scalability and universality, and can be applied to scenarios involving localized flipping of electric domains in regions of different shapes or with varying numbers of domains.

[0060] This invention provides several electrostatic shielding structures with engineering feasibility. These structures are merely illustrative examples. Based on the core ideas proposed in this invention, any electrostatic shielding structure of any shape designed and implemented by those skilled in the art without creative effort is within the scope of protection of this patent.

[0061] In the accompanying drawings, the thickness of layers and regions has been exaggerated for clarity, and the dimensional proportions between the parts shown do not reflect the actual dimensional proportions.

[0062] In the embodiments, the domain directions or polarization directions are given exemplarily to facilitate a detailed explanation of the principles. It should be understood that the domain directions or polarization directions are not limited to those shown in the embodiments of this application.

[0063] Example 1 uses finite element calculations to illustrate the effect of unshielded ferroelectric polarization charges on the storage of information "1" and "0" in a ferroelectric memory, and verifies that electrostatic shielding can suppress the depolarization field inside the ferroelectric material, thus achieving stable storage of information "1 / 0".

[0064] Figure 2 This is a schematic diagram of the finite element method (FEM) calculation model. Figure 2 (a) is a traditional ferroelectric memory structure. Figure 2 (b) A ferroelectric memory employing an electrostatic shielding structure. The model includes a first electrode 1011, a second electrode 1012, a ferroelectric material 102, and interface layers 1031 and 1032 between the ferroelectric material and the two electrodes. In the electrostatic shielding structure, the electrodes cover the interface layer regions at both ends of the ferroelectric material to provide a shielding effect.

[0065] In the model, the ferroelectric material 102 is set to have dimensions of 200 nm (length) × 50 nm (width), the interface layers 1031 and 1032 to have dimensions of 10 nm (length) × 50 nm (width), and the electrodes 1011 and 1012 to have dimensions of 100 nm (length) × 50 nm (width). The electrostatic shielding coverage length is set to 50 nm. The polarization direction of the ferroelectric material is assumed to be horizontal to the left. The remanent polarization Pr of the ferroelectric material 102 is set to 66 μC / cm. 2 The polarization direction is to the left. The interface layer 1031 contains +33 μC / cm². 2 Unshielded polarization charge, 1032 has -33 μC / cm 2 The unshielded polarized charge. Regarding material parameters, the relative permittivity of the electrodes is set to infinity, the relative permittivity of the ferroelectric material and interface layer is set to 33, and the electrode edges are grounded.

[0066] Based on the above model, steady-state finite element calculations of the electrostatic field were performed, and the results are as follows: Figure 3 As shown. Figure 3 (a) represents the ideal state in which the interface polarization charge is completely shielded. At this time, the electric field inside the ferroelectric material is zero, the polarization state is stable, and it corresponds to the stable state of "1 / 0" information storage.

[0067] Figure 3 (b) is the case of a traditional unshielded structure. Due to the presence of unshielded polarization charges at the interface, a depolarization field with the opposite direction to the polarization is generated inside the ferroelectric material, with a field strength of 1.6547 × 10⁻⁶. 8 V / m. This electric field causes the domains to flip in the opposite direction, resulting in a decrease in residual polarization. This causes the storage state to drift from "1" to "0" (or vice versa), which seriously affects the reliability of information retention.

[0068] Figure 3(c) shows the calculation results after introducing the electrostatic shielding cladding structure. At this point, the depolarization field strength within the ferroelectric body decreases to 4.2415 × 10⁻⁶. 7 The V / m value decreased by approximately 74.4%. The significant reduction in the depolarization field means that the domain states are significantly less susceptible to external disturbances, and the stability of the stored states ("1" or "0") is significantly enhanced, thereby directly improving the information retention performance of ferroelectric memories.

[0069] This embodiment demonstrates through quantitative comparison that the electrostatic shielding structure can effectively suppress the depolarization field and maintain the predetermined polarization direction of the ferroelectric domains, which is crucial for achieving stable and reliable binary information storage ("1" / "0"). This conclusion is universal and applicable to various ferroelectric material systems, providing an important theoretical basis for the application of this invention in ferroelectric memories.

[0070] Example 2 illustrates the impact of the imprinting effect on the write operation (writing "1" or "0") of ferroelectric memory through finite element calculation results, and explains how the electrostatic shielding method is used to suppress the imprinting effect of ferroelectric materials and improve the operational reliability of ferroelectric memory.

[0071] This embodiment uses the same finite element calculation model as Embodiment 1 (e.g., Figure 2 As shown), the model dimensions are set to be consistent.

[0072] To specifically simulate the interface charge effect present in actual devices, this model neglects the influence of the ferroelectric's own polarization charge and sets a value of +6.6 μC / cm in the left interface layer 1031. 2 The injected charge is set at -6.6 μC / cm in the right interface layer 1032. 2 The injected charge is used to simulate the fixed charge introduced by material defects, interface reactions, or processes.

[0073] The edge of the first electrode 1011 is grounded, and the edge of the second electrode 1012 is given an external voltage of +10V and -10V respectively, to simulate the two bias voltages of opposite polarity applied to the ferroelectric memory when writing logic "1" and "0" states.

[0074] Based on the above settings, steady-state calculations of the electrostatic field were performed, yielding the following results: Figure 4 The comparison results are shown.

[0075] Figure 4 (a) illustrates the case of an ideal, charge-free interface. When +10V and -10V write voltages are applied respectively, the electric field strength generated inside the ferroelectric material is equal in magnitude and opposite in direction, according to the imprinted field calculation formula. The imprinted field is 0 V / m. This indicates that the flipping of ferroelectric domains is completely controlled by the applied write voltage. The voltage required to flip a memory cell from state "0" to "1" (positive coercive voltage) is completely symmetrical with the voltage required to flip from "1" to "0" (negative coercive voltage), thus ensuring high consistency and reliability of write operations.

[0076] Figure 4 (b) illustrates the case where the interface-injected charge shields the domain polarization charge in a conventional unshielded structure. When the write operation time is less than the imprinting time, the interface-injected charge does not change its polarity in time after the domains suddenly reverse, significantly distorting the internal electric field distribution. This results in a marked asymmetry in the electric field strength formed inside the ferroelectric material when +10V and -10V voltages are applied. The calculated imprinting field is as high as 2.65115 × 10⁻⁶. 7 V / m. This strong imprinting field creates asymmetric pinning of the polarization direction of the ferroelectric domains, causing a significant shift in the positive and negative coercive voltages. This write voltage asymmetry severely affects the operational reliability of the memory: it may lead to incomplete writing of the "1" state or erroneous flipping of the "0" state, resulting in data errors and accelerating the performance degradation of the device during repeated read and write operations.

[0077] Figure 4 (c) demonstrates the improved effect of introducing an electrostatic shielding structure. The shielding structure effectively modulates the interference of interface charges on the internal electric field, significantly reducing the difference in the internal electric field under positive and negative write voltages. The calculated imprint field then decreases to 8.486 × 10⁻⁶. 6 The voltage per unit area (V / m) is reduced by approximately 68.0% compared to the unshielded case. Not only is the imprinting field significantly reduced, but there are also more interface charge injection paths with shorter distances. This allows the polarity of the injected charge to be changed promptly with the change of domain direction, shielding the ferroelectric polarization charge. In other words, the imprinting time is significantly shortened, which means that the symmetry of the positive and negative write voltages for ferroelectric domain flipping during high-speed read and write is significantly improved. The voltage thresholds required to write "1" and "0" states are closer, and the consistency of write operations is greatly improved.

[0078] This embodiment quantitatively demonstrates through finite element analysis that the electrostatic shielding structure can effectively suppress the imprinting effect caused by interface charge, thereby significantly improving the reliability of write operations in ferroelectric memory. This is crucial for ensuring the correctness of data writing, improving device durability, and maintaining long-term stable read / write performance, further confirming the core value of this invention in improving the performance of ferroelectric memory from the perspective of write operation reliability.

[0079] Example 3 provides a specific design scheme for a single-sided, single-end electrostatically shielded ferroelectric storage cell structure.

[0080] Figure 5This is a schematic diagram of a planar structure of a single-ended electrostatically shielded ferroelectric storage cell with an upper side provided in an embodiment of the present invention, wherein the left side is a top view and the right side is a corresponding cross-sectional view. Figure 5 As shown, the memory cell structure includes: a ferroelectric substrate 104, ferroelectric bumps 102 formed on the substrate, and a first electrode 1011 and a second electrode 1012 respectively disposed on both sides of the ferroelectric bumps.

[0081] Specifically, the ferroelectric substrate 104 includes, but is not limited to, lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, and their doped materials. The ferroelectric bumps 102 are defined and formed on the substrate using micro / nano fabrication etching processes. Subsequently, a conductive metal layer is deposited on the surfaces of the substrate 105 and the ferroelectric bumps 102 using a thin-film deposition method, and electrode patterns are defined using electron beam lithography. Then, a first electrode 1011 and a second electrode 1012, spaced apart from each other, are formed by etching. The first electrode 1011 is designed to form a covering structure on one end and part of the upper side of the ferroelectric bump 102, while the second electrode 1012 is disposed on the opposite end of the ferroelectric bump.

[0082] In this embodiment, applying a write voltage greater than the coercive voltage Vc between the first electrode and the second electrode can cause the internal domains of the device to flip, and a conductive domain wall is formed between the flipped domains and the unflipped domains. At this time, applying a read voltage between the first electrode and the second electrode can obtain the low-resistance state "1". Applying a reverse write voltage greater than the coercive voltage Vc between the first electrode and the second electrode can cause the internal domains of the device to return to their initial direction, and the conductive domain wall disappears. At this time, applying a read voltage between the first electrode and the second electrode can obtain the high-resistance state "0" (Chinese Patent Application No. CN201680061638.3).

[0083] The following will describe the fabrication process and device test results based on Example 3.

[0084] In this embodiment, the ferroelectric substrate uses X-cut 5% mol Mg-doped lithium niobate single crystal material as the substrate. After removing surface contaminants through a standard cleaning process, electron beam photoresist is first spin-coated onto the substrate surface, and the ferroelectric bump pattern is defined using electron beam lithography.

[0085] A chromium metal mask was deposited using physical vapor deposition (PVD), and a lift-off process was used to obtain the bump pattern. A plasma reactive ion etching (PRI) system was employed, using a mixture of argon and fluorine-based gases, to form a ferroelectric bump structure with steep sidewalls.

[0086] A physical vapor deposition process was used to sequentially deposit platinum electrode layers on the etched substrate surface. The substrate temperature was maintained at 250 °C during deposition to ensure good film adhesion and conductivity.

[0087] Electron beam photoresist was spin-coated again, and the electrode pattern was defined by electron beam lithography. The focus was on controlling the coating length L2 parameter of the first electrode (set to four groups: 20 nm, 65 nm, 95 nm, and 130 nm respectively).

[0088] Chromium metal was obtained using physical vapor deposition, and an electrode pattern mask was obtained using a lift-off process.

[0089] A plasma reactive ion etching system is used, employing a mixture of argon and fluorine-based gases, to form electrode structures with different coating lengths.

[0090] Figure 6 Scanning electron microscope images of a series of memory cell structures with different electrostatic shielding coverage lengths L2, prepared by the above process, are shown. The coverage lengths L2 of the devices shown are 65 nm, 95 nm, and 130 nm, respectively, which visually demonstrates the controllable fabrication of the structural morphology.

[0091] The first electrode 1011 serves as a conductive layer covering the upper side of the ferroelectric bump 102, forming a single-end electrostatic shielding structure on one side. This structure effectively shields the edge effect of the depolarization field inside the ferroelectric material and significantly suppresses the imprinting effect, thereby improving the stability of ferroelectric domain switching and enhancing the retention performance and read / write reliability of the ferroelectric memory.

[0092] Figure 7 This embodiment demonstrates the measurement results of the domain reversal hysteresis loop of the ferroelectric memory cell under different electrostatic shielding lengths, from the occurrence of... Open and open The domain reversal voltage (+ / -Vc) is obtained by switching the current. Tests show that devices with shorter envelope lengths (e.g., 20 nm) exhibit smaller absolute values ​​of negative coercivity voltage and significant asymmetry in the hysteresis loop, indicating a severe imprinting effect and poor retention of the written information. As the envelope length increases (to 95 nm and 130 nm), the absolute value of the negative coercivity voltage gradually increases, and the hysteresis loop moves towards central symmetry, indicating that the imprinting effect is effectively suppressed.

[0093] The above results demonstrate that the electrostatic shielding effect is positively correlated with the electrode coating length. A longer coating distance results in more effective electrostatic shielding of the ferroelectric domain region, thus more effectively counteracting the adverse effects of the depolarization field and improving the device's retention characteristics. This principle provides a clear technological implementation path for optimizing electrostatic shielding structure design and realizing high-performance ferroelectric memory cells.

[0094] Example 4 provides a specific design scheme for a three-sided single-ended electrostatic shielded ferroelectric storage cell structure.

[0095] Figure 8 This is a plan view of a three-sided (including left, right, and top) single-ended electrostatic shielded ferroelectric memory cell structure provided in Embodiment 4 of the present invention. The left side is a top view, and the right side is a cross-sectional view. Figure 7 As shown, the memory cell structure includes: a ferroelectric substrate 104, ferroelectric bumps 102 formed on the substrate, and a first electrode 1011 and a second electrode 1012 respectively disposed on both sides of the ferroelectric bumps.

[0096] Specifically, the ferroelectric substrate 104 includes, but is not limited to, lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, and their doped materials. The ferroelectric bumps 102 are defined and formed on the substrate using a micro / nano fabrication etching process. Subsequently, a conductive metal layer is deposited on the surfaces of the substrate 104 and the ferroelectric bumps 102 using a thin-film deposition method, and electrode patterns are defined using electron beam lithography. Then, a first electrode 1011 and a second electrode 1012, spaced apart from each other, are formed by an etching process. The first electrode 1011 is designed to form a three-sided covering structure on the top and adjacent sidewalls of the ferroelectric bump 102, while the second electrode 1012 is disposed on the opposite end of the ferroelectric bump.

[0097] In this embodiment, applying a positive write voltage greater than the coercive voltage Vc between the first electrode and the second electrode can cause the internal domains of the device to flip, and a conductive domain wall is formed between the flipped domains and the unflipped domains. At this time, applying a read voltage between the first electrode and the second electrode can obtain a low-resistance state "1". Applying a negative write voltage greater than the coercive voltage Vc between the first electrode and the second electrode can cause the internal domains of the device to return to their initial direction and the conductive domain wall disappears. At this time, applying a read voltage between the first electrode and the second electrode can obtain a high-resistance state "0".

[0098] The following describes the device test results based on Example 4.

[0099] In this embodiment, the device is a three-sided single-ended electrostatic shielding structure with different coverage lengths obtained by using the same substrate material and fabrication process as in Embodiment 3.

[0100] Figure 9 Scanning electron microscope (SEM) images of a series of memory cell structures with different electrostatic shielding coverage lengths L2, prepared by the above-described process, are presented. The coverage lengths L2 of the devices shown are 0 nm, 100 nm, 138 nm, and 185 nm, respectively, visually demonstrating the structural morphology evolution from no coverage to different degrees of three-sided coverage.

[0101] The first electrode 1011 serves as a conductive layer to form a three-sided covering structure for the ferroelectric bump 102. Compared to the single-sided covering in Embodiment 3, this structure provides electrostatic shielding and charge injection paths for the ferroelectric-electrode contact area from more physical dimensions, thereby more effectively suppressing the depolarization field, significantly shortening the time for imprinting effects, and further improving the stability and read / write speed of ferroelectric domain switching.

[0102] Figure 10 The hysteresis loop measurement results of the ferroelectric memory cell under different electrostatic shielding lengths in this embodiment are presented. The tests show that when the shielding length L2 is 0 nm (i.e., no shielding), the negative coercive voltage of the device is close to 0V, and the hysteresis loop follows the write voltage axis (V... w The severe asymmetry in the direction indicates poor retention performance, making it difficult to store information stably for a long time. With the increase of the three-sided coverage length (to 100 nm, 138 nm, 185 nm), the absolute value of the negative coercive voltage increases significantly (up to -5V or more), and the symmetry of the hysteresis loop is significantly improved.

[0103] The results demonstrate that a three-sided shielding structure more effectively enhances electrostatic shielding, and this effect is positively correlated with the shielding length. A longer shielding distance provides more comprehensive protection for the ferroelectric switching region, effectively overcoming the adverse effects of the depolarization field and thus significantly improving the device's retention characteristics. This finding further confirms the crucial role of electrostatic shielding structures in optimizing the performance of ferroelectric memory cells.

[0104] Example 5 provides several design schemes for ferroelectric storage cell structures with electrostatic shielding.

[0105] This embodiment lists several electrostatic shielding structures with engineering feasibility, specifically as follows: Figures 11 to 20 As shown in the figures, the left side of each figure is a top view of the corresponding structure, and the right side is a cross-sectional view of the structure. These structures are for illustrative purposes only. Based on the characteristics of different electrode coating dimensions, geometric shapes, and process integration, they provide a variety of feasible technical paths for optimizing electrostatic shielding effects, process compatibility, and storage density.

[0106] The specific structure types are explained below:

[0107] Figure 11 A four-sided single-ended electrostatic shielded ferroelectric memory cell structure is demonstrated, wherein the first electrode completely covers one end of the ferroelectric bump and all four sides, providing the most sufficient electrostatic shielding, and is especially suitable for application scenarios with extremely high requirements for suppressing interface effects.

[0108] Figure 12A toroidal single-end electrostatic shielded ferroelectric storage cell structure is demonstrated, in which the first electrode covers the end and sidewall of the ferroelectric body in a ring or partially encircling form. This structure not only ensures effective shielding but also simplifies the graphic complexity and reduces the difficulty of fabrication.

[0109] Figure 13 A three-sided electrostatically shielded ferroelectric storage cell structure is shown, in which the first and second electrodes cover the two ends of the ferroelectric material and the three adjacent sidewalls.

[0110] Figure 14 and Figure 15 The double-sided electrostatically shielded ferroelectric storage cell structure and its single-end variant are shown respectively, wherein the first electrode or the second electrode covers one end of the ferroelectric body and two adjacent sidewalls.

[0111] Figure 16 , Figure 17 and Figure 18 The electrostatically shielded ferroelectric storage cell structure and its single-ended variant are shown respectively, wherein the first electrode or the second electrode covers one end of the ferroelectric body and an adjacent sidewall. Figure 16 and Figure 17 Furthermore, a groove design was adopted, which helps to enhance local field modulation or adapt to specific etching and filling processes.

[0112] Figure 19 and Figure 20 These studies showcase electrostatically shielded ferroelectric memory cell structures based on single-sided and double-sided single-sided conductive domain walls. In these designs, the electrostatic shielding function is achieved by conductive domain wall layers formed within the ferroelectric material. This approach combines functional material properties with structural design, providing an innovative approach to achieving efficient electrostatic shielding at the nanoscale, which is particularly beneficial for ultra-high-density integration.

[0113] All the aforementioned structural variants provide electrostatic shielding by forming varying degrees of conductive enclosure at the interface between the ferroelectric material and the electrode in the ferroelectric memory cell through a first electrode, a second electrode, or conductive domain walls. Their core mechanisms are consistent: suppressing the depolarization field during the information retention phase to stabilize the "1" or "0" state; and suppressing the imprinting effect during the write operation phase to ensure the voltage symmetry of the "0" to "1" and "1" to "0" transitions, thus shortening the imprinting effect time. These specific implementations collectively constitute the complete design system of this invention at the device structure level, demonstrating its broad technical applicability and engineering flexibility.

[0114] Example 6 provides a design scheme for an electrostatically shielded ferroelectric storage planar array structure.

[0115] Figure 21 This is a top view schematic diagram of an electrostatically shielded ferroelectric storage planar array provided in an embodiment of the present invention. Figure 22This is a cross-sectional schematic diagram of the array structure in this embodiment. For the sake of simplicity, Figure 21 and Figure 22 The text does not depict non-core details such as the isolation layer and the peripheral operating circuits of the storage unit.

[0116] The memory array structure of this embodiment includes: a word line layer WL, a bit line layer BL, a plurality of conductive plugs 2012, a plurality of ferroelectric memory cells 202 formed by word lines and conductive plugs, and an isolation layer.

[0117] Multiple word lines WL1, WL2, and WL3 are arranged sequentially on the word line layer WL along the ferroelectric polarization direction shown in the figure. The word line structure is designed as a strip electrode with multiple raised conductive isolation structures 205. The conductive isolation structure 205 is integrally formed with the word line WL using the same conductive material and is used to provide side electrostatic shielding for adjacent ferroelectric memory cells.

[0118] An array of conductive plugs 2012 is arranged sequentially between two adjacent lines along the ferroelectric polarization direction, and each conductive plug 2012 has a conductive post connected to it.

[0119] The bit line layer BL is positioned above the word line layer and is connected to the conductive plug via conductive posts. Multiple bit lines BL1, BL2, BL3, BL4… are arranged sequentially along the vertical direction. The vertical direction is perpendicular to the ferroelectric polarization direction.

[0120] The area where the conductive plug 2012 intersects with the adjacent word line forms a ferroelectric memory cell 202. The raised conductive isolation structure 205 provides electrostatic shielding for the ferroelectric memory cell. Two adjacent ferroelectric memory cells 202 on the same word line can share a conductive isolation structure 205, thereby effectively improving the integration density of the array. The electrostatic shielding structure design can significantly improve the information retention performance of each memory cell in the array.

[0121] The ferroelectric storage device materials include, but are not limited to, lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, and their doped materials. The word lines, bit lines, and conductive plugs are conductive materials, including but not limited to tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and tantalum nitride.

[0122] In this embodiment, the initial polarization direction of the ferroelectric material points from the word line WL1 to the conductive plug 2012.

[0123] In this embodiment, the isolation layer 301 is disposed in the remaining space outside the bit line layer, word line layer, ferroelectric memory cell 202, and conductive plug 2012. Specifically, the insulating layer between the ferroelectric memory cells can be the ferroelectric material itself, and the remaining space is filled with insulating materials including but not limited to alumina, hafnium oxide, silicon oxynitride, silicon nitride, or silicon oxide.

[0124] In this embodiment, when a positive write voltage is applied simultaneously to the word line WL1 and the bit line BL1, and the memory cell at the intersection of the word line WL1 and the bit line BL1 is subjected to a bias voltage V greater than the coercivity voltage Vc, the internal domains of the device will flip, and a conductive domain wall will be formed between the flipped domains and the unflipped domains. At this time, applying a read voltage to the memory cell will yield a low-resistance state "1". When a negative write voltage is applied simultaneously to the word line WL1 and the bit line BL1, the flipped domains will return to their initial state, and the conductive domain wall will disappear. At this time, applying a read voltage to the memory cell will yield a high-resistance state "0".

[0125] During the ferroelectric domain flipping process, the conductive shielding structure 205 will shield the charge at the ferroelectric and electrode interface, significantly reducing the depolarization field, shortening the imprinting effect time, extending the domain retention time, and improving the information retention time of the storage unit.

[0126] Example 7 provides a design scheme for a ferroelectric storage planar array structure based on electrostatic shielding of conductive ferroelectric domain walls.

[0127] Figure 23 This is a top view of the array structure provided in this embodiment. Figure 24 Here is a corresponding cross-sectional diagram. For the sake of simplicity, Figure 23 and Figure 24 The text does not depict non-core details such as the isolation layer and the peripheral operating circuits of the storage unit.

[0128] The memory array structure of this embodiment includes: a word line layer WL, a bit line layer BL, a plurality of conductive plugs 2012, a plurality of ferroelectric memory cells 202 formed by word lines and conductive plugs, ferroelectric domain wall conductive layers 2051 and 2052 serving as conductive shielding structures, and an isolation layer.

[0129] Multiple word lines WL1, WL2, WL3, and WL4 are arranged sequentially along the ferroelectric polarization direction shown in the figure on the word line layer WL. The word line structure is designed as a strip electrode with multiple raised conductive isolation structures 205. The conductive isolation structure 205 is integrally formed with the word line WL using the same conductive material, and is used to form ferroelectric domain wall conductive layers 2051 and 2052 for the ferroelectric memory cell.

[0130] An array of conductive plugs 2012 is arranged sequentially between two adjacent lines along the ferroelectric polarization direction, and each conductive plug 2012 has a conductive post connected to it.

[0131] The bit line layer BL is positioned above the word line layer and connected to the conductive pillars. Multiple bit lines BL1, BL2, BL3, and BL4 are arranged sequentially along a vertical direction. This vertical direction is perpendicular to the ferroelectric polarization direction.

[0132] The area near the intersection of the conductive plug 2012 and the adjacent word line is a ferroelectric memory cell 202. The ferroelectric domain wall conductive layers 2051 and 2052 provide electrostatic shielding for the ferroelectric memory cell. Two adjacent ferroelectric memory cells 202 on the same word line can share a conductive isolation structure 205, thereby effectively improving the array's storage density. The electrostatic shielding structure design can significantly improve the information retention performance of each memory cell in the array.

[0133] The ferroelectric storage device materials include, but are not limited to, lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, and their doped materials. The word lines, bit lines, and conductive plugs are conductive materials, including but not limited to tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and tantalum nitride.

[0134] In this embodiment, the initial polarization direction of the ferroelectric material points from the word line WL1 to the conductive plug 2012.

[0135] In this embodiment, the isolation layer 301 is disposed in the remaining space outside the bit line layer, word line layer, ferroelectric memory cell 202, and conductive plug 2012. Specifically, the insulating layer between the ferroelectric memory cells can be the ferroelectric material itself, and the remaining space is filled with insulating materials including but not limited to alumina, hafnium oxide, silicon oxynitride, silicon nitride, or silicon oxide.

[0136] In the initial ferroelectric material, all domain orientations will follow the initial ferroelectric polarization direction. A write voltage greater than the first coercive voltage Vc1 is applied to all word lines WL and bit lines BL, causing all domains within the array to flip. Conductive domain walls are formed between the flipped and unflipped domains, forming ferroelectric domain wall conductive layers 2051 and 2052. Subsequently, a reverse write voltage less than the first coercive voltage but greater than the second coercive voltage Vc2 is applied to all word lines WL and bit lines BL, causing the domains of all memory cells 202 within the array to return to their initial orientation. The first coercive voltage Vc1 refers to the coercive voltage capable of flipping the domains in regions 2051 and 2052; the second coercive voltage refers to the voltage capable of flipping the domains within memory cell 202, but insufficient to flip the domains in regions 2051 and 2052.

[0137] In this embodiment, a bias voltage less than the first coercive voltage but greater than the second coercive voltage is simultaneously applied to the word line WL1 and the bit line BL1. When the memory cell at the intersection of the word line WL1 and the bit line BL1 is subjected to a write voltage V greater than the coercive voltage Vc, the internal domains inside the memory cell will flip, forming a conductive domain wall. When a read voltage is applied to the memory cell, a low-resistance state "1" can be obtained. When a reverse write voltage is simultaneously applied to the word line WL1 and the bit line BL1, the internal domains of the memory cell 202 return to their initial state, and the conductive domain wall disappears. At this time, when a read voltage is applied to the memory cell, a high-resistance state "0" can be obtained.

[0138] In this embodiment, the conductive domain walls 2051 and 2052 formed inside the ferroelectric memory cell constitute the conductive shielding structure, which is used to provide electrostatic shielding for the ferroelectric memory cell, thereby improving the retention performance and read / write speed of all devices inside the array.

[0139] Example 8 provides a three-dimensional stacked structure design for electrostatically shielded ferroelectric memory cells.

[0140] Figure 25 This is a schematic diagram of the three-dimensional stacked structure provided in this embodiment. Figure 26 This is a top view diagram corresponding to this embodiment. Figure 26 This is a cross-sectional schematic diagram corresponding to this embodiment. For the sake of simplicity, Figure 25 , Figure 26 and Figure 27 The text does not depict non-core details such as the isolation layer between the word line layer and the bit line interconnect layer, or the peripheral operation circuitry of the memory cells.

[0141] The memory array structure of this embodiment is a multi-layer stack of the planar array structure described in Embodiment 6 or 7 in the vertical direction, aiming to significantly increase storage density. This three-dimensional stacked structure includes: multiple word line layers WL and multiple isolation layers 306 stacked alternately in the out-of-plane direction, bit line electrodes 3012 formed by a number of conductive vias penetrating the stacked layers, bit line interconnect layer BL, a number of ferroelectric memory cells 302 formed by each word line layer WL and the corresponding bit line electrodes, and isolation layers.

[0142] The structure and function of each word line layer WL are similar to those in Embodiment 6 or 7. Multiple word lines (WL1-1, WL1-2, WL1-3, WL2-1...) are arranged sequentially on it along the initial ferroelectric polarization direction shown in the figure. The word line is a strip-shaped electrode with multiple raised conductive isolation structures 305. The conductive isolation structure 305 is integrally formed with the word line using the same conductive material and is used to provide side electrostatic shielding for adjacent ferroelectric memory cells in the same layer.

[0143] An array of bit line electrodes 3012 is arranged sequentially in a direction perpendicular to the ferroelectric polarization direction between adjacent word lines, with a conductive post connected to each bit line electrode 3012. The bit line electrodes 3012 penetrate out of plane, and word line layers at the same horizontal level intersect with the bit line electrodes to form a storage plane. Within each storage plane, the bit line electrodes 3012 intersect with word lines of the same layer to form ferroelectric memory cells 302 located on that plane. A raised conductive isolation structure 305 is inserted between two adjacent ferroelectric memory cells 302 on the same word line to provide electrostatic shielding.

[0144] The bit line interconnect layer BL is disposed above the word line layer and is connected to the bit line electrodes through conductive pillars. Its structure corresponds to that of planar embodiments 6 and 7. Multiple bit lines (BL1, BL2, BL3...) are arranged sequentially along a direction perpendicular to the ferroelectric polarization direction.

[0145] The word line layer BL achieves selective electrical connection at a specific level through peripheral circuitry to complete the gating operation of a specific memory plane.

[0146] The ferroelectric memory device materials include, but are not limited to, lithium niobate, lithium tantalate, bismuth ferrite, lead zirconate titanate, and their doped materials. The word line electrodes and bit line electrodes are conductive materials, including but not limited to tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and tantalum nitride.

[0147] In this embodiment, the isolation layer fills the remaining space outside the word line layer WL, bit line interconnect layer BL, ferroelectric memory cell 302 and bit line electrode 3012. Specifically, it includes the interlayer dielectric layer 306 and the isolation layer between the word line layer and the bit line interconnect layer. The insulating layer between the ferroelectric memory cells can be the ferroelectric material itself. The remaining space is filled with insulating materials including but not limited to alumina, hafnium oxide, silicon oxynitride, silicon nitride or silicon oxide.

[0148] The operating principle of this embodiment is the same as that of the planar array described in Embodiments 6 or 7. By selecting the word line WL1 and bit line electrode 3012 on a specific word line layer through the peripheral circuit, read and write operations can be performed on a specific ferroelectric memory cell 302 in the target memory plane. Applying a write voltage greater than the coercive voltage can cause the internal domains of the cell to flip and form conductive domain walls. At this time, applying a read voltage to the cell will result in a low-resistance state "1". Applying a reverse write voltage greater than the coercive voltage can cause the internal domains of the cell to return to their initial state and the conductive domain walls to disappear. At this time, applying a read voltage to the cell will result in a high-resistance state "0".

[0149] When a domain flipping operation is performed on a selected cell, the electrostatic shielding network composed of conductive isolation structures 305 in the same layer can effectively achieve electrostatic shielding, significantly reduce the impact of depolarization field on the target memory cell, shorten the imprinting effect time, and thus significantly improve the information retention performance and operational reliability of all memory cells in the entire three-dimensional stacked array.

[0150] In summary, this invention proposes a method to improve the read / write reliability of ferroelectric memories based on electrostatic shielding. By constructing a conductor surrounding the ferroelectric memory cell in the electrode region, effective electrostatic shielding is achieved, shortening the imprinting effect time. This method is applicable to various ferroelectric material systems, significantly reducing the intensity of depolarization and imprinting fields, improving hysteresis loop symmetry, increasing memory read / write speed, and is compatible with existing semiconductor manufacturing processes. Furthermore, this invention can be applied to single memory cells, planar crossbar arrays, and three-dimensional stacked structures, and is compatible with high-density memory integration schemes. While maintaining the advantages of high memory density, it comprehensively improves the stability of "1" and "0" states and the consistency of write operations in each memory cell, providing an effective technical approach for the large-scale manufacturing and application of high-speed, high-density, and highly reliable ferroelectric memories.

Claims

1. A method for improving the reliability of read / write operations of ferroelectric memory through electrostatic shielding, characterized in that, Electrostatic shielding conductive structures are introduced into the interface region between the ferroelectric material and the electrode in ferroelectric memory to accelerate the charge injection speed of the interface layer, reduce the ferroelectric depolarization field, and achieve symmetry of positive and negative write voltages during rapid operation of ferroelectric memory. This improves the reliability of read and write operations of high-density ferroelectric memory at high speed. Ferroelectric memory with introduced electrostatic shielding structures is called electrostatic shielded ferroelectric memory.

2. The method according to claim 1, characterized in that, For ferroelectric memories with ferroelectric storage cell structures, the electrostatic shielding structure and the layout of the ferroelectric memory are as follows: The ferroelectric memory comprises a ferroelectric body and a first electrode and a second electrode respectively disposed on both sides of the ferroelectric body; wherein, at least one of the first electrode and the second electrode is provided with a conductive shielding structure integrally formed or electrically connected thereto; and the conductive shielding structure at least partially covers the ferroelectric memory cell, including the end face of the corresponding side and the adjacent side face, forming a conductive enclosure of the interface layer region formed between the ferroelectric body and the electrode end face; the conductive shielding structure is physically isolated from the other electrode through a gap or an insulating dielectric layer. The conductive shielding structure, when the ferroelectric memory is in the holding state, is used to shield the depolarization field generated by the failure to compensate the ferroelectric polarization charge in the interface layer in time, so as to prevent the logic state of "1" or "0" recorded in the memory cell from being reversed due to the interference of the depolarization field or other stray electric fields, thereby improving the information non-volatile retention capability. The conductive shielding structure is used to significantly shorten the space charge injection time, i.e. the imprinting time, within the interface layer when the ferroelectric memory is in the write operation state. The injected charge can be captured by the interface defect state, timely compensate for the ferroelectric polarization charge, reduce the depolarization field, improve the read and write speed of the memory, and keep the coercive voltage required to write the "1" state of the memory cell symmetrical with the coercive voltage required to write the "0" state, thereby improving the consistency and reliability of the write operation.

3. The method according to claim 2, characterized in that, The conductive shielding structure covers a portion of the ferroelectric memory cell, including the region that is prone to forming an interface layer in contact with the electrodes; wherein, the conductive shielding structure covers the end face and side face of the ferroelectric memory cell, and the continuous length along the side face direction is not less than 1 nm and not greater than 10 nm. m; The continuous length of the conductive shielding structure along the side of the ferroelectric storage cell is related to the electrostatic shielding effect, including all or part of the four sides: top, bottom, left, and right.

4. The method according to claim 2, characterized in that, The ferroelectric materials used in the ferroelectric storage unit are selected from lithium niobate, lithium tantalate, bismuth ferrite, and lead zirconate titanate; they are single crystals, thin films, or lithium niobate, lithium tantalate, or bismuth ferrite salts doped with MgO, Mn2O5, or Fe2O3, or blackened lithium niobate or blackened lithium tantalate. The electrode and conductive shielding structure are made of metallic conductive materials or non-metallic conductive materials; the metallic conductive materials are selected from tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, silver, and gold; the non-metallic conductive materials are selected from tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, and tantalum nitride.

5. The method according to claim 1, characterized in that, The ferroelectric memory employs a crossbar storage two-dimensional array structure, specifically comprising multiple ferroelectric memory cells with electrostatic shielding structures arranged in an orthogonal grid pattern within a two-dimensional plane. Each ferroelectric memory cell includes a ferroelectric material, word line electrodes, bit line electrodes, and a conductive shielding structure. Specifically, in the crossbar storage array, multiple word line electrodes are arranged parallel to each other along a first direction, corresponding to the initial polarization direction of the ferroelectric material, and multiple bit line electrodes are arranged parallel to each other along a second direction perpendicular to the first direction. Electrical isolation and mechanical support are achieved between the word line electrodes and the bit line electrodes through an interlayer dielectric layer or gap. Each ferroelectric memory cell is located near the intersection of a word line electrode and a bit line electrode, and is connected to the corresponding word line electrode and bit line electrode. Wherein, at least one of the word line electrodes and bit line electrodes is provided with a conductive shielding structure integrally formed or electrically connected thereto; adjacent ferroelectric memory cells are provided with a shared or independent conductive shielding structure; the conductive shielding structure at least partially covers the ferroelectric memory cell, including the end face of the corresponding side and the adjacent side face, forming a conductive enclosure of the interface layer region formed between the ferroelectric body and the electrode end face; a gap or insulating dielectric layer is provided between the conductive shielding structure and the other electrode of the ferroelectric memory cell to achieve physical isolation and avoid electrical short circuit; The conductive shielding structure, when the storage unit is in the holding state, is used to shield the depolarization field or other stray electric fields generated by the uncompensated ferroelectric polarization charge in the ferroelectric and electrode interface layer region, to prevent the "1" or "0" state from being reversed. The conductive shielding structure significantly shortens the space charge injection time, i.e. the imprinting time, in the interface layer region when the memory cell is in a write operation. This space charge can shield the ferropolarized charge, reduce the depolarization field, and ensure that the domain reversal process from "0" to "1" and from "1" to "0" has equal absolute coercive voltage, thereby improving the read and write operation reliability of the entire stacked array, and improving the memory read and write speed and information retention time.

6. The method according to claim 5, characterized in that, In the ferroelectric memory cell, the conductive shielding structure covers the end face and side face of the ferroelectric memory cell, and the continuous length along the side face direction, the shape of the ferroelectric memory cell, the ferroelectric material, the materials of the electrodes and the conductive shielding structure are the same as those described in claims 2-5.

7. The method according to claim 5, characterized in that, The material of the interlayer dielectric layer is selected from the ferroelectric storage medium itself, alumina, hafnium oxide, silicon oxynitride, silicon nitride, or silicon oxide; The materials of the word line electrode, bit line electrode and the other electrode are selected from tungsten, titanium, chromium, copper, nickel, aluminum, platinum, iridium, ruthenium, tantalum, niobium, silver, gold, tungsten nitride, titanium nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide and tantalum nitride.

8. The method according to claim 1, characterized in that, The ferroelectric memory adopts a three-dimensional array stacked structure. The three-dimensional array includes multiple word line layers and multiple interlayer dielectric layers that are alternately stacked in the vertical direction, and bit line electrodes formed by several conductive vias penetrating each stacked layer, thereby forming a vertical extension structure of a multilayer crossbar memory array. Each word line layer includes a plurality of strip word line electrodes arranged parallel to a first direction, corresponding to the initial polarization direction of the ferroelectric material, and a bit line electrode array arranged between two adjacent word lines in a second direction perpendicular to the first direction; each word line electrode and the adjacent bit line electrode form a ferroelectric memory cell near the intersection, and the ferroelectric body of the cell is connected to the corresponding word line electrode and bit line electrode respectively. Wherein, at least one of the word line electrodes and bit line electrodes is provided with a conductive shielding structure integrally formed or electrically connected thereto; the conductive shielding structure is independently provided inside each ferroelectric memory layer, or forms a shared or partially shared structure between adjacent memory cells or between adjacent stacked layers; the conductive shielding structure at least partially covers the ferroelectric memory cell, including the end face of the corresponding side and the adjacent side face, forming a conductive enclosure of the interface layer region formed between the ferroelectric body and the electrode end face; a gap or insulating dielectric layer is provided between the conductive shielding structure and the other electrode of the ferroelectric memory cell to achieve physical isolation and avoid electrical short circuit; The conductive shielding structure, when the storage unit is in the holding state, is used to shield the depolarization field or other stray electric fields generated by the uncompensated ferroelectric polarization charge in the ferroelectric and electrode interface layer region, to prevent the "1" or "0" state from being reversed. The conductive shielding structure significantly shortens the space charge injection time, i.e. the imprinting time, in the interface layer region when the memory cell is in a write operation. This space charge can shield the ferropolarized charge, reduce the depolarization field, and ensure that the domain reversal process from "0" to "1" and from "1" to "0" has equal absolute coercive voltage, thereby improving the read and write operation reliability of the entire stacked array and improving the memory read and write speed and information retention time.

9. The method according to claim 8, characterized in that: In the ferroelectric memory cell, the conductive shielding structure covers the end face and side face of the ferroelectric memory cell, and the continuous length along the side face direction, the shape of the ferroelectric memory cell, the ferroelectric material, the material of the electrodes and the conductive shielding structure are the same as those described in claims 3 and 4. The materials of the interlayer dielectric layer and the insulating dielectric layer, and the materials of the word line electrode and the bit line electrode are the same as those described in claim 7.

10. An electrostatically shielded ferroelectric memory constructed in the method of claim 1, specifically constructed in the method of any one of claims 2, 3, and 4, wherein the ferroelectric memory is a ferroelectric memory cell structure; or constructed in the method of any one of claims 5, 6, and 7, wherein the ferroelectric memory is a crossbar storage two-dimensional array structure; or constructed in the method of any one of claims 8 and 9, wherein the ferroelectric memory is a three-dimensional array stacked structure.

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