An inverter circuit with an LCR parallel structure as the load and its working method

Abstract

The present invention discloses an inverter circuit with an LCR parallel structure as a load, the circuit includes an inverter circuit, a negative pressure detection circuit and a frequency regulation circuit; the detection end of the negative pressure detection circuit is connected to the inverter circuit, the output end of the negative pressure detection circuit is connected to the frequency regulation circuit, and the output end of the frequency regulation circuit outputs a driving pulse to respectively control the conduction conditions of different switch tubes in the inverter circuit. The inverter circuit with an LCR parallel structure as a load provided by the present application cleverly utilizes the characteristic parameters in the middle circuit after the upper and lower bridge arms of the inverter circuit are switched, and uses the characteristic parameters as the basis for frequency regulation to adjust the operating frequency of the inverter circuit, fully considering the actual on-off time of each switch tube in the inverter circuit, reserving reaction time for each switch tube, and effectively utilizing the resonance characteristics of the LCR parallel load to ensure that the circuit works effectively. When applied to practice, good use effects are achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electromagnetic induction, and particularly relates to an inverter control circuit. Background Art

[0002] Three-phase alternating current is converted into direct current voltage through an uncontrolled rectification and filtering circuit. This voltage is sent to a DC chopper for chopping regulation, and after becoming an approximately constant current source with adjustable power, it is input into an inverter. In the inverter, the upper and lower bridge arms are composed of paired switching tubes. By sending drive pulses through a drive circuit, the conduction and cutoff of different switching tubes are controlled, the conduction states of the upper and lower bridge arms are switched, the path of the circuit current is changed, and the flow direction of the current at the output end of the inverter is changed, so that alternating current with a corresponding alternating frequency can be obtained at the output end of the inverter and output to the load.

[0003] When the inverter uses an LCR parallel structure as the load, the specific circuit settings in the inverter will change to a certain extent with the load, and the phase of the voltage and current in the circuit will also be directly affected by the load. As Figure 1 shown is the circuit schematic diagram when a power supply including an inverter is connected to an LCR parallel load in the prior art. In this circuit, a DC source A DC and a constant current inductor L1 are provided at the front end of the inverter. A stable direct current is input into the inverter at the constant current inductor L1. The inverter is composed of four switching tubes TA / TB / TC / TD. Considering the particularity of the load, corresponding diodes DA / DB / DC / DD are respectively provided for the four switching tubes TA / TB / TC / TD in the inverter to avoid current backflow. Each switching tube is correspondingly provided with a drive circuit, and the drive circuit outputs drive pulses corresponding to the switching tube, and the corresponding switching tube is turned on or off at the expected time point, so that alternating current with a corresponding alternating frequency can be obtained at the output end of the inverter, and this alternating current is output to an LCR parallel load composed of a load capacitor C1, a load resistor R1, and a load inductor L2 to drive the load to work.

[0004] When the above-mentioned inverter uses an LCR parallel structure as the load, during operation, since the LCR parallel load has its own inherent resonance frequency, its resonance characteristics will directly affect the phase conditions of the voltage and current in the inverter. To ensure the normal operation of the inverter and ensure that the power supply can provide the most suitable alternating current for the load, generally, it is desired that the current in the inverter is slightly ahead of the voltage while the current and voltage are as consistent as possible. Therefore, it can be seen that how to control the operation of the inverter, while ensuring the long-term stable operation of each switching tube in the inverter, and ensuring that the alternating current output by the inverter can efficiently drive the LCR parallel load is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] To solve the above problems, the object of the present invention is to provide an inverter circuit with an LCR parallel structure as the load. On the basis of the traditional inverter circuit, this circuit adds a negative voltage detection circuit and a frequency adjustment circuit. The on-off conditions of each switching tube in the inverter circuit are regulated based on the real-time parameters in the inverter circuit. On the premise of ensuring the normal operation of the inverter circuit, the resonance characteristics of the LCR parallel load are matched, and the switching of the upper and lower bridge arms of the full-bridge inverter in the inverter circuit is made smoother, safer, and more reliable.

[0006] Another object of the present invention is to provide a working method for an inverter circuit with an LCR parallel structure as the load. Based on its inverter circuit, on the one hand, a reaction time for each switching tube in the full-bridge inverter to change its state is reserved, and on the other hand, the on-off moments and on-off frequencies of each switching tube are dynamically adjusted according to the indication of the real-time parameters in the inverter circuit, and the operation of the inverter circuit is controlled to ensure that its output is a smooth alternating current that matches the load.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] An inverter circuit with an LCR parallel structure as the load, the circuit includes:

[0009] A full-bridge inverter composed of paired switching tubes, an inverter circuit for converting the input direct current into alternating current;

[0010] A negative voltage detection circuit for detecting the occurrence duration of the commutation negative voltage in the inverter circuit;

[0011] And a frequency adjustment circuit for correspondingly adjusting the on-off frequency of the switching tube in the inverter circuit according to the occurrence duration of the commutation negative voltage detected by the negative voltage detection circuit;

[0012] The detection end of the negative voltage detection circuit is connected to the inverter circuit, the output end of the negative voltage detection circuit is connected to the frequency adjustment circuit, and the output end of the frequency adjustment circuit outputs drive pulses to respectively control the conduction conditions of different switching tubes in the inverter circuit.

[0013] Further, the negative voltage detection circuit includes:

[0014] A high-voltage detector with two detection ends for detecting the real-time voltage between its two detection ends;

[0015] And a negative voltage pulse generator corresponding to the high-voltage detector, which outputs a pulse with a corresponding width at the moments of the appearance and disappearance of the voltage when the high-voltage detector detects the voltage.

[0016] One detection terminal of the high-voltage detector is connected to one input terminal of the full-bridge inverter in the inverter circuit, and the other input terminal of the high-voltage detector is connected to the other input terminal of the full-bridge inverter in the inverter circuit; the output terminal of the high-voltage detector is connected to the negative voltage pulse generator.

[0017] Furthermore, the frequency adjustment circuit includes:

[0018] A negative pulse time calculator for calculating the duration of the input pulse and outputting a voltage corresponding to the duration;

[0019] And, corresponding to the setting of the negative pulse time calculator, a negative pulse time comparator for performing a comparison operation between the actual output of the negative pulse time calculator and the externally given negative pulse time;

[0020] The input terminal of the negative pulse time calculator is connected to the negative pulse generator, the output terminal of the negative pulse time calculator is connected to one input terminal of the negative pulse time comparator, and the externally given negative pulse time is connected to the other input terminal of the negative pulse comparator.

[0021] Furthermore, the frequency adjustment circuit also includes:

[0022] A V / F voltage-frequency converter for converting the input voltage into a frequency corresponding to the magnitude;

[0023] And, a PFM pulse frequency regulator for outputting the upper-bridge arm drive pulse, dead-time pulse, and lower-bridge arm drive pulse to control the on / off conditions of different arms of the full-bridge inverter in the inverter circuit;

[0024] The input terminal of the V / F voltage-frequency converter is connected to the output terminal of the negative pulse comparator, and the output terminal of the V / F voltage-frequency converter is connected to the PFM pulse frequency regulator.

[0025] Furthermore, the frequency adjustment circuit also includes a first OR gate and a second OR gate. The input terminal of the first OR gate is connected to the upper-bridge arm drive pulse and dead-time pulse output by the PFM pulse frequency regulator; the input terminal of the second OR gate inputs the lower-bridge arm drive pulse and dead-time pulse output by the PFM pulse frequency regulator; the output terminal of the first OR gate outputs the upper-bridge arm actual pulse for actually controlling the conduction or cut-off of the upper-bridge arm of the full-bridge inverter in the inverter circuit; the output terminal of the second OR gate outputs the lower-bridge arm actual pulse for actually controlling the conduction or cut-off of the lower-bridge arm of the full-bridge inverter in the inverter circuit.

[0026] Further, a monostable flip-flop is also included in the frequency adjustment circuit; one input terminal of the monostable flip-flop is connected to the output terminal of the negative voltage pulse generator, the dead-time pulse output at the output terminal of the PFM pulse frequency regulator is connected to the trigger inversion terminal of the monostable flip-flop, and the output terminal of the monostable flip-flop is respectively connected to the first OR gate and the second OR gate.

[0027] Further, the circuit also includes an emergency stop circuit; the emergency stop circuit includes:

[0028] A voltage sensor for detecting the real-time voltage between the two output terminals of the inverter circuit;

[0029] A voltage zero-crossing comparator for detecting the zero-crossing moment point of the real-time voltage between the two output terminals of the inverter circuit;

[0030] A zero-crossing pulse generator for outputting a positive zero-crossing pulse corresponding to the positive voltage zero-crossing moment point of the real-time voltage between the two output terminals of the inverter circuit and outputting a negative zero-crossing pulse corresponding to the negative voltage zero-crossing moment point of the real-time voltage between the two output terminals of the inverter circuit according to the detection result of the voltage zero-crossing comparator;

[0031] A current lag voltage cut-off device for detecting the phase relationship between the real-time voltage and the real-time current in the inverter circuit and outputting a cut-off pulse once it detects that there is real-time current lagging behind the real-time voltage in the inverter circuit;

[0032] And, a synchronization pulse generator is provided corresponding to the current lag voltage cut-off device, which emits a synchronization pulse once the current lag voltage cut-off device outputs a cut-off pulse, and further controls the inverter circuit to return to the state where the real-time current leads the real-time voltage;

[0033] The detection terminal of the voltage sensor is connected to the two output terminals of the inverter circuit, and the output terminal of the voltage sensor is connected to the voltage zero-crossing comparator; the output terminal of the voltage zero-crossing comparator is connected to the zero-crossing pulse generator, the output terminal of the zero-crossing pulse generator is connected to the current lag voltage cut-off device, the output terminal of the current lag voltage cut-off device is connected to the synchronization pulse generator, and the output terminal of the synchronization pulse generator is connected to the PFM pulse frequency regulator; the output terminal of the synchronization pulse generator is also connected to the other input terminal of the monostable flip-flop.

[0034] Further, the current lag voltage cut-off device includes a first AND gate, a second AND gate, and a third OR gate; one input terminal of the first AND gate is connected to the positive zero-crossing pulse; its other input terminal is connected to the upper bridge arm drive pulse, and its output terminal is connected to one input terminal of the third OR gate; one input terminal of the second AND gate is connected to the negative zero-crossing pulse, its other input terminal is connected to the lower bridge arm drive pulse, and its output terminal is connected to the other input terminal of the third OR gate; the output terminal of the third OR gate is connected to the synchronization pulse generator.

[0035] The present application also provides a working method for an inverter circuit with an LCR parallel structure as the load. This method is based on the above-mentioned inverter circuit with an LCR parallel structure as the load. Specifically, the PFM pulse frequency regulator issues the upper-bridge-arm drive pulse, dead-time pulse, and lower-bridge-arm drive pulse; when the upper-bridge-arm drive pulse experiences its falling edge, the dead-time pulse experiences its rising edge; when the dead-time pulse experiences its falling edge, the lower-bridge-arm drive pulse experiences its rising edge; when the lower-bridge-arm drive pulse experiences its falling edge, the dead-time pulse experiences its rising edge, and when the dead-time pulse experiences its falling edge, the upper-bridge-arm drive pulse experiences its rising edge, and so on.

[0036] When the inverter circuit with an LCR parallel structure provided in the present application is working, its circuit working principle is as follows:

[0037] In the inverter circuit with an LCR parallel structure as the load provided on the application date of the present application, the conduction and cutoff of the two switching tubes that make up the upper bridge arm of the inverter full bridge will be directly controlled by the actual upper-bridge-arm pulse: when the actual upper-bridge-arm pulse appears, the two switching tubes that make up the upper bridge arm of the inverter full bridge conduct, and vice versa; while the conduction and cutoff of the two switching tubes that make up the lower bridge arm of the inverter full bridge will be directly controlled by the actual lower-bridge-arm pulse: when the actual lower-bridge-arm pulse appears, the two switching tubes that make up the lower bridge arm of the inverter full bridge conduct, and vice versa; and in order to match the LCR parallel-type load, there is an overlap between the actual upper-bridge-arm pulse and the lower-bridge-arm drive pulse. During the overlapping time of the two, all the switching tubes in the inverter full bridge conduct.

[0038] Before the actual lower-bridge-arm pulse appears, only the switching tubes that make up the upper bridge arm in the inverter circuit conduct. At this time, the current at the output end of the inverter circuit remains at the positive maximum amplitude, and the voltage between the two output ends changes in a sine wave form;

[0039] When the actual lower-bridge-arm pulse experiences its rising edge, the commutation of the inverter loop starts, the upper and lower bridge arms start to switch, and the current at the two output ends of the inverter loop changes suddenly, rapidly decreasing from the previously maintained highest amplitude to zero, and further increasing in the reverse direction to the negative highest amplitude. During the process of the current at the two output ends of the inverter loop rapidly changing from the positive highest amplitude to the negative highest amplitude, due to the overlap between the actual lower-bridge-arm pulse and the actual upper-bridge-arm pulse, when the actual lower-bridge-arm pulse experiences its rising edge, the actual upper-bridge-arm pulse still exists. At this time, all the switching tubes in the inverter full bridge conduct, and the external constant current source is short-circuited, and the voltage between the two output ends of the inverter loop drops suddenly to 0; when the current at the two output ends of the inverter loop increases in the reverse direction to the negative highest amplitude, the commutation of the inverter loop is completed, and the inverter circuit at this time becomes the upper bridge arm cutoff and the lower bridge arm conducting.

[0040] During the process of the upper and lower arm switching of the inverter circuit, the voltages measured at the two input terminals of the inverter circuit will change synchronously with the current at its output terminal. For the voltage between the two input terminals of the inverter circuit, when experiencing the rising edge of the actual pulse of the lower arm, since the two input terminals of the inverter circuit are short-circuited, it will directly drop to 0. At the moment when the commutation of the inverter circuit is completed, because the switching tube that previously formed the upper arm has experienced the process of individual conduction - co - conduction with the switching tube that forms the lower arm - turn - off, the current flowing through it will experience the process of the positive maximum amplitude - positive decrease to 0 - negative increase - negative increase to the maximum amplitude. And because a diode is set for each switching tube in the inverter circuit, the current cannot flow reversely. Subject to the parallel - type load, at the moment when the commutation of the inverter circuit is completed, the potential relationship between its two input terminals will change, and there will be an instantaneous negative voltage in the direction completely opposite to the original voltage, and there will also be an instantaneous positive voltage between the two output terminals. The instantaneous positive voltage between the two output terminals is equal in magnitude and opposite in direction to the instantaneous negative voltage between the two input terminals. The instantaneous negative voltage that appears between the two input terminals of the inverter circuit will last for a period of time and gradually decrease to 0 as the lower arm conducts during this period; the instantaneous positive voltage that appears between the two output terminals of the inverter circuit will also gradually decrease to 0 during this period.

[0041] The above - mentioned situation will repeat during each process of the upper and lower arm exchanging conduction and the inverter circuit commuting. Therefore, it can be inferred that the moment when the rising edge of the actual pulse of the upper arm or the rising edge of the actual pulse of the lower arm is experienced in the inverter circuit is the instant when the inverter circuit starts to commute, and the moment when a negative voltage appears at the input terminal of the inverter circuit is the moment when the inverter circuit completes commutation. Between these two moments, the inverter circuit completes the upper and lower arm switching.

[0042] Generally, for an inverter circuit with an LCR parallel - resonance structure as the load, it is generally expected that the current in its inverter circuit always leads the voltage and is in a weakly capacitive state where the current phase and the voltage phase have little difference. Therefore, in the circuit provided in this application, on the premise of ensuring complete switching of the upper and lower arms, taking the negative voltage between the two input terminals as the regulation basis, detecting and calculating the existence duration of this negative voltage, changing the switching frequency of the upper and lower arms in the inverter circuit according to its duration, changing the alternating frequency of the alternating current output between the two output terminals of the inverter circuit, making it match the natural resonance frequency of the LCR parallel - resonance structure, gradually shortening the existence duration of the negative voltage between the two input terminals, gradually adjusting the real - time current and real - time voltage in the inverter circuit to be almost in step, providing an alternating current that matches the load and making the load almost reach its resonance state while ensuring the stable, safe, and smooth switching of the upper and lower arms in the inverter circuit, reducing the switching loss of the switching tubes in the inverter circuit, and maintaining the long - term stable operation of the circuit.

[0043] Therefore, in the technical solution provided by this application, the two detection ends of the high-voltage detector are connected to the two input ends of the inverter circuit. Once a negative voltage appears between the two input ends of the inverter circuit, it will be detected. The appearance of this negative voltage indicates that the commutation of the upper and lower bridge arms of the inverter circuit is completed. After the high-voltage detector detects the negative voltage and passes it through the opto-coupled negative voltage pulse generator, the negative voltage pulse generator will correspond to the negative voltage detected by the high-voltage detector. At the moment when the negative voltage is detected at the two input ends of the inverter circuit, it emits the rising edge of the negative voltage pulse, and at the moment when the negative voltage disappears at the two input ends of the inverter circuit, it emits the falling edge of the negative voltage pulse. The moments when the negative voltage appears and disappears, and its duration are recorded by the negative voltage pulse generator in the form of an output negative voltage pulse. The negative voltage pulse is sent into the negative pulse time calculator to calculate its existence duration, and the calculation result is subtracted from the externally given negative pulse time through the negative pulse time comparator, then the gap between the actual working state and the ideal working state of the current inverter circuit can be known. Sending this gap into the V / F voltage-frequency converter can provide a regulation basis for the PFM pulse frequency regulator.

[0044] Analysis shows that the PFM pulse frequency regulator emits a dead-time pulse. The moment of its rising edge indicates the start of the switching between the upper and lower bridge arms of the inverter circuit, and the switching process will last for a period of time until a negative voltage appears at the two input ends of the inverter circuit to complete the switching process. Therefore, in the technical solution provided by this application, the PFM pulse frequency regulator connects the dead-time pulse to the monostable flip-flop. At the same time, the output end of the negative voltage pulse generator is also connected to the monostable flip-flop. For the monostable flip-flop, its state starts to flip at the moment when it receives the rising edge of the dead-time pulse, and its state flips back to the original state again until it receives the rising edge of the negative voltage pulse emitted by the negative voltage pulse generator. The time length of the monostable flip-flop being triggered and flipped is the time length of the commutation of the upper and lower bridge arms in the entire inverter circuit. Connect the output of the monostable flip-flop to the first OR gate and the second OR gate. The actual pulse of the upper bridge arm output from the first OR gate is: the sum of the upper bridge arm drive pulse, the dead-time pulse, and the output pulse of the monostable flip-flop; and the actual pulse of the lower bridge arm output from the second OR gate is: the sum of the lower bridge arm drive pulse, the dead-time pulse, and the output pulse of the monostable flip-flop; there is a partial overlap period between the actual pulse of the upper bridge arm and the actual pulse of the lower bridge arm. During this overlap period, all the switching tubes of the upper and lower bridge arms are conducting.

[0045] To ensure that the inverter circuit always maintains a weakly capacitive state, an emergency stop circuit is additionally provided in the technical solution provided by this application. The voltage sensor is used to detect the voltage between the two output terminals of the inverter circuit. Once the current lags behind the voltage at the output terminal of the inverter circuit, the synchronization pulse generator immediately sends out a synchronization pulse. This synchronization pulse is connected to the PFM pulse frequency regulator, and the PFM pulse frequency regulator forcibly adjusts the output frequencies of the upper bridge arm drive pulse, dead time pulse, and lower bridge arm drive pulse, controlling the inverter circuit to return to the state where the real-time current leads the real-time voltage, ensuring that the inverter circuit always operates in a capacitive state.

[0046] The advantages of the present invention are as follows: The inverter circuit with an LCR parallel structure as the load provided by this application cleverly utilizes the characteristic parameters in the circuit after the upper and lower bridge arms of the inverter circuit are switched, and adjusts the operating frequency of the inverter circuit based on these parameters as the frequency adjustment basis. It not only fully considers the actual on and off times of each switching tube in the inverter circuit, reserves reaction time for each switching tube, but also effectively utilizes the resonance characteristics of the LCR parallel load to ensure the effective operation of the circuit. When applied in practice, good usage effects have been achieved. Brief Description of the Drawings

[0047] Figure 1 It is the circuit schematic diagram when the power supply including an inverter in the prior art is connected to an LCR parallel load.

[0048] Figure 2 It is the circuit schematic diagram when the LCR parallel resonance structure load composed of an external constant current source ADC, external constant current inductor L1, external load capacitor C1, load inductor L2, and load resistor R1 in the inverter circuit with an LCR parallel structure as the load provided in the specific embodiment is connected.

[0049] Figure 3 It is a schematic diagram of the fluctuation relationship between the upper bridge arm drive pulse PA, dead time pulse PD, lower bridge arm drive pulse PB, upper bridge arm actual pulse Pa, lower bridge arm actual pulse Pb, PH output at the output terminal of the monostable flip-flop, real-time voltage Uab, and real-time current Iab at the output terminal of the inverter circuit when the inverter circuit with an LCR parallel structure as the load provided in the specific embodiment is initially adjusted.

[0050] Figure 4 It is a schematic diagram of the fluctuation relationship between the upper bridge arm actual pulse Pa, lower bridge arm actual pulse Pb, real-time voltage Uab, real-time current Iab at the output terminal of the inverter circuit, real-time voltage Uca and real-time current Ica of one of the switching tubes in the inverter circuit, and real-time voltage Ucd at the two output terminals of the inverter circuit when the inverter circuit with an LCR parallel structure as the load provided in the specific embodiment is initially adjusted.

[0051] Figure 5 It is a schematic diagram of the fluctuation relationship among the real-time voltage Uab and real-time current Iab at the output end of the inverter loop, the real-time current Iab at the output end of the inverter loop and the real-time voltage Ucd between the two input ends, the negative voltage pulse PN output at the output end of the negative voltage pulse generator, the positive zero-crossing pulse Za of the voltage of the real-time voltage Uab between the two output ends of the inverter loop, and the negative zero-crossing pulse Zb of the real-time voltage Uab between the two output ends of the inverter loop when the inverter circuit with the LCR parallel structure as the load provided in the specific implementation manner is initially adjusted.

[0052] Figure 6 It is the negative voltage pulse PN output at the output end of the negative voltage pulse generator, the positive zero-crossing pulse Za of the voltage of the real-time voltage Uab between the two output ends of the inverter loop, the negative zero-crossing pulse Zb of the real-time voltage Uab between the two output ends of the inverter loop, the integral voltage U obtained by performing time integration on the negative voltage pulse PN in the negative voltage pulse generator, when the inverter circuit with the LCR parallel structure as the load provided in the specific implementation manner is initially adjusted. N and the peak voltage U obtained after peak holding of the integral voltage U N in the negative voltage pulse generator, max as well as the schematic diagram of the fluctuation relationship between the output regulation frequency f output at the output end of the V / F voltage-frequency converter.

[0053] Figure 7 It is a schematic diagram of the fluctuation relationship among the upper-bridge-arm drive pulse PA, dead-time pulse PD, lower-bridge-arm drive pulse PB, upper-bridge-arm actual pulse Pa, lower-bridge-arm actual pulse Pb, PH output at the output end of the monostable flip-flop, the real-time voltage Uab and real-time current Iab at the output end of the inverter loop in the circuit when the inverter circuit with the LCR parallel structure as the load provided in the specific implementation manner is adjusted.

[0054] Figure 8 It is a schematic diagram of the fluctuation relationship among the real-time voltage Uab and real-time current Iab at the output end of the inverter loop in the circuit, the real-time current Iab at the output end of the inverter loop and the real-time voltage Ucd between the two input ends, the negative voltage pulse PN output at the output end of the negative voltage pulse generator, the positive zero-crossing pulse Za of the voltage of the real-time voltage Uab between the two output ends of the inverter loop, and the negative zero-crossing pulse Zb of the real-time voltage Uab between the two output ends of the inverter loop when the inverter circuit with the LCR parallel structure as the load provided in the specific implementation manner is adjusted.

[0055] Figure 9After the inverter circuit with an LCR parallel structure as the load provided in the specific implementation manner is adjusted, the negative voltage pulse PN output at the output end of the negative voltage pulse generator in the circuit, the positive zero-crossing pulse Za of the voltage of the real-time voltage Uab between the two output ends of the inverter loop, the negative zero-crossing pulse Zb of the voltage of the real-time voltage Uab between the two output ends of the inverter loop, and the integral voltage U obtained by performing time integration on the negative voltage pulse PN in the negative voltage pulse generator N in the negative voltage pulse generator for the integral voltage U N after peak holding to obtain the peak voltage U max and the schematic diagram of the fluctuation relationship between the output regulation frequency f output at the output end of the V / F voltage-frequency converter. Specific implementation manner

[0056] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0057] To achieve the above objective, the technical solution of the present invention is as follows:

[0058] Please refer to Figure 2-9 .

[0059] An inverter circuit with an LCR parallel structure as the load, the circuit includes:

[0060] An inverter full bridge composed of paired switching tubes (TA / TB / TC / TD) for converting the input direct current into an alternating current inverter loop;

[0061] A negative voltage detection circuit for detecting the occurrence duration of the commutation negative voltage in the inverter loop;

[0062] And a frequency adjustment circuit for correspondingly adjusting the on-off frequency of the switching tubes in the inverter loop according to the occurrence duration of the commutation negative voltage detected by the negative voltage detection circuit;

[0063] The detection end of the negative voltage detection circuit is connected to the inverter loop, the output end of the negative voltage detection circuit is connected to the frequency adjustment circuit, and the output end of the frequency adjustment circuit outputs drive pulses to respectively control the conduction conditions of different switching tubes in the inverter loop.

[0064] Further, the negative voltage detection circuit includes:

[0065] A high-voltage detector having two detection ends for detecting the real-time voltage Ucd between its two detection ends;

[0066] And a negative voltage pulse generator corresponding to the high-voltage detector setting, which outputs a pulse with a corresponding width at the moment when the voltage appears and disappears when the high-voltage detector detects a voltage.

[0067] One detection terminal of the high-voltage detector is connected to one input terminal c of the full-bridge inverter in the inverter circuit, and the other input terminal of the high-voltage detector is connected to the other input terminal d of the full-bridge inverter in the inverter circuit; the output terminal of the high-voltage detector is connected to the negative voltage pulse generator, and the output terminal of the negative voltage pulse generator outputs a negative pressure pulse PN.

[0068] Furthermore, the frequency adjustment circuit includes:

[0069] A negative pulse time calculator for calculating the duration of the input pulse and outputting a voltage corresponding to the duration.

[0070] And a negative pulse time comparator corresponding to the negative pulse time calculator setting, which is used to perform a comparison operation between the actual output of the negative pulse time calculator and the externally given negative pulse time.

[0071] The input terminal of the negative pulse time calculator is connected to the negative pulse generator, the output terminal of the negative pulse time calculator is connected to one input terminal of the negative pulse time comparator, and the externally given negative pulse time is connected to the other input terminal of the negative pulse comparator. The essence of the negative pulse time calculator is a combination of a time integrator and a peak holder. After the negative pressure pulse PN output by the negative voltage pulse generator is connected to the negative pulse time calculator, the negative pulse time calculator first performs time integration on the negative pressure pulse PN to obtain an integrated voltage U N , and then further makes a peak hold on the integrated voltage U N to obtain a peak voltage U max , and this peak voltage U max is connected to the negative pulse comparator.

[0072] Furthermore, the frequency adjustment circuit also includes:

[0073] A V / F voltage-frequency converter for converting the input voltage into a frequency with a corresponding magnitude.

[0074] And a PFM pulse frequency regulator for outputting the upper-bridge arm drive pulse PA, the dead-time pulse PD, and the lower-bridge arm drive pulse PB to control the on-off conditions of different arms of the full-bridge inverter in the inverter circuit.

[0075] The input terminal of the V / F voltage-frequency converter is connected to the output terminal of the negative pulse comparator, the output terminal of the V / F voltage-frequency converter outputs an adjusted frequency f, and this adjusted frequency f is connected to the PFM pulse frequency regulator.

[0076] Further, the frequency adjustment circuit further includes a first OR gate G1 and a second OR gate G2. The input terminal of the first OR gate G1 is connected to the upper bridge arm drive pulse PA and the dead zone pulse PD output by the PFM pulse frequency regulator. The input terminal of the second OR gate G2 is input with the lower bridge arm drive pulse PB and the dead zone pulse PD output by the PFM pulse frequency regulator. The output terminal of the first OR gate G1 outputs the upper bridge arm actual pulse Pa, which is used to actually control the conduction or cutoff of the upper bridge arm of the full-bridge inverter in the inverter circuit. The output terminal of the second OR gate G2 outputs the lower bridge arm actual pulse Pb, which is used to actually control the conduction or cutoff of the lower bridge arm of the full-bridge inverter in the inverter circuit.

[0077] Further, the frequency adjustment circuit further includes a monostable flip-flop. One input terminal CLR1 of the monostable flip-flop is connected to the output terminal of the negative voltage pulse generator. The dead zone pulse PD output at the output terminal of the PFM pulse frequency regulator is connected to the trigger flip-flop terminal CP of the monostable flip-flop. The output terminal of the monostable flip-flop outputs PH, and the PH is respectively connected to the first OR gate and the second OR gate.

[0078] Further, the circuit further includes an emergency stop circuit; the emergency stop circuit includes:

[0079] A voltage sensor for detecting the real-time voltage Uab between the two output terminals a-b of the inverter circuit;

[0080] A voltage zero-crossing comparator for detecting the zero-crossing moment point of the real-time voltage Uab between the two output terminals of the inverter circuit;

[0081] A zero-crossing pulse generator for outputting a positive zero-crossing pulse Za corresponding to the positive voltage zero-crossing moment point of the real-time voltage Uab between the two output terminals of the inverter circuit and outputting a negative zero-crossing pulse Zb corresponding to the negative voltage zero-crossing moment point of the real-time voltage Uab between the two output terminals of the inverter circuit according to the detection result of the voltage zero-crossing comparator;

[0082] A current lagging voltage cut-off device for detecting the phase relationship between the real-time voltage and the real-time current in the inverter circuit and outputting a cut-off pulse once it detects that there is real-time current lagging behind the real-time voltage in the inverter circuit;

[0083] And, corresponding to the current lagging voltage cut-off device, a synchronization pulse generator that once the current lagging voltage cut-off device outputs a cut-off pulse, correspondingly issues a synchronization pulse PT to further control the inverter circuit to return to the state where the real-time current leads the real-time voltage;

[0084] The detection end of the voltage sensor is connected to the two output ends of the inverter circuit, and the output end of the voltage sensor is connected to the zero-crossing voltage comparator; the output end of the zero-crossing voltage comparator is connected to the zero-crossing pulse generator, the output end of the zero-crossing pulse generator is connected to the current lag voltage cut-off device, the output end of the current lag voltage cut-off device is connected to the synchronization pulse generator, and the output end of the synchronization pulse generator is connected to the PFM pulse frequency regulator; the output end of the synchronization pulse generator is also connected to another input end of the monostable flip-flop.

[0085] Further, the current lag voltage cut-off device includes a first AND gate G3, a second AND gate G4, and a third OR gate G5; one input end of the first AND gate G3 is connected to the positive zero-crossing pulse Za; its other input end is connected to the upper bridge arm drive pulse PA, and its output end is connected to one input end of the third OR gate G5; one input end of the second AND gate G4 is connected to the negative zero-crossing pulse Zb, its other input end is connected to the lower bridge arm drive pulse PB, and its output end is connected to the other input end of the third OR gate G5; the output end of the third OR gate G5 is connected to the synchronization pulse generator.

[0086] The present application also provides a working method for an inverter circuit with an LCR parallel structure as the load. This method is based on the above-mentioned inverter circuit with an LCR parallel structure as the load. Specifically, the PFM pulse frequency regulator issues the upper bridge arm drive pulse PA, the dead-time pulse PD, and the lower bridge arm drive pulse PB; when the upper bridge arm drive pulse PA experiences its falling edge, the dead-time pulse PD experiences its rising edge; when the dead-time pulse PD experiences its falling edge, the lower bridge arm drive pulse PB experiences its rising edge; when the lower bridge arm drive pulse PB experiences its falling edge, the dead-time pulse PD experiences its rising edge, and when the dead-time pulse PD experiences its falling edge, the upper bridge arm drive pulse PA experiences its rising edge, and so on.

[0087] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An inverter circuit with an LCR parallel structure as the load, the circuit comprising: An inverter full bridge composed of paired switching tubes, for converting the input direct current into an alternating current inverter loop; Characterized in that The circuit further comprises a negative voltage detection circuit for detecting the occurrence duration of the commutation negative voltage in the inverter loop; And a frequency adjustment circuit for correspondingly adjusting the on-off frequency of the switching tubes in the inverter loop according to the occurrence duration of the commutation negative voltage detected by the negative voltage detection circuit; The detection end of the negative voltage detection circuit is connected to the inverter loop, the output end of the negative voltage detection circuit is connected to the frequency adjustment circuit, and the output end of the frequency adjustment circuit outputs drive pulses to respectively control the conduction conditions of different switching tubes in the inverter loop; The negative voltage detection circuit comprises: A high-voltage detector having two detection ends for detecting the real-time voltage between its two detection ends; And a negative voltage pulse generator correspondingly arranged for the high-voltage detector, for outputting pulses with corresponding widths at the moments when the voltage appears and disappears when the high-voltage detector detects the voltage; one detection end of the high-voltage detector is connected to one input end of the inverter full bridge in the inverter loop, and the other input end of the high-voltage detector is connected to the other input end of the inverter full bridge in the inverter loop; the output end of the high-voltage detector is connected to the negative voltage pulse generator.

2. The inverter circuit with an LCR parallel structure as the load according to claim 1, Characterized in that The frequency adjustment circuit includes: A negative pulse time calculator for calculating the duration of the input pulse and outputting the duration as a voltage of corresponding magnitude; And a negative pulse time comparator correspondingly arranged for the negative pulse time calculator, for making a comparison operation between the actual output of the negative pulse time calculator and the externally given negative pulse time; The input end of the negative pulse time calculator is connected to the negative pulse generator, the output end of the negative pulse time calculator is connected to one input end of the negative pulse time comparator, and the externally given negative pulse time is connected to the other input end of the negative pulse time comparator.

3. The inverter circuit with an LCR parallel structure as the load according to claim 2, Characterized in that The frequency adjustment circuit further includes: A V / F voltage-frequency converter for converting the input voltage into a frequency of corresponding magnitude; And a PFM pulse frequency regulator for outputting upper bridge arm drive pulses, dead zone pulses and lower bridge arm drive pulses to control the on-off conditions of different bridge arms of the inverter full bridge in the inverter loop; The input end of the V / F voltage-frequency converter is connected to the output end of the negative pulse time comparator, and the output end of the V / F voltage-frequency converter is connected to the PFM pulse frequency regulator.

4. The inverter circuit with an LCR parallel structure as the load according to claim 3, Characterized in that The frequency regulation circuit further includes a first OR gate and a second OR gate. The input end of the first OR gate is connected to the upper-bridge-arm drive pulse and the dead-time pulse output by the PFM pulse frequency regulator. The input end of the second OR gate inputs the lower-bridge-arm drive pulse and the dead-time pulse output by the PFM pulse frequency regulator. The output end of the first OR gate outputs the actual upper-bridge-arm pulse, which is used to actually control the conduction or cut-off of the upper bridge arm of the full-bridge inverter in the inverter circuit. The output end of the second OR gate outputs the actual lower-bridge-arm pulse, which is used to actually control the conduction or cut-off of the lower bridge arm of the full-bridge inverter in the inverter circuit.

5. The inverter circuit with an LCR parallel structure as the load according to claim 4, characterized in that, the frequency regulation circuit further includes a monostable flip-flop. One input end of the monostable flip-flop is connected to the output end of the negative voltage pulse generator. The dead-time pulse output at the output end of the PFM pulse frequency regulator is connected to the trigger flip end of the monostable flip-flop. The output end of the monostable flip-flop is respectively connected to the first OR gate and the second OR gate.

6. The inverter circuit with an LCR parallel structure as the load according to claim 5, characterized in that, the circuit further includes an emergency stop circuit; the emergency stop circuit includes: a voltage sensor for detecting the real-time voltage between the two output ends of the inverter circuit; a voltage zero-crossing comparator for detecting the zero-crossing moment point of the real-time voltage between the two output ends of the inverter circuit; a zero-crossing pulse generator for outputting a positive zero-crossing pulse corresponding to the positive voltage zero-crossing moment point of the real-time voltage between the two output ends of the inverter circuit and outputting a negative zero-crossing pulse corresponding to the negative voltage zero-crossing moment point of the real-time voltage between the two output ends of the inverter circuit according to the detection result of the voltage zero-crossing comparator; a current-lagging-voltage cut-off device for detecting the phase relationship between the real-time voltage and the real-time current in the inverter circuit and outputting a cut-off pulse once it detects that there is real-time current lagging behind the real-time voltage in the inverter circuit; and a synchronization pulse generator arranged corresponding to the current-lagging-voltage cut-off device, which emits a synchronization pulse once the current-lagging-voltage cut-off device outputs a cut-off pulse, and further controls the inverter circuit to return to the state where the real-time current leads the real-time voltage; the detection end of the voltage sensor is connected to the two output ends of the inverter circuit, and the output end of the voltage sensor is connected to the voltage zero-crossing comparator; the output end of the voltage zero-crossing comparator is connected to the zero-crossing pulse generator, the output end of the zero-crossing pulse generator is connected to the current-lagging-voltage cut-off device, the output end of the current-lagging-voltage cut-off device is connected to the synchronization pulse generator, and the output end of the synchronization pulse generator is connected to the PFM pulse frequency regulator; the output end of the synchronization pulse generator is also connected to the other input end of the monostable flip-flop.

7. The inverter circuit with an LCR parallel structure as the load according to claim 6, characterized in that, The current lag voltage cut-off device includes a first AND gate, a second AND gate, and a third OR gate; one input terminal of the first AND gate is connected to a positive zero-crossing pulse; the other input terminal thereof is connected to an upper-bridge-arm driving pulse, and its output terminal is connected to one input terminal of the third OR gate; one input terminal of the second AND gate is connected to a negative zero-crossing pulse, the other input terminal thereof is connected to a lower-bridge-arm driving pulse, and its output terminal is connected to the other input terminal of the third OR gate; the output terminal of the third OR gate is connected to the synchronization pulse generator.

8. A working method of an inverter circuit with an LCR parallel structure as a load, the method being based on the inverter circuit with an LCR parallel structure as a load according to any one of claims 3-7, characterized in that the method is as follows: the PFM pulse frequency regulator issues an upper-bridge-arm driving pulse, a dead-time pulse, and a lower-bridge-arm driving pulse; when the upper-bridge-arm driving pulse experiences its falling edge, the dead-time pulse experiences its rising edge; when the dead-time pulse experiences its falling edge, the lower-bridge-arm driving pulse experiences its rising edge; when the lower-bridge-arm driving pulse experiences its falling edge, the dead-time pulse experiences its rising edge, and when the dead-time pulse experiences its falling edge, the upper-bridge-arm driving pulse experiences its rising edge, and so on.

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