An inverter circuit with an LCR series resonance structure as the load and its working method

Abstract

The present invention discloses an inverter circuit with an LCR series resonance structure as the load. The circuit includes an inverter loop for converting direct current into alternating current with a certain alternating frequency; the circuit further includes a pulse frequency adjustment drive loop for outputting upper bridge arm drive pulses, dead zone pulses, and lower bridge arm drive pulses; and, a phase difference detection loop for comparing the phase difference between the voltage leading the current in the inverter loop and outputting the magnitude of the phase difference. Compared with the prior art, in the present invention, the inverter circuit is provided with a phase difference detection loop, so that the inverter loop is adapted to the LCR series resonance structure as the load. While reserving the dead zone time for each switching tube, the whole circuit is kept working in a weakly inductive and near-resonant working state. On the one hand, it makes the load work efficiently, and on the other hand, it also makes the switching process of the upper and lower bridge arms of the inverter loop smoother, ensuring that each switching tube in the inverter loop approximately works in the soft switching state.

Description

Technical Field

[0001] The present invention belongs to the technical field of electromagnetic induction, and particularly relates to an inverter control circuit. Background Art

[0002] As an important part of a power supply, an inverter circuit is generally used to convert direct current into alternating current. When a power supply containing an inverter circuit is applied in the technical field of electromagnetic induction and is connected to a load formed by series resonance of LCR, the operating conditions of the inverter circuit and the load will be closely connected and affect each other.

[0003] As Figure 1 Shown is a circuit schematic diagram of a power supply containing an inverter circuit connected to an LCR series load in the prior art. In this circuit, an inverter full bridge is constructed by four switching tubes (TA / TB / TC / TD). After the direct current VDC passes through the filter capacitor C1, it enters the inverter full bridge. After the four switching tubes (TA / TB / TC / TD) in the full bridge, it becomes an alternating current with a certain alternating frequency. This alternating current passes through the DC blocking capacitor C2 and the matching transformer R1, and then outputs to an LCR series resonance structure composed of a load capacitor C3, a load inductor L1, and a load resistor R1.

[0004] The above-described circuit is a typical circuit when a power supply containing an inverter circuit is applied to a load that is an LCR series resonance structure. Generally speaking, considering that the switching tubes in actual applications are not ideal devices, the switching process between the upper and lower bridge arms cannot be completed instantaneously and requires a certain amount of time. Therefore, when applied to a specific scenario with an LCR series resonance structure as the load, the drive controller often outputs a dead zone pulse between the two output pulses. During the action of this dead zone pulse, neither the upper nor the lower bridge arm in the inverter circuit conducts. The dead zone pulse will leave a reaction time for each switching tube in the inverter circuit to prevent the upper and lower bridge arms from overlapping due to insufficient reaction time, the upper and lower bridge arms from conducting simultaneously at a certain moment, and the inverter circuit from short-circuiting.

[0005] When the load of a power supply containing an inverter circuit is an LCR series resonance structure, analyzing its circuit characteristics shows that the LCR series resonance structure has its inherent resonance frequency, which is jointly determined by the values of the inductance L, the capacitance C, and the resistance R; and the switching conduction frequency between the upper and lower bridge arms in the inverter circuit will directly determine the output frequency of the power supply. When the output frequency of the power supply approaches the inherent frequency of the LCR series resonance structure, the LCR series resonance structure reaches its resonance state. At this time, the voltage and current in the LCR series resonance structure are in phase, and the load will obtain excellent operating effects at this time.

[0006] Therefore, it can be inferred that when considering the reaction time of the switching tube and applying the inverter circuit to a power supply with an LCR series resonance structure as the load, how to adjust its circuit structure and how to change its drive control method to output alternating current with an expected alternating frequency, drive the load to work efficiently, and ensure smooth switching between the upper and lower bridge arms in the circuit and safe on-off of each switching tube in the circuit are technical problems that those skilled in the art urgently need to solve. Summary of the Invention

[0007] To solve the above problems, the purpose of the present invention is to provide an inverter circuit. This inverter circuit determines the working condition of the inverter loop by detecting the phase difference between the voltage and current in the circuit. On the premise of considering the dead time of the switching device in the inverter loop, it continuously adjusts the switching frequency of the upper and lower bridge arms of the inverter circuit, and while ensuring smooth switching between the upper and lower bridge arms of the inverter circuit, it outputs alternating current adapted to the LCR series resonance structure load.

[0008] To achieve the above purpose, the technical solution of the present invention is as follows:

[0009] An inverter circuit with an LCR series resonance structure as the load, the circuit includes an inverter loop for converting direct current into alternating current and outputting it to the load of the LCR series resonance structure;

[0010] The circuit also includes a pulse frequency adjustment drive loop for outputting upper bridge arm drive pulses, dead time pulses, and lower bridge arm drive pulses;

[0011] And a phase difference detection loop for comparing the phase difference between the voltage leading the current in the inverter loop and outputting the magnitude of this phase difference;

[0012] The detection end of the phase difference detection loop is connected to the inverter loop, the output end of the phase difference detection loop is connected to the pulse frequency adjustment drive loop, the upper bridge arm drive pulse and the lower bridge arm drive pulse output by the output end of the pulse frequency adjustment drive loop are connected to the inverter loop, and the dead time pulse it outputs is connected to the phase difference detection loop.

[0013] Further, the pulse frequency adjustment drive loop includes: a PFM pulse frequency regulator for respectively generating upper bridge arm control pulses, dead time pulses, and lower bridge arm control pulses.

[0014] Further, the phase difference detection loop includes:

[0015] A current sensor for detecting the magnitude of the real-time current output by the inverter loop;

[0016] A current zero-crossing comparator for detecting the zero-crossing point of the real-time current;

[0017] A current zero-crossing pulse generator for generating zero-crossing pulses corresponding to the positive current zero-crossing and the negative current zero-crossing respectively;

[0018] The detection end of the current sensor interacts with the inverter circuit. The output end of the current sensor is connected to the current zero-crossing comparator, and the output end of the current zero-crossing comparator is connected to the current zero-crossing pulse generator. The output end of the current zero-crossing pulse generator outputs a positive current zero-crossing pulse and a negative current zero-crossing pulse respectively.

[0019] Furthermore, the phase difference detection circuit further includes a monostable flip-flop. The positive current zero-crossing pulse and the negative current zero-crossing pulse output by the current zero-crossing pulse generator are respectively connected to the monostable flip-flop, and the dead-time pulse output by the PFM pulse frequency regulator is connected to the trigger inversion end of the monostable flip-flop.

[0020] Furthermore, an advance time detector for calculating the magnitude of the phase difference between the real-time voltage and the real-time current and outputting the magnitude of the phase difference in the form of the voltage magnitude;

[0021] And an advance time comparator for comparing the output result of the advance time detector with an externally given advance time value;

[0022] The input end of the advance time detector is connected to the output of the monostable flip-flop, the output end of the advance time detector is connected to the advance time comparator, and the advance time comparator is also connected to an externally given advance time value.

[0023] Furthermore, the phase difference detection circuit further includes a V / F voltage-frequency converter. The input end of the V / F voltage-frequency converter is connected to the output of the advance time comparator, and the output end of the V / F voltage-frequency converter is connected to the PFM pulse frequency regulator.

[0024] Furthermore, the circuit further includes an emergency stop circuit; the emergency stop circuit includes:

[0025] A voltage-lagging current cut-off device for monitoring the real-time current and the real-time voltage at the inverter circuit and being triggered once it is detected that there is real-time voltage lagging behind the real-time current in the inverter circuit;

[0026] And a synchronization pulse generator for responding to the voltage-lagging current cut-off device, sending out a synchronization pulse once the voltage-lagging current cut-off device is triggered, and then forcing the inverter circuit to return to the state where the real-time voltage leads the real-time current;

[0027] The input end of the voltage-lagging current cut-off device is respectively connected to the PFM pulse frequency regulator and the current zero-crossing pulse generator; the output end of the voltage-lagging current cut-off device is connected to the synchronization pulse generator, and the output end of the synchronization pulse generator is connected to the PFM pulse frequency regulator.

[0028] Furthermore, the zero-point pulse generator includes a first AND gate, a second AND gate and a first OR gate. The input end of the first AND gate is respectively connected to the upper bridge arm drive pulse output by the PFM pulse frequency regulator and the current positive zero-crossing pulse output by the current zero-point pulse generator, and the output end of the first AND gate is connected to one of the input ends of the first OR gate; the input end of the second AND gate is respectively connected to the lower bridge arm drive pulse output by the PFM pulse frequency regulator and the current negative zero-crossing pulse output by the current zero-point pulse generator, and the output end of the second AND gate is connected to the other input end of the first OR gate.

[0029] Furthermore, the present application also discloses a working method of an inverter circuit with an LCR series resonant structure as a load. The working method is based on the above-mentioned inverter circuit with an LCR series resonant structure as a load. Specifically, after the PFM pulse frequency regulator outputs an upper bridge arm drive pulse, a dead zone pulse is emitted while the upper bridge arm drive pulse undergoes a falling edge, and while the dead zone pulse undergoes a falling edge, the PFM pulse frequency regulator emits a lower bridge arm drive pulse, and while the lower bridge arm drive pulse undergoes a falling edge, the PFM pulse frequency regulator emits an upper bridge arm drive pulse again, and this is repeated.

[0030] The inverter circuit provided by the present application with an LCR series resonant structure as a load, when working, first uses a current sensor to obtain the real-time current situation at the output end of the inverter circuit, and sends the real-time current to the current zero-crossing comparator, which performs zero-crossing comparison on it to detect the zero-crossing point of the real-time current, and further uses a current zero-crossing pulse generator to generate a zero-crossing pulse according to the zero-crossing point of the real-time current, and outputs it in the form of a positive current zero-crossing pulse and a negative current zero-crossing pulse according to the specific current change trend. At this point, the output of the current zero-crossing pulse generator will characterize the phase situation of the real-time current in the inverter circuit.

[0031] In the inverter circuit with the LCR series resonant structure as the load provided in the present application, a PFM pulse frequency regulator is provided, and the upper bridge arm drive pulse output by the PFM pulse frequency regulator will directly drive the switch tube constituting the upper bridge arm to be turned on or off; the dead zone pulse output by the PFM pulse frequency regulator is sandwiched between the upper bridge arm drive pulse and the lower bridge arm drive pulse, and is used to give the switch tube reaction time to avoid the upper and lower bridge arms being turned on at the same time, resulting in direct penetration of the circuit; and the lower bridge arm drive pulse output by the PFM pulse frequency regulator will directly drive the switch tube constituting the lower bridge arm to be turned on or off; therefore, it can be inferred that the rising edge and the falling edge of the upper bridge arm drive pulse directly represent the moment when the voltage in the inverter circuit begins to change suddenly, and the same is true for the rising edge and the falling edge of the lower bridge arm drive pulse. At this point, the output of the PFM pulse frequency regulator will directly represent the phase situation of the real-time voltage in the inverter circuit.

[0032] Therefore, on the premise that the current zero-crossing pulse generator connects its output positive current zero-crossing pulse and negative current zero-crossing pulse to the monostable flip-flop, the PFM pulse frequency regulator then inputs its output dead-time pulse to the trigger inversion terminal of the monostable flip-flop. When the rising edge of the dead-time pulse output by the PFM pulse frequency regulator occurs, the monostable flip-flop will start to flip from the current stable state / temporary stable state, and invert into a temporary stable state / stable state. After flipping, it will maintain its flipped state until the current zero-crossing pulse generator inputs a positive current zero-crossing pulse or a negative current zero-crossing pulse to the monostable flip-flop. When the monostable flip-flop receives a positive current zero-crossing pulse or a negative current zero-crossing pulse, its state will flip again and return to the initial stable state / temporary stable state. Thus, the monostable flip-flop will output square waves one by one under the combined action of the current zero-crossing pulse generator and the PFM pulse frequency regulator, and the width of each square wave will directly represent the phase difference between the real-time current and the real-time voltage in the inverter circuit.

[0033] Furthermore, the output terminal of the monostable flip-flop is connected to the lead time detector. The essence of the lead time detector is a combination of a time integration circuit and a peak hold circuit. When the monostable flip-flop is triggered to flip and output a square wave, the lead time detector will start to integrate time from the rising edge of the square wave and obtain the integration peak at the falling edge of the square wave. This peak is transmitted to the peak hold circuit, and the peak hold circuit holds the peak and outputs it in the form of a voltage of corresponding magnitude. Therefore, it can be inferred that the output of the lead time detector is a voltage signal, and the magnitude of the voltage in this voltage signal directly represents the magnitude of the phase difference between the real-time current and the real-time voltage in the inverter circuit.

[0034] The output of the lead time detector is sent to the lead time comparator. At this time, the externally given lead time value input to the lead time comparator together is the ideal regulation value input by the operator according to the real-time working condition of the load. The lead time comparator compares the two, and then the gap between the current real-time working condition and the ideal working condition of the inverter circuit can be obtained. Therefore, by inputting the comparison result of the lead time comparator into the V / F voltage-frequency converter and further sending it to the PFM pulse frequency regulator, a regulation basis can be provided for the PFM pulse frequency regulator. The PFM pulse frequency regulator can adjust the switching frequency of the upper and lower bridge arms correspondingly according to the gap between the current real-time working condition and the ideal working condition of the inverter circuit, and change the alternating frequency of the alternating current output by the inverter circuit.

[0035] Repeating the above working process, the inverter circuit provided by this application will, within several cycles of starting to work, adjust the switching frequency of the upper and lower bridge arms in the inverter loop according to the phase difference between the real-time voltage and real-time current in the current inverter loop, so that the alternating frequency of the alternating current output by the inverter loop gradually approaches the natural frequency of the LCR series resonant load and finally stabilizes at the optimal switching frequency.

[0036] Therefore, it can be said that the LCR series resonant structure provided in this application for the inverter circuit of the load not only has a simple structure and is easy to implement, but also, on the premise of ensuring that the voltage in the inverter loop leads the current and leaving a reaction time for the conduction or cut-off of the switching tubes, minimizes the phase difference between the real-time current and real-time voltage in the inverter loop. While making the LCR series resonant load gradually approach its resonant state, it also enables the smooth switching of the upper and lower bridge arms in the inverter loop, and each switching tube is as close as possible to the soft-switching state, reducing the switching loss of each switching tube. When applied to a specific power supply with an LCR series resonant structure as the load, good electrical effects can be achieved. Description of the Drawings

[0037] Figure 1 is a schematic connection diagram of a power supply including an inverter circuit provided by the prior art and an LCR series load. Among them, VDC is a DC power supply; C1 is a filter capacitor, TA / TB / TC / TD are respectively four IGBT tubes constituting the inverter full bridge, C2 is a DC-blocking capacitor, T1 is a matching transformer, C3 is a load capacitor, L1 is a load inductor, and R1 is a load resistor.

[0038] Figure 2 is a circuit schematic diagram of an inverter circuit with an LCR series resonant structure as the load provided in the specific implementation manner.

[0039] Figure 3 is a schematic diagram of the fluctuation relationship between the control pulse PA of the upper bridge arm, the dead-time pulse PD, the control pulse PB of the lower bridge arm, the real-time voltage Uab in the inverter loop, the real-time current Iab, the real-time voltage Uca, and the real-time current Ica when the inverter circuit with an LCR series resonant structure as the load provided in the specific implementation manner is initially adjusted.

[0040] Figure 4 is a schematic diagram of the fluctuation relationship between the real-time voltage Uab and the real-time current Iab in the inverter loop, and the positive current zero-crossing pulse Za and the negative current zero-crossing pulse Zb output by the current zero-point pulse generator when the inverter circuit with an LCR series resonant structure as the load provided in the specific implementation manner is initially adjusted.

[0041] Figure 5It is a schematic diagram of the fluctuation relationship among the dead-time pulse PD, the positive current zero-crossing pulse Za, the negative current zero-crossing pulse Zb, the phase difference ΦUI between the real-time voltage Uab and the real-time current Iab, and the phase-difference integrated voltage UUI during the initial adjustment of the inverter circuit with an LCR series resonance structure as the load provided in the specific implementation manner.

[0042] Figure 6 It is a schematic diagram of the fluctuation relationship among the phase difference ΦUI between the real-time voltage Uab and the real-time current Iab, the peak voltage Umax, and the frequency f output at the V / F voltage-frequency converter during the initial adjustment of the inverter circuit with an LCR series resonance structure as the load provided in the specific implementation manner.

[0043] Figure 7 It is a schematic diagram of the fluctuation relationship among the upper-bridge-arm control pulse PA, the dead-time pulse PD, the lower-bridge-arm control pulse PB, the real-time voltage Uab, the real-time current Iab, the real-time voltage Uca, and the real-time current Ica in the inverter loop after the adjustment of the inverter circuit with an LCR series resonance structure as the load provided in the specific implementation manner.

[0044] Figure 8 It is a schematic diagram of the fluctuation relationship among the real-time voltage Uab, the real-time current Iab, the dead-time pulse PD, the positive current zero-crossing pulse Za output by the current zero-point pulse generator, the negative current zero-crossing pulse Zb, the phase difference ΦUI between the real-time voltage Uab and the real-time current Iab, and the phase-difference integrated voltage UUI in the inverter loop after the adjustment of the inverter circuit with an LCR series resonance structure as the load provided in the specific implementation manner.

[0045] Figure 9 It is a schematic diagram of the fluctuation relationship among the phase difference ΦUI between the real-time voltage Uab and the real-time current Iab, the phase-difference integrated voltage UUI, the peak voltage Umax, and the frequency f output at the V / F voltage-frequency converter after the adjustment of the inverter circuit with an LCR series resonance structure as the load provided in the specific implementation manner.

[0046] Figure 10 It is a schematic diagram of the fluctuation relationship among the real-time voltage Uab, the real-time current Iab, the dead-time pulse PD, the positive current zero-crossing pulse Za output by the current zero-point pulse generator, the negative current zero-crossing pulse Zb, and the synchronization pulse PT in the circuit when the phenomenon of voltage lagging behind current occurs in the inverter circuit with an LCR series resonance structure as the load provided in the specific implementation manner.

[0047] Figure 11It is a schematic diagram of the fluctuation relationship among the synchronous pulse PT, the peak voltage Umax, and the frequency f output by the V / F voltage-frequency converter in the inverter circuit with an LCR series resonance structure as the load when the voltage lags behind the current in the specific implementation manner. Specific implementation manner

[0048] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] To achieve the above objectives, the technical solution of the present invention is as follows:

[0050] Please refer to Figure 2-6 .

[0051] In this specific implementation manner, an inverter circuit with an LCR series resonance structure as the load is provided. The circuit includes an inverter loop for converting direct current into alternating current and outputting it to the load of the LCR series resonance structure;

[0052] The circuit further includes a pulse frequency adjustment drive loop for outputting upper-bridge-arm drive pulses, dead-time pulses, and lower-bridge-arm drive pulses;

[0053] And a phase difference detection loop for comparing the phase difference between the voltage and current leading in the inverter loop and outputting the magnitude of the phase difference;

[0054] The detection end of the phase difference detection loop is connected to the inverter loop, the output end of the phase difference detection loop is connected to the pulse frequency adjustment drive loop, the upper-bridge-arm drive pulses and lower-bridge-arm drive pulses output by the output end of the pulse frequency adjustment drive loop are connected to the inverter loop, and the dead-time pulses output by it are connected to the phase difference detection loop.

[0055] Further, the pulse frequency adjustment drive loop includes a PFM pulse frequency regulator for respectively generating upper-bridge-arm control pulses PA, dead-time pulses PD, and lower-bridge-arm control pulses PB.

[0056] Further, the phase difference detection loop includes:

[0057] A current sensor for detecting the magnitude of the real-time current (Iab / Ica) output by the inverter loop;

[0058] A current zero-crossing comparator for detecting the zero-crossing point of the real-time current;

[0059] A current zero-point pulse generator for respectively generating zero-crossing pulses corresponding to the positive current zero-crossing point and the negative current zero-crossing point;

[0060] The detection end of the current sensor interacts with the inverter circuit. The output end of the current sensor is connected to a current zero-crossing comparator, and the output end of the current zero-crossing comparator is connected to a current zero-point pulse generator. The output end of the current zero-point pulse generator outputs a positive current zero-crossing pulse Za and a negative current zero-crossing pulse Zb respectively.

[0061] Further, the phase difference detection circuit further includes a monostable flip-flop. The positive current zero-crossing pulse Za and the negative current zero-crossing pulse Zb output by the current zero-point pulse generator are respectively connected to the input ends CLR1 and CLR2 in the monostable flip-flop, and the dead-time pulse PD output by the PFM pulse frequency regulator is connected to the trigger inversion end CP of the monostable flip-flop.

[0062] Further, the phase difference detection circuit further includes an advance time detector. The advance time detector is used to calculate the magnitude of the phase difference ΦUI between the real-time voltage Uab and the real-time current Iab. After integrating the phase difference value ΦUI over time, a voltage UUI representing its numerical value is obtained. After performing peak holding processing on the voltage UUI, a peak voltage Umax corresponding to the phase difference between the real-time voltage Uab and the real-time current Iab is obtained, and the peak voltage Umax is output.

[0063] And, an advance time comparator for comparing the output result of the advance time detector with an externally given advance time value.

[0064] The input end of the advance time detector is connected to the output of the monostable flip-flop, the output end of the advance time detector is connected to the advance time comparator, and the advance time comparator is also connected to an externally given advance time value.

[0065] Further, the phase difference detection circuit further includes a V / F voltage-frequency converter. The input end of the V / F voltage-frequency converter is connected to the output of the advance time comparator. The V / F voltage-frequency converter outputs an adjusted frequency f, and its output end is connected to the PFM pulse frequency regulator.

[0066] Further, the circuit further includes an emergency stop circuit. The emergency stop circuit includes:

[0067] A voltage-lagging current cut-off device for monitoring the real-time current and real-time voltage at the inverter circuit and being triggered once it detects that there is a real-time voltage lagging behind the real-time current in the inverter circuit.

[0068] And, a synchronization pulse generator for responding to the voltage-lagging current cut-off device and emitting a synchronization pulse once the voltage-lagging current cut-off device is triggered, thereby forcing the inverter circuit to return to the state where the real-time voltage leads the real-time current.

[0069] The input terminals of the voltage lag current cut-off device are respectively connected to the PFM pulse frequency regulator and the current zero-crossing pulse generator; the output terminal of the voltage lag current cut-off device is connected to the synchronization pulse generator, and the output terminal of the synchronization pulse generator is connected to the PFM pulse frequency regulator.

[0070] Further, the zero-crossing pulse generator includes a first AND gate G1, a second AND gate G2, and a first OR gate G3. The input terminals of the first AND gate G1 are respectively connected to the upper-bridge-arm drive pulse PA output by the PFM pulse frequency regulator and the current positive zero-crossing pulse Za output by the current zero-crossing pulse generator, and the output terminal of the first AND gate G1 is connected to one of the input terminals of the first OR gate G3; the input terminals of the second AND gate G2 are respectively connected to the lower-bridge-arm drive pulse PB output by the PFM pulse frequency regulator and the current negative zero-crossing pulse Zb output by the current zero-crossing pulse generator, and the output terminal of the second AND gate G2 is connected to the other input terminal of the first OR gate G3.

[0071] Further, the present application also discloses a working method of an inverter circuit with an LCR series resonance structure as the load. This working method is based on the above-mentioned inverter circuit with an LCR series resonance structure as the load. Specifically, after the PFM pulse frequency regulator outputs the upper-bridge-arm drive pulse, a dead-time pulse is issued while the upper-bridge-arm drive pulse experiences a falling edge, and while the dead-time pulse experiences a falling edge, the PFM pulse frequency regulator issues the lower-bridge-arm drive pulse. While the lower-bridge-arm drive pulse experiences a falling edge, the PFM pulse frequency regulator issues the upper-bridge-arm drive pulse again, and so on.

[0072] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An inverter circuit with an LCR series resonance structure as the load. The circuit includes an inverter loop for converting direct current into alternating current and outputting it to the load of the LCR series resonance structure; Characterized in that, The circuit further includes a pulse frequency adjustment drive loop for outputting upper bridge arm drive pulses, dead zone pulses, and lower bridge arm drive pulses; And a phase difference detection loop for comparing the phase difference between the voltage leading the current in the inverter loop and outputting the magnitude of the phase difference; The detection end of the phase difference detection loop is connected to the inverter loop, the output end of the phase difference detection loop is connected to the pulse frequency adjustment drive loop, the upper bridge arm drive pulses and the lower bridge arm drive pulses output by the output end of the pulse frequency adjustment drive loop are connected to the inverter loop, and the dead zone pulses output by it are connected to the phase difference detection loop; After the pulse frequency adjustment drive loop outputs the upper bridge arm drive pulse, it emits a dead zone pulse while the upper bridge arm drive pulse experiences a falling edge. And while the dead zone pulse experiences a falling edge, the pulse frequency adjustment drive loop emits a lower bridge arm drive pulse. While the lower bridge arm drive pulse experiences a falling edge, the pulse frequency adjustment drive loop emits the upper bridge arm drive pulse again, and so on.

2. The inverter circuit with an LCR series resonance structure as the load according to claim 1, Characterized in that, The pulse frequency adjustment drive loop includes: a PFM pulse frequency regulator for respectively generating upper bridge arm control pulses, dead zone pulses, and lower bridge arm control pulses.

3. The inverter circuit with an LCR series resonance structure as the load according to claim 2, Characterized in that, The phase difference detection loop includes: A current sensor for detecting the magnitude of the real-time current output by the inverter loop; A current zero-crossing comparator for detecting the zero-crossing point of the real-time current; A current zero-point pulse generator for respectively generating zero-crossing pulses corresponding to the positive current zero-crossing point and the negative current zero-crossing point; The detection end of the current sensor interacts with the inverter loop, the output end of the current sensor is connected to the current zero-crossing comparator, and the output end of the current zero-crossing comparator is connected to the current zero-point pulse generator; The output end of the current zero-point pulse generator respectively outputs a positive current zero-crossing pulse and a negative current zero-crossing pulse.

4. The inverter circuit with an LCR series resonance structure as the load according to claim 3, Characterized in that, The phase difference detection loop further includes a monostable flip-flop. The positive current zero-crossing pulse and the negative current zero-crossing pulse output by the current zero-point pulse generator are respectively connected to the monostable flip-flop, and the dead zone pulse output by the PFM pulse frequency regulator is connected to the trigger inversion end of the monostable flip-flop.

5. The inverter circuit with an LCR series resonance structure as the load according to claim 4, Characterized in that, The phase difference detection loop further includes: An advance time detector for calculating the magnitude of the phase difference between the real-time voltage leading the real-time current and outputting the magnitude difference of the phase in the form of voltage magnitude. and an advance time comparator configured to compare the output result of the advance time detector with an externally given advance time value; The input end of the advance time detector is connected to the output of the monostable flip-flop, the output end of the advance time detector is connected to the advance time comparator, and the advance time comparator is further connected to an externally given advance time value.

6. The inverter circuit with an LCR series resonance structure as the load according to claim 5, characterized in that, the phase difference detection loop further includes a V / F voltage-frequency converter, the input end of the V / F voltage-frequency converter is connected to the output of the advance time comparator, and the output end of the V / F voltage-frequency converter is connected to the PFM pulse frequency regulator.

7. The inverter circuit with an LCR series resonance structure as the load according to claim 6, characterized in that, the circuit further includes an emergency stop loop; the emergency stop loop includes: a voltage lag current cut-off device configured to monitor the real-time current and real-time voltage at the inverter loop, and be triggered once it is detected that there is a real-time voltage lagging behind the real-time current in the inverter loop; and a synchronization pulse generator configured to respond to the voltage lag current cut-off device, generate a synchronization pulse once the voltage lag current cut-off device is triggered, and then force the inverter loop to return to the state where the real-time voltage leads the real-time current; the input end of the voltage lag current cut-off device is respectively connected to the PFM pulse frequency regulator and the current zero-crossing pulse generator; the output end of the voltage lag current cut-off device is connected to the synchronization pulse generator, and the output end of the synchronization pulse generator is connected to the PFM pulse frequency regulator.

8. The inverter circuit with an LCR series resonance structure as the load according to claim 7, characterized in that, the zero-crossing pulse generator includes a first AND gate, a second AND gate and a first OR gate, the input ends of the first AND gate are respectively connected to the upper bridge arm driving pulse output by the PFM pulse frequency regulator and the current positive zero-crossing pulse output by the current zero-crossing pulse generator, and the output end of the first AND gate is connected to one of the input ends of the first OR gate; the input ends of the second AND gate are respectively connected to the lower bridge arm driving pulse output by the PFM pulse frequency regulator and the current negative zero-crossing pulse output by the current zero-crossing pulse generator, and the output end of the second AND gate is connected to the other input end of the first OR gate.

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