A dual-frequency reconfigurable MMIC out-of-phase power amplifier and its control method

Abstract

The present invention discloses a dual-frequency reconfigurable MMIC out-of-phase power amplifier and a control method thereof. The amplifier includes a broadband input matching circuit, an RC stabilization circuit, a dual-frequency parasitic parameter compensation circuit, a dual-frequency reconfigurable power synthesis circuit, and a post-matching circuit. The dual-frequency parasitic parameter compensation circuit adopts a T-type structure to provide the input susceptance required at two frequencies, and the dual-frequency power synthesis circuit adopts a switch to control the size of the upper and lower parallel capacitors of the synthesizer, and achieves the effect of the equivalent electrical length of the upper and lower paths of the synthesizer being symmetrical about 90° by connecting capacitors of different capacitances in parallel. In the application context of high back-off efficiency power amplifiers, the present invention adopts reconfigurable technology to provide a concise and clear idea to design a dual-frequency out-of-phase power amplifier, which has the characteristics of strong practicality and easy promotion.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency microwave communication, and relates to a dual-frequency reconfigurable MMIC out-of-phase power amplifier and a control method thereof, and specifically to a dual-frequency out-of-phase power amplifier MMIC chip that can operate in two independent frequency bands and a design method thereof, which is an out-of-phase power amplifier chip that uses matching reconfigurable technology to support two different operating frequencies and ensures high amplification efficiency. Background Art

[0002] With the rapid iteration and development of wireless communication technology, RF microwave technology is gradually changing people's daily lives. Whether in the commercial and civilian fields or in the defense and military fields, RF communication technology continues to play a pivotal role at this stage. It is easy to find that with the rapid evolution of communication and radar technology, especially the increasing requirements for signal bandwidth, saturated output power, amplifier efficiency, etc., RF microwave systems have been posed with higher technical challenges, and some traditional circuit design methods are gradually unable to adapt to system indicator requirements.

[0003] As the core part of the entire transceiver, the performance of the power amplifier will directly affect the stability and energy consumption level of the entire transceiver system. As the main power-consuming component of the transceiver, improving the efficiency of the power amplifier can not only save energy and increase battery life, but also provide a stable working environment for the system with lower heat generation. However, when amplifying high peak-to-average ratio signals, traditional Class A and Class AB power amplifiers can ensure linearity requirements, but their efficiency is too low in the power back-off state. This problem directly limits the application of traditional power amplifier architectures in high-end transmitters. For the above reasons, some load-modulated power amplifiers that can take into account high back-off efficiency and good linearity are becoming increasingly popular and gradually become the preferred design solution for base station power amplifiers. Among them, the outphasing power amplifier is one of the typical representatives of high-performance load-modulated power amplifiers, and has become a hot topic in the industry in recent years.

[0004] The basic working principle of the out-of-phase power amplifier circuit is to decompose the input signal into two signals with the same amplitude and opposite phase through the signal conditioning circuit. The two decomposed signals are amplified by two saturated sub-amplifiers respectively. The two amplified equal-amplitude out-of-phase signals are vector-merged, so that the amplitude of the input modulated signal can be highly restored at the output end to achieve good linearity. At the same time, the saturated sub-amplifier ensures high efficiency during operation. Therefore, the out-of-phase power amplifier can achieve high efficiency and high-fidelity amplification of the modulated signal at the same time.

[0005] As the core of the whole out-of-phase amplifier, the design of the power combiner at the output end is crucial. Among them, the Chireix combiner with integrated sub-amplifier reactance compensation function is the most widely used structure at present. The combiner of this structure provides a suitable imaginary part compensation circuit at the synthesis end to eliminate the influence of the reactive imaginary part on the efficiency, thereby effectively ensuring the overall efficiency of the amplifier. The imaginary part compensation circuit can be a series or parallel structure. Among them, a non-equal length combiner structure based on series compensation has attracted widespread attention recently due to its simple structure and easy design characteristics.

[0006] On the other hand, due to the shortage of spectrum resources in conventional communication bands, the working spectrum of broadband communication technology in the future will continue to migrate to high frequency bands. While the increase in working frequency brings abundant bandwidth resources, it also introduces greater technical challenges. One of the prominent problems is that due to the short working wavelength of high-frequency signals, the circuit size is required to be greatly reduced, so the trend of transition from traditional PCB process to semiconductor chip process is irreversible. Microwave Monolithic Integrated Circuit (MMIC) has gradually occupied a considerable part of the civilian and military market with its miniaturization, stable performance, strong consistency, high reliability, and mass production. The flexibility of MMIC chips based on compound processes such as gallium arsenide and gallium nitride in circuit implementation makes it possible to design a power amplifier that can support multi-frequency operation. At the same time, in order to make full use of these resources, the development of multi-mode and multi-frequency communication systems has become a development trend. In order to achieve this goal, it is usually necessary to integrate multiple power amplifiers working at different frequencies, which not only increases the complexity of the design but also does not conform to the development trend of circuit lightweighting and miniaturization.

[0007] In view of the current existing needs, it is necessary to conduct research to provide a universal dual-band out-of-phase MMIC power amplifier design. Summary of the invention

[0008] One objective of the present invention is to address the deficiencies of the prior art and propose a dual-band reconfigurable MMIC out-of-phase power amplifier, specifically an out-of-phase amplifier that supports dual-band operation with a single circuit. The out-of-phase power amplifier theory based on unequal-length transmission lines is used to perform dual-band design for various parts of a single-band power amplifier. The synthesizer, which is the core part, adopts a reconfigurable T-type structure with a switch to replace the unequal-length transmission line of the synthesizer. By controlling the state of the parallel switch of the T-type structure, the equivalent electrical length of the synthesizer is controlled to achieve the dual-band function of the power amplifier.

[0009] The dual-frequency reconfigurable MMIC out-of-phase power amplifier of the present invention comprises upper and lower circuits, a dual-frequency reconfigurable power synthesis circuit, and a post-matching circuit; wherein each circuit comprises a broadband input matching circuit, an RC stabilization circuit, a gate bias circuit, a transistor, and a dual-frequency parasitic capacitance compensation circuit.

[0010] The inputs of the two broadband input matching circuits in the upper and lower circuits are equal-amplitude out-of-phase signals of different frequencies, whose amplitudes are exactly the same and whose phase relationship satisfies specific conditions. Each broadband input matching circuit adopts a classic broadband impedance matching structure, which can achieve full matching of the input impedance of the transistor at two frequency points.

[0011] The reconfigurable dual-frequency power synthesis circuit adopts a switch-controlled T-type structure parallel capacitor to ensure the impedance and phase relationship of the upper and lower synthesizers at two frequencies; it includes two upper and lower branches, both of which adopt a reconfigurable T-type structure with different parameters but the same structure, and the reconfigurable T-type structure includes a series transmission line L8, a parallel capacitor C4, a parallel capacitor C5, switches S1 and S2 respectively connecting the two parallel capacitors C4 and C5 and grounding, and a series transmission line L9. One end of the series transmission line L8 serves as the input end of the reconfigurable T-type structure, and the other end is connected to one end of the parallel capacitor C4, one end of the parallel capacitor C5, and one end of the series transmission line L9; the other ends of the parallel capacitors C4 and C5 are grounded through switches S1 and S2 respectively; the other ends of the upper and lower reconfigurable T-type structure series transmission lines L9 are connected to each other as the output end of the reconfigurable dual-frequency power synthesis circuit.

[0012] The series transmission lines L8 and L9 in the same reconfigurable T-shaped structure have the same electrical length and characteristic impedance; the parallel capacitors C4 and C5 have different capacitance values, corresponding to the capacitance values ​​required at two frequencies respectively.

[0013] The electrical length of the series transmission line L8 in the upper and lower different reconfigurable T-type structures is different, and the characteristic impedance is the same; the electrical length of the series transmission line L9 in the upper and lower different reconfigurable T-type structures is different, and the characteristic impedance is the same; the capacitance value of the parallel capacitor C4 in the upper and lower different reconfigurable T-type structures is the same, and the capacitance value of the parallel capacitor C5 is the same.

[0014] The same reconfigurable T-shaped structure in the upper and lower branches meets the following conditions:

[0015]

[0016] Where C represents the capacitance of the parallel capacitors C4 and C5 in the current reconfigurable T-type structure; the electrical lengths of the series transmission lines L8 and L9 are both θ0; Z represents the characteristic impedance of the series transmission lines L8 and L9, f=f1 or f2, represents the normalized center frequency.

[0017] Preferably, the input broadband matching can adopt a multi-stage LC topology or a broadband impedance matching structure based on network synthesis, the purpose of which is to achieve effective matching of the input impedance (usually 50 ohms) to the transistor gate impedance within a wide frequency band.

[0018] More preferably, the broadband input matching circuit comprises a series transmission line L1, a parallel short-circuited transmission line L2, a series DC blocking capacitor C1, a series transmission line L3, a parallel matching capacitor C2, and a series transmission line L4. One end of the series transmission line L1 serves as the input end of the broadband input matching circuit, the other end of the series transmission line L1 is connected to one end of the parallel short-circuited transmission line L2 and one end of the DC blocking capacitor C1, the other end of the parallel short-circuited transmission line L2 is grounded, one end of the series transmission line L3 is connected to the other end of the DC blocking capacitor C1, the other end of the series transmission line L3 is connected to one end of the parallel matching capacitor C2 and one end of the series transmission line L4, the other end of the parallel matching capacitor C2 is grounded, and the other end of the series transmission line L4 serves as the output end of the broadband input matching circuit;

[0019] Preferably, the RC stabilization circuit provides a stable working condition within the working frequency band for the transistor, thereby avoiding unnecessary self-oscillation of the amplifier;

[0020] Preferably, the RC stabilization circuit comprises a parallel RC network consisting of a resistor R1 and a capacitor C7, one end of the resistor R1 and one end of the capacitor C7 are connected as an input end of the stabilization circuit, connected to an output end of a broadband input matching circuit and an input end of a gate bias circuit; the other end of the resistor R1 and the other end of the capacitor C7 are connected as an output end of the amplifier stabilization circuit, connected to a gate of the transistor;

[0021] Preferably, the gate bias circuit comprises a parallel transmission line L5; one end of the parallel transmission line L5 is connected to the gate bias V GS Connecting, the other end of the parallel transmission line L5 is connected to the input end of the RC stabilization circuit;

[0022] Preferably, the transistor is biased in a deep class AB or class B operating state.

[0023] Preferably, the dual-frequency parasitic capacitance compensation network adopts a T-shaped structure design, which can compensate for the parasitic capacitance of the transistor at two frequency points while providing power to the drain;

[0024] More preferably, the dual-frequency parasitic capacitance compensation network includes a T-shaped structure composed of a transmission line and a parallel capacitor, which includes a parallel transmission line L6, a parallel capacitor C3, and a parallel transmission line L7; one end of the parallel transmission line L6 is connected to the drain of the transistor, and the other end is connected to one end of the parallel capacitor C3 and one end of the parallel transmission line L7, the other end of the parallel capacitor C3 is grounded, and the other end of the parallel transmission line L7 is connected to the drain power supply V DSconnected.

[0025] Preferably, the post-matching circuit is used to provide a conversion from a 50 ohm standard impedance at two frequencies to an optimal impedance required by a power synthesis network, and includes a series transmission line L10, a series transmission line L11, a parallel capacitor C6, a series DC blocking capacitor C7, a parallel inductor H1, and a series transmission line L12. One end of the series transmission line L10 is used as the input end of the post-matching circuit and is connected to the output end of the reconfigurable dual-frequency power synthesis circuit; the other end of the series transmission line L10 is connected to one end of the parallel capacitor C6 and one end of the series transmission line L11; the other end of the parallel capacitor C6 is grounded; the other end of the series transmission line L11 is connected to one end of the series DC blocking capacitor C7; the other end of the series DC blocking capacitor C7 is connected to one end of the parallel inductor H1 and one end of the series transmission line L12, the other end of the parallel inductor H1 is grounded, and the other end of the series transmission line L12 is used as the output end of the post-matching circuit and is connected to a standard 5 ohm load.

[0026] Another object of the present invention is to provide a control method for the above-mentioned dual-frequency reconfigurable MMIC out-of-phase power amplifier.

[0027] When the switch S1 of the upper and lower branches of the reconfigurable dual-frequency power synthesis circuit is turned on and the switch S2 is turned off, it is in the first working state, and the equivalent electrical length of the reconfigurable T-shaped structure meets the first working frequency f1; the equivalent electrical lengths of the upper and lower branches of the reconfigurable dual-frequency power synthesis circuit meet the characteristic of 90° central symmetry under f1;

[0028] When the switch S1 of the upper and lower branches of the reconfigurable dual-frequency power synthesis circuit is closed and the switch S2 is opened, it is in the second working state, and at this time, the equivalent electrical length of the reconfigurable T-shaped structure meets the second working frequency f2; the equivalent electrical lengths of the upper and lower branches of the reconfigurable dual-frequency power synthesis circuit meet the characteristic of 90° central symmetry under f2;

[0029] By controlling the states of the reconfigurable T-type structure switches S1 and S2, switching back and forth between two operating frequencies is achieved.

[0030] The beneficial effects of the present invention are as follows:

[0031] After two equal-amplitude but out-of-phase signals reach the transistor for amplification through the broadband input matching circuit, they are combined in the power combiner. At different frequencies, the equivalent electrical length of the combiner's T-shaped structure is adjusted by controlling the switch to achieve efficient combination. Finally, the signal reaches the load end through the rear matching circuit. The switching of the switch ultimately enables the power amplifier to operate at two frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of a dual-frequency reconfigurable MMIC out-of-phase power amplifier in the present invention.

[0033] Figure 2 The invention is a dual-frequency parasitic parameter compensation circuit based on T-type structure.

[0034] Figure 3 It is a schematic diagram of using a reconfigurable T-structure synthesizer to replace a traditional non-equal length synthesizer.

[0035] Figure 4 It is a typical T-type structure diagram.

[0036] Figure 5 It is a schematic diagram of the results of simulating the present invention at two frequencies of 10 GHz and 15 GHz using simulation software. DETAILED DESCRIPTION

[0037] The following are specific embodiments of the present invention and the accompanying drawings to further describe the technical solution of the present invention, but the present invention is not limited to these embodiments.

[0038] Figure 1 The figure shows a schematic diagram of the structure of a dual-frequency out-of-phase power amplifier in the present invention, which includes a broadband input matching circuit, an RC parallel stabilization circuit, a dual-frequency parasitic capacitance compensation circuit, a dual-frequency reconfigurable power synthesis circuit, and a post-matching circuit.

[0039] The broadband matching circuit adopts a low-Q broadband matching structure to ensure low-loss transmission of the input signal to the transistor, wherein the series capacitor used in the matching structure also serves to cut off direct current, and the parallel short-circuit line also serves as a gate bias circuit.

[0040] The RC stabilization circuit introduces lossy components to ensure the stability of the amplifier within the operating frequency band.

[0041] Figure 2 The figure shows a T-type structure for realizing parasitic capacitance compensation under dual frequencies. This structure can be used to compensate for the parasitic parameters of the transistor under two frequencies so that the optimal impedance of the saturation point and the back-off point of the transistor falls near the real axis.

[0042] The parasitic parameters of the transistor are mainly parasitic capacitance. The susceptance compensation value required at the drain of the transistor at two frequencies can be calculated by load pulling and other methods, corresponding to Figure 2 Middle Y in (f1) and Y in (f2), the susceptance value seen from the input end of the T-type structure designed for the dual-frequency parasitic capacitance compensation circuit at two operating frequencies can be expressed as:

[0043]

[0044]

[0045] where Y A (f1) and Y A (f2) are:

[0046]

[0047]

[0048]

[0049] The variables Z1 and Z2 involved in the above formula correspond to the characteristic impedances of the transmission lines L6 and L7 respectively, θ1 and θ2 correspond to the electrical lengths of the transmission lines L6 and L7 respectively; C represents the capacitance of the parallel capacitor C3; Y A (f1) represents the admittance value at the output of transmission line L6 at frequency f1, Y B (f1) represents the admittance value at the input end of the transmission line L7 at frequency f1, Y C (f1) represents the admittance value at the input end of capacitor C3 at frequency f1, Y A (f2), Y B (f2), Y C (f2) corresponds to the value at frequency f2. It should be noted that the free variables used for design in the above formula: capacitance C, electrical lengths of the transmission line θ1 and θ2, characteristic impedances Z1 and Z2 must meet the design requirements and the requirements of circuit layout processing, so that the input susceptance corresponding to the two frequencies can be achieved by designing the above T-type structure.

[0050] Figure 3 The conventional non-equal length synthesizer ( Figure 3 (a)) and reconfigurable T-shaped structure ( Figure 3 (b)). The traditional non-equal length synthesizer consists of two transmission lines with the same characteristic impedance but different electrical lengths. The transmission line structure is used to achieve imaginary part compensation. However, when the frequency changes, the dispersion effect of the transmission line makes it no longer meet the requirements. The efficiency of the synthesizer will be affected. represents the normalized frequency, f represents the actual working frequency, f0 represents the original center frequency; Δf represents the frequency change, Δf = f-f0; and the following derivation is performed:

[0051] For the synthesizer's upper path, the relationship between its actual electrical length and normalized frequency is:

[0052]

[0053] For the synthesizer's lower path, the relationship between its actual electrical length and normalized frequency is:

[0054]

[0055] From the formula derivation, it can be seen that 90°·Δf affects the upper and lower paths. Therefore, a reconfigurable structure can be used to eliminate the influence of this part. Here, a T-type structure (b) controlled by a switch is used to replace the traditional non-equal length synthesizer (a), such as Figure 3 shown.

[0056] Figure 4 The transfer matrix of a typical T-type structure shown can be expressed as:

[0057]

[0058] Where θ is the electrical length of the T-type structure series transmission line, Z is the characteristic impedance of the series transmission line, and C is the capacitance of the parallel capacitor.

[0059] Let Y c =2πfC, It can be simplified to:

[0060]

[0061] Let θ c =arctan(t), simplifying to get:

[0062]

[0063] The S of the T-type structure can be obtained from the transmission matrix 21 :

[0064]

[0065] From this, the equivalent electrical length of the T-type structure is 2θ+θ c .

[0066] Figure 3 The T-type structure of the added path reconfigurable structure shown in (b) is composed of the added path series transmission line L8, the parallel capacitors C4 and C5 connected to the ground through switches S1 and S2, and the added path series transmission line L9, wherein the electrical lengths θ of the two series transmission lines are both The lower reconfigurable T-type structure part consists of a lower series transmission line L8, parallel capacitors C4 and C5 grounded through switches S1 and S2, respectively, and a lower series transmission line L9, wherein the electrical lengths θ of the two series transmission lines are both θ0-φ / 2; the parallel capacitor C4 in the upper reconfigurable T-type structure has the same capacitance as the parallel capacitor C4 in the lower reconfigurable T-type structure, the parallel capacitor C5 in the upper reconfigurable T-type structure has the same capacitance as the parallel capacitor C5 in the lower reconfigurable T-type structure, and the corresponding states of the upper and lower paths S1 and S2 are the same.

[0067] According to the transmission matrix of the T-type structure, its S 11 :

[0068]

[0069] At this time, the impedance seen from the upper and lower input terminals of the power combiner is Z in1 and Z in2 , and through the previous analysis, it can be known that the electrical lengths of the upper and lower T-type series transmission lines are and θ0-φ / 2, the equivalent electrical lengths of the upper and lower reconfigurable T-shaped structures are 2θ0+θ c +φ and 2θ0+θ c -φ.

[0070] For the convenience of calculation, let

[0071] For the road:

[0072] For the bottom lane:

[0073] And 2θ0+θ c =90°, so we can get:

[0074]

[0075]

[0076] Total points:

[0077]

[0078]

[0079] because Therefore, it can be proved that the equivalent characteristic impedances of the upper and lower T-shaped structures obtained by the above design method are equal.

[0080] When the frequency changes, the equivalent electrical lengths of the upper and lower paths of the reconfigurable dual-frequency power synthesis circuit are:

[0081]

[0082]

[0083] In order to make the equivalent electrical lengths of the upper and lower paths satisfy the 90° central symmetry, it is necessary to always ensure

[0084]

[0085] Since the electrical length of the T-type series transmission line is fixed and θ0 is a constant, we can obtain:

[0086]

[0087] C: Capacitance of T-type parallel capacitor

[0088] θ0: The electrical length of the series transmission line in the T-type structure

[0089] Z: T-type structure series transmission line characteristic impedance

[0090] is the normalized frequency

[0091] f: actual operating frequency

[0092] because The value changes with the frequency. The value will affect the impedance trajectory of the reconfigurable dual-frequency power synthesis circuit, causing it to deviate from the optimal impedance point. The load impedance can also affect the impedance trajectory of the reconfigurable dual-frequency power synthesis circuit. Therefore, the load impedance can be adjusted to alleviate the problem. The post-matching structure in Figure 1 is used to achieve this function, so it is necessary to obtain the optimal load impedance at two frequency points through simulation, and then design Figure 1 The post-matching structure shown is used to achieve impedance transformation at two frequency points.

[0093] The design method of the dual-band power amplifier is implemented by the following steps:

[0094] Step 1: Design an RC stabilization circuit and adjust the size of the RC stabilization circuit capacitor C7 and resistor R1 to make the transistor stability factor greater than 1 within a wide frequency band.

[0095] Step 2: Design a power amplifier biased in Class AB and use the broadband input matching circuit described above. This structure is used for both the upper and lower paths.

[0096] Step 3: Debug the dual-frequency parasitic capacitance compensation circuit. The T-type structure parasitic parameter compensation circuit used needs to provide the reactance required at two frequencies.

[0097] Step 4: Debug the reconfigurable dual-frequency power synthesis circuit. Debug the series transmission lines L8 and L9 of the same reconfigurable T-type structure, ensure that the parameters of the series transmission lines L8 and L9 are the same, and design the electrical length of the series transmission lines L8 and L9 at the center frequency; control the on and off states of the switches S1 and S2 according to the requirements, adjust the capacitance of the upper and lower parallel capacitors C4 in the first working state, and adjust the capacitance of the upper and lower parallel capacitors C5 in the second working state, so that the equivalent electrical lengths of the upper and lower reconfigurable T-type structures can meet the requirements of non-equal length structures in both working states, that is, the equivalent electrical lengths of the upper and lower paths are symmetrical about the 90° center in the two working states, and ensure that the equivalent characteristic impedances of the upper and lower paths are the same.

[0098] Step 5: Debug the post-matching circuit. By observing the position of the impedance trajectory of the reconfigurable dual-frequency power synthesis circuit on the Smith original diagram and referring to the performance results of the simulation at this time, find out the optimal load impedance required by the synthesizer at the two frequencies, and debug the various parameters of the post-matching circuit mentioned above to achieve the conversion from the standard 50 ohms to the optimal impedance at the two operating frequencies.

[0099] Step 6: Combine and debug the debugged broadband input matching circuit, RC stabilization circuit, dual-frequency parasitic capacitance compensation circuit, dual-frequency reconfigurable power synthesis circuit, and post-matching circuit.

[0100] Figure 5 The figure shows the result of data simulation of the design of the present invention in ADS. From the simulation results, it can be seen that when the amplifier works at 10GHz, the saturated output power is greater than 32dBm, the saturated output efficiency is 55.8%, and the efficiency of 6dB power back-off is 54%; when the amplifier works at 15GHz, the saturated output power is greater than 31dBm, the saturated output efficiency is 65%. The efficiency of 6dB power back-off is 61%. The simulation results show that the design realizes the dual-frequency operation function of the amplifier.

[0101] The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention. It is obvious to those skilled in the art that various modifications to these embodiments can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A dual-frequency reconfigurable MMIC out-of-phase power amplifier, comprising upper and lower circuits, a dual-frequency reconfigurable power synthesis circuit, and a post-matching circuit; two input ends of the dual-frequency reconfigurable power synthesis circuit are respectively connected to the output ends of the upper and lower circuits, the output end of the dual-frequency reconfigurable power synthesis circuit is connected to the input end of the post-matching circuit, and the output end of the post-matching circuit is connected to a 50 ohm load; wherein each circuit in the upper and lower circuits comprises a broadband input matching circuit, an RC stabilization circuit, a gate bias circuit, a transistor, and a dual-frequency parasitic capacitance compensation circuit, the output of the broadband input matching circuit is connected to the input of the RC stabilization circuit, one end of the gate bias circuit is connected to the input end of the RC stabilization circuit, and the other end of the gate bias circuit is connected to the gate bias V GS The output terminal of the RC stabilization circuit is connected to the gate of the transistor, one end of the dual-frequency parasitic capacitance compensation network is connected to the drain of the transistor, and the other end of the dual-frequency parasitic capacitance compensation network is connected to the drain power supply V DS , the drain of the transistor serves as the output of the circuit; it is characterized by: The reconfigurable dual-frequency power synthesis circuit includes an upper and lower branch; the upper and lower branches adopt a reconfigurable T-type structure with different parameters but the same structure, and the reconfigurable T-type structure includes a series transmission line L8, a parallel capacitor C4, a parallel capacitor C5, switches S1 and S2 respectively connected to the two parallel capacitors C4 and C5 and grounded, and a series transmission line L9; one end of the series transmission line L8 serves as the input end of the reconfigurable T-type structure, and the other end is connected to one end of the parallel capacitor C4, one end of the parallel capacitor C5, and one end of the series transmission line L9; the other ends of the parallel capacitors C4 and C5 are grounded through switches S1 and S2 respectively; the other ends of the series transmission lines L9 of the upper and lower reconfigurable T-type structures are connected to each other as the output end of the reconfigurable dual-frequency power synthesis circuit; In the same branch reconfigurable T-shaped structure, the series transmission lines L8 and L9 have the same electrical length and characteristic impedance; the parallel capacitors C4 and C5 have different capacitance values, corresponding to the capacitance values ​​required at two frequencies respectively; In the reconfigurable T-type structure with different upper and lower branches, the electrical length of the series transmission line L8 is different, and the characteristic impedance is the same; the electrical length of the series transmission line L9 is different, and the characteristic impedance is the same; the capacitance value of the parallel capacitor C4 is the same, and the capacitance value of the parallel capacitor C5 is the same; The same reconfigurable T-shaped structure meets the following conditions: Where C represents the capacitance of the parallel capacitors C4 and C5 in the current reconfigurable T-type structure; the electrical lengths of the series transmission lines L8 and L9 are both θ0; Z represents the characteristic impedance of the series transmission lines L8 and L9, f=f1 or f2, represents the normalized center frequency; The inputs of the two broadband input matching circuits in the upper and lower circuits are equal-amplitude, out-of-phase signals of different frequencies; they include a series transmission line L1, a parallel short-circuit transmission line L2, a series DC-isolating capacitor C1, a series transmission line L3, a parallel matching capacitor C2, and a series transmission line L4; one end of the series transmission line L1 serves as the input end of the broadband input matching circuit, the other end of the series transmission line L1 is connected to one end of the parallel short-circuit transmission line L2 and one end of the DC-isolating capacitor C1, the other end of the parallel short-circuit transmission line L2 is grounded, one end of the series transmission line L3 is connected to the other end of the DC-isolating capacitor C1, the other end of the series transmission line L3 is connected to one end of the parallel matching capacitor C2 and one end of the series transmission line L4, the other end of the parallel matching capacitor C2 is grounded, and the other end of the series transmission line L4 serves as the output end of the broadband input matching circuit; The RC stabilization circuit includes a parallel RC network composed of a resistor R1 and a capacitor C7. One end of the resistor R1 and one end of the capacitor C7 are connected as the input end of the stabilization circuit, connected to the output end of the broadband input matching circuit and the input end of the gate bias circuit; the other end of the resistor R1 and the other end of the capacitor C7 are connected as the output end of the amplifier stabilization circuit, connected to the gate of the transistor; The gate bias circuit includes a parallel transmission line L5; one end of the parallel transmission line L5 is connected to the gate bias V GS Connecting, the other end of the parallel transmission line L5 is connected to the input end of the RC stabilization circuit; The post-matching circuit is used to provide conversion from a 50-ohm standard impedance at two different frequencies to an optimal impedance required by a dual-frequency reconfigurable power synthesis circuit, and includes a series transmission line L10, a series transmission line L11, a parallel capacitor C6, a series DC blocking capacitor C7, a parallel inductor H1, and a series transmission line L12; one end of the series transmission line L10 serves as an input end of the post-matching circuit and is connected to an output end of the reconfigurable dual-frequency power synthesis circuit; the other end of the series transmission line L10 is connected to one end of the parallel capacitor C6 and one end of the series transmission line L11; the other end of the parallel capacitor C6 is grounded; the other end of the series transmission line L11 is connected to one end of the series DC blocking capacitor C7; the other end of the series DC blocking capacitor C7 is connected to one end of the parallel inductor H1 and one end of the series transmission line L12, the other end of the parallel inductor H1 is grounded, and the other end of the series transmission line L12 serves as an output end of the post-matching circuit and is connected to a standard 50-ohm load.

2. A dual-frequency reconfigurable MMIC out-of-phase power amplifier according to claim 1, characterized in that The transistors are biased in deep class AB or class B operation.

3. A dual-frequency reconfigurable MMIC out-of-phase power amplifier according to claim 1, characterized in that The dual-frequency parasitic capacitance compensation network adopts a T-type structure to compensate for the parasitic capacitance of the transistor at two different frequencies while providing power to the drain.

4. A dual-frequency reconfigurable MMIC out-of-phase power amplifier according to claim 3, characterized in that The dual-frequency parasitic capacitance compensation network includes a T-shaped structure composed of a transmission line and a parallel capacitor, which includes a parallel transmission line L6, a parallel capacitor C3, and a parallel transmission line L7; one end of the parallel transmission line L6 is connected to the drain of the transistor, and the other end is connected to one end of the parallel capacitor C3 and one end of the parallel transmission line L7, the other end of the parallel capacitor C3 is grounded, and the other end of the parallel transmission line L7 is connected to the drain power supply V DS connected.

5. A control method for a dual-frequency reconfigurable MMIC out-of-phase power amplifier according to any one of claims 1 to 4, characterized in that: When the switch S1 of the upper and lower branches of the reconfigurable dual-frequency power synthesis circuit is turned on and the switch S2 is turned off, it is in the first working state, and the equivalent electrical length of the reconfigurable T-shaped structure meets the first working frequency f1; the equivalent electrical lengths of the upper and lower branches of the reconfigurable dual-frequency power synthesis circuit meet the characteristic of 90° central symmetry under f1; When the switch S1 of the upper and lower branches of the reconfigurable dual-frequency power synthesis circuit is closed and the switch S2 is opened, it is in the second working state, and at this time, the equivalent electrical length of the reconfigurable T-shaped structure meets the second working frequency f2; the equivalent electrical lengths of the upper and lower branches of the reconfigurable dual-frequency power synthesis circuit meet the characteristic of 90° central symmetry under f2; By controlling the states of the reconfigurable T-type structure switches S1 and S2, switching back and forth between two operating frequencies is achieved.

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