Power amplifier power regulation circuit and power amplifier

Abstract

The present invention provides a power amplifier power regulation circuit and a power amplifier, comprising: a bias current generating circuit, a current magnitude control circuit, and a bias current output control circuit. The bias current generating circuit is configured to generate a plurality of different bias currents, with its output end connected to the current magnitude control circuit. The current magnitude control circuit includes a plurality of first control switches, each of whose output ends is connected to the bias current output control circuit. The bias current output control circuit includes a plurality of second control switches, each of whose output ends is connected to an output branch. The present invention can implement the input of a plurality of bias currents, thereby enabling the power amplifier to operate in a plurality of operating modes.

Description

Technical field

[0001] The present invention relates to the field of electronic technology, and in particular to a power amplifier power regulation circuit and a power amplifier. [Background Technology]

[0002] RF power amplifiers are widely used in various wireless communication devices and electronic systems. Their key technical specifications include output power, efficiency, and linearity. Power amplifiers typically operate in different modes, with transmit power set within a certain range. Furthermore, requirements for gain, current, and other parameters vary across these modes. Therefore, the ability to precisely and flexibly adjust certain performance parameters of power amplifiers is of great practical significance. [Summary of the invention]

[0003] The object of the present invention is to overcome at least one of the above technical problems and to provide a power amplifier power regulation circuit and a power amplifier.

[0004] In order to achieve the above-mentioned object, the present invention provides a power amplifier power regulation circuit, comprising: a bias current generating circuit, a current magnitude control circuit, and a bias current output control circuit;

[0005] The bias current generating circuit is used to generate a variety of different bias currents, and its output end is connected to the current magnitude control circuit;

[0006] The current magnitude control circuit includes a plurality of first control switches, and the output end of each first control switch is respectively connected to the bias current output control circuit;

[0007] The bias current output control circuit includes a plurality of second control switches, and the output end of each second control switch is respectively connected to an output branch.

[0008] Preferably, the bias current generating circuit includes a first operational amplifier and a first MOS transistor connected to the output end of the first operational amplifier, and the input voltage controls the first MOS transistor to generate different bias currents through the first operational amplifier.

[0009] Preferably, the current control circuit includes a plurality of first output control MOS transistors connected in parallel, and the output ends of the first operational amplifier are respectively connected to the gates of the first output control MOS transistors through the first control switches, and the corresponding first output control MOS transistors are mirrored to output bias currents of corresponding magnitudes by controlling the first control switches.

[0010] Preferably, the bias current generating circuit further includes: a second operational amplifier, and a second MOS transistor connected to the output terminal of the second operational amplifier, the source of the second MOS transistor being connected to the drain of the first MOS transistor and the negative input terminal of the second operational amplifier, the drain of the second MOS transistor being connected to the positive input terminal of the first operational amplifier, and the positive input terminal of the second operational amplifier being input with a reference voltage.

[0011] Preferably, the bias current output control circuit further includes: a third operational amplifier, a second output control MOS transistor connected to the output end of the third operational amplifier, the third operational amplifier is connected to the second output control MOS transistor through the second control switch, and the output branch is connected to the drain of the second output MOS transistor.

[0012] In a second aspect, the present invention provides a power amplifier, comprising a power amplification circuit and a power regulation circuit, wherein the power regulation circuit comprises: a bias current generating circuit, a current magnitude control circuit, and a bias current output control circuit;

[0013] The bias current generating circuit is used to generate a variety of different bias currents, and its output end is connected to the current magnitude control circuit;

[0014] The current magnitude control circuit includes a plurality of first control switches, and the output end of each first control switch is respectively connected to the bias current output control circuit;

[0015] The bias current output control circuit includes a plurality of second control switches, and the output end of each second control switch is respectively connected to an output branch;

[0016] The power amplifier circuit includes a plurality of power amplifier groups, wherein a bias current input terminal of each power amplifier group is connected to one or more of the output branches.

[0017] Preferably, the bias current generating circuit includes a first operational amplifier and a first MOS transistor connected to the output end of the first operational amplifier, and the input voltage controls the first MOS transistor to generate different bias currents through the first operational amplifier; the current magnitude control circuit includes a plurality of first output control MOS transistors connected in parallel, and the output ends of the first operational amplifier are respectively connected to the gates of the first output control MOS transistors through the first control switches, and the corresponding first output control MOS transistors are mirrored to output bias currents of corresponding magnitudes by controlling the first control switches.

[0018] Preferably, the bias current generating circuit further includes: a second operational amplifier, and a second MOS transistor connected to the output terminal of the second operational amplifier, the source of the second MOS transistor being connected to the drain of the first MOS transistor and the negative input terminal of the second operational amplifier, the drain of the second MOS transistor being connected to the positive input terminal of the first operational amplifier, and the positive input terminal of the second operational amplifier being input with a reference voltage.

[0019] Preferably, the bias current output control circuit further includes: a third operational amplifier, a second output control MOS transistor connected to the output end of the third operational amplifier, the third operational amplifier is connected to the second output control MOS transistor through the second control switch, and the output branch is connected to the drain of the second output MOS transistor.

[0020] Compared to related technologies, the regulation circuit of the present invention generates a bias current by adjusting the input voltage and current branch switches. This bias current is then transmitted to the bias circuit of the power amplifier. During this transmission process, the switch can adjust the current output of different output branches and adjust the bias of different power amplifiers as needed, thereby achieving different output powers of the power amplifier.

Brief Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0022] Figure 1 2 is a schematic diagram of a power amplifier according to an embodiment of the present invention. [Specific implementation method]

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] Example 1

[0025] See also Figure 1As shown, an embodiment of the present invention provides a power regulation circuit 100 for a power amplifier, comprising: a bias current generating circuit 110, a current magnitude control circuit 120, and a bias current output control circuit 130; wherein the bias current generating circuit 110 is used to generate a plurality of different bias currents, and its output end is connected to the current magnitude control circuit 120; the current magnitude control circuit 120 includes a plurality of first control switches (S11 to S1N), and the output end of each first control switch is respectively connected to the bias current output control circuit 130; the bias current output control circuit 130 includes a plurality of second control switches (S21 to S2N), and the output end of each second control switch is respectively connected to an output branch (IO_1 to IO_N).

[0026] In this embodiment, the bias current generating circuit 110 further includes a first operational amplifier OP1 and a first MOS transistor P1 connected to the output terminal of the first operational amplifier OP1. An input voltage VIN controls the first MOS transistor P1 via the first operational amplifier OP1 to generate different bias currents. The bias current generating circuit 110 receives input voltage VIN and controls the first MOS transistor P1 via the first operational amplifier OP1 to generate different bias currents. In this embodiment, the input voltage VIN can be constant or variable.

[0027] In this embodiment, the current control circuit 120 further includes a plurality of first output control MOS transistors (P11 to P1N) connected in parallel. The output end of the first operational amplifier OP1 is connected to the gate of the first output control MOS transistors (P11 to P1N) through the first control switches (S11 to S1N), respectively. By controlling the first control switches, the corresponding first output control MOS transistors are mirrored to output bias currents of corresponding magnitudes.

[0028] In this embodiment, the bias current generating circuit 110 further includes: a second operational amplifier OP2, and a second MOS transistor P2 connected to the output terminal of the second operational amplifier OP2. The source of the second MOS transistor P2 is connected to the drain of the first MOS transistor P1 and the negative input terminal of the second operational amplifier OP2. The drain of the second MOS transistor P2 is connected to the positive input terminal of the first operational amplifier OP1. The positive input terminal of the second operational amplifier OP2 is input with a reference voltage VREF.

[0029] In this embodiment, the bias current output control circuit 130 further includes: a third operational amplifier OP3, and second output control MOS transistors (P21 to P2N) connected to the output end of the third operational amplifier OP3. The third operational amplifier OP3 is connected to the second output control MOS transistors via the second control switches (S21 to S2N), and the output branches are connected to the drains of the second output MOS transistors.

[0030] In this embodiment, the power regulation circuit 100 generates current through a bias current generating circuit, mirrors the selected current through a current magnitude control circuit, and selects an output branch for output through a bias current output control circuit 130, thereby achieving the purpose of accurately providing different bias currents to the power amplifier, enabling the power amplifier to operate in more modes.

[0031] Example 2

[0032] like Figure 1 As shown, an embodiment of the present invention further provides a power amplifier, including a power amplifier circuit 200 and a power regulation circuit 100, wherein the power regulation circuit includes: a bias current generating circuit 110, a current magnitude control circuit 120, and a bias current output control circuit 130; wherein the bias current generating circuit 110 is used to generate multiple different bias currents, and its output end is connected to the current magnitude control circuit 120; the current magnitude control circuit 120 includes a plurality of first control switches (S11-S1N), the output end of each first control switch is respectively connected to the bias current output control circuit 130; the bias current output control circuit 130 includes a plurality of second control switches (S21-S2N), the output end of each second control switch is respectively connected to an output branch (IO_1-IO_N); the power amplifier circuit 200 includes a plurality of power amplifier groups (PA_1-PA_N), wherein the bias current input end (IBLAS_1-IBLAS_N) of each power amplifier group is connected to one or more of the output branches (IO_1-IO_N).

[0033] In this embodiment, the bias current generating circuit 110 further includes a first operational amplifier OP1 and a first MOS transistor P1 connected to the output terminal of the first operational amplifier OP1. An input voltage VIN controls the first MOS transistor P1 via the first operational amplifier OP1 to generate different bias currents. The bias current generating circuit 110 receives input voltage VIN and controls the first MOS transistor P1 via the first operational amplifier OP1 to generate different bias currents. In this embodiment, the input voltage VIN can be constant or variable.

[0034] In this embodiment, the current control circuit 120 further includes a plurality of first output control MOS transistors (P11 to P1N) connected in parallel. The output end of the first operational amplifier OP1 is connected to the gate of the first output control MOS transistors (P11 to P1N) through the first control switches (S11 to S1N), respectively. By controlling the first control switches, the corresponding first output control MOS transistors are mirrored to output bias currents of corresponding magnitudes.

[0035] In this embodiment, the bias current generating circuit 110 further includes: a second operational amplifier OP2, and a second MOS transistor P2 connected to the output terminal of the second operational amplifier OP2. The source of the second MOS transistor P2 is connected to the drain of the first MOS transistor P1 and the negative input terminal of the second operational amplifier OP2. The drain of the second MOS transistor P2 is connected to the positive input terminal of the first operational amplifier OP1. The positive input terminal of the second operational amplifier OP2 is input with a reference voltage VREF.

[0036] In this embodiment, the bias current output control circuit 130 further includes: a third operational amplifier OP3, and second output control MOS transistors (P21 to P2N) connected to the output end of the third operational amplifier OP3. The third operational amplifier OP3 is connected to the second output control MOS transistors via the second control switches (S21 to S2N), and the output branches are connected to the drains of the second output MOS transistors.

[0037] Furthermore, each of the power amplifier groups is connected to a plurality of power regulation circuits 100 ( Figure 1 Only one power regulating circuit 100 is shown. By connecting multiple power regulating circuits 100, more types of bias current inputs can be selected.

[0038] Furthermore, each of the output branches is respectively connected to one or more power amplifier groups, thereby achieving more bias current input options.

[0039] In this embodiment, the power regulation circuit 100 generates current via a bias current generation circuit, mirrors the selected current output via a current magnitude control circuit, and selects an output branch for output via a bias current output control circuit 130. This accurately provides different bias currents to the power amplifier, enabling the power amplifier to operate in a variety of modes. Furthermore, by connecting different output branches to the bias current input terminals of a power amplifier group, or connecting to multiple power regulation circuits, and by varying the connection methods, a variety of bias current inputs can be implemented.

[0040] The above description is only an embodiment of the present invention. It should be pointed out that those skilled in the art can make improvements without departing from the creative concept of the present invention, but these improvements all fall within the scope of protection of the present invention.

Claims

1. A power amplifier power regulation circuit, characterized in that: include: A bias current generating circuit, a current magnitude control circuit, and a bias current output control circuit; The bias current generating circuit is used to generate a variety of different bias currents, and its output end is connected to the current magnitude control circuit; The current magnitude control circuit includes a plurality of first control switches, and the output end of each first control switch is respectively connected to the bias current output control circuit; The bias current output control circuit includes a plurality of second control switches, and the output end of each second control switch is respectively connected to an output branch; The bias current output control circuit further includes: a third operational amplifier, a second output control MOS transistor connected to the output end of the third operational amplifier, the third operational amplifier is connected to the second output control MOS transistor via the second control switch, and the output branch is connected to the drain of the second output control MOS transistor.

2. The power amplifier power regulation circuit according to claim 1, wherein: The bias current generating circuit includes a first operational amplifier and a first MOS transistor connected to the output end of the first operational amplifier. The input voltage controls the first MOS transistor to generate different bias currents through the first operational amplifier.

3. The power amplifier power regulation circuit according to claim 2, wherein: The current control circuit includes a plurality of first output control MOS transistors connected in parallel. The output ends of the first operational amplifier are respectively connected to the gates of the first output control MOS transistors through the first control switches. By controlling the first control switches, the corresponding first output control MOS transistors are mirrored to output bias currents of corresponding magnitudes.

4. The power amplifier power regulation circuit according to claim 3, wherein: The bias current generating circuit further includes: a second operational amplifier, and a second MOS transistor connected to the output terminal of the second operational amplifier, the source of the second MOS transistor being connected to the drain of the first MOS transistor and the negative input terminal of the second operational amplifier, the drain of the second MOS transistor being connected to the positive input terminal of the first operational amplifier, and the positive input terminal of the second operational amplifier being input with a reference voltage.

5. A power amplifier, comprising a power amplification circuit and a power regulation circuit, characterized in that: The power regulation circuit includes: a bias current generating circuit, a current magnitude control circuit, and a bias current output control circuit; The bias current generating circuit is used to generate a variety of different bias currents, and its output end is connected to the current magnitude control circuit; The current magnitude control circuit includes a plurality of first control switches, and the output end of each first control switch is respectively connected to the bias current output control circuit; The bias current output control circuit includes a plurality of second control switches, and the output end of each second control switch is respectively connected to an output branch; The power amplifier circuit includes a plurality of power amplifier groups, wherein the bias current input terminal of each power amplifier group is connected to one or more of the output branches; The bias current output control circuit further includes: a third operational amplifier, a second output control MOS transistor connected to the output end of the third operational amplifier, the third operational amplifier is connected to the second output control MOS transistor via the second control switch, and the output branch is connected to the drain of the second output control MOS transistor.

6. The power amplifier according to claim 5, wherein: The bias current generating circuit includes a first operational amplifier and a first MOS transistor connected to the output end of the first operational amplifier. The input voltage controls the first MOS transistor through the first operational amplifier to generate different bias currents. The current magnitude control circuit includes a plurality of first output control MOS transistors connected in parallel. The output ends of the first operational amplifier are respectively connected to the gates of the first output control MOS transistors through the first control switches. By controlling the first control switches, the corresponding first output control MOS transistors are mirrored to output bias currents of corresponding magnitudes.

7. The power amplifier according to claim 6, wherein: The bias current generating circuit further includes: a second operational amplifier, and a second MOS transistor connected to the output terminal of the second operational amplifier, the source of the second MOS transistor being connected to the drain of the first MOS transistor and the negative input terminal of the second operational amplifier, the drain of the second MOS transistor being connected to the positive input terminal of the first operational amplifier, and the positive input terminal of the second operational amplifier being input with a reference voltage.

8. The power amplifier according to claim 5, wherein: Each of the power amplifier groups is connected to a plurality of power regulation circuits; Alternatively, each of the output branches is connected to one or more of the power amplifier groups.

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