Coordinating error correction

Abstract

This topic relates to coordinating error correction. A memory device may, for example, indicate to an external device that an error has been detected in data stored by the memory device and requested by the external device, based on a comparison between an error correction code stored when the data is written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of whether the compared error correction codes match or based on the match can be provided to the external device. The external device can use the indication to detect errors in a received version of the data or to manage data storage in the memory device, or both, and other operations.

Description

[0001] Cross-references

[0002] This patent application claims priority to PCT / US2020 / 044034, filed July 29, 2020, entitled "Coordinated Error Correction," by Schaefer et al., which also claims priority to U.S. Patent Application No. 16 / 940,783, filed July 28, 2020, entitled "Coordinated Error Correction," and U.S. Provisional Patent Application No. 62 / 885,925, filed August 13, 2019, entitled "Coordinated Error Correction," each of which is assigned to the assignee and each of which is expressly incorporated herein by reference. Technical Field

[0003] This technical field relates to coordination error protection. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, frequently represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM, on the other hand, may lose its stored state when disconnected from external power.

[0006] In some cases, data stored in a memory device may become corrupted. Some memory devices are configured to detect or correct such data corruption or errors (e.g., data errors) internally, and thus recover data stored before the corruption. Summary of the Invention

[0007] A method is disclosed herein. The method may include: receiving a read command from a host device at a memory device including a memory array; reading a dataset from the memory array at least in part based on the read command; changing the values ​​of bits in the dataset at least in part based on performing an error correction procedure on the dataset to obtain a modified dataset; and transmitting the modified dataset and an indication of the change to the host device.

[0008] A method is disclosed herein. The method may include: transmitting a read command to a memory device; receiving from the memory device a dataset associated with the read command and an indication that the memory device attempts to correct a first error associated with the dataset; performing an error correction procedure on a payload contained in the dataset; determining a second error associated with the payload based at least in part on the error correction procedure for the payload; and discarding the dataset received from the memory device based at least in part on the second error and the indication.

[0009] This document discloses an apparatus. The apparatus may include: a memory array; error correction logic coupled to the memory array and configured to: generate a first error correction code for a dataset read from the memory array; identify errors in the dataset read from the memory array based at least in part on the first error correction code and a second error correction code obtained from the memory array; and attempt to correct the errors; an indication component coupled to the error correction logic and configured to generate an indication of attempting to correct the errors; and an output component configured to output the indication to a host device of the apparatus.

[0010] A method is disclosed herein. The method may include: receiving a read command from a host device at a memory device including a memory array; reading a dataset from the memory array at least in part based on the read command; identifying errors contained in the dataset read from the memory array; attempting to correct the errors at least in part based on generating the modified dataset; and transmitting the modified dataset and an indication of attempting to correct the errors to the host device. Attached Figure Description

[0011] Figure 1 Examples of coordinated error correction systems as disclosed in this document are illustrated.

[0012] Figure 2 Examples of memory dies with coordinated error correction as disclosed herein are illustrated.

[0013] Figure 3 This document describes an example of a checker matching checker that supports coordinated error correction, as disclosed herein.

[0014] Figure 4A and 4B An exemplary error indication circuit that supports coordinated error correction, as disclosed herein, is described.

[0015] Figure 5 Examples of memory systems that support coordinated error correction, as disclosed herein, are illustrated.

[0016] Figure 6 A block diagram illustrating a memory array that supports coordinated error correction according to aspects of this disclosure.

[0017] Figure 7 A block diagram illustrating a host device supporting coordinated error correction according to aspects of this disclosure.

[0018] Figures 8 to 10 The flowchart illustrates one or more methods for supporting coordinated error correction based on examples disclosed herein. Detailed Implementation

[0019] Memory devices can operate as part of electronic devices under various conditions, such as personal computers, wireless communication devices, servers, Internet of Things (IoT) devices, and electronic components of motor vehicles. In some cases, memory devices supporting applications (e.g., motor vehicles, in some cases having autonomous or semi-autonomous driving capabilities) may be subject to increased reliability constraints. Therefore, memory devices (e.g., DRAM) used in some applications are expected to operate with reliability subject to relatively high industry standards or specifications (e.g., higher reliability constraints).

[0020] In some cases, memory devices may use error detection / correction techniques to increase the reliability of the stored data. Some error detection / correction techniques used in memory devices include Single Bit Error (SBE) Correction (SEC), Double Bit Error (DBE) Detection (DED), and SECDED. In some cases, external devices that store data in memory devices (e.g., host devices) may also use internal error detection / correction techniques to verify the reliability of data received from the memory.

[0021] In some cases, the error detection / correction techniques used at the memory device differ from those used at the host device. For example, host devices operating in safety-critical environments (e.g., automotive, aviation, etc.) may use more robust error detection / correction techniques than memory devices. In some situations, using different error detection / correction techniques at the host and memory devices can lead to additional errors. For instance, if a memory device applies SECDED to requested data containing two or more bit errors, the memory device may improperly flip the correct bits of the requested data, increasing the number of bit errors from two to three. Therefore, when the memory device transmits data with three bit errors, a host device using SECDED may fail to detect and / or correctly identify the bit errors in the received data, whereas the host device would have been able to detect the two initial bit errors.

[0022] Therefore, more generally, when there are more errors in the data set read from the memory device than the on-die ECC scheme at the memory device can properly handle (e.g., detect and / or correct), the on-die ECC scheme can introduce one or more additional errors, which can result in a dataset (when sent to the host device) containing a larger total number of errors than the host-based ECC scheme can properly handle (in some cases where the host-based ECC will already be able to properly handle the initial number of errors (before the on-die ECC scheme is applied to the data)).

[0023] According to the techniques described herein, to increase the reliability of data transfer between a memory device and a host device, the memory device may indicate to the host device when it detects an error contained in or otherwise associated with the requested data (e.g., an error in the data, an error in the parity bit associated with the data). By receiving an indication that an error was detected at the memory device, the host device can avoid using data containing a number of errors that would otherwise exceed the capabilities of the techniques used by the host device; for example, a host device using SECDED technology can avoid using data containing three errors. Furthermore, the host device can take subsequent actions based on whether an error was detected in the requested data. For example, the host device can prevent the memory device from storing data in certain memory locations that continuously store corrupted data. In other instances, if the memory device indicates that no error was detected in the requested data, the host device can avoid performing error detection, thereby improving the efficiency of the host device. In other instances, the memory location can be used to perform a target “scrubbing” procedure during which data stored in pages associated with previously identified data errors (e.g., since or since the last scrubbing procedure) is read and rewritten in a corrected (via ECC on the die) version of the stored data, and pages not associated with such previously identified data errors are skipped during the scrubbing procedure.

[0024] The features of this disclosure are initially described in the context of a memory system. The features of this disclosure are further described below in the context of a checksum matching checker supporting coordinated error correction and a memory subsystem. These and other features of this disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flowcharts relating to coordinated error correction.

[0025] Figure 1 This describes an example of a system 100 utilizing one or more memory devices, as disclosed herein. System 100 may include an external memory controller 105, a memory device 110, and multiple channels 115 coupling the external memory controller 105 to the memory device 110. System 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0026] System 100 may include aspects of an electronic device, such as a computing device, mobile computing device, wireless device, or graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, Internet-connected device, etc. Memory device 110 may be a component of a system configured to store data for one or more other components of system 100. In some instances, system 100 is configured for bidirectional wireless communication with other systems or devices using a base station or access point. In some instances, system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0027] At least some portions of system 100 may be instances of host devices. Such host devices may be instances of devices that use memory to execute processes, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, or other fixed or portable electronic devices. In some cases, a host device may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device. In some instances, system 100 is a graphics card.

[0028] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses / spaces that system 100 may use or reference. In some instances, memory device 110 may be configured to work with at least one or more different types of system 100. Signaling between components of system 100 and memory device 110 can be used to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packages of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0029] Memory device 110 may be configured to store data for components of system 100. In some cases, memory device 110 may act as a slave device to system 100 (e.g., responding to and executing commands provided by system 100 via external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (e.g., memory chips) supporting a desired or specified capacity for data storage. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or package (also known as a multi-chip memory or package).

[0030] System 100 may further include processor 120, basic input / output system (BIOS) component 125, one or more peripheral components 130, and input / output (I / O) controller 135. The components of system 100 may be electrically connected to each other via bus 140.

[0031] Processor 120 may be configured as at least some part of control system 100. Processor 120 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination of these types of components. In such cases, processor 120 may be an instance of central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances.

[0032] BIOS component 125 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100. BIOS component 125 may also manage data flow between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0033] Peripheral component 130 can be any input or output device, or an interface to such a device, which can be integrated into or with system 100. Examples may include a disk controller, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, serial or parallel port, or peripheral card slot, such as Peripheral Component Interconnect (PCI) or dedicated graphics port. Peripheral component 130 can be any other component that a person skilled in the art would understand as a peripheral device.

[0034] I / O controller 135 manages data communication between processor 120 and peripheral components 130, input devices 145, or output devices 150. I / O controller 135 can manage peripheral devices that are not integrated into system 100 or are not integrated with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0035] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or can be managed by I / O controller 135.

[0036] Output 150 may represent a device or signal external to system 100, configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, audio speaker, printing device, or another processor on a printed circuit board. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or can be managed by I / O controller 135.

[0037] The components of system 100 may consist of general-purpose or special-purpose circuit systems designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive components.

[0038] Memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., a grid), wherein each memory cell is configured to store at least one bit of digital data. Reference Figure 2 The characteristics of memory array 170 and / or memory cells are described in more detail.

[0039] Memory device 110 may be an example of a two-dimensional (2D) memory cell array or a three-dimensional (3D) memory cell array. For example, a 2D memory device may comprise a single memory die 160. A 3D memory device may comprise two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked one on top of the other or adjacent to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, hierarchy, layer, or die. A 3D memory device may comprise any number of stacked memory dies 160-N (e.g., two highs, three highs, four highs, five highs, six highs, seven highs, eight highs). This increases the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn can reduce manufacturing costs or improve the performance of the memory array, or both. In some 3D memory devices, different stacks may share at least one common access line, such that some stacks may share at least one of word lines, digital lines and / or board lines.

[0040] Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. Therefore, device memory controller 155 may include hardware, firmware, and software that enables memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information associated with memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and / or commands from external memory controller 105. For example, memory device 110 may receive a write command instructing memory device 110 to store certain data on behalf of a component of system 100 (e.g., processor 120), or a read command instructing memory device 110 to provide certain data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 may be combined with a local memory controller 165 of memory die 160 to control the operation of memory device 110 as described herein. Examples of components included in the device memory controller 155 and / or local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, amplifiers, filters, etc.

[0041] A local memory controller 165 (e.g., local to memory die 160) may be configured to control the operation of memory die 160. Furthermore, the local memory controller 165 may be configured to communicate with device memory controller 155 (e.g., to receive and transmit data and / or commands). The local memory controller 165 may support device memory controller 155 in controlling the operation of memory device 110 as described herein. In some cases, memory device 110 may not include device memory controller 155, and either local memory controller 165 or external memory controller 105 may perform the various functions described herein. Therefore, the local memory controller 165 may be configured to communicate with device memory controller 155, communicate with other local memory controllers 165, or communicate directly with external memory controller 105 or processor 120.

[0042] External memory controller 105 may be configured to facilitate the transfer of information, data, and / or commands between components of system 100 (e.g., processor 120) and memory device 110. External memory controller 105 may act as a communication link between components of system 100 and memory device 110, allowing components of system 100 to operate without needing to know the operational details of the memory device. Components of system 100 may present requests (e.g., read or write commands) to external memory controller 105 that external memory controller 105 may fulfill. External memory controller 105 may translate or interpret communications exchanged between components of system 100 and memory device 110. In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0043] In some cases, the external memory controller 105 or another component of system 100, or its functionality as described herein, may be implemented by processor 120. For example, external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by processor 120 or another component of system 100. Although external memory controller 105 is depicted as being external to memory device 110, in some cases, external memory controller 105, or its functionality as described herein, may be implemented by memory device 110. For example, external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by device memory controller 155 or one or more local memory controllers 165. In some cases, external memory controller 105 may be distributed across processor 120 and memory device 110, such that portions of external memory controller 105 are implemented by processor 120, and other portions are implemented by device memory controller 155 or local memory controller 165. Similarly, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may be performed by the external memory controller 105 (separate from or included in the processor 120).

[0044] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some instances, channels 115 facilitate communication between external memory controller 105 and memory device 110. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal comprising one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. Pins may be instances of conductive input or output points of devices of system 100, and pins may be configured to act as part of a channel.

[0045] In some cases, the pins or pads of the terminals may be part of the signal path of channel 115. Additional signal paths may be coupled to the terminals of the channel to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths within memory device 110 or its components, such as signal paths within memory die 160) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0046] Channel 115 (and associated signal paths and terminals) can be dedicated to transmitting a specific type of information. In some cases, channel 115 can be an aggregated channel and therefore can contain multiple individual channels. For example, data channel 190 can be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (containing sixteen signal paths), etc. Signals transmitted via the channel can use dual data rate (DDR) signaling. For example, some symbols of the signal can be recorded on the rising edge of the clock signal, and other symbols of the signal can be recorded on the falling edge of the clock signal. Signals transmitted via the channel can use single data rate (SDR) signaling. For example, one symbol of the signal can be recorded for each clock cycle.

[0047] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, CA channel 186 may contain a read command for the address of desired data. In some cases, CA channel 186 may be recorded on the rising and / or falling clock edges. In some cases, CA channel 186 may contain any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0048] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between high and low states and coordinate the operation of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., CK_t and CK_c signals), and the signal paths of CK channel 188 may be configured accordingly. In some cases, the clock signals may be single-ended. CK channel 188 may contain any number of signal paths. In some cases, clock signals CK (e.g., CK_t and CK_c signals) may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Clock signals CK may therefore be referred to differently as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK can be generated by the system clock, which may include one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0049] In some cases, channel 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transmit information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110. In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may contain any number of signal paths.

[0050] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. While the 'W' in WCK nominally stands for "write," the write clock signals WCK (e.g., WCK_t and WCK_c signals) provide a timing reference generally used for access operations of memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to transmit a common data clock signal between external memory controller 105 and memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write or read operations) of external memory controller 105 and memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t and WCK_c signals), and the signal paths of the WCK channel may be configured accordingly. The WCK channel may contain any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (e.g., an oscillator, crystal, logic gate, transistor, etc.).

[0051] In some cases, one of the other channels 192 may be configured to carry an indicator of detected and / or corrected errors associated with the data of the read operation or another activity of the ECC system within the memory device 110. In some cases, such an indicator may be carried by one or more other channels 115 (e.g., one or more DQ channels 190 or CA channels 186). The memory device 110 may perform an error detection operation on the data read from the memory array 170. The error detection operation may detect single-bit errors, double-bit errors, and errors affecting more than two bits. The memory device 110 may use parity information to perform an error detection procedure to detect and / or correct errors within the data retrieved from the memory array 170 during a read operation. In some cases, the memory device 110 may associate each bit of the data read during a read operation with two or more bits of parity information. For example, the memory device 110 may use two or more sets of parity bits to detect errors within a matrix of data. Each set of parity bits may correspond to a dimension of the data matrix. Therefore, each bit of data within the matrix can be associated with two or more parity bits corresponding to the parity dimension. The memory device 110 can output an indicator of detected and / or corrected errors via another channel 192. The indicator may include a flag indicating the detected error. Alternatively, the indicator may include an indication of the type of error detected or corrected within the data read from the memory array 170. In another case, the indicator may be transmitted via the DQ channel 190.

[0052] In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels can be configured to transmit error detection signals, such as checksums, to improve system reliability. EDC channels can contain any number of signal paths.

[0053] Channel 115 can use various architectures to couple external memory controller 105 to memory device 110. Examples of various architectures may include buses, point-to-point connections, cross switches, high-density in-cell modules such as silicon in-cell modules, or channels formed in an organic substrate, or combinations thereof. For example, in some cases, the signal path may at least partially contain high-density in-cell modules, such as silicon in-cell modules or glass in-cell modules.

[0054] Various modulation schemes can be used to modulate the signals transmitted on channel 115. In some cases, binary symbol (or binary hierarchy) modulation schemes can be used to modulate the signals transmitted between external memory controller 105 and memory device 110. A binary symbol modulation scheme can be an example of an M-ary modulation scheme where M equals two. Each symbol in a binary symbol modulation scheme can be configured to represent one bit of digital data (e.g., a symbol can represent logic 1 or logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), single-pole coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and so on.

[0055] In some cases, multi-symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between external memory controller 105 and memory device 110. A multi-symbol modulation scheme can be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of a multi-symbol modulation scheme can be configured to represent more than one bit of digital data (e.g., a symbol can represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal or a PAM4 signal can be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols are alternatively referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0056] Memory device 110 may support an internal (e.g., on-die) ECC scheme configured to detect and, in at least some cases, correct errors in data read from memory array 170. Furthermore, memory device 110 may indicate to external memory controller 105 when the ECC scheme at memory device 110 has detected an error associated with the dataset (e.g., by sending signaling conveying the indication simultaneously with sending the dataset, or by storing the indication so that external memory controller 105 may later poll memory device 110 for the indication or memory device 110 may later include the indication in an error report).

[0057] Figure 2 This describes an example of a memory die 200 as disclosed herein. The memory die 200 may be a reference. Figure 1An example of the described memory die 160. In some cases, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0058] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing a programmable state. Other memory devices and components are also possible in other memory architectures. For example, a nonlinear dielectric material may be used.

[0059] Operations such as reading and writing can be performed on memory cells 205 by activating or selecting access lines such as word lines 210 and / or digital lines 215. In some cases, digital line 215 may also be referred to as a bit line. References to access lines, word lines, and digital lines or the like are interchangeable without affecting understanding or operation. Activating or selecting word line 210 or bit line 215 may involve applying a voltage to the respective line.

[0060] The memory die 200 may include access lines (e.g., word lines 210 and digital lines 215) arranged in a grid pattern. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215. A single memory cell 205 can be accessed at its intersection by biasing word lines 210 and digital lines 215 (e.g., by applying a voltage to word lines 210 or digital lines 215).

[0061] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 260 and activate word lines 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 260 and activate digital lines 215 based on the received column addresses. For example, memory die 200 may contain multiple word lines 210 labeled WL_1 to WL_M and multiple digital lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Therefore, by activating word lines 210 and digital lines 215, such as WL_1 and DL_3, memory cell 205 at their intersection can be accessed. The intersection point of word lines 210 and digital lines 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205.

[0062] Memory cell 205 may include logic storage components, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell board reference voltage, such as Vpl, or may be grounded, such as Vss. In some cases, voltage source 240 may be an example of a board line coupled to a board line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes an electronic connection between two components.

[0063] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 235. Capacitor 230 can be electrically connected to digital line 215 using switch assembly 235. For example, when deactivating switch assembly 235, capacitor 230 can be isolated from digital line 215, and when activating switch assembly 235, capacitor 230 can be coupled to digital line 215. In some cases, switch assembly 235 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the transistor's threshold voltage. In some cases, switch assembly 235 can be a p-type transistor or an n-type transistor. Word line 210 can be electrically connected to the gate of switch assembly 235, and switch assembly 235 can be activated / deactivated based on the voltage applied to word line 210.

[0064] Word line 210 may be a conductive line electrically connected to memory cell 205 for performing access operations on memory cell 205. In some architectures, word line 210 may be electrically connected to the gate of switching component 235 of memory cell 205 and may be configured to control the switching component 235 of memory cell 205. In some architectures, word line 210 may be electrically connected to the node of capacitor in memory cell 205, and memory cell 205 may not include a switching component.

[0065] Digital line 215 may be a conductive line connecting memory cell 205 and sensing component 245. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 235 of memory cell 205 may be configured to couple and / or isolate capacitor 230 of memory cell 205 from digital line 215. In some architectures, memory cell 205 may be electrically connected (e.g., constantly) to digital line 215.

[0066] Sensing component 245 may be configured to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. In some cases, the charge stored by memory cell 205 may be extremely small. Therefore, sensing component 245 may include one or more sensing amplifiers to amplify the signal output by memory cell 205. The sensing amplifier may detect small changes in charge on digital line 215 during a read operation and may generate a signal corresponding to logic state 0 or logic state 1 based on the detected charge. During a read operation, capacitor 230 of memory cell 205 may output a signal (e.g., release charge) to its corresponding digital line 215. The signal may change the voltage of digital line 215. Sensing component 245 may be configured to compare the signal received from memory cell 205 across digital line 215 with a reference signal 250 (e.g., a reference voltage). Sensing component 245 may determine the stored state of memory cell 205 based on the comparison. For example, in binary signaling, if digital line 215 has a higher voltage than reference signal 250, then sensing component 245 can determine that the stored state of memory cell 205 is logic 1, and if digital line 215 has a lower voltage than reference signal 250, then sensing component 245 can determine that the stored state of memory cell 205 is logic 0.

[0067] Sensing component 245 may include various transistors or amplifiers to detect and amplify differences in the signal. The detected logic state of memory cell 205 can be output via I / O 255 ​​through ECC block 265. ECC block 265 can perform error correction operations on the detected logic state of memory cell 205 and output data (e.g., stored data or corrected data) via I / O 255. In some other cases, the detected logic state of memory cell 205 may bypass ECC block 265 and be output via I / O 255. In some cases, the detected logic state of memory cell 205 may be output to both ECC block 265 and I / O 255. Here, while ECC block 265 performs error correction operations on the detected logic state of memory cell 205, the detected logic state of memory cell 205 may be output from memory die 200 via I / O 255. In some cases, sensing component 245 may be part of another component (e.g., column decoder 225, row decoder 220). In some cases, the sensing component 245 may be electronically connected to the row decoder 220 or the column decoder 225.

[0068] The local memory controller 260 can control the operation of the memory cell 205 via various components (e.g., row decoder 220, column decoder 225, sensing component 245, and ECC block 265). The local memory controller 260 can be a reference... Figure 1 An example of a local memory controller 165 is described. In some cases, one or more of the row decoder 220, column decoder 225, sensing component 245, and ECC block 265 may be located in the same location as the local memory controller 260. The local memory controller 260 may be configured to receive signals from an external memory controller 105 (or reference 105). Figure 1 The described device memory controller 155 receives commands and / or data, translates the commands and / or data into information usable by the memory die 200, performs one or more operations on the memory die 200, and transfers data from the memory die 200 to an external memory controller 105 (or device memory controller 155) in response to performing one or more operations. The local memory controller 260 can generate row and column address signals to activate target word lines 210 and target digital lines 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current described herein may be adjusted or varied, and may differ for the various operations described in operating the memory die 200.

[0069] In some cases, the local memory controller 260 may be configured to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cell 205 to which the write operation will be performed. The local memory controller 260 may identify a target word line 210 and a target digital line 215 (e.g., the address of the target memory cell 205) that are electrically connected to the target memory cell 205. The local memory controller 260 may activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. The local memory controller 260 may apply a specific signal (e.g., voltage) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205, the specific state (e.g., charge) indicating a desired logic state.

[0070] During a write operation, ECC block 265 or local memory controller 260 may generate error detection or correction information. For example, as part of a write operation, ECC block 265 may receive data from a host device. ECC block 265 may determine or generate error detection or correction information associated with the data. In some cases, ECC block 265 may contain error detection logic or may cause error detection logic (not shown) to perform the error detection operations described herein. ECC block 265 may store data and error detection or correction information in one or more memory cells 205 as part of a write operation. The type of error detection or correction information generated by ECC block 265 may correspond to the type of error detection operation performed by ECC block 265. For example, if ECC block 265 performs a SEC or SECDED error detection operation, then ECC block 265 may generate a SEC or SECDED codeword as part of the write operation. The SEC or SECDED codeword may correspond to error detection information used by ECC block 265 to detect and / or correct errors within the data when performing the SEC or SECDED error detection operation respectively. Alternatively, if ECC block 265 performs an error detection operation based on the parity bit, then ECC block 265 may generate the parity bit as part of the write operation.

[0071] In some cases, the local memory controller 260 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cell 205 to which the read operation will be performed. The local memory controller 260 may identify a target word line 210 and a target digital line 215 (e.g., the address of the target memory cell 205) that are electrically connected to the target memory cell 205. The local memory controller 260 may activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 245 in response to a bias access line. The sensing component 245 may amplify the signal. The local memory controller 260 may activate the sensing component 245 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 250. Based on the comparison, the sensing component 245 may determine the logical state stored in the memory cell 205. As part of a read operation, the local memory controller 260 may transmit the logical state stored in the memory cell 205 to the external memory controller 105 (or the device memory controller 155).

[0072] During a read operation, ECC block 265 can retrieve data and associated error detection or correction information from the array of memory cells 205. ECC block 265 can perform error correction operations based on the data and error detection or correction information. Performing error correction operations at the memory device (e.g., by ECC block 265 or local memory controller 260) improves the reliability of the memory device. ECC block 265 can be configured to perform a single type of error detection operation (e.g., SEC or SECDED error detection operation, parity bit-based error detection operation), or can be configured to perform a combination of error detection operations (e.g., parity bit-based error detection operation and SEC or SECDED error detection operation).

[0073] In some memory architectures, accessing memory cell 205 can degrade or destroy the logic state stored in memory cell 205. For example, a read operation performed in a DRAM architecture can partially or completely discharge the capacitor of the target memory cell. Local memory controller 260 can perform a rewrite or refresh operation to restore the memory cell to its initial logic state. Local memory controller 260 can rewrite the logic state to the target memory cell after a read operation. In some cases, a rewrite operation can be considered part of a read operation. Additionally, activating a single access line (e.g., word line 210) can interfere with the state stored in some memory cells electrically connected to said access line. Therefore, a rewrite or refresh operation can be performed on one or more memory cells that may not have been accessed yet.

[0074] Figure 3 This document describes an example of a checker matching checker that supports coordinated error correction, as disclosed herein.

[0075] The parity checker 300 may be configured to determine and indicate whether an on-die ECC component (e.g., error correction / detection circuitry 330) has detected an error associated with data stored in the memory array (e.g., an error in the data or an error in the parity bit associated with the data). The parity checker 300 may include error correction / detection circuitry 330 and error indication circuitry 335.

[0076] Error correction / detection circuit 330 can be configured to detect errors in data stored in a memory cell. Error correction / detection circuit 330 can also be configured to correct errors in the data by toggling identified corrupted data bits (e.g., changing a corrupted data bit from "1" to "0" and vice versa). In some cases, error correction / detection circuit 330 can be configured to detect single-bit errors (SBE) in the requested data and correct single-bit errors in the requested data, for example, error correction / detection circuit 330 can be configured to use SEC technology. In other cases, error correction / detection circuit 330 can be configured to detect double-bit errors (DBE) and correct single-bit errors in the requested data, for example, error correction / detection circuit 330 can be configured to use SECDED technology. In still other cases, error correction / detection circuit 330 can be configured to detect triple-bit errors (TBE). These are examples, and error correction / detection circuit 330 can be configured to detect up to any first number of errors and correct up to any second number of errors (the second number may be different from or the same as the first number). Error correction / detection circuitry 330 may be further configured to provide the altered data (e.g., “corrected” data) to an external device. It should be understood that the techniques described herein can be applied to ECC schemes configured to detect and / or correct any number of errors, and any specific number used herein is for illustrative purposes only and is not limiting.

[0077] Error correction / detection circuit 330 may include storage check sub-circuit 305, access check sub-circuit 310, and matching circuit 315. When error correction / detection circuit 330 is configured to detect two-bit errors, storage check sub-circuit 305, access check sub-circuit 310, and matching circuit 315 may each be configured to output additional check bits relative to when they are configured to implement the SEC scheme.

[0078] The storage check sub-circuit 305 can be configured to generate error correction codes for data after storing data within the memory array. In some cases, the error correction codes generated by the storage check sub-circuit 305 may be referred to as "stored error correction codes" or "stored codewords".

[0079] Access check subcircuit 310 can be configured to generate another error correction code when reading data from the memory array (e.g., when an external device requests data stored in the memory array). The error correction code generated by access check subcircuit 310 may be referred to as a "computed error correction code" or "computed codeword". In some cases, access check subcircuit 310 may use the same algorithm as storage check subcircuit 305 to generate the computed error correction code.

[0080] The matching circuit 315 can be configured to compare the stored error correction code with the calculated error correction code. In some cases, the matching circuit 315 can compare the stored and calculated error correction codes by performing an XOR operation on corresponding bits of the stored and calculated error correction codes. If every bit of the stored and calculated error correction codes is the same, for example, if the stored and calculated error correction codes match, then the matching circuit 315 can output all zeros (e.g., ...). Figure 3 (As shown in the diagram). Otherwise, if the stored and calculated error correction codes do not match, the matching circuit 315 may output one or more non-zero values.

[0081] In some cases, the matching circuit 315 can also be configured to output the position of the damaged bit in the data set or associated with the stored error correction code based on a comparison between the stored error correction code and the calculated error correction code. For example, when the matching circuit 315 outputs a non-zero value, all outputs of the matching circuit can be used to represent the position of the damaged bit in the stored codeword; for example, the outputs of the matching circuit 315 can represent up to 2^8 different bit positions.

[0082] Error indication circuit 335 may be configured to indicate whether error correction / detection circuit 330 has detected an error in or otherwise associated with data requested from the memory array. Error indication circuit 335 may include logic circuitry 320 and memory error line 325.

[0083] Logic circuit 320 can be configured to determine whether matching circuit 315 outputs any (or a certain other threshold number) non-zero values. In some cases, logic circuit 320 determines whether matching circuit 315 outputs one or more non-zero values ​​based on analysis of each bit output by matching circuit 315. That is, logic circuit 320 can perform one or more OR operations on all bits output by matching circuit 315. In these cases, if the output of matching circuit 315 contains all zeros, then logic circuit 320 can output a first signal (e.g., a virtual ground voltage) indicating a match (or "match signal"). And if the output of matching circuit 315 contains one or more non-zero values, then logic circuit 320 can output a second signal (e.g., a power supply voltage) indicating a mismatch (or "mismatch signal").

[0084] In some cases, when the matching circuit 315 outputs a zero value indicating a match (which can be represented by a virtual ground supply voltage), the logic circuit 320 outputs a Boolean "false". And if the output of the matching circuit contains at least one non-zero value, then in the case of the matching circuit 315, the logic circuit 320 outputs a Boolean "true", thus indicating a mismatch.

[0085] In other cases, if the output of the matching circuit 315 contains all zeros or fewer than a certain threshold number of non-zero values ​​(e.g., a single non-zero value), then the logic circuit 320 outputs "false," indicating a match or substantially a match. In some cases, only one or fewer than a certain threshold number of non-zero values ​​may indicate an error in the ECC bit and no error in the stored data. And if the output of the matching circuit 315 contains a number of non-zero values ​​that meet a threshold (e.g., two or more), then the logic circuit 320 outputs "true," indicating a mismatch. In some cases, the error correction / detection circuit 330 may rewrite the stored error correction code using the calculated error correction code after recognizing that the matching circuit 315 outputs only one non-zero value and the corresponding data can be transmitted to the device requesting the data.

[0086] The output of logic circuit 320 may be signaled via memory error line 325. In some cases, the output of logic circuit 320 is signaled via memory error line 325 as a "memory parity flag". In some cases, the memory parity flag is included in the data stream, for example, appended to the requested data. In some cases, the memory parity flag is signaled via a dedicated pin (e.g., simultaneously with the data stream signaled via one or more other pins (meaning at least partially overlapping in time)).

[0087] In some cases, latch 340 may be configured to store the output of logic circuitry 320 as a memory check flag, which may be accessed by an external device. In some cases, the data stored in the latch is accessed upon request by an external device (e.g., polling). In other cases, the data stored in the latch is provided to an external device during some error reporting procedure. In some cases, the output of logic circuitry 320 may be stored in latch 340 instead of being signaled to an external device via memory error line 325.

[0088] In some cases, the error indication circuit 335 may be further configured to store a memory address associated with the error (corrected data). The error indication circuit 335 may output the stored memory address alone or in combination with a memory check flag via the memory error line 325. In some cases, the indicated stored memory address is doubled to the memory check flag, for example, an external device may determine to detect and / or correct an error at the error correction / detection circuit 330 based on receiving a non-zero value via the memory error line 325. In some cases, the stored address is an actual address (or "physical address") in the memory array. In other cases, the stored address is an address different from the physical address, but is an address (or "logical address") used by an external device to access data in the memory array.

[0089] In some instances, when an ECC scheme supported by error correction / detection circuitry 330 is overpowered by data containing more bit errors than the maximum number that the ECC scheme can detect or correct, error correction / detection circuitry 330 may inappropriately alias (e.g., flip or otherwise alter) bits with correct values, or otherwise introduce or fail to correct errors in the data set read from the memory array. For example, when error correction / detection circuitry 330 is configured with an SEC scheme, error correction / detection circuitry 330 may detect unit errors in requested data that actually contain two or more bit errors. In these cases, error correction / detection circuitry 330 may fail to attempt to correct the detected errors by flipping undamaged bits in the requested data at the bit location indicated by matching circuitry 315 (e.g., turning a two-bit error into a three-bit error) (this type of operation may be referred to as "aliasing"). In some cases, error correction / detection circuitry 330 may provide the altered data to an external device requesting the data.

[0090] When the error correction / detection circuit 330 causes aliasing in data requested from the device, it prevents the external device from detecting errors in the requested data that have already been detected by the external device in other ways. For example, an external device using a SECDED scheme that has detected a two-bit error in the requested data may not reliably detect a three-bit error in the requested data caused by the error correction / detection circuit 330. By using the error indication circuit 335 to identify and signal the error correction / detection circuit 330 that detects and attempts to correct errors, the external device can determine whether the memory device has detected an error, attempted to correct the error, or otherwise may have caused aliasing due to the attempted correction by the error correction / detection circuit 330, as described herein and relative to... Figure 5 To elaborate further.

[0091] Figure 4A An exemplary error indication circuit that supports coordinated error correction, as disclosed herein, is described.

[0092] Error indicator circuit 400-a can be Figure 3 An example of an error indication circuit 335 is provided, and similarly configured, to signal when an error detection circuit detects and / or corrects an error in the requested data. Error indication circuit 400-a may include logic circuitry 405-a and a memory error line 410-a.

[0093] The 405-a logic circuit can be Figure 3An example of logic circuit 320 is provided, and similarly configured, to determine whether the matching circuit has identified a match between the stored and computed error correction codes. As shown in Table 1, logic circuit 405 may include a series of OR gates (or “OR tree”) that output a first voltage signal (e.g., a virtual ground voltage or “0”) when all inputs S0 to S7 are zero (e.g., in the case of a match between the stored and computed error correction codes). When any of inputs S0 to S7 is non-zero (e.g., in the case of a mismatch between the stored and computed error correction codes), logic circuit 405 may also output a complementary voltage signal (e.g., a supply voltage or “1”).

[0094] Match output (state) Logic circuit output All zeros (match) low voltage Non-zero (mismatch) High voltage

[0095] Table 1

[0096] Memory error line 410-a can be Figure 3 An example of a memory error line, and similarly configured as such, is used to deliver the output of the logic circuitry to other components, such as external devices. Memory error line 410-a can be used to deliver the output of logic circuitry 405-a. In some cases, the voltage of memory error line 410-a is sent directly to the external device as a memory check flag. That is, when the voltage of memory error line 410-a rises or falls, the external device can immediately notify the error correction / detection circuitry that an error has been detected. In other cases, the voltage of memory error line 410-a can be written to a register in the memory device. In these cases, the external device can poll the register or access the register during error reporting mode.

[0097] Figure 4B An exemplary error indication circuit that supports coordinated error correction, as disclosed herein, is described.

[0098] Error indication circuit 400-b can be Figure 3 An example of an error indication circuit 335 is provided, and similarly configured, to signal when an error detection circuit detects and / or corrects errors in the requested data. Error indication circuit 400-b may include decoder 415-b and memory error line 410-b.

[0099] Decoder 415-b can be Figure 3An example of logic circuit 320 is provided, and similarly, for logic circuit 320 to determine whether the matching circuit has identified a match between the stored and computed error correction codes. As shown in Table 2A, decoder 415-b may include a circuit system that produces a Boolean “false” when all inputs S0 to S7 are zero (e.g., when a match exists between the stored and computed error correction codes), and a Boolean “true” when any of inputs S0 to S7 is non-zero (e.g., when a mismatch exists).

[0100] Match output (state) Decoder internal logic Decoder output All zeros (match) Fake low voltage Non-zero value (no match) real High voltage

[0101] Table 2A

[0102] Alternatively, as shown in Table 2B, decoder 415-b may include a circuitry that produces a Boolean “false” if (1) all inputs S0 to S7 are zero or (2) only one of inputs S0 to S7 (or less than a certain other threshold number) is equal to a non-zero value. Decoder 415-b may also produce a Boolean “true” if more than one of inputs S0 to S7 (or at least another threshold number) is non-zero. By using a decoder that produces a Boolean “false” if only a threshold number of inputs S0 to S7 are non-zero, error indication circuitry 400-b may ignore errors occurring in the error correction code but not errors occurring in the requested data, for example, errors isolated by the error correction code may be ignored.

[0103] Match output (state) Decoder internal logic Decoder output All zeros (match) Fake low voltage A non-zero value (almost a match) Fake low voltage Multiple non-zero values ​​(no match) real High voltage

[0104] Table 2B

[0105] If decoder 415-b generates a Bollinger "false", then decoder 415-b can be configured to output a first voltage signal (e.g., a virtual ground voltage or "0"). If decoder 415-b generates a Bollinger "true", then decoder 415-b can be configured to output a complementary voltage signal (e.g., a supply voltage or "1").

[0106] Memory error line 410-b can be Figure 3An example of a memory error line, and similarly configured as such, is used to deliver the output of the logic circuitry to other components, such as external devices. Memory error line 410-b can be used to deliver the output of decoder 415-b. In some cases, the voltage of memory error line 410-b is sent directly to the external device as a memory check flag. That is, when the voltage of memory error line 410-b rises or falls, the external device can immediately notify the error correction / detection circuitry that an error has been detected. In other cases, the voltage of memory error line 410-b can be written to a register in the memory device. In these cases, the external device polls the register or can access the register during error reporting mode.

[0107] Figure 5 Examples of memory systems that support coordinated error correction, as disclosed herein, are illustrated. Memory system 500 includes memory device 505 and host 525.

[0108] Memory device 505 may be configured to store data, for example, memory device 505 may be configured to store application data for host 525. Memory device 505 may include a data bus 510 (e.g., one or more DQ channels 190), a memory parity checker 515, and a memory error line 520. The memory parity checker 515 may be connected to... Figure 3 The checksum matching checker 300 is similarly or identically configured to detect and / or correct errors in the requested data before delivery. The memory checksum matching checker 515 may also be similarly configured to indicate to an external device, such as host 525, that an error has been detected in the requested data and / or the address associated with the requested data.

[0109] Data bus 510 can be configured to deliver data stored in memory device 505 to host parity checker 530. In some cases, data bus 510 can deliver data after receiving a request for data (e.g., a read command) from host 525. In some instances, data bus 510 can deliver the requested data after the requested data has been processed by memory parity checker 515, for example, after the parity checker detects and corrects identified errors in the requested data.

[0110] Memory error line 520 may be configured to deliver an output signal generated by a parity match checker to logic component 540. In some instances, memory error line 520 may deliver a memory parity flag, indicating whether memory parity match checker 515 has detected an error in data requested by host 525 (e.g., by indicating a match or mismatch) and / or the address associated with the requested data. In some cases, memory error line 520 is a conductive trace. In other cases, memory error line 520 is a wireless link.

[0111] The host 525 can be configured to access data stored in the memory device 505 to support the functionality of the application. The host 525 may include a host checksum match checker 530, a channel error line 535, a logic component 540, and a data error line 545.

[0112] The host checksum match checker 530 can be configured to detect errors in data received from the memory device 505 (e.g., data received via the data bus 510) and indicate whether an error has been detected in data received via the channel error line 535. The host checksum match checker 530 can also be configured to correct errors detected in the received data. The host checksum match checker 530 can be coupled with… Figure 3 The checksum matching checker 300 is configured similarly. For example, the host checksum matching checker 530 may support online ECC for the host 525. In some cases, the host checksum matching checker 530 may include initial checksum circuitry that calculates the initial error correction code for the application data before the host 525 writes the application data and initial error correction code to the memory device 505 (e.g., as part of a single data burst, which may alternatively be referred to as a data packet, data packet, or data codeword).

[0113] The host parity checker 530 may further include: an access parity circuit that, after receiving data from the memory device 505, calculates a computed error correction code for the application data (e.g., by parsing the received data burst corresponding to a previously written data burst, parsing the data burst to obtain a first data burst subset corresponding to the previously written application data (payload) and a second data burst subset corresponding to parity information of the first subset (initial error correction code of the payload) previously calculated (generated) by the host 525); a matching circuit that compares the initial and computed error correction codes to determine the presence of an error in the received data; and an error indication circuit that indicates the presence of an error in the received data. In some cases, the error correction / detection circuitry included in the host parity checker 530 may be configured to detect double-bit errors and correct single errors in the received data (e.g., the host parity checker 530 may use SECDED technology), and each of the stored parity circuitry, access parity circuitry, and matching circuitry may be configured to output additional parity bits.

[0114] The channel error line 535 may be configured to deliver an output signal generated by the host checker 530 to the logic component 540. In some instances, the channel error line 535 may deliver a "channel checker flag," which indicates whether the host checker 530 has detected an error in the received version of data requested from the memory device 505. In some cases, the channel error line 535 is a conductive trace.

[0115] Logic component 540 can be configured to determine whether one or both of the host parity match checker 530 or the memory parity match checker 515 have detected an error in the processed dataset. In some cases, if both the memory parity flag and the channel parity flag indicate that an error has been detected, then logic component 540 outputs a multi-bit error flag. For example, when both the memory parity flag and the channel parity flag indicate a mismatch, logic component 540 can output a multi-bit error flag indicating that a multi-bit error has occurred.

[0116] Data error line 545 can be configured to deliver an output signal generated by logic component 540. In some instances, data error line 545 can deliver a multi-bit error flag indicating that requested data stored in memory device 505 contains multiple corrupted bits. In some cases, data error line 545 is a conductive trace. In other cases, data error line 545 is a wireless link.

[0117] In some cases, host 525 uses the outputs of memory parity checker 515, host parity checker 530, and logic component 540 to detect errors (including multi-bit errors) in the received data, as shown in Table 3. Table 3 may correspond to an example where memory device 505 uses SEC technology and host 525 uses SECDED technology.

[0118]

[0119]

[0120] Table 3

[0121] Host 525 may also use the outputs of memory parity checker 515, host parity checker 530, and logic component 540 to manage the processing of data received from memory. In some instances, after receiving an indication from memory parity checker 515 that no errors were detected in the requested data, host 525 may abandon the execution of error detection procedures for the received data. For example, if memory parity checker 515 is operating using the SEC scheme and / or link protection (e.g., CRC or link ECC) to transmit data via the memory channel, and host parity checker 530 is using the SECDED scheme, then host 525 may avoid performing ECC in certain situations, as depicted in Table 4.

[0122]

[0123] Table 4

[0124] In some cases, if the memory check flag indicates that a certain type of error (e.g., SBE) should be corrected, then the host 525 may further avoid performing ECC calculations.

[0125] In another instance, if the memory checker 515 is operating with the SECDED scheme and / or link protection (e.g., CRC or link ECC) to transmit data via the memory channel, and the host checker 530 is using the SECDED scheme, then the host 525 may avoid performing ECC in certain scenarios, as depicted in Table 5.

[0126]

[0127]

[0128] Table 5

[0129] In some cases, if the memory check flag indicates that a certain type of error (e.g., SBE) should be corrected, then the host 525 may further avoid performing ECC calculations.

[0130] Host 525 can also use the outputs of memory parity checker 515, host parity checker 530, and logic component 540 to manage data storage in memory. In some instances, after identifying that data stored in memory device 505 contains multiple bit errors, host 525 can blacklist the memory address associated with the data. That is, host 525 can instruct memory device 505 that application data for host 525 will not be stored at the blacklisted memory address in the memory array of memory device 505.

[0131] Alternatively, host 525 or memory device 505 may use information to perform “intelligent cleanup” of the memory array in memory device 505, which involves periodically reading the contents of the memory array using error correction techniques to perform error correction on the contents of the memory array and rewriting the data identified as corrupted using a corrected version of the data, which may be referred to as “cleanup”. That is, host 525 may trigger memory device 505 (or memory device 505 itself) to clean up (e.g., only) data located at memory addresses that have been identified and / or indicated by memory device 505 as corrupted. During a relevant period of time (e.g., throughout the entire operating history of the device, or since the last cleanup procedure), the cleanup procedure may skip (ignore) pages or other sets of memory cells not associated with the identified errors.

[0132] In some instances, host 525 may not include host checksum matching checker 530; for example, host 525 may not generate a host checksum flag. In these cases, host 525 may use the output of memory checksum matching checker 515 to detect or assist in the detection of errors in received data.

[0133] For example, if the memory checker 515 is operating with SEC scheme and / or link protection (e.g., CRC or link ECC) to transmit data via the memory channel, and the host 525 does not contain a host checker 530, then the host 525 may avoid performing ECC in certain scenarios, as depicted in Table 6.

[0134]

[0135]

[0136] Table 6

[0137] In another instance, if the memory checker 515 is operating with the SECDED scheme and / or link protection (e.g., CRC or link ECC) to transmit data via the memory channel, and the host 525 does not contain a host checker 530, then the host 525 may avoid performing ECC in certain scenarios, as depicted in Table 7.

[0138]

[0139] Table 7

[0140] Figure 6 A block diagram 600 illustrates a memory array 605 supporting coordinated error correction according to an example disclosed herein. The memory array 605 may be as described in the references... Figures 1 to 5 Examples of aspects of the described memory array. Memory array 605 may include command manager 610, read component 615, error correction component 620, data transfer unit 625, matching component 630, error indication component 635, and data manager 640. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0141] Command manager 610 can receive read commands from host device at a memory device containing a memory array. In some instances, command manager 610 can receive read commands from host device at a memory device containing a memory array. In some instances, command manager 610 can receive a second read command from host device at a memory device.

[0142] The read component 615 can read datasets from the memory array based on read commands.

[0143] Error correction component 620 may modify the values ​​of bits in a dataset to obtain a modified dataset based on performing an error correction procedure on the dataset. In some instances, error correction component 620 may read the dataset from a memory array based on a read command. In some instances, error correction component 620 may identify errors contained in the dataset read from the memory array. In some instances, error correction component 620 may attempt to correct errors at least in part based on generating the modified dataset. In some instances, error correction component 620 may read a first error correction code from the memory array at a memory device based on a read command. In some instances, error correction component 620 may generate a second error correction code at a memory device based on the dataset read from the memory array. In some instances, error correction component 620 may store an indication of an address associated with the dataset based on the modification.

[0144] In some instances, error correction component 620 may read a second dataset from the memory array based on a second read command. In some instances, error correction component 620 may perform an error correction procedure on the second dataset. In some instances, error correction component 620 may determine that the second dataset is error-free based on an error correction procedure used for the second dataset.

[0145] Data transmitter 625 may transmit the modified dataset and an indication of the change to the host device. In some instances, data transmitter 625 may transmit the modified dataset and an indication of attempting to correct errors to the host device. In some instances, data transmitter 625 may transmit a second dataset and an indication that the second dataset has not been changed to the host device. In some instances, data transmitter 625 may receive a request for an indication of change from the host device, and the transmission is made in response to the request.

[0146] Matching component 630 can determine that a set of one or more bits of the second error correction code differs from a corresponding set of one or more bits of the first error correction code, the change being based on the number of bits included in the set of one or more bits satisfying a threshold. In some cases, the threshold is one bit. In other cases, the threshold is two bits. In some instances, matching component 630 can perform a set of XOR operations, wherein each XOR operation in the set is based on bits of the second error correction code and corresponding bits of the first error correction code, wherein the determination is based on a set of XOR operations. In some instances, matching component 630 can generate an indication of change based on the result of the set of XOR operations.

[0147] Error indication component 635 can generate a corresponding indication of whether the bits of the second error correction code match the corresponding bits of the first error correction code, for a set of bits included in the second error correction code, wherein the determination is based on the corresponding indication. In some instances, error indication component 635 can store a modified indication at a memory device. In some cases, the modified indication includes an indication that the memory device attempts to correct an error associated with the dataset. In some cases, the modified indication is transmitted simultaneously with at least a portion of the modified dataset.

[0148] The data manager 640 can execute a cleanup program to correct erroneous data stored in the memory array, wherein executing the cleanup program involves cleaning only a subset of the memory array containing memory cells associated with addresses.

[0149] Figure 7 A block diagram 700 illustrates a host device 705 supporting coordinated error correction according to an example disclosed herein. The host device 705 may be as described in the references... Figures 1 to 6Examples of aspects of the described host device. Host device 705 may include command manager 710, data manager 715, error correction component 720, matching component 725, and error indication component 730. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0150] Command manager 710 can transmit read commands to a memory device. In some instances, command manager 710 can transmit a second read command to a memory device. In some instances, command manager 710 can transmit a third read command to a memory device.

[0151] Data manager 715 may receive from the memory device a dataset associated with a read command and an indication that the memory device attempts to correct a first error associated with the dataset. In some instances, data manager 715 may discard the dataset received from the memory device based on a second error and the indication.

[0152] In some instances, the data manager 715 may receive from the memory device a second dataset associated with a second read command and an indication that the memory device attempts to correct a first error associated with the second dataset. In some instances, the data manager 715 may perform operations based on a second payload.

[0153] In some instances, the data manager 715 may receive from the memory device a third dataset associated with a third read command and an indication that the third dataset is error-free.

[0154] Error correction component 720 can perform error correction procedures on the payload contained in the dataset. In some instances, error correction component 720 can determine a second error associated with the payload based on the error correction procedures used for the payload.

[0155] In some instances, error correction component 720 may perform an error correction procedure on a second payload contained in a second dataset. In some instances, error correction component 720 may determine that the second payload is error-free based on the error correction procedure performed on the second payload.

[0156] In some instances, the error correction component 720 may skip the error correction process for a third payload contained in a third dataset based on an indication that the second dataset is error-free.

[0157] In some instances, error correction component 720 may perform an error correction procedure on the payload in response to an instruction from the memory device to attempt to correct a first error associated with the dataset. In some instances, error correction component 720 may obtain a first error correction code from the dataset. In some instances, error correction component 720 may generate a second error correction code based on the dataset. In some instances, error correction component 720 may identify an address associated with the dataset. In some instances, error correction component 720 may store the address in a list of defective addresses associated with the memory device.

[0158] Matching component 725 can determine a mismatch between the bits of the second error correction code and the corresponding bits of the first error correction code, wherein the determination that the second error is associated with the payload is based on the mismatch.

[0159] Error indication component 730 can transmit a second error indication to a memory device.

[0160] Figure 8 The flowchart illustrates one or more methods 800 for supporting coordinated error correction according to aspects of this disclosure. The operation of method 800 may be implemented by a memory array or its components as described herein. For example, the operation of method 800 may be implemented by, as referenced... Figure 6 The described memory array performs the functions described. In some instances, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the described functions. Alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0161] At 805, the memory array can receive read commands from the host device at the memory device containing the memory array. The operation of 805 can be performed according to the method described herein. In some instances, aspects of the operation of 805 can be derived from, as referenced... Figure 6 The command manager described is executed.

[0162] At 810, the memory array can read a dataset from the memory array based on a read command. The operation of 810 can be performed according to the methods described herein. In some instances, aspects of the operation of 810 can be derived from, as referenced... Figure 6 The described reading component is executed.

[0163] At 815, the memory array can change the values ​​of bits in the dataset based on performing an error correction procedure on the dataset to obtain a modified dataset. Operation of 815 can be performed according to the method described herein. In some instances, aspects of the operation of 815 can be derived from, as referenced... Figure 6 The described error correction component is executed.

[0164] At 820, the memory array can transfer the modified dataset and instructions for the changes to the host device. Operation of 820 can be performed according to the methods described herein. In some instances, aspects of the operation of 820 can be determined by reference to [reference needed]. Figure 6 The described data transfer device is executed.

[0165] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a read command from a host device at a memory device comprising a memory array; reading a dataset from the memory array based on the read command; changing the values ​​of bits in the dataset based on performing an error correction procedure on the dataset to obtain a modified dataset; and transmitting the modified dataset and an indication of the change to the host device.

[0166] In some instances of the method 800 and apparatus described herein, performing an error correction procedure on a dataset may include operations, features, means, or instructions for: reading a first error correction code from a memory array at a memory device based on a read command; generating a second error correction code at a memory device based on the dataset read from the memory array; and determining that a set of one or more bits of the second error correction code differs from a corresponding set of one or more bits of the first error correction code, the change being based on the number of bits contained in the set of one or more bits satisfying a threshold.

[0167] In some instances of the method 800 and device described herein, the threshold may be one bit. In other instances of the method 800 and device described herein, the threshold may be two bits.

[0168] Some instances of the method 800 and apparatus described herein may further include operations, features, means, or instructions for performing a set of XOR operations, wherein each XOR operation in the set is based on bits of a second error correction code and corresponding bits of a first error correction code, wherein the determination may be based on the set of XOR operations.

[0169] Some instances of the methods 800 and devices described herein may further include instructions for operations, features, means, or instructions that produce changes based on the results of a set of XOR operations.

[0170] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for generating a corresponding indication of whether the bits of the second error correction code match the corresponding bits of the first error correction code for a set of bits contained in the second error correction code, wherein the determination may be based on the corresponding indication.

[0171] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: receiving a second read command from a host device at a memory device; reading a second dataset from a memory array based on the second read command; performing an error correction procedure on the second dataset; determining, based on the error correction procedure for the second dataset, that the second dataset may not contain errors; and transmitting an indication to the host device that the second dataset and the second dataset may not have been changed.

[0172] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: storing an indication of change at a memory device, and receiving a request for the indication of change from a host device, the transmission being in response to the request.

[0173] In some instances of the method 800 and device described herein, the indication of change includes an indication that the memory device attempts to correct errors associated with the dataset.

[0174] In some instances of the method 800 and device described herein, the indication of change may be transmitted simultaneously with at least a portion of the dataset being changed.

[0175] Some instances of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: storing addresses associated with a dataset based on changes; and performing a cleanup procedure to correct erroneous data stored in a memory array, wherein performing the cleanup procedure includes cleaning only a subset of the memory array containing memory cells associated with addresses.

[0176] Figure 9 The flowchart illustrates one or more methods 900 for supporting coordinated error correction according to aspects of this disclosure. Operation of method 900 may be implemented by a host device or its components as described herein. For example, operation of method 900 may be performed by, as referenced... Figure 7 The described host device performs the function. In some instances, the host device may execute a set of instructions to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0177] At 905, the host device can transmit a read command to the memory device. The operation of 905 can be performed according to the method described herein. In some instances, aspects of the operation of 905 can be derived from, as referenced... Figure 7 The command manager described is executed.

[0178] At 910, the host device may receive from the memory device a dataset associated with a read command and an indication that the memory device attempts to correct a first error associated with the dataset. The operation of 910 can be performed according to the method described herein. In some instances, aspects of the operation of 910 may be derived from, as referenced... Figure 7 The described data manager is executed.

[0179] At point 915, the host device can perform an error correction procedure for the payload contained in the dataset. The operation of point 915 can be performed according to the methods described herein. In some instances, aspects of the operation of point 915 can be derived from, as referenced... Figure 7 The described error correction component is executed.

[0180] At 920, the host device can determine a second error associated with the payload based on an error correction procedure used for the payload. Operation 920 can be performed according to the method described herein. In some instances, aspects of the operation of 920 can be derived from, as referenced... Figure 7 The described error correction component is executed.

[0181] At 925, the host device may discard the dataset received from the memory device based on a second error and indication. The operation of 925 can be performed according to the method described herein. In some instances, aspects of the operation of 925 may be provided as referenced. Figure 7 The described data manager is executed.

[0182] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting a read command to a memory device; receiving from the memory device a dataset associated with the read command and an indication that the memory device attempts to correct a first error associated with the dataset; performing an error correction procedure for a payload contained in the dataset; determining a second error associated with the payload based on the error correction procedure for the payload; and discarding the dataset received from the memory device based on the second error and the indication.

[0183] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for: transmitting a second read command to a memory device; receiving from the memory device a second dataset associated with the second read command and an indication that the memory device attempts to correct a first error associated with the second dataset; performing an error correction procedure for a second payload contained in the second dataset; determining, based on the error correction procedure for the second payload, that the second payload may be error-free; and performing operations based on the second payload.

[0184] Some instances of the method 900 and apparatus described herein may further include operations, features, means, or instructions for: transmitting a third read command to a memory device; receiving from the memory device a third dataset associated with the third read command and an indication that the third dataset may be error-free; and skipping an error correction procedure for a third payload contained in the third dataset based on the indication that the second dataset may be error-free.

[0185] Some instances of the method 900 and device described herein may further include operations, features, means, or instructions for performing an error correction procedure for a payload in response to an instruction from a memory device to attempt to correct a first error associated with a dataset.

[0186] In some instances of the method 900 and apparatus described herein, performing an error correction procedure for a payload may include operations, features, means, or instructions for: obtaining a first error correction code from a dataset; generating a second error correction code based on the dataset; and determining a mismatch between bits of the second error correction code and corresponding bits of the first error correction code, wherein determining that a second error may be associated with the payload may be based on the mismatch.

[0187] Some instances of the method 900 and apparatus described herein may further include operations, features, means, or instructions for: identifying addresses associated with a dataset; and storing addresses into a list of defective addresses associated with a memory device.

[0188] Some examples of the method 900 and device described herein may further include operations, features, means, or instructions for transmitting an indication of a second error to a memory device.

[0189] Figure 10 The flowchart illustrates one or more methods 1000 for supporting coordinated error correction according to aspects of this disclosure. The operation of method 1000 may be implemented by a memory array or its components as described herein. For example, the operation of method 1000 may be implemented by, as referenced... Figure 6 The described memory array performs the functions described. In some instances, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the described functions. Alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0190] At point 1005, the memory array may receive a read command from the host device at the memory device containing the memory array. The operation at point 1005 can be performed according to the method described herein. In some instances, aspects of the operation at point 1005 may be derived from, as referenced... Figure 6 The command manager described is executed.

[0191] At position 1010, the memory array can read a dataset from the memory array based on a read command. The operation at position 1010 can be performed according to the method described herein. In some instances, aspects of the operation at position 1010 can be derived from, as referenced... Figure 6 The described error correction component is executed.

[0192] At point 1015, the memory array can identify errors contained in the dataset read from the memory array. Operation at point 1015 can be performed according to the method described herein. In some instances, aspects of operation at point 1015 can be derived from, as referenced... Figure 6 The described error correction component is executed.

[0193] At point 1020, the memory array may attempt to correct errors, at least in part, based on the generated modified dataset. Operation at point 1020 can be performed according to the methods described herein. In some instances, aspects of operation at point 1020 may be derived from, as referenced... Figure 6 The described error correction component is executed.

[0194] At position 1025, the memory array can transmit the modified dataset and instructions to attempt error correction to the host device. Operation of position 1025 can be performed according to the method described herein. In some instances, aspects of the operation of position 1025 can be derived from, as referenced... Figure 6 The described data transfer device is executed.

[0195] In some instances, the device as described herein may perform one or more methods, such as method 1000. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a read command from a host device at a memory device comprising a memory array; reading a dataset from the memory array based on the read command; identifying errors contained in the dataset read from the memory array; attempting to correct the errors at least in part based on the generation of the modified dataset; and transmitting the modified dataset and an instruction to attempt to correct the errors to the host device.

[0196] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0197] Describe a device. The device may include: a memory array; error correction logic coupled to the memory array and usable for: an indication component coupled to the error correction logic and usable for: generating an indication of an attempt to correct an error; and an output component usable for: outputting the indication to a host device of the device.

[0198] In some instances, error correction logic can be used to identify errors by comparing each bit in a first error correction code with the corresponding bit in a second error correction code.

[0199] In some instances, bit-by-bit comparisons may be based on a set of XOR operations, each XOR operation in which corresponds to a first corresponding bit contained in a first error correction code and a second corresponding bit contained in a second error correction code.

[0200] In some instances, error correction logic can be used to generate a set of indications based on a comparison of a first error correction code and a second error correction code, each indication indicating whether there is a mismatch between a first corresponding bit contained in the first error correction code and a second corresponding bit contained in the second error correction code, and the indication component can be used to generate an indication to attempt to correct an error in response to a set of indications indicating at least a threshold number of mismatches.

[0201] Some instance devices may include error correction logic that can be used to attempt to correct errors based on a set of one or more mismatches indicating at least a threshold number.

[0202] In some instances, one or more mismatches of the threshold number can be a single mismatch. In other instances, one or more mismatches of the threshold number can be two mismatches.

[0203] In some instances, the cleanup component is coupled with error correction logic and can be used to correct erroneous data stored in the memory array, where the cleanup component can be used to ignore the first part of the memory array based on the error being identified as corresponding to the second part of the memory array.

[0204] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0205] As used herein, the term "virtual ground" refers to a circuit node that is maintained at approximately zero volts (0V) without being directly coupled to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0V in a steady state. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground connection" implies a connection to approximately 0V.

[0206] The terms “electronically connected,” “conductively contacted,” “connected,” “coupled,” and “coupleable” refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacted, connected, or coupled) to each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacted, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0207] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via a conductive path; in a closed-circuit relationship, signals can be transmitted between components via a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted. The term "coupleable" refers to a component configured to couple with another component to provide a closed-circuit relationship that allows signals to be transmitted between components via a conductive path.

[0208] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between them using previously permitted conductive paths.

[0209] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0210] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated via lightly doped semiconductor regions or a channel. If the channel is n-type (e.g., most carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0211] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0212] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0213] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0214] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0215] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed so that portions of the functionality are implemented in different physical locations. Furthermore, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of, for example, at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0216] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0217] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operations, comprising: reading a data set and an error correction code associated with the data set from a memory array based at least in part on a clean-up procedure with respect to a subset of addresses of the memory array; altering values of bits in the data set by on-die error correction circuitry of the memory array and based at least in part on one or more unit errors for the data set to obtain an altered data set; and storing the altered data set to the memory array based at least in part on an address of the data set, wherein the subset of addresses includes the address of the data set.

2. The method of claim 1, further comprising: receiving a command to perform the clean-up procedure, wherein reading the data set and the error correction code, altering the values of the bits, and storing the altered data set are in response to the command.

3. The method of claim 1, wherein reading the data set and the error correction code, altering the values of the bits, and storing the altered data set are performed periodically.

4. The method of claim 1, further comprising: storing an indication of the subset of addresses, wherein the clean-up procedure with respect to the subset of addresses is based at least in part on the indication of the subset of addresses.

5. The method of claim 4, wherein the subset of addresses comprises one or more row addresses.

6. The method of claim 1, wherein the clean-up procedure is based at least in part on a unit error correction scheme according to an on-die error correction code.

7. The method of claim 1, further comprising: detecting the one or more unit errors based at least in part on a syndrome match check operation for the data set and the error correction code associated with the data set.

8. The method of claim 1, wherein the memory array comprises a dynamic random access memory (DRAM).

9. A memory system, comprising: one or more memory devices comprising one or more memory arrays, the one or more memory devices configured to: read a data set and an error correction code associated with the data set from the one or more memory arrays based at least in part on a clean-up procedure with respect to a subset of addresses of the one or more memory arrays; alter values of bits in the data set by on-die error correction circuitry of the one or more memory arrays and based at least in part on one or more unit errors for the data set to obtain an altered data set; and store the altered data set to the one or more memory arrays based at least in part on an address of the data set, wherein the subset of addresses includes the address of the data set.

10. The memory system of claim 9, wherein the one or more memory devices are further configured to: receive a command from a host device to perform the clean-up procedure, wherein reading the data set and the error correction code, altering the values of the bits, and storing the altered data set are in response to the command.

11. The memory system of claim 9, wherein reading the data set and the error correction code, altering the values of the bits, and storing the altered data set are performed periodically.

12. The memory system of claim 9, wherein the one or more memory devices are further configured to: store an indication of the subset of addresses, wherein the scrub is based at least in part on the indication of the subset of addresses.

13. The memory system of claim 12, wherein the subset of addresses comprises one or more row addresses.

14. The memory system of claim 9, wherein the scrub is based at least in part on a unit error correction scheme according to an on-die error correction code.

15. The memory system of claim 9, wherein the one or more memory devices are further configured to: detect the one or more unit errors based at least in part on a syndrome match check operation for the data set and the error correction code associated with the data set.

16. The memory system of claim 9, wherein the one or more memory arrays comprise dynamic random access memory (DRAM).

17. A memory system, comprising: one or more controllers configured to transmit a read command to one or more memory devices to read a data set from one or more memory arrays of the one or more memory devices; and the one or more memory devices comprising the one or more memory arrays, wherein the one or more memory devices are configured to: read, responsive to the read command, the data set and an error correction code associated with the data set from the one or more memory arrays based at least in part on a scrub of a subset of addresses of the one or more memory arrays; alter, by on-die error correction circuitry of the one or more memory arrays and based at least in part on one or more unit errors for the data set, values of bits in the data set to obtain an altered data set; and store the altered data set to the one or more memory arrays based at least in part on an address of the data set, wherein the subset of addresses includes the address of the data set.

18. The memory system of claim 17, wherein the one or more memory devices are further configured to: receive a command from one or more host devices to perform the scrub, wherein reading the data set and the error correction code, altering the values of the bits, and storing the altered data set are responsive to the command.

19. The memory system of claim 17, wherein reading the data set and the error correction code, altering the values of the bits, and storing the altered data set are performed periodically.

20. The memory system of claim 17, wherein the one or more memory devices are further configured to: store an indication of the subset of addresses, wherein the scrub is based at least in part on the indication of the subset of addresses, wherein the subset of addresses comprises one or more row addresses.

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