Field-effect transistors with improved gate structures

Abstract

A field-effect transistor includes a gate contact and a gate metal forming a vertical structure, the vertical structure having sides and a top surrounded by an air gap formed between the source electrode and the drain electrode of the field-effect transistor.

Description

Technical Field

[0001] This disclosure generally relates to field-effect transistors, and more specifically, to FETs having a gate structure that, when contacted and connected with an interconnect based on embedded copper, has low capacitance and low resistance. Background Technology

[0002] As is known in the art, the geometric scaling down of field-effect transistor (FET) device dimensions has a significant impact on high-frequency performance. Typically, as transistor size shrinks, both the gate length and source-drain spacing decrease. With shrinking size, the gate is placed more extensively within the source-drain region, achieving the maximum potential performance improvement by positioning the gate closer to the source than the drain. Simultaneously, the resistance increases, particularly the gate resistance, which negatively impacts the transistor's frequency response and noise figure. Furthermore, the dielectric load near the gate electrode also adversely affects the transistor's frequency response.

[0003] As is well known in the art, the fabrication of GaN HEMT transistor devices and integrated circuits has been demonstrated in silicon CMOS "similar" single or dual damascene wafer processes (see LaRoche et al., "Towards a Si Foundry-Compatible, High-Performance, ≤0.25μm Gate, GaN-on-Si MMIC Process on High-Resistivity"). <111> Si With A Cu Damascene BEOL", CS Man Tech Conference May 16th-19th, Miami, FL). This is possible due to the compatibility of CMOS integration processes and metallization schemes with GaN integrated circuit processes. For this reason, as mentioned above, when using CMOS "similar" processes, due to the downward dimensional expansion of the gate length in GaN HEMTs and the minimal dielectric load, attention must be paid to the gate size, location, resistance, and dielectric load near the gate.

[0004] In CMOS-like processes, the fine-line geometry of large-scale FETs is defined using conventional photolithography or electron beam lithography, which restricts the size, aspect ratio, and location of the gates in the source and drain regions. Sidewall image transfer technology, which defines thin-film sidewalls on a sacrificial core or die, is commonly used in nanoscale CMOS processes. Furthermore, damascene interconnects in CMOS processes often use metallized air gaps to improve the frequency response of passive interconnects; see, for example, "Multilevel Interconnect With Air-Gap Structure for Next-Generation Interconnections," Junji Noguchi et al., IEEE Transactions on Electron Devices, Vol. 56, Issue 11, Nov 2009. However, the transistors themselves are still charged by the damascene oxide, which reduces their frequency response. Summary of the Invention

[0005] According to this disclosure, a field-effect transistor is provided having a gate contact and a gate metal forming a vertical structure having sides and a top surrounded by an air gap formed between the source electrode and the drain electrode of the field-effect transistor.

[0006] In one embodiment, the source electrode and the drain electrode are damascene structures.

[0007] In one embodiment, the gate contacts and gate metal form a vertical structure having sides and a top surrounded by an air gap that extends vertically to a level parallel to the top of the grooving structure.

[0008] In one embodiment, the gate contact comprises a plurality of stacked damascene metal layers.

[0009] In one embodiment, the gate contact comprises a plurality of stacked damascene metal layers that extend vertically to a horizontal level parallel to the top of the damascene structure.

[0010] In one embodiment, the field-effect transistor is a mesa structure, wherein the gate contact and gate metal form a vertical structure having sides and top surrounded by an air gap formed between the source and drain electrodes and between the mesa edges perpendicular to the gate direction.

[0011] In one embodiment, a field-effect transistor structure is provided, comprising: a III-N buffer layer; a III-N channel layer disposed on the III-N buffer layer; a barrier layer disposed on the channel layer; wherein a 2DEG (two-dimensional electron gas) is formed in the channel layer; a horizontally extending, uniformly thick doped GaN (gallium nitride) layer disposed on the III-N buffer layer, the uniformly thick doped GaN layer having a vertically extending hole having a vertically extending sidewall terminating at a horizontally extending upper surface portion of the III-N buffer layer; and a gate electrode comprising: a vertical stem portion extending into the hole, which includes a portion of the III-N buffer layer. A portion of a III-N channel layer and a portion of a buffer layer (barrier layer), wherein the portion of the III-N buffer layer, the portion of the III-N channel layer, and the portion of the buffer layer form a vertical stack; wherein the vertical stack extends vertically upward into the via and is located between the vertically extending sidewalls of the via; and a gate metal disposed on the stack; source and drain contacts making ohmic contact with the upper surface portion of a horizontally extending doped GaN layer of uniform thickness; and wherein a gate electrode is disposed between the source and drain electrodes.

[0012] In one embodiment, a gate contact is disposed on a gate metal, and the source and drain contacts have lower portions; and the gate contact and the lower portions of the source and drain contacts have upper surfaces disposed in a common plane.

[0013] In one embodiment, the source and drain electrodes are a mosaic structure.

[0014] In one embodiment, the gate contacts and gate metal form a vertical structure having sides and a top surrounded by an air gap that extends vertically to a level parallel to the top of the grooving structure.

[0015] In one embodiment, the gate contacts and gate metal form a vertical structure having sides and a top surrounded by an air gap.

[0016] In one embodiment, the gate contact comprises a plurality of stacked damascene metal layers.

[0017] In one embodiment, the gate contact includes a plurality of stacked damascene metal layers that extend vertically to a horizontal level parallel to the top of the damascene structure.

[0018] In one embodiment, the gate contact includes a plurality of stacked damascene metal layers surrounded by a non-conformal oxide, thereby forming a horizontal air gap that extends vertically to the top of the damascene structure next to these metal layers.

[0019] In one embodiment, a method for forming a field-effect transistor is provided, comprising: forming a die on a surface of a semiconductor body; forming a first dielectric spacer layer having an inner sidewall on an outer sidewall of the die and a bottom on the semiconductor body; forming a gate electrode having an inner sidewall on an outer sidewall of the first dielectric spacer layer and a bottom on the semiconductor body; forming a second dielectric layer having an inner sidewall on an outer sidewall of the gate electrode and a bottom on the semiconductor body; wherein the width of the first dielectric spacer layer is different from the width of the second dielectric spacer layer; and, after forming the first dielectric layer and the second dielectric layer, removing the die while leaving the bottom of the gate electrode on the semiconductor.

[0020] In one embodiment, a method for forming a field-effect transistor (FET) is provided, the FET having a pair of electrically interconnected gate electrodes, one of the gate electrodes being disposed between a first source electrode and a drain electrode, and the other of the gate electrodes being disposed between a drain electrode and a second source electrode, the method comprising: forming a die on a surface of a semiconductor body; forming a first pair of dielectric spacers, wherein each dielectric spacer has an inner sidewall located on a corresponding outer sidewall of a pair of opposing outer sidewalls of the die; forming the pair of gate electrodes, one of the gate electrodes being formed on an outer sidewall of the first dielectric spacer in the first pair of dielectric spacers, and the other of the gate electrodes being formed on a second dielectric spacer in the first (pair) of dielectric spacers; forming a second pair of dielectric spacers, wherein each dielectric spacer has an inner sidewall located on an outer sidewall of a corresponding gate electrode in the pair of gate electrodes; wherein the widths of the first pair of dielectric spacers and the second pair of dielectric spacers are different; and removing the die after forming the first pair of dielectric spacers and the second pair of dielectric spacers.

[0021] With this arrangement, the self-aligned gate and regenerated ohmics utilizing planar gate technology and a copper damascene structure provide tighter dimensional control, with the gate dielectric also acting as a spacer to improve access resistance through contact with the damascene metallization and gate aspect ratio. This approach allows us to achieve small source-drain gaps. The high manufacturability of this process is guaranteed by its entirely subtractive nature, its lift-based processing, and the fact that the gate is stabilized in oxide before forming an air gap at the end of the front-end-of-line (FEoL) processing (to reduce parasitic capacitance and improve gain). The copper damascene, along with the self-aligned GAN HEMT, planar structure, and adjacent HEMT air gaps, reduces capacitance. Attached Figure Description

[0022] Figure 1-67C, 8-12, 12A, 13-14, 15A-15B, 16A, 16B, 17A, 17B, 18A-18I are simplified, schematic cross-sectional views of the steps for forming a field-effect transistor according to the present disclosure;

[0023] Figure 4A , 5A 6A, 7A, 7B, 8A, 13A, and 14A are simplified, schematic planar diagrams of the steps for forming a field-effect transistor according to this disclosure. Figure 4 , 5 6, 7C, 8, 13, and 14 respectively along Figure 4A , 5A Cut lines 4-4, 5-5, 6-6, 7C-7C, 8-8, 13-13, and 14-14 from lines 6A, 7B, 8A, 13A, and 14A;

[0024] Figure 19 This is a simplified, schematic plan view of a field-effect transistor based on the present disclosure. Figure 19A Along Figure 19 Cut off line 19A-19A in the middle;

[0025] Figure 19B This is a simplified, schematic cross-sectional view of a field-effect transistor according to the present disclosure. Figure 19B Along Figure 19 Cut off line 19B-19B in the middle;

[0026] Figure 19A This is a simplified, schematic cross-sectional view of a field-effect transistor according to an alternative embodiment of the present disclosure;

[0027] Figure 20A-20F 20J-20W is a simplified, schematic cross-sectional view of the steps for forming a field-effect transistor according to a second alternative embodiment of the present disclosure;

[0028] Figure 20G , 20H 20I and 20X are simplified, schematic plan views of field-effect transistors according to a second alternative embodiment of the present disclosure at various stages of their manufacture; Figure 20F , 20J and Figure 20W Along respectively Figure 20G , 20I Cut off lines 20F-20F, 20J-20J, and 20W-20W in 20X;

[0029] Figure 20X yes Figure 20W A simplified, schematic planar diagram of the formation of a field-effect transistor; and

[0030] Figure 21This is a simplified, schematic cross-sectional view of a field-effect transistor according to an alternative embodiment of the present disclosure.

[0031] The same reference numerals in each figure indicate the same element. Detailed Implementation

[0032] Now for reference Figure 1 The figure shows a substrate 10, which is, for example, silicon (Si) or silicon carbide, having a III-V layer, which is, for example, aluminum nitride (AlN), gallium nitride (GaN), or a combination thereof. A nucleation layer or buffer / back barrier layer 12 is epitaxially formed on the upper surface of the substrate 10. An undoped III-V layer 14, which is, for example, a gallium nitride (GaN) layer 14 epitaxially formed on the upper surface of layer 12, and a III-V layer 16, which is, for example, an AlGaN (aluminum gallium nitride) layer 16 epitaxially formed on the upper surface of GaN layer 14, are shown in the figure. As shown, GaN layer 14 provides carrier channels.

[0033] refer to Figure 2 As shown in the figure, a silicon oxide layer 18 is formed on the upper surface of layer 14.

[0034] Now for reference Figure 3 As shown in the figure, the isolation region 20 is formed to extend through the silicon dioxide layer 18, the AlGaN layer 16, and the GaN layer 14, and into the upper part of the buffer layer 12; here, for example, this isolation region 20 is formed by oxygen ion implantation. It should be understood that the layers can be etched to form a conventional mesa isolation structure.

[0035] Now for reference Figure 4 and Figure 4A As shown in the figure, a sacrificial hard mask 22 is formed in any conventional manner on a portion of the upper surface of the silicon oxide layer 18. Here it is a four-sided, rectangular mandrel or core, for example, polycrystalline silicon, silicon nitride, aluminum oxide, amorphous carbon or other suitable hard mask material.

[0036] Now for reference Figure 5 and Figure 5A ,exist Figure 4 A conformal (conformal) dielectric spacer layer 24 is deposited on the entire upper surface of the structure shown. This layer is made of polycrystalline silicon (Al2O3), silicon nitride, silicon oxide, amorphous carbon, or other suitable materials. The deposition is achieved by, for example, chemical vapor deposition (CVD), sputtering, or atomic layer deposition (ALD).

[0037] refer to Figure 6 and Figure 6AA portion of the dielectric spacer layer 24 is removed from the upper surface of the core mold 22 and the upper surface of the oxide layer 18 using plasma-directed etching, inductively coupled plasma (ICP) etching, or reactive ion etching (RIE) to produce the structure shown in the figure.

[0038] refer to Figure 7A ,like Figure 7A , 7B As shown in 7C, the core mold 22 is removed by selective wet or dry etching, and then a pair of opposing dielectric spacer layers 24B is removed by a trim masking lithography process, leaving another pair of opposing dielectric spacer layers 24A.

[0039] refer to Figure 8 and Figure 8A The exposed portion of the silicon oxide layer 18 is removed, for example by plasma etching to expose the top portion of the GaN epitaxial layer 14; it should be noted that the portion of the silicon oxide layer 18 below the dielectric spacer layer 24 is still retained, as shown in the figure.

[0040] Now for reference Figure 9 The exposed portion of AlGaN layer 16 is removed, then the exposed portion of GaN layer 14 is removed, and subsequently the exposed upper portion of AlN layer 12 is removed; the removal is achieved here by selective wet or dry etching; it should be noted that portions of AlGaN layer 16, GaN layer 14, and AlN layer 12 located below dielectric spacer layer 12, as well as portions of isolation region 20, are still retained, as shown in the figure.

[0041] Now for reference Figure 10 An N++ doped GaN layer 30 is formed on the exposed portion of the AlN layer 12; that is, the so-called regenerated layer, as shown, has a portion 30A deposited on the dielectric spacer layer 24 using molecular beam epitaxy or metal-organic chemical vapor deposition (MOCVD).

[0042] Now for reference Figure 11 Wet or dry selective polycrystalline GaN etching is used to remove portions deposited on the dielectric spacer layer 24, thereby forming Figure 12 The structure shown.

[0043] refer to Figure 12A A photoresist layer 32 is formed on a portion of the structure to expose a portion 30 of the N++ regenerated ohmic layer 30; it should be noted that both ends of the photoresist layer 32 extend over a portion of the implantation region 20, such as Figure 12A As shown. A suitable wet or plasma etching process was used to etch and remove the exposed portion 30 of the regenerated ohmic layer 30. Figure 13 and Figure 13AThen, the exposed portions of the dielectric spacer layer 24 and the photoresist layer 32 are removed to form... Figure 14 and Figure 14A The structure shown.

[0044] refer to Figure 15A A thin dielectric layer 38, such as SiNx, is formed on the surface, followed by chemical mechanical polishing to expose the upper portion of the silicon dioxide layer 18, such as... Figure 15B As shown.

[0045] Referring to Figure 16, as shown, the exposed portion of the silicon dioxide layer 18 is removed by selective wet or dry etching, thereby exposing the lower portion of the AlGaN layer 16.

[0046] refer to Figure 16A First, a dielectric liner material 70A, such as SiNx or Al2O3, is deposited in a conformal manner on the structure, and then... Figure 16B The directional etching shown leaves a portion 70B of the dielectric liner layer on the sidewalls and gate opening of the regenerated ohmic layer 30, as... Figure 16B As shown.

[0047] Now for reference Figure 17A As shown in the figure, a gate metal layer 42a (e.g., a lower layer of titanium nitride (TiN) and an upper layer of tungsten (W)) is sputter-deposited onto the structure. Figure 17B As shown, photoresist mask 46 is used for dry etching to pattern layer 42a into a pair of Schottky gate metal contacts 42a, 42b.

[0048] Now for reference Figure 18A-18I It describes the pair of source contacts 50S and drain contacts 50D. Figure 18D I) The process of forming a mosaic structure (e.g., a damascus structure) that makes ohmic contact with the N++ regenerated ohmic layer 30. Therefore, refer to Figure 18A ,like Figure 18A As shown, an additional silicon nitride (SiNx) stop etch layer 47a is deposited on the SiNx layer 38 and a pair of Schottky gate metal contacts 42a and 42b.

[0049] refer to Figure 18B A dielectric layer 48a (e.g., silicon dioxide) is deposited on the SiNx layer 47a by chemical vapor deposition (CVD), planarized by chemical mechanical planarization (CMP), and patterned and etched by photolithography to first form a pair of windows 48WG1 and 48WG2 for gate contacts 42a and 42b. Figure 18B Then, windows 48WS1, 48WS2, and 48WD are formed for a pair of source contacts 50S and drain contacts 50D. Figure 18D, 18I Remove the exposed portion of SiNx layer 47 to form windows 501 and 502. Figure 18C This exposes portions of the gate and N++ regenerated ohmic layer 30, where a pair of source contacts 50S, a drain contact 50D, and two gate contacts 50G will pass through the metal layer V in windows 501 and 502. O Additional electroplating and chemical mechanical polishing (CMP) are applied to (copper) as follows: Figure 18D As shown in the image.

[0050] refer to Figure 18E Similarly, a dielectric layer 47b (here, for example, silicon nitride) is deposited, followed by a silicon dioxide layer 44b; a window (not shown) is formed therein, and an upper metal layer M1 (here, copper) is deposited onto the metal layer V through the window. O The top layer is shown in the figure; then another silicon nitride layer 47c is deposited (as shown in Figure 18E) to form an inlaid structure 49S1, 49D1, which respectively contact the lower part of the source and drain contacts (S and D). Figure 18H ).

[0051] This process is repeated, such as Figure 18G and Figure 18H As shown, inlay structures 49S2 and 49D2 are formed to be used on the upper part of the source and drain contacts (S and D), respectively. Figure 18H .

[0052] Next, the air gap 60 is etched into the structure using conventional photolithography etching techniques to form... Figure 18I The structure shown.

[0053] As described above, the source and drain contacts here are 50S and 50D ( Figure 18I The SiNx and SiO dielectric layers are formed into an inlaid structure. Figure 18I As shown, it is formed to provide access to the source and drain electrodes 50S and 50D and the gate contacts 42a, 42b. Figure 18B Provides upper (here, copper (Cu)) contact metal layers V0, M1, V1, and M2, such as Figure 18I As shown.

[0054] refer to Figure 19 , Figure 19A and Figure 19B This forms an alternative mosaic structure for the source and drain electrodes 50S and 50D, which has a non-conformal mosaic oxide that creates cavitation 51.

[0055] Now for reference Figure 20A-20VAlternative embodiments will be described below. Here, the separation between the gate electrode and the source electrode will differ from the separation between the gate electrode and the drain electrode; that is, a so-called asymmetric gate FET gate structure.

[0056] Therefore, here, in core mold 22 as described above Figure 4 After the formation, Figure 4 A layer 241 of uniform thickness W1 is formed on the surface of the structure shown. This layer is, for example, an Al2O3, SiO2, SiN, polycrystalline silicon, or amorphous carbon layer deposited by CVD, ALD, or sputtering, to produce... Figure 20A The structure shown.

[0057] refer to Figure 20B As shown in the figure, a portion of layer 241 is removed using directional etching, such as plasma, ICP, or RIE. The mandrel and spacer materials, as well as the etching conditions, are selected to provide good dry etching selectivity to produce… Figure 20B The structure shown. It is worth noting that, as shown in the figure, a portion of layer 241 is retained on the vertical sidewall of core mold 22.

[0058] refer to Figure 20C As shown in the figure, layer 242 is deposited on the structure. Here, layer 242 is: Al2O3, SiO2, SiN, polycrystalline silicon, amorphous carbon layer or other suitable material deposited by CVD, ALD or sputtering.

[0059] refer to Figure 20D As shown in the figure, a portion of layer 242 is removed using, for example, directional etching via plasma, ICP, or RIE, to produce Figure 20D The structure shown is illustrated. It should be noted that a portion of layer 242 remains on the vertical sidewall of layer 241, as described above, where the vertical sidewall of layer 241 is located on the vertical sidewall of core mold 22, as shown in the figure.

[0060] refer to Figure 20E A uniformly deposited layer 243 is formed, wherein layer 243 has a thickness W2, and W2 differs from W1 in the structure shown. Here, layer 243 is: Al2O3, SiO2, SiN, polycrystalline silicon, amorphous carbon layer or other suitable material deposited by CVD, ALD or sputtering.

[0061] refer to Figure 20F and Figure 20G As shown in the figure, a portion of layer 243 is removed using, for example, directional etching via plasma, ICP, or RIE, to produce Figure 20F The structure shown is as follows. It is worth noting that, as shown in the figure, a portion of layer 243 is retained on the vertical sidewall of layer 242.

[0062] refer to Figures 20H-20J , such as with Figure 7A The description involves removing the core mold 22 using selective wet or dry etching, followed by removing paired opposing layers 241, 242, and 243 using a trim-mask lithography process, as described above. Figure 7B and Figure 7C The relevant description leaves another pair of opposing layers 241, 242, and 243 to produce Figure 20I and Figure 20J The structure shown.

[0063] refer to Figure 20K As mentioned above Figure 8 The description states that the exposed portion of oxide layer 18 was removed.

[0064] refer to Figure 20L As mentioned above Figure 9 The description states that the exposed portions of layers 16 and 14 should be removed.

[0065] refer to Figure 20M As mentioned above Figure 10 The relevant description describes the deposition of an N++GaN layer 30 on the structure shown by MBE and MOCVD.

[0066] refer to Figure 20N ,like Figure 12 As described, portions of layer 30 on the upper surfaces of layers 221, 222, and 223 are removed by selective dry or wet etching.

[0067] refer to Figure 200 A photoresist layer 32 is formed on a portion of the structure to expose a portion 30A of the N++ regenerated ohmic layer 30; it should be noted that both ends of the photoresist layer 32 extend over a portion of the implantation region 30, as described above. Figure 12A As stated in [the text]. Figure 20P As shown, after removing the mask 34, an etching process is used to form the mesa structure 35, as described above. Figure 14 and Figure 14A As described in [the text].

[0068] refer to Figure 20Q A dielectric layer 38 (e.g., SiNx) is formed on the surface, followed by chemical mechanical polishing, such as... Figure 20R As shown, the upper surfaces of layers 241, 242, and 243 are exposed.

[0069] refer to Figure 20S The surface of the structure is masked but has windows to expose the portion indicated by arrow 39. This exposed portion is then subjected to dry selective etching to remove layer 242, thereby exposing the underlying portion of oxide layer 18. This exposed portion of layer 18 is then removed by plasma etching, ICP, or RIE to produce a structure as shown in the image. Figure 20SThe structure shown exposes the lower part of layer 16.

[0070] refer to Figure 20T A gate metal layer structure 44, for example, a lower layer of titanium nitride (TiN) and an upper layer of tungsten (W) are deposited on the structure in a blanket manner, as shown in the figure.

[0071] refer to Figure 20U Dry etching is performed on photoresist mask 46 to pattern layer 44 into a pair of Schottky gate metal contacts 44a, 44b, as shown in the figure and with Figure 17B Related descriptions and Figure 20V As shown in the image.

[0072] refer to Figure 20W ,like Figure 18A As described above, a silicon nitride (SiNx) etch stop layer 47 is deposited on the SiNx layer 38 and a pair of Schottky gate metal contacts 44a, 44b. Then the process continues. Figures 18B to 18I The process described in the text.

[0073] It should be understood that, in order to reduce gate resistance and thus improve frequency response, additional Cu Damascene metal layers M1 and V1 and M2 are stacked, for example, above the V0 gate Cu Damascene (damascene, damascene) layer V0 that contacts the gate metal layers 42a and 42b. It should be understood that more or fewer Cu Damascene layers can be stacked above the V0 gate. Figure 21 As shown, the cross-section is formed as described above.

[0074] It should now be understood that the field-effect transistor according to this disclosure includes a gate contact and a gate metal forming a vertical structure having sides and a top surrounded by an air gap formed between the source and drain electrodes of the field-effect transistor. The field-effect transistor may individually or in combination include one or more of the following features: wherein the source and drain electrodes are damascene (damascus) structures; wherein the gate contact and the gate metal form a vertical structure having sides and a top surrounded by an air gap extending vertically to a level parallel to the top of the damascene structure; wherein the gate contact includes a plurality of stacked damascene metal layers; wherein the gate contact includes a plurality of stacked damascene metal layers extending vertically to a level parallel to the top of the damascene structure; or wherein the field-effect transistor is a mesa structure, and wherein the gate contact and the gate metal form a vertical structure having sides and a top surrounded by an air gap formed between the source and drain electrodes and perpendicular to the gate direction between the edges of the mesa structure.

[0075] It should now be understood that the field-effect transistor structure according to this disclosure includes: a III-N buffer layer; a III-N channel layer disposed on the III-N buffer layer; a barrier layer disposed on the channel layer; wherein a 2DEG is formed in the channel layer; a horizontally extending doped GaN layer of uniform thickness disposed on the III-N buffer layer, the uniformly thick doped GaN layer having a vertically extending hole having vertically extending sidewalls terminating at the horizontally extending upper surface portion of the III-N buffer layer; and a gate electrode including: a vertical stem portion extending into the hole, which includes: a portion of the III-N buffer layer. A portion of a III-N channel layer and a portion of a buffer layer, the portion of the III-N buffer layer, the portion of the III-N channel layer and the portion of the buffer layer forming a vertical stack of the portion of the III-N buffer layer, the portion of the III-N channel layer and the portion of the buffer layer; wherein the vertical stack extends vertically upward into the hole and is located between the vertically extending sidewalls of the hole; and a gate metal disposed on the stack; source and drain contacts in ohmic contact with the upper surface portion of a horizontally extending doped GaN layer of uniform thickness; and wherein the gate electrode is disposed between the source and drain electrodes. The field-effect transistor structure may individually or in combination include one or more of the following features: a gate contact disposed on a gate metal, wherein the source and drain contacts have lower portions; wherein the gate contact and the lower portions of the source and drain contacts have upper surfaces disposed in a common plane; wherein the source and drain electrodes are damascene structures; wherein the gate contact and the gate metal form a vertical structure having sides and a top surrounded by an air gap that extends vertically to a level parallel to the top of the damascene structure; wherein the gate contact and the gate metal form a vertical structure having sides and a top surrounded by an air gap; wherein the gate contact includes a plurality of stacked damascene metal layers; or wherein the gate contact includes a plurality of stacked damascene metal layers that extend vertically to a level parallel to the top of the damascene structure.

[0076] It should now be understood that the method for forming a field-effect transistor according to this disclosure includes: forming a die on the surface of a semiconductor body; forming a first dielectric spacer layer having an inner sidewall located on an outer sidewall of the die and having a bottom located on the semiconductor body; forming a gate electrode having an inner sidewall located on an outer sidewall of the first dielectric spacer layer and having a bottom located on the semiconductor body; forming a second dielectric layer having an inner sidewall located on an outer sidewall of the gate electrode and having a bottom located on the semiconductor body; wherein the width of the first dielectric spacer layer is different from the width of the second dielectric spacer layer; and, after forming the first dielectric layer and the second dielectric layer, removing the die while leaving the bottom of the gate electrode on the semiconductor body.

[0077] It should now also be understood that the method for forming a field-effect transistor according to this disclosure (the field-effect transistor having a pair of electrically interconnected gate electrodes, one of which is disposed between a first source electrode and a drain electrode, and the other of which is disposed between a drain electrode and a second source electrode) includes: forming a die on the surface of a semiconductor body; forming a first pair of dielectric spacers, wherein each dielectric spacer has an inner sidewall located on a corresponding outer sidewall of a pair of opposing outer sidewalls of the die; forming the pair of gate electrodes, one of which is formed on the outer sidewall of a first pair of dielectric spacers, and the other of which is formed on a second pair of dielectric spacers; forming a second pair of dielectric spacers, wherein each dielectric spacer has an inner sidewall located on the outer sidewall of a corresponding one of the gate electrodes; wherein the widths of the first pair of dielectric spacers and the second pair of dielectric spacers are different; and removing the die after forming the first pair of dielectric layers and the second pair of dielectric layers.

[0078] Some embodiments of this disclosure have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of this disclosure. Therefore, other embodiments are also within the scope of the following claims.

Claims

1. A field-effect transistor, comprising: A gate contact and gate metal forming a vertical structure, the vertical structure having sides and top surrounded by an air gap formed between the source electrode and the drain electrode of the field-effect transistor; as well as A vertical stack, the vertical stack comprising: A portion of the III-N buffer layer, a portion of the III-N channel layer, and a portion of the III-V buffer layer; and A uniformly thick, horizontally extending doped GaN layer is disposed on the III-N buffer layer. The uniformly thick, horizontally extending doped GaN layer has a vertically extending hole with vertically extending sidewalls that terminate at the horizontally extending upper surface portion of the III-N buffer layer. The vertical stack extends vertically upward into the hole and is located between the vertically extending sidewalls of the hole. The vertical structure is disposed on the vertical stack.

2. The field-effect transistor according to claim 1, wherein, The source electrode and the drain electrode are an embedded structure.

3. The field-effect transistor according to claim 2, wherein, The vertical structure has sides and a top surrounded by an air gap that extends vertically to a level parallel to the top of the inlay structure.

4. The field-effect transistor according to claim 3, wherein, The gate contact comprises multiple stacked damascene metal layers.

5. The field-effect transistor according to claim 4, wherein, The gate contact comprises the plurality of stacked damascene metal layers that extend vertically to a horizontal plane parallel to the top of the damascene structure.

6. The field-effect transistor according to claim 5, wherein, The field-effect transistor is a mesa structure, wherein the vertical structure has sides and a top surrounded by an air gap formed between the source electrode and the drain electrode and between the edges of the mesa structure perpendicular to the direction of the gate.

7. A field-effect transistor structure, comprising: III-N buffer layer; III-N channel layer disposed on the III-N buffer layer; III-V barrier layer disposed on the III-N channel layer 2DEGs were formed in the channel layer; A uniform thickness, horizontally extending doped GaN layer is disposed on the III-N buffer layer. The uniform thickness, horizontally extending doped GaN layer has a vertically extending hole with vertically extending sidewalls that terminate at the horizontally extending upper surface portion of the III-N buffer layer. Gate electrode, comprising: A vertical stack, which includes: Part of the III-N buffer layer; A portion of the III-N channel layer; and Part of the III-V barrier layer Wherein, the vertical stack extends vertically upward into the hole and is located between the vertically extending sidewalls of the hole; and Gate metal disposed on the vertical stack; and Source and drain contacts that make ohmic contact with the upper surface portion of the uniformly thick, horizontally extending doped GaN layer; wherein the gate electrode is disposed between the source and drain contacts.

8. The field-effect transistor structure according to claim 7, comprising: A gate contact disposed on the gate metal, wherein the source contact and the drain contact have lower portions; and wherein the lower portions of the gate contact and the source contact and the drain contact have upper surfaces disposed in a common plane.

9. The field-effect transistor structure according to claim 8, wherein, The source and drain contacts are in an embedded structure.

10. The field-effect transistor structure according to claim 9, wherein, The gate contact and gate metal form a vertical structure having sides and a top surrounded by an air gap that extends vertically to a level parallel to the top of the inlay structure.

11. The field-effect transistor structure according to claim 8, wherein, The gate contact and gate metal form a vertical structure, the vertical structure having sides and a top surrounded by an air gap.

12. The field-effect transistor structure according to claim 10, wherein, The gate contact comprises multiple stacked damascene metal layers.

13. The field-effect transistor structure according to claim 12, wherein, The gate contact includes the plurality of stacked damascene metal layers that extend vertically to a horizontal level parallel to the top of the damascene structure.

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