Clock synchronization method, device and system

Abstract

The embodiments of this specification provide a method, device and system for clock synchronization, wherein the method for clock synchronization applied to a programmable device includes: in response to receiving a clock synchronization request, generating a DMA read instruction, reading a first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and updating the first timestamp to an internal clock, thereby achieving the effect of precise synchronization of the programmable device and the virtual machine clock.

Description

Technical Field

[0001] The embodiments of this specification relate to the field of computer technology, and in particular to a method for clock synchronization. One or more embodiments of this specification also relate to a clock synchronization apparatus, system, computing device, and computer-readable storage medium. Background Art

[0002] Programmable devices, such as field programmable gate arrays (FPGAs), solve the problem of customized circuits and can be used to design products for various industries. For example, based on programmable devices, software simulation can be used to create a complete computer system or virtual machine with complete hardware system functions and running in a completely isolated environment.

[0003] In some projects, programmable device time and virtual machine time are needed to perform time-related tasks. For example, in a network diagnosis project, it is necessary to conduct full-link latency analysis from application to kernel, programmable device, and virtual machine. Latency analysis generally considers the programmable device time and virtual machine time to be synchronized, and subtracts the absolute time to determine the network latency between the two.

[0004] However, since the virtual machine time and the programmable device time are not actually synchronized, it brings certain difficulties to the execution of related projects. Summary of the invention

[0005] In view of this, the embodiments of this specification provide a method for clock synchronization. One or more embodiments of this specification also relate to a clock synchronization device, system, computing device, and computer-readable storage medium to solve the technical defects existing in the prior art.

[0006] According to the first aspect of the embodiments of this specification, a clock synchronization method is provided, which is applied to a programmable device, including: in response to receiving a clock synchronization request, generating a DMA read instruction, reading a first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and updating the first timestamp to an internal clock, so that the programmable device is synchronized with the clock of the virtual machine.

[0007] Optionally, after updating the first timestamp to the internal clock, it also includes: controlling the internal clock to start timing based on the time value of the first timestamp; generating a DMA read instruction in response to receiving the next clock synchronization request; reading the second timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and simultaneously obtaining the first timing value of the internal clock; calculating the time compensation value using the difference between the first timing value and the second timestamp; compensating the first timing value using the time compensation value to obtain a compensated time value; updating the compensated time value to the internal clock to synchronize the clock of the programmable device with that of the virtual machine.

[0008] Optionally, the calculating of the time compensation value by using the difference between the first timing value and the second timestamp includes: obtaining the unit time compensation value according to the unit time compensation value being equal to the synchronization interval between both ends divided by the virtual machine synchronization interval, wherein the synchronization interval between both ends is equal to the absolute value of the difference between the first timing value and the second timestamp, and the virtual machine synchronization interval is equal to the difference between the second timestamp and the first timestamp. The compensating the first timing value by using the time compensation value to obtain the compensated time value includes: if the first timing value is greater than the second timestamp, obtaining a negative compensated time value according to the compensated time value being equal to the difference between the first timing value and the unit time compensation value; and obtaining a positive compensated time value according to the compensated time value being equal to the sum of the first timing value and the unit time compensation value if the first timing value is less than the second timestamp.

[0009] Optionally, generating a DMA read instruction in response to receiving a clock synchronization request includes: generating a DMA read instruction in response to receiving a clock synchronization request issued by a first program through a register write operation; the first program is a control program of the I / O interface between the virtual machine and the programmable device, and the clock synchronization request is generated by the first program in response to synchronization information received from the virtual machine, and the synchronization information is issued by the virtual machine to the first program when writing a first timestamp to the DMA memory.

[0010] Optionally, it also includes: setting a synchronization status register when a clock synchronization request is received; when the clock of the programmable device is synchronized with that of the virtual machine, it also includes: clearing the synchronization status register, so that when the first program detects that the synchronization status register is cleared through polling, it returns a synchronization completion status to the virtual machine, so that the virtual machine stops updating the timestamp on the DMA memory.

[0011] According to a second aspect of the embodiments of this specification, there is provided a clock synchronization device, which is configured in a programmable device, and includes: a read instruction generation module, configured to generate a DMA read instruction in response to receiving a clock synchronization request. A time reading module, configured to read a first timestamp currently written by a virtual machine from a DMA memory through the DMA read instruction. A time update module, configured to update the first timestamp to an internal clock, so that the programmable device is synchronized with the clock of the virtual machine.

[0012] According to the third aspect of the embodiments of this specification, a clock synchronization method is provided, which is applied to a virtual machine, including: writing the current first timestamp of the virtual machine into a DMA memory, and issuing synchronization information that enables a programmable device to receive a clock synchronization request; wherein the clock synchronization request enables the programmable device to generate a DMA read instruction, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and updates the first timestamp to an internal clock, so that the programmable device is synchronized with the clock of the virtual machine.

[0013] Optionally, writing the current first timestamp of the virtual machine into the DMA memory includes: writing the current timestamp of the virtual machine into the pre-allocated DMA memory at a preset frequency.

[0014] Optionally, the sending of synchronization information to enable the programmable device to receive a clock synchronization request includes: sending synchronization information to a first program so that the first program sends a corresponding clock synchronization request to the programmable device through a register write operation, and the first program is a control program of the I / O interface between the virtual machine and the programmable device.

[0015] Optionally, the method further includes: receiving a synchronization completion status returned when the first program detects through polling that the synchronization status register is cleared; and stopping updating the timestamp on the DMA memory.

[0016] According to the fourth aspect of the embodiments of this specification, there is provided a clock synchronization device, which is configured in a virtual machine, and includes: a time writing module, which is configured to write the current first timestamp of the virtual machine into the DMA memory. An information issuing module, which is configured to issue synchronization information that enables the programmable device to receive a clock synchronization request. The clock synchronization request enables the programmable device to generate a DMA read instruction, and read the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and update the first timestamp to the internal clock, so that the programmable device is synchronized with the clock of the virtual machine.

[0017] According to a fifth aspect of the embodiments of this specification, a clock synchronization system is provided, comprising: a virtual machine, configured to write a current first timestamp of the virtual machine into a DMA memory, and to issue synchronization information for a programmable device to receive a clock synchronization request. The programmable device is configured to generate a DMA read instruction in response to receiving the clock synchronization request, read the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, update the first timestamp to an internal clock, and synchronize the clock of the programmable device with that of the virtual machine.

[0018] According to the sixth aspect of the embodiments of this specification, a computing device is provided, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the clock synchronization method described in any embodiment of this specification.

[0019] According to the seventh aspect of the embodiments of this specification, a computer-readable storage medium is provided, which stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the steps of the clock synchronization method described in any embodiment of this specification are implemented.

[0020] An embodiment of the present specification provides a method for clock synchronization applied to a programmable device. Since the programmable device generates a DMA read instruction in response to receiving a clock synchronization request, the first timestamp currently written by the virtual machine is read from the DMA memory through the DMA read instruction, and the first timestamp is updated to the internal clock. Therefore, the virtual machine and the programmable device synchronize the clock by using shared DMA memory, so that the programmable device reads the current timestamp of the virtual machine from the DMA memory, reducing the intermediate process and achieving the effect of accurate synchronization of the programmable device and the virtual machine clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flow chart of a clock synchronization method provided by an embodiment of this specification;

[0022] Figure 2 is a schematic diagram of a clock synchronization process provided by an embodiment of this specification;

[0023] Figure 3 It is a structural schematic diagram of a clock synchronization device provided by an embodiment of this specification;

[0024] Figure 4 is a structural schematic diagram of a clock synchronization device provided by another embodiment of the present specification;

[0025] Figure 5is a flow chart of a clock synchronization method provided by another embodiment of this specification;

[0026] Figure 6 is a structural schematic diagram of a clock synchronization device provided by another embodiment of the present specification;

[0027] Figure 7 It is a structural diagram of a clock synchronization system provided by an embodiment of this specification;

[0028] Figure 8 It is a structural block diagram of a computing device provided by an embodiment of this specification. DETAILED DESCRIPTION

[0029] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0030] The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms of "a", "said" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0031] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0032] First, the terms involved in one or more embodiments of this specification are explained:

[0033] A virtual machine (VM) is a complete computer system that is simulated by software and has complete hardware system functions and runs in a completely isolated environment.

[0034] Clock synchronization is the process of providing a unified time scale for distributed systems through certain operations on local clocks.

[0035] FPGA, Field Programmable Gate Array, is a product further developed on the basis of programmable devices such as PAL and GAL. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0036] In this specification, a clock synchronization method is provided. This specification also relates to a clock synchronization device, a computing device, and a computer-readable storage medium, which are described in detail one by one in the following embodiments.

[0037] Figure 1 A flowchart of a clock synchronization method provided according to an embodiment of the present specification is shown. The method can be applied to a programmable device and includes steps 102 to 106.

[0038] Step 102: In response to receiving a clock synchronization request, generate a DMA read instruction.

[0039] For example, the clock synchronization request may be issued by the virtual machine or the control program of the I / O interface between the virtual machine and the programmable hardware to the programmable hardware, and may be generated when the virtual machine writes the first timestamp to the DMA memory and issues a synchronization instruction. The timestamp may be stored in the computer in a numerical value for indicating time.

[0040] Step 104: read the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction.

[0041] Step 106: Update the first timestamp to the internal clock to synchronize the clock of the programmable device with that of the virtual machine.

[0042] It should be noted that the first time is updated to the internal clock, and the internal clock is timed based on the first time. If time compensation is not considered, the programmable device and the virtual machine clock can be basically synchronized based on the first time. If time compensation is considered, after the first time is updated to the internal clock, some error evaluation methods can be used to perform time compensation, and the compensated time value can be updated to the internal clock, so that the programmable device and the virtual machine clock can be accurately synchronized.

[0043] For example, in an FPGA, the internal clock can be a 64-bit counter that starts counting when the FPGA is powered on and can be updated by the FPGA at any time as needed.

[0044] Since the programmable device generates a DMA read instruction in response to receiving a clock synchronization request, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and updates the first timestamp to the internal clock, the virtual machine and the programmable device synchronize the clock by using the shared DMA memory, so that the programmable device reads the current timestamp of the virtual machine from the DMA memory, reducing the intermediate process and achieving the effect of accurate synchronization of the programmable device and the virtual machine clock.

[0045] Next, an implementation method of assisting the front-end and back-end cooperation in clock synchronization through a control program of an I / O interface between a virtual machine and a programmable device is described in detail.

[0046] For example, a programmable device generates a DMA read instruction in response to receiving a clock synchronization request, which may include: generating a DMA read instruction in response to receiving a clock synchronization request issued by a first program through a register write operation; the first program is a control program of the I / O interface between the virtual machine and the programmable device, and the clock synchronization request is generated by the first program in response to synchronization information received from the virtual machine, and the synchronization information is sent by the virtual machine to the first program when writing a first timestamp to the DMA memory.

[0047] The first program may be a component of a front-end or back-end program responsible for front-end and back-end interaction in a system architecture with a virtual machine as the front-end and a programmable device as the back-end. The front-end or back-end program is a program that implements data exchange between the virtual machine and the host machine. In this embodiment, the clock synchronization request is sent to the programmable device through the first program to avoid the virtual machine directly sending information to the programmable device to affect the normal execution of the virtual machine.

[0048] In addition, in order to reduce the additional consumption of computing resources, in one or more embodiments of the present specification, the programmable device may also set the synchronization status register when receiving a clock synchronization request; when the programmable device is synchronized with the clock of the virtual machine, the synchronization status register is cleared, so that when the first program detects through polling that the synchronization status register is cleared, it returns the synchronization completion status to the virtual machine, so that the virtual machine stops updating the timestamp on the DMA memory.

[0049] Taking FPGA as an example, the virtual machine timestamp update can be enabled before starting time synchronization. For example, the virtual machine software can send clock synchronization instructions to the FPGA through the PCIe register channel. In order to avoid the problems of long paths, large delays, and inaccurate synchronization when the timestamp is synchronized through software, according to the above embodiment, the first program can be used to notify the FPGA hardware DMA read synchronization to reduce the intermediate process. The specific process includes:

[0050] Before the virtual machine software starts time synchronization, enable timestamp update first;

[0051] The virtual machine software writes the current timestamp of the virtual machine to the pre-allocated DMA memory at a frequency of, for example, every 10us;

[0052] The virtual machine software sends a synchronization instruction to the first program;

[0053] The first program notifies the FPGA that synchronization is required through a register write operation, and the FPGA internal synchronization status register is set;

[0054] The FPGA generates a DMA read instruction, reads the virtual machine timestamp value back to the FPGA, and then updates it to the internal counter; at the same time, the synchronization status register is cleared;

[0055] The first program detects the status of the synchronization status register by polling, and a "0" indicates that the synchronization is completed, and returns the synchronization status to the virtual machine software;

[0056] The virtual machine software stops updating the timestamp on the DMA memory;

[0057] After the above process, the timestamp of the FPGA's internal clock is synchronized with the virtual machine's clock.

[0058] Due to possible reasons such as the timing jitter of the internal clock, there may be a certain amount of time error accumulation after a period of time after the clock is synchronized. Therefore, in practical applications, in order to ensure the synchronization of the timestamps in the network data stream of the board containing programmable devices and the virtual machine, clock synchronization can be triggered regularly, for example, time synchronization is performed every 3 seconds, so as to reduce the degree of time error accumulation between the virtual machine and the programmable device. At the same time, the programmable device can perform some error compensation to minimize the time error at both ends.

[0059] For example, the FPGA internal clock is the value of a 64-bit counter. This counter uses the FPGA master clock to count, and the clock frequency is 200MHz. For example, the specification of the clock crystal is ±20ppm, and the theoretical maximum deviation is 40us / s. Therefore, after the FPGA internal clock is synchronized with the virtual machine, there will be a certain deviation after a period of time, and this count value needs to be corrected.

[0060] Therefore, the method provided in the embodiment of the present specification, after updating the first timestamp to the internal clock, also includes: controlling the internal clock to start timing based on the time value of the first timestamp; generating a DMA read instruction in response to receiving the next clock synchronization request; reading the second timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and simultaneously obtaining the first timing value of the internal clock; calculating the time compensation value using the difference between the first timing value and the second timestamp; compensating the first timing value using the time compensation value to obtain the compensated time value; updating the compensated time value to the internal clock to synchronize the clock of the programmable device with that of the virtual machine.

[0061] In this embodiment, since the first timing value is the time value of the internal clock at the next synchronization, and the second timestamp is the time value of the virtual machine at the next synchronization, the cumulative error of the internal clock can be evaluated based on the difference between the two, the timing of the internal clock can be compensated, and the accuracy of clock synchronization can be improved.

[0062] The method provided in the embodiments of this specification does not limit the specific implementation method of how to use the difference between the first timing value and the second timestamp to evaluate the cumulative error and compensate. For example, in some implementations, the difference between the two can be taken as an intermediate value to obtain a time compensation value for compensation, and positive and negative compensation can be performed based on the first timing value. For example, in other implementations, the unit time compensation value can be calculated more precisely and used to compensate for more accurately.

[0063] Next, combine Figure 2 The schematic diagram of the clock synchronization process shown in FIG. 1 is used to explain in detail the principle of the implementation method of using the unit time compensation value for compensation:

[0064] During the first synchronization, the virtual machine CN (VM) writes the current time value T1 to the DMA memory, and the programmable device (FPGA in MOC) sends a request for a DMA read instruction (request) to read T1 back (reponse with data (T1)). The internal clock of the programmable device is refreshed to T1 at this time, and then starts timing, such as adding 1 every 1us. During the first synchronization, the time deviation between the internal clock of the programmable device and the virtual machine is T DELAY1 (Synchronization delay), that is, virtual machine time T VM Equal to the time T of the internal clock FPGA With synchronization delay T DELAY1 The sum of T VM =T FPGA +T DELAY1 .

[0065] During the second synchronization, the virtual machine writes the current time value T2 to the DMA memory, and the programmable device sends a DMA read instruction request (request) to read T2 back (reponse with data (T2)). The internal clock of the programmable device now times to T3. Assuming that the second synchronization delay is T DELAY2 ,but:

[0066] Clock deviation between the two sides T diff =|(T3-T1)-(T2-T1)|+|T DELAY2 -T DELAY1 |, where T3-T1 is the time interval between two synchronizations of the internal clock, and T2-T1 is the time interval between two synchronizations of the virtual machine.

[0067] Assuming that the two synchronization delays are the same, the clock deviation on both sides is T diff =|T3-T2|, and the interval between the two synchronizations is T WIN =T2-T1, the unit time compensation value δ=T diff / T WIN =|T3-T2| / (T2-T1), which is the compensation time value between two synchronizations. The programmable device can use this unit time compensation value to perform positive or negative compensation on the time of the internal clock.

[0068] In summary, the calculation of the time compensation value by using the difference between the first timing value and the second timestamp may include: obtaining the unit time compensation value according to the unit time compensation value being equal to the synchronization interval between both ends divided by the virtual machine synchronization interval, wherein the synchronization interval between both ends is equal to the absolute value of the difference between the first timing value and the second timestamp, and the virtual machine synchronization interval is equal to the difference between the second timestamp and the first timestamp. The compensation of the first timing value by using the time compensation value to obtain the compensated time value may include: if the first timing value is greater than the second timestamp, obtaining the negative compensated time value according to the compensated time value being equal to the difference between the first timing value and the unit time compensation value; and obtaining the positive compensated time value according to the compensated time value being equal to the sum of the first timing value and the unit time compensation value if the first timing value is less than the second timestamp.

[0069] For example, the use of the difference between the first timing value and the second timestamp to calculate the time compensation value includes: according to the unit time compensation value being equal to the synchronization interval between both ends divided by the virtual machine synchronization interval, obtaining the unit time compensation value, wherein the synchronization interval between both ends is equal to the absolute value of the difference between the first timing value and the second timestamp, and the virtual machine synchronization interval is equal to the difference between the second timestamp and the first timestamp. The use of the time compensation value to compensate the first timing value to obtain the compensated time value includes: if the first timing value is greater than the second timestamp, according to the compensated time value being equal to the difference between the first timing value and the unit time compensation value, obtaining a negative compensated time value; if the first timing value is less than the second timestamp, according to the compensated time value being equal to the sum of the first timing value and the unit time compensation value, obtaining a positive compensated time value.

[0070] It can be seen that by performing two clock synchronizations, when T DELAY1 =T DELAY2 In the case of, the unit time compensation value can be calculated by the above calculation method to obtain the compensated time value.

[0071] In some other implementations, due to the influence of delay deviation of register channels, the delay of two synchronization processes may not be consistent. In this case, in order to make clock compensation more accurate, T DELAY1 With T DELAY2 The deviation between them is evaluated and involved in the above compensation calculation, and the method provided in the embodiment of this specification is not limited to this.

[0072] Corresponding to the above method embodiment, this specification also provides a clock synchronization device embodiment configured in a programmable device. Figure 3 FIG. 1 is a schematic diagram showing the structure of a clock synchronization device provided by an embodiment of the present specification. Figure 3 As shown, the device includes: a read instruction generating module 302 , a time reading module 304 and a time updating module 306 .

[0073] The read instruction generation module 302 may be configured to generate a DMA read instruction in response to receiving a clock synchronization request.

[0074] The time reading module 304 may be configured to read the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction.

[0075] The time updating module 306 may be configured to update the first timestamp to an internal clock so as to synchronize the clocks of the programmable device and the virtual machine.

[0076] Since the programmable device generates a DMA read instruction in response to receiving a clock synchronization request, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and updates the first timestamp to the internal clock, the virtual machine and the programmable device synchronize the clock by using the shared DMA memory, so that the programmable device reads the current timestamp of the virtual machine from the DMA memory, reducing the intermediate process and achieving the effect of accurate synchronization of the programmable device and the virtual machine clock.

[0077] Figure 4 FIG. 2 shows a schematic diagram of a clock synchronization device provided by another embodiment of the present specification. Figure 4 As shown, the device may further include: a timing control module 308 , a secondary synchronization receiving module 310 , a time acquisition module 312 at both ends, a compensation calculation module 314 , and a time compensation module 316 .

[0078] The timing control module 308 may be configured to control the internal clock to start timing based on the time value of the first timestamp after the first timestamp is updated to the internal clock.

[0079] The secondary synchronization receiving module 310 may be configured to generate a DMA read instruction in response to receiving a next clock synchronization request.

[0080] The two-end time acquisition module 312 may be configured to read the second timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and simultaneously acquire the first timing value of the internal clock.

[0081] The compensation calculation module 314 may be configured to calculate a time compensation value using a difference between the first timing value and the second timestamp.

[0082] The time compensation module 316 may be configured to compensate the first timing value using the time compensation value to obtain a compensated time value.

[0083] The time updating module 306 may also be configured to update the compensated time value to an internal clock so that the programmable device is synchronized with the clock of the virtual machine.

[0084] In this embodiment, since the first timing value is the time value of the internal clock at the next synchronization, and the second timestamp is the time value of the virtual machine at the next synchronization, the cumulative error of the internal clock can be evaluated based on the difference between the two, the timing of the internal clock can be compensated, and the accuracy of clock synchronization can be improved.

[0085] Specifically, for example, the compensation calculation module 314 can be configured to obtain a unit time compensation value according to a unit time compensation value being equal to the synchronization interval between both ends divided by the virtual machine synchronization interval, wherein the synchronization interval between both ends is equal to the absolute value of the difference between the first timing value and the second timestamp, and the virtual machine synchronization interval is equal to the difference between the second timestamp and the first timestamp. The time compensation module 316 can be configured to obtain a negative compensated time value according to a compensated time value being equal to the difference between the first timing value and the unit time compensation value if the first timing value is greater than the second timestamp; and obtain a positive compensated time value according to a compensated time value being equal to the sum of the first timing value and the unit time compensation value if the first timing value is less than the second timestamp.

[0086] Next, the implementation method of assisting the front-end and back-end cooperation in clock synchronization through the control program of the I / O interface between the virtual machine and the programmable device is described in detail. Figure 4 As shown, the read instruction generation module 302 can be configured to generate a DMA read instruction in response to receiving a clock synchronization request issued by a first program through a register write operation; the first program is a control program of the I / O interface between the virtual machine and the programmable device, and the clock synchronization request is generated by the first program in response to the synchronization information received from the virtual machine, and the synchronization information is sent by the virtual machine to the first program when writing a first timestamp to the DMA memory.

[0087] For example, the device may also include: a synchronization status update module 318, which can be configured to set the synchronization status register when a clock synchronization request is received, and clear the synchronization status register when the clock of the programmable device is synchronized with the clock of the virtual machine, so that when the first program detects that the synchronization status register is cleared through polling, it returns a synchronization completion status to the virtual machine, so that the virtual machine stops updating the timestamp on the DMA memory.

[0088] The above is a schematic scheme of the clock synchronization apparatus configured in a programmable device of this embodiment. It should be noted that the technical scheme of the clock synchronization apparatus configured in a programmable device and the technical scheme of the clock synchronization method applied to a programmable device belong to the same concept, and the details of the technical scheme of the clock synchronization apparatus configured in a programmable device that are not described in detail can all be referred to the description of the technical scheme of the clock synchronization method applied to a programmable device.

[0089] Corresponding to the above-mentioned clock synchronization method embodiment applied to a programmable device, this specification also provides a clock synchronization method applied to a virtual machine. Figure 5 FIG. 1 is a flow chart of a clock synchronization method provided by an embodiment of the present specification. Figure 5 As shown, the method may include: step 502 and step 504.

[0090] Step 502: Write the current first timestamp of the virtual machine into the DMA memory.

[0091] Step 504: Send synchronization information to enable the programmable device to receive a clock synchronization request.

[0092] Among them, the clock synchronization request enables the programmable device to generate a DMA read instruction, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, updates the first timestamp to the internal clock, and synchronizes the clock of the programmable device with that of the virtual machine.

[0093] It should be noted that there is no mandatory execution order between step 502 and step 504, and step 502 may be executed first, or step 504 may be executed first. In the case where the virtual machine writes updated timestamps to the DMA memory at a certain frequency, the first timestamp is the latest timestamp written by the virtual machine when the programmable device reads the timestamp from the DMA.

[0094] Since the virtual machine writes the current first timestamp of the virtual machine into the DMA memory and sends out synchronization information for the programmable device to receive the clock synchronization request, the programmable device generates a DMA read instruction in response to receiving the clock synchronization request, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and updates the first timestamp to the internal clock. Therefore, the virtual machine and the programmable device synchronize the clock by using the shared DMA memory, so that the programmable device reads the current timestamp of the virtual machine from the DMA memory, reducing the intermediate process and achieving the effect of accurate synchronization of the programmable device and the virtual machine clock.

[0095] In order to ensure the accuracy of clock synchronization as much as possible and reduce the time consumption during the synchronization process, in one or more embodiments of this specification, writing the current first timestamp of the virtual machine into the DMA memory includes: writing the current timestamp of the virtual machine to the pre-allocated DMA memory at a preset frequency.

[0096] In one or more embodiments, the sending of synchronization information for the programmable device includes: sending synchronization information to a first program, so that the first program sends a corresponding clock synchronization request to the programmable device through a register write operation, and the first program is a control program of the I / O interface between the virtual machine and the programmable device. In this embodiment, the clock synchronization request is sent to the programmable device through the first program, so as to avoid the virtual machine directly sending information to the programmable device to affect the normal execution of tasks by the virtual machine.

[0097] In order to reduce the additional consumption of computing resources, in one or more embodiments of the present specification, the method further includes: receiving the synchronization completion status returned when the first program detects that the synchronization status register is cleared by polling; and stopping updating the timestamp on the DMA memory.

[0098] The above is a schematic scheme of the method for clock synchronization applied to a virtual machine of this embodiment. It should be noted that the technical scheme of the method for clock synchronization applied to a virtual machine and the technical scheme of the method for clock synchronization applied to a programmable device described above belong to the same concept, and the details of the technical scheme of the method for clock synchronization applied to a virtual machine that are not described in detail can all be referred to the description of the technical scheme of the method for clock synchronization applied to a programmable device described above.

[0099] Corresponding to the above-mentioned clock synchronization method embodiment applied to a programmable device, this specification also provides a clock synchronization device configured in a virtual machine. Figure 6 FIG. 1 is a schematic diagram showing the structure of a clock synchronization device provided by an embodiment of the present specification. Figure 6 As shown, the device may include: a time writing module 602 and an information sending module 604.

[0100] The time writing module 602 may be configured to write the current first timestamp of the virtual machine into the DMA memory.

[0101] The information issuing module 604 may be configured to issue synchronization information for enabling the programmable device to receive a clock synchronization request.

[0102] Among them, the clock synchronization request enables the programmable device to generate a DMA read instruction, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, updates the first timestamp to the internal clock, and synchronizes the clock of the programmable device with that of the virtual machine.

[0103] Since the virtual machine writes the current first timestamp of the virtual machine into the DMA memory and sends out synchronization information for the programmable device to receive the clock synchronization request, the programmable device generates a DMA read instruction in response to receiving the clock synchronization request, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and updates the first timestamp to the internal clock. Therefore, the virtual machine and the programmable device synchronize the clock by using the shared DMA memory, so that the programmable device reads the current timestamp of the virtual machine from the DMA memory, reducing the intermediate process and achieving the effect of accurate synchronization of the programmable device and the virtual machine clock.

[0104] For example, the time writing module 602 may be configured to write the current timestamp of the virtual machine into the pre-allocated DMA memory at a preset frequency.

[0105] The information sending module 604 can be configured to send synchronization information to the first program, so that the first program sends a corresponding clock synchronization request to the programmable device through a register write operation. The first program is a control program of the I / O interface between the virtual machine and the programmable device.

[0106] In order to reduce the consumption of computing resources, the time writing module 602 can also be configured to receive the synchronization completion status returned when the first program detects that the synchronization status register is cleared through polling, and stop updating the timestamp on the DMA memory.

[0107] The above is a schematic scheme of the clock synchronization device configured in the virtual machine of this embodiment. It should be noted that the technical scheme of the clock synchronization device configured in the virtual machine and the technical scheme of the clock synchronization method applied to the programmable device described above belong to the same concept, and the details of the technical scheme of the clock synchronization device configured in the virtual machine that are not described in detail can all be referred to the description of the technical scheme of the clock synchronization method applied to the programmable device described above.

[0108] Figure 7 FIG. 1 is a schematic diagram showing the structure of a clock synchronization system provided by an embodiment of the present specification. Figure 7 As shown, the system may include: a virtual machine 702 and a programmable device 704 .

[0109] The virtual machine 702 may be configured to write the current first timestamp of the virtual machine into the DMA memory, and to issue synchronization information for enabling the programmable device to receive a clock synchronization request.

[0110] The programmable device 704 can be configured to generate a DMA read instruction in response to receiving a clock synchronization request, read the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, update the first timestamp to the internal clock, and synchronize the clock of the programmable device with that of the virtual machine.

[0111] Figure 8 The block diagram of a computing device 800 according to an embodiment of the present specification is shown. The components of the computing device 800 include but are not limited to a memory 810 and a processor 820. The processor 820 is connected to the memory 810 via a bus 830, and a database 850 is used to store data.

[0112] The computing device 800 also includes an access device 840 that enables the computing device 800 to communicate via one or more networks 860. Examples of these networks include a public switched telephone network (PSTN), a local area network (LAN), a wide area network (WAN), a personal area network (PAN), or a combination of communication networks such as the Internet. The access device 840 may include one or more of any type of network interface (e.g., a network interface card (NIC)) that is wired or wireless, such as an IEEE 802.11 wireless local area network (WLAN) wireless interface, a World Wide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a universal serial bus (USB) interface, a cellular network interface, a Bluetooth interface, a near field communication (NFC) interface, and the like.

[0113] In one embodiment of the present specification, the above components of the computing device 800 and Figure 8 Other components not shown in the figure may also be connected to each other, for example, via a bus. It should be understood that Figure 8 The computing device structure block diagram shown is only for the purpose of illustration, and is not intended to limit the scope of this specification. Those skilled in the art can add or replace other components as needed.

[0114] The computing device 800 may be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., a tablet computer, a personal digital assistant, a laptop computer, a notebook computer, a netbook, etc.), a mobile phone (e.g., a smart phone), a wearable computing device (e.g., a smart watch, smart glasses, etc.), or other types of mobile devices, or a stationary computing device such as a desktop computer or PC. The computing device 800 may also be a mobile or stationary server.

[0115] The processor 820 is used to execute the following computer executable instructions:

[0116] In response to receiving a clock synchronization request, a DMA read instruction is generated; a first timestamp currently written by the virtual machine is read from the DMA memory through the DMA read instruction; the first timestamp is updated to an internal clock to synchronize the clock of the programmable device with that of the virtual machine.

[0117] or,

[0118] Write the current first timestamp of the virtual machine into the DMA memory, and issue synchronization information to enable the programmable device to receive a clock synchronization request; wherein the clock synchronization request enables the programmable device to generate a DMA read instruction, and read the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, update the first timestamp to the internal clock, and synchronize the clock of the programmable device with that of the virtual machine.

[0119] The above is a schematic scheme of a computing device of this embodiment. It should be noted that the technical scheme of the computing device and the technical scheme of the clock synchronization method described above are of the same concept, and the details not described in detail in the technical scheme of the computing device can be referred to the description of the technical scheme of the clock synchronization method described above.

[0120] An embodiment of the present specification further provides a computer-readable storage medium storing computer instructions, which are used when executed by a processor to:

[0121] In response to receiving a clock synchronization request, a DMA read instruction is generated; a first timestamp currently written by the virtual machine is read from the DMA memory through the DMA read instruction; the first timestamp is updated to an internal clock to synchronize the clock of the programmable device with that of the virtual machine.

[0122] or,

[0123] Write the current first timestamp of the virtual machine into the DMA memory, and issue synchronization information to enable the programmable device to receive a clock synchronization request; wherein the clock synchronization request enables the programmable device to generate a DMA read instruction, and read the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, update the first timestamp to the internal clock, and synchronize the clock of the programmable device with that of the virtual machine.

[0124] The above is a schematic scheme of a computer-readable storage medium of this embodiment. It should be noted that the technical scheme of the storage medium and the technical scheme of the clock synchronization method described above belong to the same concept, and the details not described in detail in the technical scheme of the storage medium can be referred to the description of the technical scheme of the clock synchronization method described above.

[0125] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0126] The computer instructions include computer program codes, which may be in source code form, object code form, executable files or some intermediate forms, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0127] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0128] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0129] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to only the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of this specification, so that technicians in the relevant technical field can well understand and use this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A clock synchronization method, applied to a programmable device, comprising: In response to receiving a clock synchronization request, generating a DMA read instruction, wherein the clock synchronization request is generated when the virtual machine writes a first timestamp to the DMA memory and issues a synchronization instruction, and the first timestamp is a latest timestamp written by the virtual machine when the programmable device reads the timestamp from the DMA; Reading the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction; The first timestamp is updated to the internal clock so that the programmable device is synchronized with the clock of the virtual machine, wherein after the first timestamp is updated to the internal clock, a second synchronization is included. When the second synchronization has the same synchronization delay, the programmable device uses a unit time compensation value to perform positive and negative compensation on the time of the internal clock, and the unit time compensation value is calculated by the synchronization interval at both ends and the synchronization interval of the virtual machine.

2. The method according to claim 1, after updating the first timestamp to the internal clock, further comprising: Controlling an internal clock to start timing based on the time value of the first timestamp; In response to receiving a next clock synchronization request, generating a DMA read instruction; Reading the second timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, and simultaneously obtaining the first timing value of the internal clock; Calculating a time compensation value using a difference between the first timing value and the second timestamp; Compensating the first timing value using the time compensation value to obtain a compensated time value; The compensated time value is updated to an internal clock so that the programmable device is synchronized with the clock of the virtual machine.

3. The method according to claim 2, wherein the calculating the time compensation value by using the difference between the first timing value and the second timestamp comprises: The unit time compensation value is obtained according to that the unit time compensation value is equal to the synchronization interval between both ends divided by the virtual machine synchronization interval, wherein the synchronization interval between both ends is equal to the absolute value of the difference between the first timing value and the second timestamp, and the virtual machine synchronization interval is equal to the difference between the second timestamp and the first timestamp; The using the time compensation value to compensate the first timing value to obtain a compensated time value includes: If the first timing value is greater than the second timestamp, a negative compensated time value is obtained according to the compensated time value being equal to the difference between the first timing value and the unit time compensation value; If the first timing value is less than the second timestamp, a positive compensated time value is obtained according to the compensated time value being equal to the sum of the first timing value and the unit time compensation value.

4. The method according to claim 1, wherein in response to receiving a clock synchronization request, generating a DMA read instruction comprises: In response to receiving a clock synchronization request issued by the first program through a register write operation, generating a DMA read instruction; The first program is a control program of the I / O interface between the virtual machine and the programmable device. The clock synchronization request is generated by the first program in response to synchronization information received from the virtual machine. The synchronization information is sent by the virtual machine to the first program when writing a first timestamp to the DMA memory.

5. The method according to claim 4, further comprising: When receiving a clock synchronization request, the synchronization status register is set; When the programmable device is synchronized with the clock of the virtual machine, it also includes: clearing the synchronization status register, so that when the first program detects that the synchronization status register is cleared through polling, it returns the synchronization completion status to the virtual machine, so that the virtual machine stops updating the timestamp on the DMA memory.

6. A clock synchronization device, configured in a programmable device, comprising: A read instruction generation module is configured to generate a DMA read instruction in response to receiving a clock synchronization request, wherein the clock synchronization request is generated when the virtual machine writes a first timestamp to the DMA memory and issues a synchronization instruction, and the first timestamp is a latest timestamp written by the virtual machine when the programmable device reads the timestamp from the DMA; A time reading module is configured to read the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction; A time update module is configured to update the first timestamp to an internal clock so that the programmable device is synchronized with the clock of the virtual machine, wherein after the first timestamp is updated to the internal clock, a second synchronization is included. When the second synchronization has the same synchronization delay, the programmable device uses a unit time compensation value to perform positive and negative compensation on the time of the internal clock, and the unit time compensation value is calculated by the synchronization interval at both ends and the synchronization interval of the virtual machine.

7. A clock synchronization method, applied to a virtual machine, comprising: Writing the current first timestamp of the virtual machine into the DMA memory, and issuing synchronization information for causing the programmable device to receive a clock synchronization request, wherein the first timestamp is the latest timestamp written by the virtual machine when the programmable device reads the timestamp from the DMA; Among them, the clock synchronization request enables the programmable device to generate a DMA read instruction, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, updates the first timestamp to the internal clock, and synchronizes the clock of the programmable device with that of the virtual machine. Among them, after updating the first timestamp to the internal clock, it includes a second synchronization. When the second synchronization has the same synchronization delay, the programmable device uses a unit time compensation value to perform positive and negative compensation on the time of the internal clock. The unit time compensation value is calculated by the synchronization interval at both ends and the synchronization interval of the virtual machine.

8. The method according to claim 7, wherein writing the current first timestamp of the virtual machine into the DMA memory comprises: Write the current timestamp of the virtual machine to the pre-allocated DMA memory at a preset frequency.

9. The method according to claim 7, wherein the step of issuing synchronization information for causing the programmable device to receive a clock synchronization request comprises: The synchronization information is sent to the first program, so that the first program sends a corresponding clock synchronization request to the programmable device through a register write operation, wherein the first program is a control program of the I / O interface between the virtual machine and the programmable device.

10. The method according to claim 9, further comprising: receiving a synchronization completion status returned when the first program detects through polling that the synchronization status register is cleared; Stop timestamp updates on DMA memory.

11. A clock synchronization device, configured in a virtual machine, comprising: A time writing module is configured to write a current first timestamp of the virtual machine into the DMA memory, wherein the first timestamp is a latest timestamp written by the virtual machine when the programmable device reads the timestamp from the DMA; An information sending module is configured to send synchronization information for enabling the programmable device to receive a clock synchronization request; Among them, the clock synchronization request enables the programmable device to generate a DMA read instruction, and reads the first timestamp currently written by the virtual machine from the DMA memory through the DMA read instruction, updates the first timestamp to the internal clock, and synchronizes the clock of the programmable device with that of the virtual machine. Among them, after updating the first timestamp to the internal clock, it includes a second synchronization. When the second synchronization has the same synchronization delay, the programmable device uses a unit time compensation value to perform positive and negative compensation on the time of the internal clock. The unit time compensation value is calculated by the synchronization interval at both ends and the synchronization interval of the virtual machine.

12. A clock synchronization system, comprising: The virtual machine is configured to write a current first timestamp of the virtual machine into the DMA memory, and to issue synchronization information for causing the programmable device to receive a clock synchronization request, wherein the first timestamp is a latest timestamp written by the virtual machine when the programmable device reads the timestamp from the DMA; A programmable device is configured to generate a DMA read instruction in response to receiving a clock synchronization request, read a first timestamp currently written by a virtual machine from a DMA memory through the DMA read instruction, update the first timestamp to an internal clock, and synchronize the clock of the programmable device with that of the virtual machine, wherein after updating the first timestamp to the internal clock, a second synchronization is included, and when the second synchronization has the same synchronization delay, the programmable device uses a unit time compensation value to perform positive and negative compensation on the time of the internal clock, and the unit time compensation value is calculated by the synchronization interval at both ends and the synchronization interval of the virtual machine.

13. A computing device comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the clock synchronization method described in any one of claims 1 to 5 or 7 to 10 are implemented.

14. A computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the steps of the clock synchronization method according to any one of claims 1 to 5 or 7 to 10.

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