A multi-processor instruction execution method, computing device and storage medium

Abstract

The present invention discloses a multi-processor instruction execution method, a computing device and a storage medium, and includes the steps of: submitting a first operation instruction for an application to access data in an internal memory to a first processor; when the first processor cannot normally execute the first operation instruction due to the storage address of the data accessed by the first operation instruction, generating a second operation instruction according to the data access exception message generated by the first processor, and the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction; submitting the second operation instruction to the first processor so that the first processor accesses the data in the internal memory according to the second operation instruction; when the second processor executes the first operation instruction, submitting the second operation instruction to the second processor so that the second processor accesses the data in the internal memory according to the second operation instruction. The present invention can reduce the need to perform a cache flushing operation on the processor when the processors do not execute the instruction at the same time, thereby improving the system operation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer instruction execution, and in particular to a multi-processor instruction execution method, a computing device and a storage medium. Background Art

[0002] With the continuous development of computer technology, more and more applications have been developed. Correspondingly, the application data is increasing, and the data structure is becoming more and more complex. Therefore, the system's access performance to complex data structures in memory is becoming more and more important, directly affecting the running speed of key applications. When storing data, special storage situations often occur. When applications access these stored data, the processor does not support special access instructions for the data, and an error will occur. The processor cannot directly process such access instructions to read data.

[0003] Therefore, in the prior art, in order to access these stored data, a method of changing the data storage method is adopted, so that the instructions for application access to these data become normal instructions, and the processor can execute and read the data. However, due to the large number of application programs, the data storage structure that needs to be modified is also very large, and some data storage structures may not be convenient to modify. The workload is not only very huge, but also cannot solve all data storage problems. This method is even more unable to coordinate the data storage structure to be modified in the case of multiple processors.

[0004] Therefore, a new multi-processor instruction execution method is needed. Summary of the invention

[0005] To this end, the present invention provides an instruction execution method for a multi-processor, in an effort to solve or at least alleviate the above problems.

[0006] According to one aspect of the present invention, there is provided a method for executing instructions of a multi-processor, which is suitable for execution in a computing device, wherein the computing device comprises a first processor, a second processor, an internal memory, and runs one or more applications, wherein a storage area of ​​the internal memory is mapped to a storage space, and the application accesses data in the internal memory with a storage address in the storage space, and the method comprises the steps of: submitting a first operation instruction for the application to access data in the internal memory to the first processor; when the first processor cannot normally execute the first operation instruction due to the storage address of the data accessed by the first operation instruction, generating a second operation instruction according to a data access exception message generated by the first processor, the second operation instruction being suitable for accessing the data to be accessed by the first operation instruction, and the first processor and the second processor will not generate a data access exception message when executing the second operation instruction; submitting the second operation instruction to the first processor so that the first processor accesses the data in the internal memory according to the second operation instruction; and when the second processor executes the first operation instruction, submitting the second operation instruction to the second processor so that the second processor accesses the data in the internal memory according to the second operation instruction.

[0007] Optionally, in the method according to the present invention, generating a second operation instruction based on a data access exception message generated by a first processor includes the steps of: determining whether a replacement flag is set at an instruction address of the instruction stream where the first operation instruction is located; if the replacement flag is not set, generating a second operation instruction based on the data access exception message; and setting a replacement flag at the instruction address of the instruction stream where the first operation instruction is located.

[0008] Optionally, the method according to the present invention also includes the step of: when the second processor executes the first operation instruction and generates a data access exception message, determining whether a replacement flag is set for the instruction address of the first operation instruction; if the replacement flag is set, ignoring the data access exception message.

[0009] Optionally, in the method according to the present invention, the computing device also includes a second instruction cache, and the instruction cache stores multiple operation instructions to be executed. The method also includes the steps of: when the second processor sequentially extracts the first operation instruction in the instruction cache from the second instruction cache for execution, submitting the second operation instruction for applying access to data in the internal memory to the second instruction cache, so that the second processor executes the second operation instruction to access the data in the internal memory after executing other instructions to be executed in the second instruction cache.

[0010] Optionally, in the method according to the present invention, generating a second operation instruction according to a data access exception message includes the steps of: replacing a first target address of the first operation instruction with a second target address; and generating a second operation instruction according to the second target address.

[0011] Optionally, in the method according to the present invention, replacing the first target address of the first operation instruction with the second target address includes the steps of: calculating a storage address and an offset according to the first target address; and generating the second target address according to the storage address and the offset.

[0012] Optionally, in the method according to the present invention, the computing device also includes a first instruction cache, and submitting the second operation instruction to the first processor includes the steps of: submitting the second operation instruction to the first instruction cache so that the first processor obtains and processes the second operation instruction from the first instruction cache.

[0013] Optionally, in the method according to the present invention, the first operation instruction includes a non-boundary operation instruction, and the second operation instruction includes a boundary operation instruction.

[0014] According to another aspect of the present invention, a computing device is provided, comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing a multi-processor instruction execution method according to the present invention.

[0015] According to another aspect of the present invention, a computer-readable storage medium storing one or more programs is provided, wherein the one or more programs include instructions that, when executed by a computing device, cause the computing device to execute a method in a multi-processor instruction execution method according to the present invention.

[0016] The multi-processor instruction execution method of the present invention is suitable for execution in a computing device, wherein the computing device includes a first processor, a second processor, an internal memory, and runs an operating system and one or more applications, wherein a storage area of ​​the internal memory is mapped to a storage space, and the application accesses data in the internal memory with a storage address in the storage space, and the method includes the steps of: submitting a first operation instruction for the application to access data in the internal memory to the first processor, and when the first processor cannot normally execute the first operation instruction due to the storage address of the data accessed by the first operation instruction, generating a second operation instruction according to a data access exception message generated by the first processor, the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the first processor and the second processor will not generate a data access exception message when executing the second operation instruction, thereby solving the problem of error reporting when processing and executing the operation instruction, and enabling the processor to normally access the data according to the second operation instruction.

[0017] When the first processor generates a data access exception message, the second operation instruction is submitted to the first processor, and the second operation instruction is not immediately submitted to the second processor, and unnecessary cache flushing operations are not performed. When the second processor needs to execute the first operation instruction, the second operation instruction is submitted to the second processor so that the second processor can access the data in the internal memory according to the second operation instruction. Therefore, in most cases, when the processors do not execute the instruction at the same time, the cache flushing operation on the processors is reduced, thereby improving the system operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. By reading the following detailed description in conjunction with the accompanying drawings, the above and other purposes, features and advantages disclosed by the present invention will become more apparent. Throughout the present disclosure, the same reference numerals generally refer to the same parts or elements.

[0019] Figure 1 A schematic diagram showing a structure of a processor deployed in a computing device according to an exemplary embodiment of the present invention is shown;

[0020] Figure 2 shows a block diagram of a computing device 200 according to an exemplary embodiment of the present invention;

[0021] Figure 3 A schematic flow chart showing a multiprocessor instruction execution method 300 according to an exemplary embodiment of the present invention; and

[0022] Figure 4 A schematic diagram of a process for processing a data access exception message according to an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to enable the scope of the present disclosure to be fully conveyed to those skilled in the art. The same reference numerals generally refer to the same components or elements.

[0024] Figure 1 FIG. 2 shows a schematic diagram of a structure in which a processor is deployed in a computing device according to an exemplary embodiment of the present invention. Figure 1As shown, the computing device 100 includes a first processor 130 and a second processor 140. The first processor 130 and the second processor 140 work in coordination. The computing device 100 also includes a first instruction cache 131, a first data cache 132, a second instruction cache 141 and a second data cache 142.

[0025] According to an embodiment of the present invention, the first instruction cache 131 and the first data cache 132 may be integrated in the first processor 130, and the second instruction cache 141 and the second data cache 142 may be integrated in the second processor 140. The present invention does not limit the deployment method of the first instruction cache 131, the first data cache 132, the second instruction cache 141 and the second data cache 142, for example, they may also be deployed on the internal memory 150. In order to facilitate the description of the deployment method of the processor and the method 300, the first instruction cache 131 and the second data cache 141 are separately described in the following. Figure 1 Shown in.

[0026] Figure 1 The computing device 100 also includes an internal memory 150; an operating system 120 is also installed in the computing device 100, and an application 110 runs on the operating system 120. The present invention does not limit the specific type of the operating system 120. Figure 1 The number of applications shown is only exemplary. There is no limit to the number and type of applications running on the operating system 120. The internal memory 150 is suitable for storing operating data of the operating system 120 and the applications 110, and the first processor 130 and the second processor 140 are suitable for processing the operating data.

[0027] Figure 1 The specific structure of the computing device 200 is as follows: Figure 2 Provide detailed explanation. Figure 2 FIG. 2 shows a block diagram of a computing device 200 according to an exemplary embodiment of the present invention. Figure 2 As shown, in a basic configuration 202, computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between processor 204 and system memory 206.

[0028] Depending on the desired configuration, the processor 204 can be any type of processor, including but not limited to: a microprocessor (μP), a microcontroller (μC), a digital information processor (DSP), or any combination thereof. The processor 204 can include one or more levels of cache such as a primary cache 210 and a secondary cache 212, a processor core 214, and registers 216. An example processor core 214 can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. An example memory controller 218 can be used with the processor 204, or in some implementations, the memory controller 218 can be an internal part of the processor 204.

[0029] Depending on the desired configuration, the system memory 206 may be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. The system memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the program 222 may be arranged to be executed by one or more processors 204 on the operating system using the program data 228 to execute the instructions 223 of the method 300 according to the present invention.

[0030] The computing device 200 may also include a storage interface bus 234. The storage interface bus 234 enables communication from storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to the basic configuration 202 via the bus / interface controller 230. At least a portion of the operating system 220, the program 222, and the data 224 may be stored on the removable storage 236 and / or the non-removable storage 238, and when the computing device 200 is powered on or the program 222 is to be executed, it is loaded into the system memory 206 via the storage interface bus 234 and executed by the one or more processors 204.

[0031] The computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to the basic configuration 202 via the bus / interface controller 230. Example output devices 242 include a graphics processing unit 248 and an audio processing unit 250. They can be configured to facilitate communication with various external devices such as a display or speakers via one or more A / V ports 252. Example peripheral interfaces 244 may include a serial interface controller 254 and a parallel interface controller 256, which may be configured to facilitate communication with external devices such as input devices (e.g., keyboards, mice, pens, voice input devices, touch input devices) or other peripherals (e.g., printers, scanners, etc.) via one or more I / O ports 258. Example communication devices 246 may include a network controller 260, which may be arranged to communicate with one or more other computing devices 262 via a network communication link via one or more communication ports 264.

[0032] A network communication link can be an example of a communication medium. Communication media can generally be embodied as computer-readable instructions, data structures, program modules in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium. A "modulated data signal" can be a signal in which one or more of its data sets or its changes can be carried out in a manner that encodes information in the signal. As non-limiting examples, communication media can include wired media such as a wired network or a dedicated line network, and various wireless media such as sound, radio frequency (RF), microwave, infrared (IR) or other wireless media. The term computer-readable medium used herein can include both storage media and communication media.

[0033] In the computing device 200 according to the present invention, the program 222 includes multiple program instructions of the multi-processor instruction execution method 300, and these program instructions can instruct the processor 204 to execute some steps of the multi-processor instruction execution method 300 running in the computing device 200 of the present invention, so that each part in the computing device 200 implements the multi-processor execution instruction by executing the multi-processor instruction execution method 300 of the present invention.

[0034] The computing device 200 can be implemented as a server, such as a file server 240, a database 250, a server, an application server, etc. These electronic devices can be such as personal digital assistants (PDAs), wireless network browsing devices, application-specific devices, or hybrid devices that can include any of the above functions. It can be implemented as a personal computer including desktop computers and notebook computer configurations. In some embodiments, the computing device 200 is also configured as a multi-processor instruction execution method 300.

[0035] Figure 3 FIG. 3 is a flow chart of a multiprocessor instruction execution method 300 according to an exemplary embodiment of the present invention. The multiprocessor instruction execution method 300 of the present invention is suitable for execution in a computing device, and is further suitable for execution by a processor such as Figure 1 The operating system 120 shown in FIG. Figure 3 As shown, the instruction execution method 300 starts at step S310, submitting a first operation instruction for the application 110 to access data in the internal memory to the first processor 130. When the application 110 needs to read data in the internal memory 150, it needs to submit the first operation instruction for reading data to the first processor 130 for execution via the operating system 120. The storage area of ​​the internal memory is mapped into a storage space, and the application 110 accesses the data in the internal memory with a storage address in the storage space.

[0036] Subsequently, step S320 is executed. When the first processor 130 cannot execute the first operation instruction normally due to the storage address of the data accessed by the first operation instruction, a second operation instruction is generated according to the data access exception message generated by the first processor 130. The second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the first processor 130 and the second processor will not generate a data access exception message when executing the second operation instruction.

[0037] When data is stored in the internal memory 150 in a special case, the processor (the processor includes the first processor 130 and the second processor 140) cannot execute the special operation instruction, and a data access exception message will be generated. According to one embodiment of the present invention, when the data to be read by the application 110 is stored out of bounds in the internal memory 150, the first operation instruction is an out-of-bounds memory access instruction, and the data access exception message is an out-of-bounds memory access exception. Out-of-bounds means that the starting position of the data stored in the memory is not aligned with the natural boundary of the data of this type stored sequentially in the memory. For example, a 32-bit register, when storing data normally, the register stores a complete 32-bit data, and the first address of the data storage is the first address of the register. But when the storage is out of bounds, the calculator only stores part of the 32-bit data, and the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. The other part of the 32-bit data is stored in the next register in turn. The out-of-bounds memory access exception means that on a processor that does not support direct access to out-of-bounds data, direct access to out-of-bounds data will cause the processor to throw an exception. The processor cannot completely retrieve the 32-bit data stored in the divided state according to one instruction, so the processor throws an exception.

[0038] The data access exception message includes the instruction address and exception type of the first operation instruction. Application 110 generates a series of operation instructions during operation, and these operation instructions are collected to form an instruction stream. The first operation instruction is an operation instruction in the instruction stream of application 110, and the instruction address of the first operation instruction is the position of the first operation instruction in the instruction stream. The exception type is when the processor cannot execute the first operation instruction normally, and this situation belongs to which type of exception. According to one embodiment of the present invention, the exception type includes an out-of-bounds access exception. When the first operation instruction is an out-of-bounds access instruction, the corresponding exception type is an out-of-bounds access exception.

[0039] When generating the second operation instruction according to the data access exception message generated by the first processor 130, it is determined whether the instruction address of the instruction stream where the first operation instruction is located is set with a replacement flag. If the replacement flag is not set, the second operation instruction is generated according to the data access exception message, and the replacement flag is set at the instruction address of the instruction stream where the first operation instruction is located.

[0040] When the first operation instruction triggers a data access exception message for the first time, the data access exception message is processed and the first operation instruction is replaced with the second operation instruction; after the replacement, a replacement flag is set according to the instruction address to indicate that the first operation instruction under the instruction address has been processed and there is no need to repeat the instruction replacement operation.

[0041] Figure 4FIG. 2 shows a flow chart of processing a data access exception message according to an exemplary embodiment of the present invention. Figure 4 As shown, each time a data exception message is processed, first determine whether there is a replacement mark under the instruction address. By determining whether there is a replacement mark, determine whether it is the first time to process the data exception message triggered by the instruction. If there is no replacement mark under the instruction address, the instruction is replaced. Subsequently, if there is a replacement mark under the instruction address, the data access exception message is ignored and no unnecessary processing is performed on it.

[0042] When the processor 150 generates a data access exception message due to the storage address of the data accessed by the first operation instruction, and generates a second operation instruction according to the data access exception message, a first data block is generated according to the data access exception message. The first data block includes an instruction address and an exception type, and the data access exception message generated by the processor 150 is captured. When the first data block is generated according to the data access exception message, the instruction address and the exception type are packaged to facilitate processing of the data access exception message.

[0043] Then, the instruction replacement strategy of the data abnormal access message is determined according to the first data block. The computing device also stores an instruction replacement strategy table, which is pre-written by the developer and stored in the computing device. The replacement strategy table includes an exception type and a replacement strategy. Each exception type corresponds to a replacement strategy. According to the exception type in the first data block, the instruction replacement strategy table is queried to determine the instruction replacement strategy of the data abnormal access message, and the second data block is generated according to the first data block and the instruction replacement strategy. The replacement strategy includes whether to replace the instruction and what kind of replacement to perform. The exception type of the replacement strategy table includes the out-of-bounds access exception, and the corresponding replacement strategy is to replace the out-of-bounds access instruction with the bounds access instruction. Replacing the out-of-bounds access instruction with the bounds access means that the instruction is to be replaced, and the out-of-bounds access instruction is replaced with the bounds access instruction.

[0044] The execution generates a second operation instruction according to the instruction replacement strategy, and the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the processor will not generate a data access exception message when executing the second operation instruction. When the second operation instruction is generated according to the instruction replacement strategy, the storage address and the offset are calculated according to the first target address, and the second target address is generated according to the storage address and the offset. According to one embodiment of the present invention, when the first operation instruction is an out-of-bounds access instruction and the exception type is an out-of-bounds access exception, when the second operation instruction is generated, the first target address of the first operation instruction is replaced with the second target address according to the instruction replacement strategy, and the second operation instruction is generated according to the second target address. The first target address and the second target address are both addresses of the data that the application 110 wants to read in the storage space. However, the address where the data is stored in the form of the first target address is not bounded, and the address where the data is stored in the form of the second target address is bounded.

[0045] When replacing the first target address of the first operation instruction with the second target address according to the instruction replacement strategy, the instruction replacement strategy replaces the non-boundary access instruction with the boundary access instruction, and the second operation instruction is the boundary access instruction. The second operation instruction is logically equivalent to the first operation instruction.

[0046] When the first target address of the first operation instruction is replaced with the second target address, the storage address and the offset are calculated according to the first target address, and the second target address is generated according to the storage address and the offset.

[0047] According to one embodiment of the present invention, the first operation instruction is load Ra.32, disp1(Rb1.32), which is an instruction for loading a 32-bit integer whose first target address is Rb1+disp1 into register Ra, wherein Rb1 represents the first address of register Rb, and disp1 is the offset of the 32-bit integer on the first address of register Rb.

[0048] In order to retrieve the 32-bit data separated in two consecutive registers, the number of bits of the first operation instruction needs to be doubled, that is, each two consecutive 32-bit registers in the internal memory 160 are regarded as a whole for operation. For example, the 0th 32-bit register and the 1st 32-bit register are regarded as a 64-bit register for operation, and the subsequent registers are operated in the same way.

[0049] When calculating the storage address of the second operation instruction, the address of the original register Rb is calculated according to the merging situation. The original register Rb is the i-th register. When i is an odd number, the original register Rb is merged with the next register as a whole to obtain the merged register Rb. The address Rb1 of the original register Rb is still the address Rb2 of the merged register Rb. When i is an even number, the original register Rb is merged with the previous register as a whole to obtain the merged register Rb. The address of the original register Rb plus the number of operation bits, that is, Rb1+32, is used as the address Rb2 of the merged register Rb.

[0050] When calculating the offset of the second operation instruction, use the following formula to calculate the offset:

[0051] disp2=(Rb1+disp1)-(Rb1+disp1)%64

[0052] A second target address Rb2+disp2 is generated according to the storage address and the offset.

[0053] Then, a second operation instruction is generated according to the second target address: load Ra.64, disp2 (Rb2.32). The second operation instruction indicates that the 32-bit integer whose second target address is Rb2+disp2 is read from the 64-bit aligned register into the register Ra.

[0054] Subsequently, step S330 is executed to submit the second operation instruction to the first processor 130, so that the first processor 130 accesses the data in the internal memory according to the second operation instruction. When the second operation instruction is submitted to the first processor 130, the second operation instruction is submitted to the first instruction cache 131, so that the first processor 130 obtains and processes the second operation instruction from the first instruction cache 131.

[0055] The first instruction cache 131 is suitable for storing multiple instructions to be executed. When the second operation instruction is submitted to the first processor 130, the second operation instruction is added to the instruction sequence of the first instruction cache 131, so that the first processor 130 sequentially executes the multiple instructions in the first instruction cache 131. When the first processor executes the second operation instruction, the second operation instruction is obtained from the first instruction cache 131, and the second operation instruction is processed to obtain data from the internal memory 150. At this time, the internal memory 150 transmits the data to the first processor 130 through the communication bus, and also stores the data transmission to the first data cache 132. The first data cache 132 stores the data required for the operation of the first processor 130. When the first processor 130 needs related data next time, the data is directly queried from the first data cache 132. If the query hits, the data is obtained from the first data cache 132. If the query is not found, the data is queried from the internal memory.

[0056] A second processor is also deployed in the computer. When a second operation instruction is generated according to the data access exception message generated by the first processor 130 and the second operation instruction is submitted to the first instruction cache 131 of the first processor 130, it is usually necessary in the prior art to flush the cache of the second processor and synchronize the instruction caches of the first processor 130 and the second processor to avoid inconsistent instructions between the CPUs.

[0057] In the present invention, the cache flushing operation is not performed, which saves computer resources and improves the operating efficiency of the system and application 110 in the computer. Since the second processor generally does not execute the first operation instruction at the same time as the first processor 130, the second processor will execute the first operation instruction at the same time as the first processor 130 with a low probability, including but not limited to repeated iterations and recalculations of the same data. In this case, an error will be generated if the instruction synchronization is not performed. Therefore, it is not necessary to perform a cache flushing operation every time the first instruction cache 131 in the first processor 130 loads the second operation instruction, which causes a huge waste of resources.

[0058] In the present invention, the second processor asynchronously executes the first operation instruction and synchronously executes the first operation instruction. In most cases, step S350 is executed, and when the second processor asynchronously executes the first operation instruction, the second operation instruction is submitted to the second processor so that the second processor accesses the data in the internal memory according to the second operation instruction.

[0059] Since the second processor asynchronously executes the instruction stream containing the first operation instruction, the operating system 120 directly submits the instruction stream after the instruction replacement to the second processor, and the instruction address is already the second operation instruction that replaces the first operation instruction. At this time, the instruction stream loaded by the second processor is already the instruction stream after the instruction replacement, and when the second processor executes to the instruction address, it can directly read data from the memory according to the second operation instruction, and no error will be generated.

[0060] In a few cases, the second processor executes the first operation instruction synchronously. At this time, the second instruction cache 141 corresponding to the second processor still contains the first operation instruction. Since the instruction synchronization operation is not performed, the second processor synchronously executes the first operation instruction and generates a data access exception message.

[0061] However, since the first processor 130 has executed the instruction stream and processed the exception message during execution and set a replacement flag, when the second processor synchronously executes the first operation instruction and generates a data access exception message, the operating system 120 determines whether the instruction address of the first operation instruction is set with a replacement flag. If the replacement flag is set, the data access exception message is ignored.

[0062] After the data exception message of the second processor synchronously executing the first operation instruction is ignored, the second processor sequentially extracts the first operation instruction in the instruction cache from the second instruction cache 141 for execution. At this time, a vacancy appears in the second instruction cache 141, and the operating system 120 submits the second operation instruction of the application 110 to access the data in the internal memory to the second instruction cache 141, and adds it to the instruction queue of the second instruction cache 141. After the second processor executes other instructions to be executed in the second instruction cache 141, it executes the second operation instruction to access the data in the internal memory, thereby achieving the purpose of accessing the memory. Similarly, the internal memory 150 transmits the data to the second processor through the communication bus at this time, and also stores the data transmission to the second data cache 142. The second data cache 142 stores the data required for the operation of the first processor 130. When the second processor needs relevant data next time, it directly queries the data from the first data cache 132. If the query hits, it obtains the data from the second data cache 142. If it is not found, it queries the data from the internal memory.

[0063] The multi-processor instruction execution method of the present invention is suitable for execution in a computing device, wherein the computing device includes a first processor, a second processor, an internal memory, and runs an operating system and one or more applications, wherein a storage area of ​​the internal memory is mapped to a storage space, and the application accesses data in the internal memory with a storage address in the storage space, and the method includes the steps of: submitting a first operation instruction for the application to access data in the internal memory to the first processor, and when the first processor cannot normally execute the first operation instruction due to the storage address of the data accessed by the first operation instruction, generating a second operation instruction according to a data access exception message generated by the first processor, the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the first processor and the second processor will not generate a data access exception message when executing the second operation instruction, thereby solving the problem of error reporting when processing and executing the operation instruction, and enabling the processor to normally access the data according to the second operation instruction.

[0064] When the first processor generates a data access exception message, the second operation instruction is submitted to the first processor, and the second operation instruction is not immediately submitted to the second processor, and unnecessary cache flushing operations are not performed. When the second processor needs to asynchronously execute the first operation instruction, the second operation instruction is submitted to the second processor so that the second processor can access the data in the internal memory according to the second operation instruction. Therefore, in most cases, when the processors do not execute the instruction at the same time, the cache flushing operation on the processors is reduced, thereby improving the system operation efficiency.

[0065] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0066] A9. A method as described in A8, wherein the first operation instruction includes a non-boundary operation instruction, and the second operation instruction includes a boundary operation instruction.

[0067] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim.

[0068] Those skilled in the art will appreciate that the modules or units or groups of the devices in the examples disclosed herein may be arranged in the device as described in the embodiment, or alternatively may be located in one or more devices different from the devices in the example. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0069] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or groups in the embodiments may be combined into one module or unit or group, and in addition they may be divided into a plurality of submodules or subunits or subgroups. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0070] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present invention and to form different embodiments.

[0071] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0072] The various techniques described herein may be implemented in combination with hardware or software, or a combination thereof. Thus, the method and apparatus of the present invention, or some aspects or portions of the method and apparatus of the present invention may be in the form of program codes (i.e., instructions) embedded in a tangible medium, such as a floppy disk, a CD-ROM, a hard disk drive, or any other machine-readable storage medium, wherein when the program is loaded into a machine such as a computer and executed by the machine, the machine becomes a device for practicing the present invention.

[0073] In the case where the program code is executed on a programmable computer, the computing device generally includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store the program code; the processor is configured to execute the method for determining the shutdown state of the device of the present invention according to the instructions in the program code stored in the memory.

[0074] By way of example and not limitation, computer readable media include computer storage media and communication media. Computer readable media include computer storage media and communication media. Computer storage media stores information such as computer readable instructions, data structures, program modules or other data. Communication media generally embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and includes any information delivery medium. Any combination of the above is also included within the scope of computer readable media.

[0075] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0076] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative, not restrictive, with respect to the scope of the present invention, which is defined by the appended claims.

Claims

1. A multi-processor instruction execution method, suitable for execution in a computing device, the computing device comprising a first processor, a second processor, an internal memory, and running one or more applications, the storage area of ​​the internal memory is mapped as a storage space, and the application accesses data in the internal memory with a storage address in the storage space, the method comprising the steps of: Submitting a first operation instruction for the application to access data in the internal memory to the first processor; When the first processor cannot normally execute the first operation instruction due to the storage address of the data accessed by the first operation instruction, a second operation instruction is generated according to the data access exception message generated by the first processor, the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the first processor and the second processor will not generate a data access exception message when executing the second operation instruction; submitting the second operation instruction to the first processor so that the first processor accesses the data in the internal memory according to the second operation instruction; When the second processor executes the first operation instruction, submitting the second operation instruction to the second processor so that the second processor accesses the data in the internal memory according to the second operation instruction; The step of generating a second operation instruction according to the data access exception message generated by the first processor comprises the following steps: Determining whether a replacement flag is set for an instruction address of the instruction stream where the first operation instruction is located; If the replacement flag is not set, generating a second operation instruction according to the data access exception message; Setting a replacement flag at the instruction address of the instruction stream where the first operation instruction is located; When the second processor generates a data access exception message by executing the first operation instruction, determining whether a replacement flag is set for the instruction address of the first operation instruction; If the replacement flag is set, the data access exception message is ignored; The computing device further includes a second instruction cache, wherein the second instruction cache stores a plurality of operation instructions to be executed, and the method further includes the steps of: When the second processor sequentially extracts the first operation instruction in the second instruction cache from the second instruction cache for execution, the second operation instruction for the application to access the data in the internal memory is submitted to the second instruction cache, so that the second processor executes the second operation instruction to access the data in the internal memory after executing other instructions to be executed in the second instruction cache.

2. The method of claim 1, wherein: The generating of the second operation instruction according to the data access exception message comprises the steps of: replacing the first target address of the first operation instruction with a second target address; A second operation instruction is generated according to the second target address.

3. The method of claim 2, wherein: The replacing the first target address of the first operation instruction with the second target address comprises the steps of: Calculate a storage address and an offset according to the first target address; A second target address is generated according to the storage address and the offset.

4. The method of claim 3, wherein: The computing device further includes a first instruction cache, and submitting the second operation instruction to the first processor includes the steps of: The second operation instruction is submitted to the first instruction cache, so that the first processor obtains and processes the second operation instruction from the first instruction cache.

5. The method of claim 4, wherein: The first operation instruction includes a non-boundary operation instruction, and the second operation instruction includes a boundary operation instruction.

6. A computing device comprising: one or more processors; Memory; as well as One or more devices comprising instructions for executing the method according to any one of claims 1-5.

7. A computer-readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device cause the computing device to perform the method according to any one of claims 1 to 5.

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