Data storage management method and storage device

Abstract

The present application proposes a data management method with an adjustable mapping table, which can dynamically select the most efficient operating mode to manage the mapping table according to the size, existence and total capacity specifications of the external memory of the storage device. First, after the storage device is turned on, it executes the program in the firmware to check whether there is external memory in the storage device. When the storage device has the external memory and is in an available state, the capacity ratio of the available capacity of the storage cell array and the external memory is further calculated. When the capacity ratio is not greater than the threshold, the external memory is used to execute the first-level mapping mode. When the capacity ratio is greater than or equal to the threshold, the external memory and the internal memory in the control chip are used to execute the second-level mapping mode. When the external memory does not exist or is unavailable, the internal memory and the storage cell array are used to execute the second-level mapping mode.

Description

Technical Field

[0001] The present application relates to the field of storage devices, and in particular to a method for dynamically adjusting a management mapping table. Background Art

[0002] Storage devices (such as solid-state drives and flash drives) maintain an internal mapping table that translates logical page addresses to physical page addresses. Each time a user writes to a logical page, a new mapping relationship is created. This mapping relationship is added (for the first write) or modified (for an overwrite) to the mapping table. When a user reads a logical page, the storage device first searches the mapping table for the corresponding physical page, then accesses the flash memory to read the corresponding data.

[0003] For storage devices with large-capacity onboard external memory (such as dynamic random access memory (DRAM)), the entire mapping table is generally stored in the external memory, which is called full external memory mode, allowing for quick access to the mapping relationship. Another type of storage device with small-capacity onboard external memory stores part of the mapping table in the external memory, which is called partial external memory mode. There is also a type of storage device with no external memory mode (RAM-less mode) that uses two-level mapping. First-level mapping means that all data is directly managed by a single mapping table. Second-level mapping adds and updates a second, smaller mapping table in the internal memory of the controller chip to manage the first mapping table, which then manages all data. The so-called external memory is memory located outside the controller chip, while the so-called internal memory is memory located within the controller chip. Both external and internal memory are located within the storage device.

[0004] For most storage devices, different hardware architectures and flash memory capacities use different mapping management methods, resulting in different firmware versions that are incompatible with each other. Therefore, a method for dynamically adjusting the mapping management table to match the three storage management mapping table methods mentioned above and reduce firmware development and maintenance costs is needed. Summary of the Invention

[0005] In order to solve the problem of storage device management mapping table under different hardware conditions, this application proposes a data management method that can dynamically adjust the mapping table. It can manage the mapping table by selecting the most efficient operating mode according to the presence, size and total capacity specifications of the external memory.

[0006] In one embodiment, a data storage management method is provided for enabling data access in a storage device. The storage device may include at least a control chip, firmware, and a memory cell array. The storage device may or may not include external memory. This data storage management method can determine the presence of external memory in real time to determine the operating mode.

[0007] First, after the storage device is powered on, it executes a program in the firmware to check whether the storage device has external memory that is not in the control chip. If the storage device has the external memory and it is in an available state, it further calculates the capacity ratio of the available capacity of the storage cell array and the available capacity of the external memory.

[0008] When the capacity ratio is not greater than a threshold, the external memory is used to execute a first-level mapping mode.

[0009] When the capacity ratio is greater than the threshold, a secondary mapping mode is executed using the external memory and the internal memory in the control chip.

[0010] When the external memory does not exist or is unavailable, the secondary mapping mode is executed using the internal memory and the storage cell array.

[0011] In a further embodiment, the storage device is connected to a host for receiving an access request. The access request includes a logical address of data. When the first-level mapping mode is executed using the external memory, a first mapping table is established in the external memory for mapping the logical address to a physical address in the storage cell array.

[0012] In a further embodiment, when the two-level mapping mode is executed using the external memory and the internal memory, a first mapping table is established in the external memory for mapping the logical addresses to physical addresses in the memory cell array, and a second mapping table is established in the internal memory for managing the first mapping table. Furthermore, the storage device can adjust the mapping granularity of the first and second mapping tables based on the size ratio of the external memory to the internal memory.

[0013] In a further embodiment, when the two-level mapping mode is executed using the internal memory and the storage cell array, a third mapping table is established in the storage cell array to map the logical addresses to physical addresses in the storage cell array, and the second mapping table is established in the internal memory to manage the third mapping table. Furthermore, the storage device can adjust the mapping granularity of the second and third mapping tables based on the size ratio of the internal memory to the storage cell array.

[0014] Another embodiment of the present application provides a storage device for connecting to a host, receiving access requests, and accessing data. The device comprises at least a storage cell array, a control chip, and firmware. The storage cell array comprises multiple storage blocks, each of which comprises multiple storage pages for storing data. The control chip, connected to the storage cell array, comprises a conversion circuit and internal memory for accessing data in the storage cell array according to the access request. The firmware, connected to the control chip, causes the conversion circuit in the control chip to execute a data management method. When executing the data management method, the control chip determines whether the storage device has external memory. If the storage device has the external memory and it is available, the control chip calculates the capacity ratio of the available capacity of the storage cell array and the external memory. If the capacity ratio is not greater than a threshold, the control chip executes a primary mapping mode using the external memory. If the capacity ratio is greater than the threshold, the control chip executes a secondary mapping mode using the external memory and the internal memory in the control chip. If the external memory does not exist or is unavailable, the secondary mapping mode is executed using the internal memory and the storage cell array.

[0015] In summary, the storage device of the present application can configure mapping tables in external memory, internal memory, and the storage cell array, and adjust the mapping granularity and FTL algorithm of these mapping tables to adapt to various hardware conditions in the storage device. The advantages of this embodiment include that only one set of firmware needs to be designed to adapt to different hardware architectures and flash memory capacities on the production line, greatly reducing firmware development time and maintenance costs. After the product is sold, if a memory failure occurs during use or if memory expansion is required, the storage device 100 can also flexibly adjust its operating mode through self-testing after powering on. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 1 is an architectural diagram of a storage device 100 and a host 130 according to an embodiment of the present application;

[0018] Figure 2 is a diagram of the memory cell array 200 according to an embodiment of the present application; and

[0019] Figure 3 This is a flow chart of the data management method according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] Figure 1 : is an architectural diagram of a storage device 100 and a receiving host 130 according to an embodiment of the present application. An embodiment of the present application proposes a storage device 100 that can access a host 130 via a bus and receive various access requests transmitted by the host 130 to perform data access. The storage device 100 includes at least one or more storage cell arrays 200, a control chip 110, and firmware 104. The storage cell array 200 may include multiple storage blocks, each storage block includes multiple storage pages, and each storage page includes multiple storage cells, each of which can be used to store one or more bits of data. The control chip 110 is connected to the storage cell array 200 and includes a conversion circuit 112 and an internal memory 114 for reading or writing data in the storage cell array 200 according to the access request transmitted by the host 130. The firmware 104 is connected to the control chip 110 and is used to enable the conversion circuit 112 in the control chip 110 to execute a data management method.

[0022] The conversion circuit 112, also commonly referred to as the Flash Transition Layer (FTL), is responsible for converting the logical block address (LBA) in the host 130's access request into a physical block address (PBA). Address conversion requires the use of a mapping table. The mapping table stores the correspondence between logical addresses and physical addresses. The logical address is the host 130's understanding of the data storage location. Since the storage device 100 may be a device architecture of various specifications, the host 130 is essentially unable to manage the storage cell array 200 in the storage device 100. Therefore, the host 130's access to data is expressed using a consistent logical address. As for the physical address where the data is actually stored, it is converted by the conversion circuit 112 in the control chip 110 according to the mapping table. For example, the conversion circuit 112 in the control chip 110 reads the mapping information #M from the mapping table to process the host 130's request to read or write data #D.

[0023] In the storage device 100, the mapping table usage typically varies depending on the hardware conditions. For example, the size of the external memory 120 and the capacity ratio of the storage cell array 200 in the storage device 100 affect the mapping table configuration and granularity. In some storage devices 100 that do not have external memory 120, the mapping table configuration parameters are completely different. Furthermore, an area in the external memory 120 is typically allocated as a cache 124. The usage of the cache 124 also affects the remaining space in the external memory 120, further affecting the granularity of the mapping table configuration. During use, the external memory 120 may also experience a fault and become disabled, or require expansion, upgrade, or replacement, making the originally configured mapping table parameters no longer applicable. When a storage device 100 leaves the factory, the FTL algorithm and mapping table configuration parameters in the firmware 104 are already fixed. To cope with various different situations, multiple versions of firmware must be prepared for updating and replacement, which is a complex process and difficult to implement. Therefore, the present application proposes a data management method with flexible adjustment capabilities, which is described below.

[0024] After the storage device 100 is powered on, the control chip 110 loads and executes a data management program from the firmware 104 to determine whether the storage device 100 has an external memory 120. Based on the existence and availability of the external memory 120, as well as the ratio of its available capacity to the capacity of the memory cell array 200, the following three usage scenarios can be distinguished.

[0025] When the storage device 100 confirms that it has an external memory 120 and that the external memory 120 is available, the control chip 110 calculates the ratio of the available capacity of the memory cell array 200 to that of the external memory 120. The external memory 120 may have a portion allocated as a cache 124 for data access, or may have a portion that is damaged or used to store data required for other internal operations. Therefore, the available capacity may be less than the originally designed total capacity.

[0026] Generally speaking, each cell in the mapping table stores a 32-bit physical address, pointing to a 4KB data space. Therefore, the mapping table size is 1 / 1000 of the total storage device capacity. This mapping granularity is for example only, representing a balance between performance and cost. The actual mapping granularity used in a design is not limited to 1 / 1000.

[0027] In other words, this embodiment can use the ratio of the total capacity of the storage cell array 200 in the storage device to the size of the external memory 120 as a basis for dynamically adjusting the mapping management table. The capacity ratio P can be expressed as:

[0028] P = storage cell array capacity / external memory available capacity

[0029] For example, if the storage cell array capacity = 1TB and the external memory available capacity = 2GB, then P = 500.

[0030] When the capacity ratio P is not greater than a threshold, the control chip 110 uses the external memory 120 to execute a first-level mapping mode. In this embodiment, the threshold can be set to 1000. The first-level mapping mode refers to using a single mapping table to handle all logical-to-physical address conversions. More specifically, when using the external memory 120 to execute the first-level mapping mode, the control chip 110 establishes a first mapping table 122 in the external memory 120 for mapping logical addresses used by the host 130 to physical addresses in the storage cell array 200.

[0031] When the capacity ratio P is greater than the threshold, the control chip 110 executes a two-level mapping mode using the external memory 120 and the internal memory 114 within the control chip 110. When executing the two-level mapping mode using the external memory 120 and the internal memory 114, the control chip 110 establishes a first mapping table 122 in the external memory 120 for mapping logical addresses used by the host 130 to physical addresses within the storage cell array 200, and establishes a second mapping table 116 in the internal memory 114 for managing the first mapping table 122. The capacity of the internal memory 114 is typically smaller than that of the external memory 120, but it offers better speed and performance. In other words, when the capacity of the storage cell array 200 exceeds 1,000 times the available capacity of the external memory 120, the first mapping table 122 within the external memory 120 cannot effectively manage address translation within the storage cell array 200. This embodiment flexibly addresses this situation by utilizing a smaller second mapping table 116 in conjunction with the first mapping table 122 in a secondary mapping mode to effectively manage data access. Furthermore, the storage device 100 can adjust the mapping granularity of the first mapping table 122 and the second mapping table 116 based on the size ratio of the external memory 120 to the internal memory 114 to optimize management efficiency.

[0032] If the storage device 100 does not have an external memory 120, the external memory 120 is unusable, or the available capacity of the external memory 120 is insufficient, the control chip 110 may use the internal memory 114 in conjunction with the storage cell array 200 to execute the secondary mapping mode. More specifically, when executing the secondary mapping mode using the internal memory 114 and the storage cell array 200, the control chip 110 establishes a third mapping table 212 in the storage cell array 200 to map logical addresses used by the host 130 to physical addresses in the storage cell array 200, and establishes a second mapping table 116 in the internal memory 114 to manage the third mapping table 212. The capacity of the storage cell array 200 is typically large enough to allocate an area for the third mapping table 212. However, since the storage cell array 200 typically utilizes flash memory, its access speed and performance cannot compare to the external memory 120 and internal memory 114. To balance performance and capacity, the present embodiment adopts a two-level mapping mode to enable the second mapping table 116 and the third mapping table 212 to operate in coordination. Furthermore, the storage device 100 can adjust the mapping granularity of the second mapping table 116 and the third mapping table 212 based on the size ratio of the internal memory 114 and the storage cell array 200 to optimize data management efficiency.

[0033] Figure 2 This is a diagram of the memory cell array 200 architecture of an embodiment of the present application. The memory cell array 200 generally includes a plurality of die 206 arranged in an array. Each die 206 (Die) is also called a LUN, which can be divided into a plurality of planes 208 (Plane). Each plane 208 includes a plurality of blocks 202 (Block). Each block 202 can be further divided into a plurality of pages (Page) (not shown). Each block 202 has an independent address number, and the location of each page can be found by adding an offset to the address number. Each page includes a plurality of memory cells, each of which is used to store one or more bits of data.

[0034] Blocks 202 and pages are common units of granularity used for data storage in a mapping table. For example, one of the primary tasks of the control chip 110 is to translate logical addresses used by the host 130 into physical addresses within the memory cell array 200. This correspondence is stored in the mapping table described in this embodiment. For access efficiency, the contents of the mapping table are cached in the external memory 120 and provide power-off protection.

[0035] There are several basic types of data management methods implemented based on blocks 202 and pages. Generally speaking, page-level mapping is a straightforward and simple mapping scheme. Each logical page corresponds to its own physical page. However, due to the large number of pages in memory cell array 200, a much larger memory capacity is required to process them, resulting in high costs.

[0036] Another method for implementing mapping is block-level mapping, which can significantly reduce the memory required for mapping tables. However, since each data write is performed in blocks, and each block has a large storage capacity, writing a large number of small data items can significantly reduce block utilization.

[0037] In other words, page-level mapping and block-level mapping are two extreme applications. Later, various hybrid mapping methods emerged that balance the advantages of both, such as log-block mapping. Simply put, a large number of small data write requests are temporarily mapped to cache 124 until they accumulate into complete blocks of data. The data is then officially copied to a separate physical block, and the logical block address mapping points to the separate physical block.

[0038] As described above, the primary and secondary mapping modes described in this embodiment utilize different storage schemes and mapping table sizes to coordinate mapping algorithms, flexibly adapting to various application scenarios and efficiently implementing address translation functions. When the conversion circuit 112 utilizes the first mapping table 122, the second mapping table 116, and the third mapping table 212, it can further utilize various FTL algorithms to further optimize management efficiency, such as garbage collection, direct mapping, inverse mapping, variable length mapping, demand-based FTL, lazy FTL, clustered page-level mapping, and many other variant mapping algorithms. Therefore, this application does not limit the use of any specific FTL algorithm or the detailed internal format of the mapping table. Based on the architecture proposed in this embodiment, various hardware conditions can be flexibly adapted to meet various requirements.

[0039] Each plane 208 includes a register 204 that stores detailed parameter settings for that plane 208, such as latency parameters, cell level, or other attributes. The level determines the number of bits each memory cell can represent, such as single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC). The memory cell array 200 includes an interface 210 that connects to the host 130 via the control chip 110.

[0040] Figure 3 The data management method of this application can be summarized as follows: Figure 3 Flowchart of . In step 301, the storage device 100 is turned on. In step 303, the storage device 100 obtains hardware information, such as whether the storage cell array 200 exists and its size. For example, the firmware 104 can store a machine code to record the hardware configuration information of the storage device 100 when it leaves the factory. On the other hand, the storage device 100 can also perform a self-test when it is turned on to confirm the hardware status. In step 305, if it is detected that the storage device 100 contains an available external memory 120, step 307 is performed to calculate the capacity ratio P of the storage cell array 200 and the external memory 120.

[0041] In step 309, a determination is made as to whether the capacity ratio P is greater than a threshold. For example, if P is less than or equal to 1000, the process proceeds to step 313, where the first-level mapping mode is executed using external memory 120. This step utilizes external memory 120 entirely for mapping, also known as full RAM mode. The FTL algorithm in control chip 110 can also be adjusted accordingly, for example by selecting an appropriate mapping granularity and mapping rules.

[0042] On the other hand, if it is determined in step 309 that the capacity ratio P is greater than 1000, step 311 is performed to execute the secondary mapping mode using the external memory 120 and the internal memory 114. This situation is also called partial RAM mode.

[0043] If, in step 305, it is determined that the external memory 120 does not exist in the storage device 100, or that the external memory 120 is unavailable, the process proceeds to step 315, where the internal memory 114 and the memory cell array 200 are used to execute the secondary mapping mode. This situation, because the external memory 120 is not used, is also referred to as the RAM-less mode. Finally, in step 317, the mapping table usage mode determination process of this embodiment ends.

[0044] In an embodiment of the present application, the storage device 100 may be a storage device. The connection with the host 130 may be a universal serial bus (USB) or an external serial industrial standard interface (e-SATA). The external memory 120 may be a synchronous dynamic random access memory (SDRAM). In a further embodiment, in the host 130 connected to the storage device 100, an external mapping table 134 may also be configured in the host memory 132 as a substitute or synchronous backup for the first mapping table 122 or the third mapping table 212. When the host 130 accesses the storage device 100, the external mapping table 134 may be used to increase efficiency, such as organizing a large number of fragmented access requests, or caching a large number of repeated access actions. Although this embodiment is based on Figure 1 The hardware architecture shown is representative, but it is understood that Figure 1 This is merely a functional example. In physical design, the memory device 100 may further include other necessary elements for operation, and the internal arrangements of the control chip 110 and the memory cell array 200 may also have other different variations.

[0045] In a further embodiment, although not shown, it is understood that the third mapping table 212 may be mapped by the control chip 110 by selecting multiple blocks 202 in one or more planes 208 from the storage device 200 .

[0046] In summary, the storage device 100 of the present application can configure mapping tables in the external memory 120, the internal memory 114, and the memory cell array 200, and adjust the mapping granularity of these mapping tables to adapt to various hardware conditions within the storage device 100. Advantages of this embodiment include requiring only one set of firmware to adapt to different hardware architectures and flash memory capacities on the production line, significantly reducing firmware development time and maintenance costs. After the product is sold, if a memory failure occurs during use or if memory expansion is required, the storage device 100 can flexibly adjust its operating mode through self-testing after power-on.

[0047] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0048] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A data storage management method for enabling a storage device to access data, wherein the storage device comprises at least a control chip, firmware, and a storage cell array; The data storage management method is characterized by comprising: determining whether the storage device includes an external memory that is not in the control chip; When the storage device has the external memory and is in an available state, calculating a capacity ratio between the available capacity of the storage cell array and the available capacity of the external memory; When the capacity ratio is not greater than a threshold, executing a first-level mapping mode using the external memory; When the capacity ratio is greater than the threshold, executing a secondary mapping mode using the external memory and the internal memory in the control chip; and When the external memory does not exist or is unavailable, the secondary mapping mode is executed using the internal memory and the storage cell array.

2. The data storage management method according to claim 1, wherein: The storage device receives an access request, wherein the access request includes a logical address of data; wherein: When the external memory is used to execute the first-level mapping mode, a first mapping table is established in the external memory for mapping the logical address to the physical address in the storage cell array.

3. The data storage management method according to claim 1, wherein: The storage device receives an access request, wherein the access request includes a logical address of data; wherein: When the secondary mapping mode is executed using the external memory and the internal memory, a first mapping table is established in the external memory for corresponding the logical address to the physical address in the storage cell array, and a second mapping table is established in the internal memory for managing the first mapping table.

4. The data storage management method according to claim 3, wherein: Also includes: The mapping granularity of the first mapping table and the second mapping table is adjusted according to the size ratio of the external memory and the internal memory.

5. The data storage management method according to claim 1, wherein: The storage device receives an access request, wherein the access request includes a logical address of data; wherein: When the secondary mapping mode is executed using the internal memory and the storage cell array, a third mapping table is established in the storage cell array for corresponding the logical address to the physical address in the storage cell array, and a second mapping table is established in the internal memory for managing the third mapping table.

6. A storage device for connecting to a host and receiving access requests for data access, characterized in that: include: A memory cell array includes multiple memory blocks, each memory block includes multiple memory pages for storing data; a control chip connected to the memory cell array, comprising a conversion circuit and an internal memory, and configured to access data in the memory cell array according to the access request; Firmware, connected to the control chip, used to enable the conversion circuit in the control chip to execute the data management method; wherein: When executing the data management method, determining whether the storage device has an external memory that is not in the control chip; When the storage device has the external memory and is in an available state, calculating a capacity ratio between the available capacity of the storage cell array and the available capacity of the external memory; When the capacity ratio is not greater than a threshold, executing a first-level mapping mode using the external memory; When the capacity ratio is greater than the threshold, executing a secondary mapping mode using the external memory and the internal memory in the control chip; and When the external memory does not exist or is unavailable, the secondary mapping mode is executed using the internal memory and the storage cell array.

7. The storage device according to claim 6, wherein: in: The access request includes a logical address of the data; When the external memory is used to execute the first-level mapping mode, the control chip establishes a first mapping table in the external memory for mapping the logical address to the physical address in the storage cell array.

8. The storage device according to claim 6, wherein: The access request includes a logical address of the data; When the secondary mapping mode is executed using the external memory and the internal memory, the control chip establishes a first mapping table in the external memory for corresponding the logical address to the physical address in the storage cell array, and establishes a second mapping table in the internal memory for managing the first mapping table.

9. The storage device according to claim 8, wherein The control chip adjusts the mapping granularity of the first mapping table and the second mapping table according to the size ratio of the external memory and the internal memory.

10. The storage device according to claim 6, wherein: The access request includes a logical address of the data; When the secondary mapping mode is executed using the internal memory and the storage cell array, the control chip establishes a third mapping table in the storage cell array for corresponding the logical address to the physical address in the storage cell array, and establishes a second mapping table in the internal memory for managing the third mapping table.

Images