A solid state drive FTL algorithm address mapping method

Abstract

The present invention provides a solid-state hard disk FTL algorithm address mapping method. For a solid-state hard disk composed of N NAND Flashes, each page of the N NAND Flashes is uniformly managed according to the page address sequence number, and a logical page set and a physical page set are defined. A page set represents a set of the Mth page sequence numbers of the N NAND Flashes, and the mapping relationship from the logical page set to the physical page set represents the mapping of the logical address to the physical address; wherein M is less than or equal to the total number of physical pages of each NAND Flash. The scheme of the present invention can significantly reduce the consumed resources, and has nothing to do with the number of NAND Flashes. No matter how many NAND Flashes there are in the solid-state hard disk, the present invention only needs to consume fixed resources to complete an efficient address mapping algorithm.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a solid state hard disk FTL algorithm address mapping method. Background Art

[0002] With the booming development of the semiconductor industry, high-performance memory NAND Flash has emerged. NAND Flash memory uses semiconductors as storage media and has the advantages of high speed, low energy consumption and shock resistance. The basic storage unit of NAND Flash is composed of blocks. Each block is composed of several pages. Among them, the smallest read and write unit is a page, and the smallest erase unit is a block. Before programming a page, it is necessary to erase the block where the page is located. Due to this feature of NAND Flash, it cannot perform the original text write operation, and the data needs to be written to the replacement page, which requires the support of the FTL algorithm. One of the core modules of the FTL algorithm is the address mapping module.

[0003] In order to pursue high performance, most of them adopt page mapping mechanism. Under this mapping mechanism, since the NAND Flash mapping table represents the mapping relationship between logical page address (LPA) and physical page address (PPA), the PPA can be easily found through LPA. For NAND Flash, the larger the capacity, the larger the address mapping table. For example, for the L85C series 256GB capacity NAND Flash (see Figure 1 ), this type of NAND Flash has 33536 blocks, each block has 512 pages, that is, it contains a total of 33536*512=17170432 pages, and for the page mapping table, a total of 17170432 entries are required. For large-capacity SSDs, a general 2TB solid-state drive requires 8 NAND Flashes of this model, which requires a total of 17170432*8=137363456 entries. Each entry is represented by 4-Byte data, occupying a total of 137363456*4=549453824Bytes (524MB) of data space. This is unrealistic for solid-state drive controllers with limited resources. Therefore, many page address mapping algorithms do not load all entries into the RAM inside the controller, but use a CACHE mechanism to save part of the page table in RAM. The quality of the algorithm is related to the design of the CACHE. However, no matter how the CACHE is designed, loading and rewriting the CACHE will take time and cause performance loss. Summary of the invention

[0004] In view of the problems existing in the prior art, a solid-state drive FTL algorithm address mapping method is provided, which can implement the page mapping algorithm under limited resources. Only one table entry is needed to represent the mapping relationship of N pages, and the required memory resources are one-Nth of the previous mapping algorithm.

[0005] The technical solution adopted by the present invention is as follows: a solid-state hard disk FTL algorithm address mapping method, for a solid-state hard disk composed of N NAND Flashes, each page of the N NAND Flashes is uniformly managed according to the page address sequence number, a logical page set and a physical page set are defined, a page set represents the set of the Mth page sequence numbers of the N NAND Flashes, and the mapping relationship from the logical page set to the physical page set is used to represent the mapping of the logical address to the physical address; wherein M is less than or equal to the total number of physical pages of each NAND Flash.

[0006] Furthermore, a data structure L2P_PAGE_SET[M] is defined to store a mapping relationship between a logical page set LOGIC_PAGE_SET[M] and a physical page set PHYSICAL_PAGE_SET[M], wherein the logical page set LOGIC_PAGE_SET[M] and the physical page set PHYSICAL_PAGE_SET[M] respectively represent the sets of logical and physical M-th page numbers of N NAND Flash slices in the solid-state drive, i.e., {(1,M), (2,M)…(N,M)}.

[0007] Furthermore, the data structure L2P_PAGE_SET[M] occupies 4 bytes in total, and the initial value is the default value 0xFFFFFFF, indicating that the page set is not mapped.

[0008] Furthermore, a data structure PAGE_STATUS[M] is defined, where each unit of the data structure is 1 byte and there are M items in total, which are used to represent the status of the corresponding page set; wherein the page set status includes free pages, valid pages, discarded pages, and damaged pages.

[0009] Furthermore, when writing data, the data sent by the host is cached; the logical address sent by the host is converted into the page number P1, and the data structure PAGE_STATUS[M] is queried to find the unused page set number N free , set L2P_PAGE_SET[P1] = N free , mapping LOGIC_PAGE_SET[P1] to PHYSICAL_PAGE_SET[N free ], and set PAGE_STATUS[P1] to the valid page status; finally, write the cached data concurrently to PHYSICAL_PAGE_SET[N free]The writing process is completed in each page in the collection.

[0010] Furthermore, when reading data, a cache is allocated; the logical address sent by the host is converted into a page number P2, and the data structure L2P_PAGE_SET[P2] is queried to find the corresponding physical page set number N free , get PHYSICAL_PAGE_SET[N free ], concurrently read data from the corresponding physical page and store it in the allocated cache, and set PAGE_STATUS[P1] to the idle state to complete the data reading process.

[0011] Compared with the prior art, the beneficial effect of adopting the above technical solution is: the solution proposed by the present invention can significantly reduce the consumed resources and is independent of the number of NAND Flash slices. No matter how many NAND Flash slices there are in the solid-state drive, the present invention only needs to consume fixed resources to complete an efficient address mapping algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 FIG. 4 is a diagram of the physical structure of NAND Flash in one embodiment of the present invention.

[0013] Figure 2 Schematic diagram of data structure in one embodiment of the present invention.

[0014] Figure 3 It is a schematic diagram of the mapping relationship in one embodiment of the present invention. DETAILED DESCRIPTION

[0015] The present invention is further described below in conjunction with the accompanying drawings.

[0016] The present invention proposes a solid state hard disk FTL algorithm address mapping method. For a solid state hard disk composed of N NAND Flashes, each page of the N NAND Flashes is uniformly managed according to the page address sequence number, and a logical page set and a physical page set are defined. A page set represents a set of M-th page sequence numbers of the N NAND Flashes, and the mapping relationship between the logical page set and the physical page set is used to represent the mapping of the logical address to the physical address; wherein M is less than or equal to the total number of physical pages of each NAND Flash.

[0017] In this embodiment, a data structure LOGIC_PAGE_SET is proposed. The data structure is a set of pages with the same serial number of N NAND Flash. Taking the solid state drive MT29F2T08CVCBB as an example, Figure 1As shown in the figure, the NAND Flash has a total of 17170432 pages, with page numbers 0 to 17170431. The 0th page of the first NAND Flash is defined as (1,0), the 0th page of the second NAND Flash is defined as (2,0), and so on. The 0th page of the Nth NAND Flash is (N,0). Then LOGIC_PAGE_SET(0) represents the set of page 0 on all NAND Flashes, that is, {(1,0), (2,0)…(N,0)}.

[0018] Correspondingly, the data structure L2P_PAGE_SET[M] is also defined, where M is the total number of physical pages of each NAND Flash. This data stores the mapping relationship between the logical page set LOGIC_PAGE_SET and the physical page set PHYSICAL_PAGE_SET. Different from the general design, the mapping of the logical address to the physical address is a mapping of two sets, such as Figure 2 As shown in the figure, the data structure has 4 bytes in total, and the initial value is the default value 0xFFFFFFF, indicating that the page set is not mapped. For example, if L2P_PAGE_SET[3]=4, it means that the physical page set mapped by LOGIC_PAGE_SET(3) is PHYSICAL_PAGE_SET(4), then {(1,3), (2,3)…(N,3)} is mapped to {(1,4), (2,4)…(N,4)}, as shown in the figure. Figure 3 shown.

[0019] In this embodiment, a data structure PAGE_STATUS[M] is also proposed. Each unit of the data structure is 1 byte, and there are M items in total. The data structure indicates the status of the corresponding page set. The page set status includes free page, valid page, discarded page and damaged page.

[0020] According to the address mapping design of this embodiment, when writing data, it is necessary to allocate a cache according to N times the page capacity, and the cache is used to store the data sent by the host. The logical address sent by the host is converted into a page number P, and the PAGE_STATUS[M] data structure is queried to find the unused page set number Nfree, and the page set is mapped to L2P_PAGE_SET, that is, L2P_PAGE_SET[P] is set to Nfree, and L2P_PAGE_SET[P] is mapped to PHYSICAL_PAGE_SET[Nfree], that is, the mapping of {(1, P), (2, P)...(N, P)} to {(1, Nfree), (2, Nfree)...(N, Nfree)} is completed, and PAGE_STATUS[P] is set to the valid page status. Subsequently, the data is concurrently written to each page in the PHYSICAL_PAGE_SET[Nfree] set to complete the writing process.

[0021] When reading data, it is necessary to allocate a cache according to N times the page capacity, which is used to store data read from NAND Flash. Convert the logical address sent by the host into a page number P, query the L2P_PAGE_SET data structure, find L2P_PAGE_SET[P]=Nfree, obtain the PHYSICAL_PAGE_SET[Nfree] page set, that is, the mapping of {(1,Nfree), (2,Nfree)...(N,Nfree)}, and concurrently read the data from the set page and store it in the allocated cache to complete the data reading process.

[0022] Micron's MT29F2T08CVCBB NAND Flash is used as the test object. The physical structure of this NAND Flash is shown in the figure below. Figure 1 As shown, this type of NAND Flash has 33536 physical blocks, each physical block has 512 pages, and this type of NAND Flash has a total of 17170432 pages. Assuming that there are N NAND Flash in the solid-state drive, managing N NAND Flash of this model requires managing a total of N*17170432 page units. Taking N as 8 as an example, the general address mapping algorithm requires 8*17170432 entries, and each entry occupies 4 bytes of storage resources, which requires 8*17170432*4=549453824Bytes.

[0023] If the design of the present invention is adopted, managing 8 NAND Flashes needs to rely on the L2P_PAGE_SET data structure, which has a total of 17170432 items, each of which occupies 4 bytes, and requires 17170432*4=68681728Bytes, which is 1 / 8 of the general algorithm.

[0024] It can be seen that the design of the present invention has nothing to do with the number of NAND Flashes. No matter how many NAND Flashes the solid-state drive has, the present invention only needs to consume fixed resources to complete an efficient address mapping algorithm.

[0025] The present invention is not limited to the above-mentioned specific embodiments. The present invention extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed. If non-substantial changes or improvements made by those skilled in the art without departing from the spirit of the present invention should fall within the scope of protection of the claims of the present invention.

[0026] All features disclosed in this specification, or steps in all methods or processes disclosed, except mutually exclusive features and / or steps, can be combined in any manner.

[0027] Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. A solid state drive FTL algorithm address mapping method, It is characterized in that For a solid-state drive composed of N NAND Flashes, each page of the N NAND Flashes is uniformly managed according to the page address sequence number, and a logical page set and a physical page set are defined. A page set represents the set of the Mth page sequence numbers of the N NAND Flashes, and the mapping relationship between the logical page set and the physical page set represents the mapping of the logical address to the physical address; wherein M is less than or equal to the total number of physical pages of each NAND Flash; Define a data structure L2P_PAGE_SET[M] to store the mapping relationship between the logical page set LOGIC_PAGE_SET[M] and the physical page set PHYSICAL_PAGE_SET[M], where the logical page set LOGIC_PAGE_SET[M] and the physical page set PHYSICAL_PAGE_SET[M] respectively represent the set of logical and physical M-th page numbers of N NAND Flash slices in the solid-state drive, that is, {(1,M), (2,M)…(N,M)}; The data structure L2P_PAGE_SET[M] occupies 4 bytes in total, and the initial value is the default value 0xFFFFFFF, indicating that the page set is not mapped.

2. The solid state drive FTL algorithm address mapping method according to claim 1, It is characterized in that Define a data structure PAGE_STATUS[M], where each unit is 1 byte and there are M items in total, which are used to represent the status of the corresponding page set; wherein the page set status includes free page, valid page, discarded page and damaged page.

3. The solid state drive FTL algorithm address mapping method according to claim 2, It is characterized in that When writing data, cache the data sent by the host; convert the logical address sent by the host into page number P1, query the data structure PAGE_STATUS[M], and find the unused page set number N free , set L2P_PAGE_SET[P1] = N free , mapping LOGIC_PAGE_SET[P1] to PHYSICAL_PAGE_SET[N free ], and set PAGE_STATUS[P1] to the valid page status; finally, write the cached data concurrently to PHYSICAL_PAGE_SET[N free ]The writing process is completed in each page in the collection.

4. The solid state drive FTL algorithm address mapping method according to claim 3, It is characterized in that When reading data, allocate cache; convert the logical address sent by the host into page number P2, query the data structure L2P_PAGE_SET[P2], and find the corresponding physical page set number N free , get PHYSICAL_PAGE_SET[N free ], concurrently read data from the corresponding physical page and store it in the allocated cache, and set PAGE_STATUS[P1] to the idle state to complete the data reading process.

Images