Functional verification method, system, electronic device for verification and storage medium designed

Abstract

Embodiments of the present application provide a designed function verification method and system, an electronic device for verification and a storage medium, wherein the method comprises: judging whether an interruption occurs to a design under test in a current clock cycle; if yes, determining interruption trigger information of the design under test for executing the interruption, and register information updated by executing the interruption; generating interruption retirement information of the design under test based on the interruption trigger information and the register information, and saving the interruption retirement information into a retirement information queue; controlling simulation execution of a reference model based on information saved in the retirement information queue, and obtaining register information updated by the reference model based on the simulation execution; and determining a verification result based on the register information updated by the design under test and the register information updated by the reference model. Further, the retirement information queue can also save microcode retirement information, and embodiments of the present application can provide function verification support for designs with complex instruction set types.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of logic system design, and particularly relate to a designed function verification method and system, an electronic device for verification, and a storage medium. BACKGROUND

[0002] Logic system design (design for short) refers to the design of integrated circuits such as CPUs (central processing units), ASICs (application specific integrated circuits), and SoCs (system-on-chip).

[0003] To verify the function of the design, the design needs to be simulated under a verification platform. However, for a design of a complex instruction set type, the design has complex situations such as disassembling instructions into microcodes (uops) for execution and interrupt occurring during the execution of the microcodes. Therefore, how to provide function verification support for the design of the complex instruction set type has become a problem to be solved by those skilled in the art. SUMMARY

[0004] Therefore, embodiments of the present application provide a designed function verification method and system, an electronic device for verification, and a storage medium to provide function verification support for the design of the complex instruction set type.

[0005] To achieve the above object, embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, embodiments of the present application provide a designed function verification method, comprising:

[0007] determining whether an interrupt occurs to the design under test in a current clock cycle;

[0008] if the interrupt occurs to the design under test in the current clock cycle, determining interrupt trigger information of the design under test for executing the interrupt, and obtaining register information updated by the design under test for executing the interrupt;

[0009] generating interrupt retirement information of the design under test based on the interrupt trigger information and the register information, and saving the interrupt retirement information of the design under test into a preset retirement information queue;

[0010] controlling the simulation execution of the reference model based on the information saved in the retirement information queue, and obtaining register information updated by the reference model based on the simulation execution;

[0011] determining a verification result based on the register information updated by the design under test and the register information updated by the reference model.

[0012] In a second aspect, an embodiment of the present application provides a verification system, comprising: a design under test, a general verification component, and a reference model;

[0013] The general verification component is configured to determine whether the design under test has an interrupt in a current clock cycle, determine interrupt trigger information of the design under test executing the interrupt, and obtain register information updated by the design under test executing the interrupt, generate interrupt retirement information of the design under test based on the interrupt trigger information and the register information, save the interrupt retirement information of the design under test into a preset retirement information queue, control simulation execution of the reference model based on information saved in the retirement information queue, obtain register information updated by the reference model based on the simulation execution, and determine a verification result based on the register information updated by the design under test and the register information updated by the reference model.

[0014] In a third aspect, an embodiment of the present application provides an electronic device for verification, comprising at least one memory and at least one processor. The memory stores one or more computer executable instructions, and the processor invokes the one or more computer executable instructions to perform the function verification method of the design according to the first aspect.

[0015] In a fourth aspect, an embodiment of the present application provides a storage medium, which stores one or more computer executable instructions. When the one or more computer executable instructions are executed, the function verification method of the design according to the first aspect is implemented.

[0016] The embodiments of the present application can monitor the design under test in real time. When the design under test has an interrupt in a current clock cycle, the interrupt trigger information is determined and the register information updated by the design under test executing the interrupt is obtained, so that the interrupt retirement information used for interrupt verification of the design under test is generated based on the interrupt trigger information and the register information. The interrupt retirement information can be saved into a retirement information queue, so that the embodiments of the present application can control the reference model to at least implement simulation execution such as interrupt based on information saved in the retirement information queue. Furthermore, the embodiments of the present application can at least implement interrupt verification of the design under test based on the register information updated by the design under test and the register information updated by the reference model based on the simulation execution. The embodiments of the present application can at least implement co-simulation of the design and the reference model for the interrupt by generating and saving the interrupt retirement information into the retirement information queue when the design has complex conditions such as interrupt, thereby providing function verification support when the design has complex conditions such as interrupt. It can be seen that the embodiments of the present application can provide function verification support for a design of a complex instruction set type with complex conditions such as interrupt. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only only the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of the provided drawings.

[0018] Figure 1 The architecture diagram of the verification system provided by the embodiments of the present application.

[0019] Figure 2 Another architecture diagram of the verification system provided by the embodiments of the present application.

[0020] Figure 3 Still another architecture diagram of the verification system provided by the embodiments of the present application.

[0021] Figure 4 The example diagram of the retirement information queue provided by the embodiments of the present application.

[0022] Figure 5 Still another architecture diagram of the verification system provided by the embodiments of the present application.

[0023] Figure 6 The flowchart of the designed functional verification method provided by the embodiments of the present application.

[0024] Figure 7 The example diagram of the information structure in the retirement information queue provided by the embodiments of the present application.

[0025] Figure 8 Another flowchart of the designed functional verification method provided by the embodiments of the present application.

[0026] Figure 9 The block diagram of the electronic device for verification provided by the embodiments of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely below with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments only are part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor belong to the scope of protection of the present application.

[0028] With the evolution of integrated circuit technology, the design of complex instruction set type generally adopts superscalar structure to improve performance. For example, high-performance CPU chips supporting complex instruction set type introduce branch prediction, out-of-order execution, multi-level cache, simultaneous multithreading, multi-core, and other technologies to improve IPC (Instruction Per Clock, the number of instructions executed per clock cycle).

[0029] In the design of complex instruction set type, the execution granularity of the design is microcode, that is, the instruction needs to be disassembled into multiple microcodes through decoding, and the execution of the instruction is implemented by executing multiple microcodes. In the process of designing and executing microcode, the design also needs to handle various interrupt conditions (such as asynchronous interrupts). Therefore, for the design of complex instruction set type, the verification complexity of the design is high, and the verification platform needs to provide corresponding verification support for the design of complex instruction set type.

[0030] Embodiments of the present application can support functional verification of a design. It should be noted that the verification of the design is divided into pre-silicon verification and post-silicon verification; the pre-silicon verification is further divided into functional verification and formal verification, etc. In the process of functional verification, the design and the reference model need to be compared, and it is judged whether the functions executed by the design and the reference model are consistent, so as to realize the functional verification of the design.

[0031] Figure 1 An exemplary architecture diagram of a verification system provided by an embodiment of the present application is shown. Figure 1 The verification system shown can be a verification platform built for verifying a design. The verification platform is, for example, a UVM (Universal Verification Methodology) environment. As an optional implementation, UVM can be implemented based on Testbench, which is a verification means that can simulate the input excitation and output check of the design in the actual environment, thereby analyzing and checking the design at the software level. For example, Figure 1 As shown, the verification system can include a design under test (DUT) 110, a universal verification component (UVC) 120, a reference model (Reference Model) 130, and a test stimulus (Test stimulus) 140.

[0032] The design under test 110 is a design to be verified (for example, a design to be functionally verified) by an embodiment of the present application, which can be a complex instruction set type design, such as a CPU chip supporting a complex instruction set type.

[0033] The general verification component 120 is a verification component for implementing co-simulation of the design under test 110 and the reference model 130 according to the embodiments of the present application. In the embodiments of the present application, on the one hand, the general verification component 120 needs to support the interrupt verification of the design under test 110 during the execution of microcode; on the other hand, the general verification component 120 needs to support the instruction execution verification of the design under test 110 in the granularity of microcode.

[0034] The reference model 130 is a model for co-simulation with the design under test 110, and the reference model 130 can be simulated and executed under the control of the general verification component 120. For example, the reference model 130 can be simulated and executed for instructions under the control of the general verification component 120, so as to realize the instruction execution verification of the design under test 110 through the instruction execution result of the design under test 110 and the instruction execution result of the reference model 130. For another example, the reference model 130 can be simulated and executed for interrupts under the control of the general verification component 120, so as to realize the interrupt verification of the design under test 110 through the interrupt execution result of the design under test 110 and the interrupt execution result of the reference model 130. In some embodiments, the granularity of the reference model 130 for simulating and executing instructions can be instruction level or microcode level. When the granularity of the reference model 130 for simulating and executing instructions is instruction, the embodiments of the present application can realize the synchronization between the microcode-accurate design under test and the instruction-accurate reference model.

[0035] In some embodiments, the reference model 130 can be written in C / C++ language and can realize the function simulation of various instructions of the design under test 110. The reference model 130 can support multi-thread simulation. For example, the reference model 130 can support multi-thread instruction level simulation. The reference model 130 can run test stimuli independently as a platform for stimulus development, or can be integrated into a verification platform for co-simulation with the design under test.

[0036] The test stimulus 140 can be used to provide test stimuli for the design under test 110 and the reference model 130. As an optional implementation, the test stimulus 140 can be a binary file developed based on assembly language and compiled by a compiler as the test stimulus for the design under test 110 and the reference model 130. As an optional implementation, the test stimulus 140 can provide stimuli including directed test stimulus, random test stimulus, and program fragments extracted based on benchmark, etc. As an optional implementation, the test stimulus 140 can send the stimuli to the design under test 110 and the reference model 130 through backdoor loading, so as to ensure that the design under test 110 and the reference model 130 use the same stimuli.

[0037] In some embodiments, when the design under test 110 uses a high-performance superscalar structure, the design under test 110 can use an out-of-order execution scheme to improve instruction parallelism. In this case, as an optional implementation, Figure 2 An exemplary architecture diagram of a verification system provided by an embodiment of the present application is shown. In combination with Figure 1 and Figure 2 As shown, the design under test 110 can include a Retire Order Buffer (ROB) 111, a register file 112, and an execution unit 113.

[0038] The ROB 111 is used to implement instruction order submission and precise exception. The ROB 111 can track instructions that have been issued in the pipeline of the design under test 110, record information such as whether the instructions have been executed and whether there are exceptions, and sequentially submit the executed instructions, while saving the register information updated by the executed instructions to the register file 112.

[0039] In the case where the design under test 110 uses microcode as the execution granularity, as an optional implementation, after the design under test 110 obtains an instruction, the instruction can be disassembled into multiple microcodes through decoding; then, after register renaming, the multiple microcodes of the instruction can be dispatched to an issue queue and the ROB 111. The ROB 111 will track the status of the instruction in the pipeline, and when the instruction is executed and there is no exception, the ROB 111 will submit the instruction and cause the microcodes of the instruction to retire (also referred to as exit) from the ROB 111, while updating the register information corresponding to the executed instruction in the register file 112, for example, updating the execution result of the instruction in the register file 112.

[0040] That is, when the execution granularity of the design under test 110 is microcode, the ROB 111 is a microcode-granularity instruction reordering queue, and the microcodes corresponding to the out-of-order executed instructions retire in the ROB 111, and the ROB 111 can record the retired microcode information. In some embodiments, a design (for example, a high-performance CPU chip) generally supports multiple microcode information or instructions to retire in the same clock cycle, and therefore the ROB 111 can support multiple microcode information to retire in one clock cycle. For example, the ROB 111 supports a group of 8 microcode information to retire in one clock cycle.

[0041] The register file 112 is a register collection of the design under test 110. As an optional implementation, the registers corresponding to various functional modules of the design under test 110 can be physically arranged separately.

[0042] The execution unit 113 is a final unit device of the design under test 110 to execute instructions, and supports out-of-order execution of the instructions. When the execution granularity of the design under test 110 is microcode, the execution unit 113 implements instruction execution in the granularity of microcode. If an interruption occurs in the process of executing the microcode, the execution unit 113 can have corresponding interruption information.

[0043] In some embodiments, the design under test 110 can be a CPU chip, which can include a core cluster, and the core cluster can include a plurality of CPU cores. Each CPU core can include a reorder buffer 111, a register file 112, an execution unit 113, and the like. As an optional implementation, Figure 3 An exemplary architecture diagram of a verification system provided by an embodiment of the present application is shown. In combination with the foregoing description of the design under test 110, the architecture diagram of the verification system is described. Figure 2 And Figure 3 As shown, the design under test 110 can be a core cluster 300, which includes a plurality of CPU cores 310 to 31n. The specific value of n can be determined according to the design requirements of the CPU chip, and the embodiments of the present application are not limited thereto. Each CPU core can be provided with a reorder buffer 111, a register file 112, an execution unit 113, and the like. Each CPU core can support SMT (Simultaneous Multithreading), and a plurality of logical cores can be generated by one CPU core. The plurality of logical cores generated by one CPU core can share a plurality of registers in the CPU core, or each logical core can have a private part of the registers. Based on the architecture shown, Figure 3 As shown in the architecture, the general verification component 120 can be used to verify each CPU core. It should be noted that, Figure 3 The structure of the design under test shown is only optional, and the embodiments of the present application can also support a design under test having only a single CPU core, and the like.

[0044] As a core component of the verification system, the general verification component 120 needs to support interruption verification of the design under test 110 in the process of executing the microcode, and also needs to support instruction execution verification of the design under test 110 in the granularity of microcode.

[0045] In some embodiments, to implement the interrupt validation of the DUT 110, the general verification component 120 can monitor whether the DUT has an interrupt in each clock cycle, for example, monitor whether there is interrupt information in the execution unit 113 in each clock cycle. When the general verification component 120 monitors that the DUT has an interrupt in a clock cycle, the general verification component 120 can determine the interrupt trigger information of the DUT executing the interrupt, and the register information updated by the DUT executing the interrupt (for example, the result of the DUT executing the interrupt), so as to enable the reference model 130 to simulate executing the interrupt by using the interrupt trigger information subsequently. Then, the general verification component 120 can compare the register information updated by the DUT 110 executing the interrupt with the register information updated by the reference model 130 simulating executing the interrupt, to implement the interrupt validation of the DUT 110.

[0046] In some embodiments, to implement the microcode-granularity instruction execution validation of the DUT 110, the general verification component 120 can obtain a plurality of pieces of microcode information retired by the DUT 110 in each clock cycle, and obtain the register information updated by the DUT 110 executing the instructions corresponding to the microcode (for example, the result of the DUT executing the instructions). Where an instruction is decomposed into a plurality of pieces of microcode for execution, the register information updated by the DUT executing the instructions can be saved in the register file 112, and the general verification component 120 can obtain the register information updated by the DUT executing the instructions from the register file 112 in each clock cycle. As an optional implementation, the general verification component 120 can obtain the retired microcode information from the reorder buffer 111 in each clock cycle, and obtain the values of the registers updated by the DUT executing the instructions from the register file 112.

[0047] The general verification component 120 can control the reference model 130 to simulate executing the instructions corresponding to the microcode based on the microcode information retired by the DUT 110 in each clock cycle, so that the reference model 130 implements the co-simulation with the DUT 110. Then, the general verification component 120 can obtain the register information updated by the reference model 130 simulating executing the instructions, and compare the register information updated by the DUT 110 executing the instructions with the register information updated by the reference model 130 simulating executing the instructions, to implement the microcode-granularity instruction execution validation of the DUT 110. In some embodiments, the granularity of the reference model 130 simulating executing the instructions can be instruction level or microcode level. When the granularity of the reference model 130 simulating executing the instructions is instruction level, the embodiment of the present application can implement the synchronization between the microcode-accurate DUT and the instruction-accurate reference model.

[0048] As an optional implementation, the register file 112 can include multiple types of registers, such as general-purpose registers, instruction pointer registers, flag registers, floating-point registers, segment registers, vector extension instruction set registers, and the like. The general-purpose verification component 120 can obtain the values of the registers from the multiple types of registers when obtaining the register information updated by the interruption of the design under test 110 or the register information updated by the execution of the instruction.

[0049] In some embodiments, the interruption verification of the design under test 110 can be prioritized over the instruction execution verification of the design under test; based on this, the general-purpose verification component 120 performs the interruption verification of the design under test 110 if it monitors the interruption of the design under test in a clock cycle, and performs the instruction execution verification of the design under test 110 based on the microcode information with which the design under test retires in the clock cycle if it does not monitor the interruption of the design under test in the clock cycle.

[0050] The general-purpose verification component 120 can uniformly implement the information for the interruption verification of the design under test and the information for the instruction execution verification of the design under test at the information structure level; based on this, the embodiments of the present application provide interruption retirement information for the interruption verification and microcode retirement information for the instruction execution verification. The interruption retirement information can include the interruption trigger information of the interruption of the design under test and the register information updated by the interruption of the design under test; the interruption retirement information can be generated by the general-purpose verification component 120 after it monitors the interruption of the design under test. The microcode retirement information can include the boundary microcode information of the last execution of the multiple pieces of microcode information of the instruction disassembly and the register information updated by the execution of the instruction of the design under test; the general-purpose verification component 120 can generate the microcode retirement information if it does not detect the interruption of the design under test in a clock cycle. That is, for any clock cycle, the general-purpose verification component 120 generates the interruption retirement information if it monitors the interruption of the design under test, and generates the microcode retirement information if it does not monitor the interruption of the design under test.

[0051] In some embodiments, a retirement information queue can be arranged in the general-purpose verification component 120, and the information saved in the retirement information queue can be the interruption retirement information and the microcode retirement information; for example, the general-purpose verification component 120 saves the generated interruption retirement information and microcode retirement information in the retirement information queue in the order of generation. Figure 4 An optional example diagram of the retirement information queue is shown by way of example. As shown in Figure 4 The retirement information queue saves multiple pieces of information, which can be interruption retirement information or microcode retirement information. For example, the general-purpose verification component 120 saves the generated information in the retirement information queue each time it generates the interruption retirement information or the microcode retirement information.

[0052] Based on the information stored in the retirement information queue, the general verification component 120 can sequentially extract information from the retirement information queue to perform simulation verification of the design under test. If the information extracted by the general verification component 120 from the retirement information queue is interrupted retirement information, the general verification component 120 can perform interrupted verification of the design under test. If the information extracted by the general verification component 120 from the retirement information queue is microcode retirement information, the general verification component 120 can perform instruction execution verification of the design under test. In some embodiments, when the information in the retirement information queue is not empty, the general verification component 120 can sequentially perform simulation verification of the design under test based on the information existing in the retirement information queue.

[0053] In some embodiments, the general verification component can be divided into a monitoring section and a verification control section. The monitoring section monitors the design under test and collects data, generating information to be stored in a retirement information queue. The verification control section, based on the information in the retirement information queue, performs simulation verifications such as interrupt verification and instruction execution verification of the design under test. As an optional implementation, Figure 5 Another architectural diagram of the verification system provided in this application is illustrated as an example. Combined with... Figure 1 , Figure 2 , Figure 3 and Figure 5 As shown, the general verification component 120 may include a monitor 121, a scoreboard 122, and a retirement information queue 123. The monitor 121 is the monitoring component of the general verification component; the scoreboard 122 is the verification control component of the general verification component. In some embodiments, the retirement information queue 123 may be disposed within the scoreboard 122; for example, the retirement information queue 123 may be embodied in the scoreboard 122.

[0054] Monitor 121 can monitor the design under test (DUT) 110 in real time. On one hand, monitor 121 monitors whether the DUT 110 is interrupted in each clock cycle. When monitor 121 detects that the DUT 110 is interrupted in a certain clock cycle, the monitor can determine the interrupt trigger information of the DUT 110 and obtain the register information updated by the DUT 110 during the interrupt. Based on the interrupt trigger information and the obtained register information, the monitor generates interrupt retirement information and saves it to the retirement information queue 123. On the other hand, when monitor 121 detects that the DUT 110 is not interrupted in a certain time cycle, the monitor can obtain multiple microcode messages retired by the DUT 110 in that clock cycle and the register information updated by the DUT 110's executed instructions. Based on the multiple microcode messages, the monitor determines the boundary microcode message of the last executed instruction. Based on the boundary microcode message and the obtained register information, the monitor generates microcode retirement information and saves it to the retirement information queue 123.

[0055] The scoreboard 122 can extract information from the retirement information queue 123 when the information in the retirement information queue 123 is not empty, and control the simulation execution of the reference model 130 based on the extracted information to implement the simulation verification of the design under test. For example, the scoreboard 122 extracts the information of an interrupt retirement from the retirement information queue 123, and controls the simulation execution of the reference model 130 based on the interrupt retirement to implement the interrupt verification of the design under test. For another example, the scoreboard 122 extracts the information of microcode retirement from the retirement information queue 123, and controls the simulation execution of the reference model 130 based on the microcode retirement to implement the instruction execution verification of the design under test.

[0056] It should be noted that the division of the general verification component 120 into the monitor 121, the scoreboard 122, and the retirement information queue 123 is only an optional division manner, and the embodiments of the present application are not limited to other division manners of the general verification component 120. For example, the general verification component 120 can use an integral device to complete the functions of the monitor 121 and the scoreboard 122.

[0057] As an optional implementation, Figure 6 An optional flowchart of a method for verifying the function of a design according to an embodiment of the present application is shown. The method flow can be implemented by a general verification component, such as the general verification component 120 shown in FIG. 1. Figure 6 As shown in the figure, the method flow can include the following steps.

[0058] In step S610, the design under test is monitored in real time.

[0059] The general verification component can monitor the design under test in real time. For example, in each clock cycle, the general verification component can monitor whether an interrupt occurs in the design under test, monitor the microcode information retired by the reorder buffer of the design under test, monitor the register information updated by the register file of the design under test when the design under test executes an interrupt or an instruction, and the like.

[0060] In some embodiments, step S610 can be implemented by a monitor. For example, the monitor can monitor whether there is interrupt information in the execution unit in each clock cycle; the monitor can monitor the microcode information retired by the reorder buffer of the design under test in each clock cycle; and the monitor can monitor the register information updated by the register file of the design under test when the design under test executes an interrupt or an instruction.

[0061] In step S611, it is determined whether an interrupt occurs in the design under test in the current clock cycle. If yes, step S612 is performed; if no, step S614 is performed.

[0062] The current clock cycle can be the current clock cycle of the design under test, and the current clock cycle is in dynamic change as time goes on.

[0063] In some embodiments, the universal verification component can monitor whether there is interrupt information in the execution unit of the design under test in the current clock cycle, if yes, it is determined that the design under test has an interrupt in the current clock cycle, if not, it is determined that the design under test has no interrupt in the current clock cycle. In some embodiments, the interrupt can be an asynchronous interrupt.

[0064] As an optional implementation, step S611 can be implemented by the monitor.

[0065] In step S612, interrupt trigger information of the interrupt executed by the design under test is determined, and register information updated by the interrupt executed by the design under test is obtained.

[0066] When the design under test has an interrupt in the current clock cycle, the universal verification component needs to determine the interrupt trigger information of the interrupt executed by the design under test. The interrupt trigger information can be understood as the information of the interrupt executed by the design under test. In some embodiments, if the execution granularity of the design under test is microcode, the interrupt of the design under test can be that the execution unit has an interrupt and performs interrupt response in the process of executing the microcode. Since the response time of the design under test to the interrupt (such as an asynchronous interrupt) is not fixed, the application embodiment can obtain the microcode entry address corresponding to the interrupt and the interrupt valid signal from the reorder buffer of the design under test; and process the microcode entry address and the interrupt valid information to obtain the interrupt trigger information. As an optional implementation, the interrupt trigger information can include thread number corresponding to the interrupt, interrupt type, interrupt number and the like. The universal verification component can process the microcode entry address and the interrupt valid information obtained from the reorder buffer to obtain the interrupt trigger information such as the thread number corresponding to the interrupt, the interrupt type, the interrupt number and the like.

[0067] When the design under test has an interrupt in the current clock cycle, the universal verification component can further obtain the register information updated by the design under test executing the interrupt from the register file of the design under test. As an optional implementation, the universal verification component can obtain the information of multiple types of registers updated by the design under test executing the interrupt from the register file of the design under test. For example, the values of the general register, the instruction pointer register, the flag register, the floating point register, the segment register, the vector extension instruction set register and the like updated by the design under test executing the interrupt are obtained from the register file of the design under test.

[0068] As an optional implementation, step S612 can be implemented by the monitor.

[0069] In step S613, based on the interrupt trigger information and the obtained register information, the interrupt retirement information of the design under test is generated, and the interrupt retirement information is saved to the retirement information queue.

[0070] After the general verification component determines the interrupt trigger information of the execution interruption of the design under test and acquires the register information updated by the execution interruption of the design under test, the general verification component can generate interrupt retirement information for interrupt verification of the design under test based on the interrupt trigger information and the corresponding register information. The interrupt retirement information generated by the general verification component can be saved into the retirement information queue. In some embodiments, the general verification component can package the interrupt trigger information and the corresponding register information to obtain the interrupt retirement information.

[0071] As an optional implementation, step S613 can be implemented by the monitor.

[0072] Based on steps S611 to S613, the general verification component can generate interrupt retirement information for interrupt verification of the execution of the design under test when the design under test is interrupted and save the interrupt retirement information into the retirement information queue to provide a basis for subsequent simulation of the execution interruption of the design under test by the general verification component controlling the reference model. It can be understood that, as time elapses, the general verification component can generate multiple pieces of interrupt retirement information and sequentially save the interrupt retirement information into the retirement information queue in the case where the design under test is interrupted multiple times.

[0073] In step S614, multiple pieces of microcode information retired by the design under test in the current clock cycle and register information updated by instructions corresponding to the microcode executed by the design under test are acquired.

[0074] The general verification component monitors whether the design under test is interrupted in the current clock cycle. If the design under test is not interrupted in the current clock cycle, the general verification component can acquire multiple pieces of microcode information retired by the design under test in the current clock cycle and register information updated by instructions corresponding to the microcode executed by the design under test to generate microcode retirement information for instruction execution verification of the design under test. It should be noted that one instruction can be decoded into multiple pieces of microcode for execution, and the instructions corresponding to the microcode can be regarded as instructions corresponding to the multiple pieces of microcode information retired.

[0075] In some embodiments, based on the microcode information of the design under test saved in the reorder buffer and the register information saved in the register file, the general verification component can acquire multiple pieces of microcode information retired by the design under test in the current clock cycle from the reorder buffer of the design under test and acquire register information updated by instructions executed by the design under test from the register file of the design under test.

[0076] As an optional implementation, the general verification component can acquire information of multiple types of registers updated by instructions executed by the design under test from the register file of the design under test. For example, the general verification component can acquire values of general registers, instruction pointer registers, flag registers, floating point registers, segment registers, vector extension instruction set registers and the like updated by instructions executed by the design under test from the register file of the design under test.

[0077] As an optional implementation, step S614 can be implemented by the monitor.

[0078] In step S615, boundary microcode information corresponding to the instruction boundary is determined from the plurality of microcode information.

[0079] In some embodiments, the reference model can be an instruction-level model (e.g., the execution granularity of the reference model is an instruction) when the reference model simulates the execution of the instruction in the subsequent control. Therefore, after the general verification component obtains the plurality of microcode information retired by the design under test in the current clock cycle, the general verification component needs to determine the boundary microcode information corresponding to the instruction boundary from the plurality of microcode information, so as to determine the execution boundary of the instruction in the case of microcode granularity execution of the instruction.

[0080] As an optional implementation, the reorder buffer can support the retirement of a plurality of microcode information in one clock cycle, and the plurality of microcode information can have an execution order. The last executed microcode can be regarded as the boundary of the instruction, and the last executed microcode information can be referred to as boundary microcode information in the embodiments of the present application. That is, among the plurality of microcode obtained by decoding an instruction, the last executed microcode corresponds to the instruction boundary.

[0081] Based on the fact that the number of microcode information retired by the design under test in the current clock cycle is a plurality, the embodiments of the present application can determine the boundary microcode information by judging whether the plurality of microcode information corresponds to the instruction boundary one by one. If the currently judged microcode information does not correspond to the instruction boundary, the next microcode information in the plurality of microcode information is judged whether it corresponds to the instruction boundary, until the boundary microcode information corresponding to the instruction boundary is determined.

[0082] As an optional implementation, step S615 can be implemented by the monitor.

[0083] In step S616, based on the boundary microcode information and the register information updated by the execution of the instruction by the design under test, microcode retirement information of the design under test is generated, and the microcode retirement information of the design under test is saved to the retirement information queue.

[0084] After the general verification component determines the boundary microcode information corresponding to the current clock cycle of the design under test and obtains the register information updated by the execution of the corresponding instruction by the microcode of the design under test, the general verification component can generate microcode retirement information for verifying the instruction execution of the design under test based on the boundary microcode information and the corresponding register information. The microcode retirement information generated by the general verification component can be saved to the retirement information queue. In some embodiments, the general verification component can package the boundary microcode information and the corresponding register information, thereby obtaining the microcode retirement information.

[0085] As an optional implementation, step S616 can be implemented by the monitor.

[0086] Based on steps S614 to S616, the general verification component can generate microcode retirement information and save it to the retirement information queue during clock cycles when the design under test is not interrupted, thus providing a basis for the general verification component to control the reference model to simulate and execute instructions. It is understood that as clock cycles progress, the general verification component can generate multiple microcode retirement messages and save them to the retirement information queue during multiple clock cycles when no interruption occurs.

[0087] Based on steps S610 to S616, the retirement information queue can store multiple pieces of information, which may include interrupted retirement information and microcode retirement information. To achieve a unified information structure for interrupted retirement information and microcode retirement information, this application embodiment further provides an information structure for storing information in the retirement information queue. Figure 7 An example diagram illustrating the information structure in a retirement information queue is shown below. Figure 7 As shown, the information in this retirement information queue has at least three data fields: an interrupt data field, a microcode data field, and a register information data field. The interrupt data field records interrupt trigger information, the microcode data field records boundary microcode information, and the register information data field records register information. Based on... Figure 7 As an optional implementation, the information structure shown in this application embodiment can use the interrupt data field and register information data field when generating interrupt retirement information, while the microcode data field is left empty; for example, this application embodiment can store the interrupt trigger information of the design under test executing the interrupt in the interrupt data field, store the register information updated by the design under test executing the interrupt in the register information field, and leave the microcode data field unused, thereby obtaining the interrupt retirement information. Based on Figure 7 As an optional implementation, the information structure shown in this application embodiment allows the use of the microcode data field and register information data field when generating microcode retirement information, while leaving the interrupt data field unused. For example, this application embodiment can store boundary microcode information in the microcode data field, store register information updated by the instruction executed by the design under test in the register information field, and leave the interrupt data field unused, thereby obtaining microcode retirement information. Based on the information structure provided in this application embodiment, this application embodiment can use the same type of information structure to generate interrupt retirement information and microcode retirement information, and save them to the retirement information queue. As an optional implementation, the information structure provided in this application embodiment can be called a retirement item.

[0088] In step S617, information is extracted from the retirement information queue.

[0089] In some embodiments, the embodiments of the present application can extract information from the retirement information queue when the retirement information queue is not empty, so as to implement corresponding simulation verification of the design under test based on the extracted information. For example, if the extracted information is interrupt retirement information, the embodiments of the present application can implement interrupt verification of the design under test, and if the extracted information is microcode retirement information, the embodiments of the present application can implement instruction execution verification of the design under test.

[0090] In some embodiments, the information in the retirement information queue can be saved in the order of generation, and the embodiments of the present application can extract the information in the retirement information queue in sequence.

[0091] As an optional implementation, the retirement information queue can be arranged in the scoreboard, for example, the general verification component can instantiate the retirement information queue in the scoreboard. In further optional implementations, the retirement information queue can be in the form of an array.

[0092] As an optional implementation, if the general verification component detects that the data size of the retirement information queue is greater than 0, it can be considered that the retirement information queue is not empty, and the embodiments of the present application can extract information from the retirement information queue. The embodiments of the present application implement simulation verification of the design under test based on the fact that the retirement information queue is not empty, i.e. extracting information from the retirement information queue, and the information in the retirement information queue is generated based on real-time monitoring of the design under test. Therefore, the embodiments of the present application can implement real-time simulation verification of the design under test based on the information saved in the retirement information queue in real time during real-time monitoring of the design under test, thereby improving the verification efficiency of the design under test.

[0093] As an optional implementation, step S617 can be implemented by the scoreboard in the general verification component.

[0094] In step S618, if the extracted information is interrupt retirement information, the embodiments of the present application control the reference model to simulate execution of the interrupt according to the interrupt trigger information in the interrupt retirement information, and obtain register information updated by the reference model simulating execution of the interrupt.

[0095] If the information extracted from the retire information queue by the general verification component is an interrupt retire information, the general verification component can perform interrupt verification on the design under test. Since the design under test needs to be simulated together with the reference model, the general verification component can control the reference model to simulate the execution of the interrupt based on the interrupt retire information. In some embodiments, the general verification component can control the reference model to simulate the execution of the interrupt based on the interrupt trigger information in the interrupt retire information. For example, the general verification component can pass the interrupt trigger information to the reference model, so that the reference model simulates the execution of the interrupt based on the interrupt trigger information. In one example, the general verification component can send the interrupt trigger information to the reference model and control the reference model to perform single-step execution, so that the reference model can simulate the execution of the interrupt based on the thread number, the interrupt type, the interrupt number, etc. in the interrupt trigger information, and update the register information corresponding to the execution of the interrupt in the register file of the reference model (e.g. the result of the execution of the interrupt).

[0096] As an optional implementation, the reference model 130 can simulate all the functions of the instruction set of the design under test, and has a register file consistent with the design under test. That is, the reference model itself has a register file, and the register file of the reference model is consistent with the register file of the design under test in terms of settings. For example, in the case where the register file of the design under test has multiple types of registers (e.g. general-purpose registers, instruction pointer registers, flag registers, floating-point registers, segment registers, vector extension instruction set registers, etc.), the reference model can also set a register file of multiple types of registers.

[0097] After the general verification component controls the reference model to simulate the execution of the interrupt, the general verification component can obtain the register information updated by the reference model in simulating the execution of the interrupt from the register file of the reference model. For example, the general verification component can obtain the values of the registers updated by the reference model in simulating the execution of the interrupt from the multiple types of registers of the reference model.

[0098] In step S619, the register information updated by the design under test in executing the interrupt is compared with the register information updated by the reference model in simulating the execution of the interrupt.

[0099] After the general verification component obtains the register information updated by the reference model in simulating the execution of the interrupt, the general verification component can compare the register information based on the register information in the interrupt retire information; and determine the verification result of the design under test in executing the interrupt based on the comparison result.

[0100] In some embodiments, the embodiments of the present application can compare the information related to the execution of the interrupt in all the registers of the design under test and the reference model.

[0101] In step S620, it is determined whether the comparison result is consistent. If yes, step S617 is performed, and if no, step S621 is performed.

[0102] If the updated register information of the design under test is consistent with the updated register information of the reference model simulation execution, it can be concluded that the execution of the design under test is correct. In this embodiment, the process can return to step S617, extract the next piece of information from the retirement information queue for simulation verification of the design under test, until the number of pieces of information extracted from the retirement information queue for simulation verification reaches the set upper limit, at which point the verification of the design under test can be stopped.

[0103] In step S621, an error message is output and the process exits.

[0104] If the updated register information of the design under test is inconsistent with the updated register information of the reference model simulation, this embodiment of the application can provide error information and exit the verification process of the design under test. Alternatively, in the provided error information, this embodiment of the application can output the name of the register with inconsistent register information and the corresponding instruction.

[0105] In some embodiments, in the case of a reference model simulation execution interruption, if the register information updated by the execution interruption of the design under test is consistent with the register information updated by the simulation execution interruption of the reference model, the execution interruption of the design under test can be considered correct, and the next piece of information is extracted from the retirement information queue for simulation verification of the design under test; if they are inconsistent, an error is reported and the system exits, and the name of the register with inconsistent information and the instruction are printed.

[0106] In step S622, if the extracted information is microcode retirement information, the reference model is controlled to simulate the execution of instructions based on the boundary microcode information in the microcode retirement information, and the register information updated by the reference model to simulate the execution of instructions is obtained.

[0107] Based on the microcode retirement information extracted from the retirement information queue in step S617, the general verification component can perform instruction execution verification on the design under test. Since the design under test requires simulation verification in conjunction with a reference model, the general verification component can control the reference model to simulate instruction execution based on the microcode retirement information. In some embodiments, the general verification component can control the reference model to execute instructions step-by-step based on the boundary microcode information in the microcode retirement information.

[0108] After the general verification component controls the reference model to simulate and execute instructions, the general verification component can obtain the register information updated by the simulated instructions from the reference model's register file. For example, the general verification component can obtain the values ​​of the registers updated by the simulated instructions from various types of registers in the reference model.

[0109] In step S623, the register information updated by the to-be-tested design execution instruction is compared with the register information updated by the reference model simulation execution instruction.

[0110] After the universal verification component acquires the register information updated by the reference model simulation execution instruction, the universal verification component can compare the register information based on the register information in the microcode retirement information; and determine the verification result of the to-be-tested design execution instruction based on the comparison result.

[0111] In some embodiments, most of the registers are updated and information is captured before the instruction is retired, so the register information only needs to be synchronized to the instruction retirement stage, but there is a delay in updating the information of the segment register (the segment register is used in the design to support the segmented management mode). Based on this, the embodiments of the present application can determine whether the instruction delays updating the segment register through a defer (delay) signal, i.e., the defer signal can be used to indicate whether the instruction delays updating the segment register; for example, if the defer signal is valid, the segment register is updated with a delay, and if the defer signal is invalid, the segment register is not updated with a delay. Therefore, when the segment registers in the register stacks of the to-be-tested design and the reference model are set, the embodiments of the present application need to determine, based on the defer signal, whether to use the information in the segment register when acquiring the register information of the to-be-tested design and the reference model and / or comparing the register information.

[0112] In some embodiments, the embodiments of the present application can carry the defer signal in the microcode retirement information when generating the microcode retirement information, so as to determine whether to acquire and compare the information of the segment register in the to-be-tested design and the reference model through the defer signal in the microcode retirement information. As an optional implementation, if the defer signal is invalid and the instruction (which can correspond to the boundary microcode information) is a normal instruction, the embodiments of the present application can acquire the information of the segment register when acquiring the register information of the to-be-tested design and the reference model, and compare the register information of all registers when comparing the register information of the to-be-tested design and the reference model. For example, if the instruction is a normal instruction and the defer signal is invalid, the universal verification component can compare the register information of all registers updated by the to-be-tested design execution instruction with the register information of all registers updated by the reference model simulation execution instruction.

[0113] As an optional implementation, if the defer signal is valid and the instruction is a normal instruction, the embodiments of the present application can not acquire the information of the segment register when acquiring the register information of the to-be-tested design and the reference model, and can not compare the information of the segment register when comparing the register information of the to-be-tested design and the reference model. For example, if the instruction is a normal instruction and the defer signal is valid, the register information of all registers except the segment register updated by the to-be-tested design execution instruction is compared with the register information of all registers except the segment register updated by the reference model simulation execution instruction.

[0114] After step S623, the process can go to step S620, and decide the subsequent step flow based on the comparison result. In some embodiments, for the case of executing instructions for the reference model simulation, if the register information updated by the instructions executed by the design under test is consistent with the register information updated by the instructions executed by the reference model simulation, it can be considered that the instructions executed by the design under test are correct, and the next information is extracted from the retirement information queue for simulation verification of the design under test; if not, an error is reported and the process is exited, and the names of the inconsistent registers and the instructions are printed.

[0115] As an optional implementation, steps S617 to S623 can be implemented by a scoreboard in the general verification component.

[0116] In further embodiments, in the case where the design under test includes multiple CPU cores, different CPU cores can run at different frequencies, and in this case, the general verification component needs to obtain the retired microcode information (the reorder buffer is composed of multiple pipelines, and RE4 is one of the pipelines) at the pipeline RE4 of each CPU core, and obtain the register information at other different pipelines; in order to achieve consistency of the information, the microcode information and the register information obtained from the design under test can be synchronized (for example, the synchronization point is 12 clock cycles after RE4), which can cause a delay of several cycles between the execution of the instructions of the design under test and the single-step execution of the reference model. For example, the microcode of part of the CPU cores is retired first, but due to the low frequency of the part of the CPU cores, after 12 clock cycles, the part of the CPU cores reaches the synchronization point later, and at this time, if the general verification component controls the reference model to perform simulation execution according to the time of reaching the synchronization point, it will be inconsistent with the order of execution of the instructions in the design under test. That is, when different CPU cores run at different frequencies, the reference model can have the case of executing the instructions retired first.

[0117] To solve the above problems, the embodiment of the present application can set a time stamp of instruction execution when obtaining the retired microcode information from the design under test, and the time stamp is further carried in the microcode retirement information formed by the boundary microcode information. That is, the time stamp of the instruction executed by the design under test can be carried in the microcode retirement information, and based on this, the embodiment of the present application can control the reference model to simulate the execution of the instruction according to the time stamp in the microcode retirement information (for example, control the single-step execution order of the reference model according to the time stamp in the microcode retirement information) after obtaining the microcode retirement information in the retirement information queue, so as to ensure that the instructions retired first in the design under test are executed first for simulation verification. For example, for multiple pieces of microcode retirement information in the retirement information queue, the embodiment of the present application can control the reference model to simulate the execution of the instruction according to the order of the time stamps, so that the reference model first simulates the execution of the instruction of the microcode retirement information with the time stamp in the front.

[0118] That is, when the design under test is a single-core single-thread processor, the embodiment of the present application can not introduce the time stamp; and when the design under test is a multi-core multi-thread processor, since the storage order of the microcode retirement information in the retirement information queue is not the real retirement order, the time stamp is used to record the real retirement time of the microcode retirement information, and the retirement order is judged based on the time stamp of the microcode retirement information when the reference model is called, so that the reference model first simulates the execution of the instruction of the microcode retirement information with the time stamp in the front.

[0119] In the embodiment of the present application, the general verification component (for example, the monitor therein) may have the following situations to handle when generating the interrupt retirement information and the microcode retirement information:

[0120] The response time of the design under test (for example, a CPU core) to the asynchronous interrupt is not fixed, so the monitor needs to obtain the interrupt trigger information of the design under test executing the asynchronous interrupt; for example, the thread number, the interrupt type, the interrupt number and other interrupt trigger information are obtained according to the microcode entry address corresponding to the interrupt and the interrupt valid signal; the interrupt trigger information and the corresponding register information can be packaged as interrupt retirement information;

[0121] Most of the registers are updated and captured before the instruction retirement, but the information update of the segment register has a delay, and the embodiment of the present application needs to judge whether the segment register is updated with delay by the defer signal, and carry the defer signal in the microcode retirement information, so as to decide whether to compare the information of the segment register of the design under test and the reference model based on the defer signal;

[0122] When different CPU cores run at different frequencies, the reference model can have the situation of executing instructions after retirement, so the monitor can stamp the timestamps of instruction execution when capturing microcode information, and carry them in the microcode retirement information, so that the subsequent reference model can simulate the execution of instructions according to the timestamps in the microcode retirement information, to ensure that the reference model simulates the execution of instructions first.

[0123] It should be noted that, Figure 6 The method flowchart shown is only an optional method flowchart for implementing design verification by the embodiments of the present application. For a complex instruction set type design, the embodiments of the present application can also only implement the interrupt verification of the design (the specific implementation of interrupt verification can refer to the corresponding part in the foregoing, which will not be expanded here), or only implement the instruction execution verification of the design in the granularity of microcode (the specific implementation of instruction execution verification can refer to the corresponding part in the foregoing, which will not be expanded here). In the case of implementing only the interrupt verification or the instruction execution verification of the design, the embodiments of the present application can monitor the design under test in real time, and correspondingly generate interrupt retirement information or microcode retirement information, and save them into the retirement information queue. Thus, based on the information in the retirement information queue, the simulation execution of the reference model is controlled, the interrupt verification or the instruction execution verification of the design is implemented, and the functional verification support is provided for the complex instruction set type design.

[0124] As an optional implementation, Figure 8 An exemplary another optional flowchart of the functional verification method of the design provided by the embodiments of the present application is shown. The method flowchart can be implemented by the general verification component. Referring to Figure 8 The method flowchart can include the following steps.

[0125] In step S810, it is judged whether an interrupt occurs in the current clock cycle of the design under test.

[0126] The embodiments of the present application can monitor the design under test in real time to judge whether an interrupt occurs in the current clock cycle of the design under test. The optional implementation process of step S810 can refer to the corresponding description in the foregoing, which will not be repeated here.

[0127] In step S811, if an interrupt occurs in the current clock cycle of the design under test, the interrupt trigger information of the interrupt executed by the design under test is determined, and the register information updated by the design under test when executing the interrupt is acquired.

[0128] In step S812, based on the interrupt trigger information and the register information, the interrupt retirement information of the design under test is generated, and the interrupt retirement information of the design under test is saved into the retirement information queue.

[0129] The optional implementation processes of step S811 and step S812 can refer to the corresponding description in the foregoing, which will not be repeated here.

[0130] In step S813, based on the information saved in the retirement information queue, the simulation execution of the reference model is controlled, and the register information updated by the reference model based on the simulation execution is obtained.

[0131] In step S814, based on the register information updated by the design under test and the register information updated by the reference model, the verification result is determined.

[0132] In some embodiments, the retirement information queue can save interrupt retirement information, and the embodiments of the present application can control the simulation execution of interrupts of the reference model based on the interrupt retirement information saved in the retirement information queue, and obtain the register information updated by the simulation execution of interrupts of the reference model; thereby comparing the register information updated by the execution of interrupts of the design under test recorded in the interrupt retirement information and the register information obtained by the simulation execution of interrupts of the reference model, implementing the interrupt verification of the design under test, and obtaining the verification result. The implementation process and technical details of the interrupt verification of the design under test can refer to the corresponding descriptions in the foregoing, which will not be described here.

[0133] In further embodiments, the retirement information queue can also save microcode retirement information, and the embodiments of the present application can control the simulation execution of instructions of the reference model based on the microcode retirement information saved in the retirement information queue, thereby implementing the instruction execution verification of the design under test in the granularity of microcode. The implementation process and technical details of generating the microcode retirement information, and the implementation process and technical details of the instruction execution verification of the design under test can refer to the corresponding descriptions in the foregoing, which will not be described here.

[0134] The embodiments of the present application can monitor the design under test in real time, when there is an interrupt of the design under test in the current clock cycle, determine the interrupt trigger information and obtain the register information updated by the execution of the interrupt of the design under test, thereby generating the interrupt retirement information for the interrupt verification of the design under test by using the interrupt trigger information and the register information. The interrupt retirement information can be saved in the retirement information queue, so that the embodiments of the present application can control the simulation execution of at least interrupts of the reference model based on the information saved in the retirement information queue. Further, the embodiments of the present application can implement at least the interrupt verification of the design under test by using the register information updated by the design under test and the register information updated by the reference model based on the simulation execution. The embodiments of the present application can implement the co-simulation of the design and the reference model for interrupts by generating and saving the interrupt retirement information in the retirement information queue at least in the complex case where there is an interrupt of the design, thereby providing the functional verification support at least in the complex case where there is an interrupt of the design. It can be seen that the embodiments of the present application can provide the functional verification support for the design of the complex instruction set type with complex cases such as interrupts.

[0135] Further, the embodiment of the present application can also generate microcode retirement information for instruction execution verification of the design under test from the microcode execution granularity when there is no interrupt in the current clock cycle. The microcode retirement information can be saved into the retirement information queue, so that the embodiment of the present application can control the simulation execution of the reference model implementation instructions based on the information saved in the interrupt retirement information, and implement the instruction execution verification of the design under test. Therefore, the embodiment of the present application can provide functional verification support for the design of a complex instruction set type with interrupts, instruction disassembly for microcode execution, and the like.

[0136] The scheme provided by the embodiment of the present application has at least the following advantages:

[0137] The interrupt scenario (for example, asynchronous interrupt) of the design is monitored, and the interrupt retirement information carrying the interrupt trigger information and the register information is generated, and then the interrupt trigger information in the interrupt retirement information is delivered to the reference model, and the interrupt verification of the design is implemented by comparing the execution results (register information) of the design and the reference model, so that the verification personnel do not need to develop other tools to test the interrupt, and the verification resources are saved;

[0138] The synchronous comparison between the design under test based on the microcode granularity and the reference model based on the instruction granularity is implemented, and the reference model based on the microcode does not need to be developed, the complexity of the reference model is reduced, and the verification time is shortened;

[0139] When the register information comparison is performed, the register information obtained from the register stack of the design under test and the reference model can cover multiple types of registers, so that the information comparison of multiple types of registers in the design verification is supported, and the accuracy of the design verification is improved;

[0140] The retirement information queue can extract information and perform corresponding verification when the information is not empty, the real-time performance and efficiency of the design verification are improved, and the errors existing in the design can be found in real time;

[0141] The design under test can support single-core, multi-core and multi-thread processors, and the synchronization problem of different CPU cores running at different frequencies is solved by carrying the time stamp in the microcode retirement information, and the clock frequency test scenario is enriched.

[0142] In a further optional implementation, the embodiment of the present application can use other languages or verification libraries to build a verification platform in addition to supporting the use of UVM to build a verification platform, such as the verilog language, the C++ language, and the like. The reference model used by the embodiment of the present application is not limited to the instruction level, and can also be the microcode level. The embodiment of the present application can implement verification for the RTL (register transfer level) design, and can also be applicable to the simulation verification of the netlist design, and can also implement verification for the design of a hardware accelerator.

[0143] The verification scheme designed by the embodiments of the present application is introduced from the functional perspective of the verification system below. In combination with the verification system structure shown in Figures 1 to 5 The verification system provided by the embodiments of the present application can at least include: a design under test, a general verification component and a reference model.

[0144] The general verification component is configured to determine whether the design under test has an interrupt in a current clock cycle; if the design under test has an interrupt in the current clock cycle, determine interrupt trigger information of the design under test executing the interrupt, and acquire register information updated by the design under test executing the interrupt; generate interrupt retirement information of the design under test based on the interrupt trigger information and the register information, and save the interrupt retirement information of the design under test into a preset retirement information queue; control simulation execution of the reference model based on the information saved in the retirement information queue, and acquire register information updated by the reference model based on the simulation execution; and determine a verification result based on the register information updated by the design under test and the register information updated by the reference model.

[0145] In some embodiments, the general verification component can include a monitor and a scoreboard, and the scoreboard is provided with a retirement information queue.

[0146] The monitor is specifically configured to determine whether the design under test has an interrupt in a current clock cycle; if the design under test has an interrupt in the current clock cycle, determine interrupt trigger information of the design under test executing the interrupt, and acquire register information updated by the design under test executing the interrupt; generate interrupt retirement information of the design under test based on the interrupt trigger information and the register information, and save the interrupt retirement information of the design under test into a preset retirement information queue.

[0147] The scoreboard is specifically configured to control simulation execution of the reference model based on the information saved in the retirement information queue, and acquire register information updated by the reference model based on the simulation execution; and determine a verification result based on the register information updated by the design under test and the register information updated by the reference model.

[0148] In further embodiments, the monitor is further configured to, if the design under test has no interrupt in a current clock cycle, acquire a plurality of microcode information retired by the design under test in the current clock cycle and register information updated by the design under test executing instructions corresponding to the microcode; determine boundary microcode information corresponding to instruction boundaries from the plurality of microcode information; generate microcode retirement information of the design under test based on the boundary microcode information and the register information updated by the design under test executing the instructions, and save the microcode retirement information of the design under test into the retirement information queue.

[0149] In some embodiments, the information saved in the retirement information queue has an interrupt data field, a microcode data field and a register information data field; wherein the interrupt retirement information uses the interrupt data field to record interrupt trigger information, uses the register information data field to record register information, and the microcode data field is empty; and the microcode retirement information uses the microcode data field to record boundary microcode information, uses the register information data field to record register information, and the interrupt data field is empty.

[0150] In one aspect, in some embodiments, the scoreboard is configured to control simulation execution of the reference model based on the information saved in the retirement information queue, and to obtain register information updated by the reference model based on the simulation execution, by: in response to the retirement information queue being not empty, extracting information from the retirement information queue; and if the extracted information is interrupt retirement information, controlling the reference model to simulate execution of an interrupt according to interrupt trigger information in the interrupt retirement information, and obtaining register information updated by the reference model in simulating execution of the interrupt.

[0151] The scoreboard is configured to determine the verification result based on the register information updated by the design under test and the register information updated by the reference model, by: comparing the register information updated by the design under test in executing the interrupt with the register information updated by the reference model in simulating execution of the interrupt, and determining the verification result based on a comparison result.

[0152] In some embodiments, the monitor is configured to determine the interrupt trigger information of the interrupt executed by the design under test, by: obtaining a microcode entry address corresponding to the interrupt and an interrupt valid signal; and processing the microcode entry address and the interrupt valid signal to obtain the interrupt trigger information of the interrupt executed by the design under test.

[0153] In some embodiments, the design under test can include a reorder buffer and a register file; and the monitor is configured to obtain the microcode entry address corresponding to the interrupt and the interrupt valid signal, by: obtaining the microcode entry address corresponding to the interrupt and the interrupt valid signal from the reorder buffer of the design under test.

[0154] The monitor is configured to obtain the register information updated by the design under test in executing the interrupt, by: obtaining the register information updated by the design under test in executing the interrupt from the register file of the design under test.

[0155] In another aspect, in some embodiments, the scoreboard is configured to control simulation execution of the reference model based on the information saved in the retirement information queue, and to obtain register information updated by the reference model based on the simulation execution, by: in response to the retirement information queue being not empty, extracting information from the retirement information queue; and if the extracted information is microcode retirement information, controlling the reference model to simulate execution of an instruction according to boundary microcode information in the microcode retirement information, and obtaining register information updated by the reference model in simulating execution of the instruction.

[0156] The scoreboard is configured to determine the verification result based on the register information updated by the to-be-tested design and the register information updated by the reference model, and includes: comparing the register information updated by the to-be-tested design executing the instruction with the register information updated by the reference model simulating execution of the instruction, and determining the verification result based on a comparison result.

[0157] In some embodiments, the monitor configured to determine the boundary microcode information corresponding to the instruction boundary from the plurality of microcode information includes: judging whether the plurality of microcode information corresponds to the instruction boundary one by one until the boundary microcode information corresponding to the instruction boundary is determined; and wherein the last microcode executed in the plurality of microcodes obtained by the instruction decoding corresponds to the instruction boundary.

[0158] In some embodiments, the monitor configured to obtain the plurality of microcode information retired by the to-be-tested design in the current clock cycle includes: obtaining the plurality of microcode information retired by the to-be-tested design in the current clock cycle from a reorder buffer of the to-be-tested design.

[0159] The monitor configured to obtain the register information updated by the to-be-tested design executing the microcode corresponding instruction includes: obtaining the register information updated by the to-be-tested design executing the instruction from a register file of the to-be-tested design.

[0160] In some embodiments, the microcode retirement information carries a delay signal, and the delay signal is used to indicate whether to delay updating the segment register, wherein if the delay signal is valid, the segment register is delayed, and if the delay signal is invalid, the segment register is not delayed.

[0161] The scoreboard is configured to compare the register information updated by the to-be-tested design executing the instruction with the register information updated by the reference model simulating execution of the instruction, and includes:

[0162] If the instruction is a normal instruction and the delay signal is invalid, the register information of all registers updated by the to-be-tested design executing the instruction is compared with the register information of all registers updated by the reference model simulating execution of the instruction.

[0163] If the instruction is a normal instruction and the delay signal is valid, the register information of all registers updated by the to-be-tested design executing the instruction except the segment register is compared with the register information of all registers updated by the reference model simulating execution of the instruction except the segment register.

[0164] In some embodiments, the scoreboard is configured to determine the verification result based on the comparison result, and the determining includes: outputting error information and exiting if the comparison result is inconsistent; and outputting information that the design under test is executed correctly, and extracting the next information in the retired information queue until the number of pieces of information for simulation verification extracted from the retired information queue reaches a set upper limit if the comparison result is consistent.

[0165] In some embodiments, the microcode retired information carries a time stamp of an instruction executed by the design under test; and the plurality of pieces of microcode retired information in the retired information queue are executed in the reference model in chronological order of the time stamps.

[0166] In some embodiments, the monitor is configured to determine whether the design under test has an interrupt in a current clock cycle, and the determining includes: monitoring whether the design under test has interrupt information in an execution unit in the current clock cycle, and determining that the design under test has an interrupt in the current clock cycle if the design under test has the interrupt information, or determining that the design under test does not have an interrupt in the current clock cycle if the design under test does not have the interrupt information.

[0167] In some embodiments, the design under test includes a CPU core cluster, the CPU core cluster includes a plurality of CPU cores, and one CPU core includes a reorder buffer area, a register file and an execution unit.

[0168] In further embodiments, the verification system provided by the embodiments of the present application can further include a test stimulus.

[0169] The embodiments of the present application further provide a verification electronic device. The verification electronic device can be an electronic device with data processing capability, such as a computer or a server. In the embodiments of the present application, the verification electronic device can build a general verification component through a program. As an optional implementation, Figure 9 An optional block diagram of the verification electronic device provided by the embodiments of the present application is shown in FIG. 1. Figure 9 As shown in FIG. 1, the verification electronic device can include at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4.

[0170] In the embodiments of the present application, the number of the processor 1, the communication interface 2, the memory 3 and the communication bus 4 is at least one, and the processor 1, the communication interface 2 and the memory 3 complete communication with each other through the communication bus 4.

[0171] Optionally, the communication interface 2 can be an interface of a communication module for network communication.

[0172] Optionally, the processor 1 can be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a NPU (Neural Processing Unit), a FPGA (Field Programmable Gate Array), a TPU (Tensor Processing Unit), an AI chip, an ASIC (Application Specific Integrated Circuit), or an integrated circuit configured to implement one or more embodiments of the present application, etc.

[0173] The memory 3 can include a high-speed RAM memory, and can also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0174] The memory 3 stores one or more computer executable instructions, and the processor 1 invokes the one or more computer executable instructions to execute the designed function verification method provided by the embodiments of the present application.

[0175] The embodiments of the present application also provide a storage medium, which can store one or more computer executable instructions, and the one or more computer executable instructions are executed to implement the designed function verification method provided by the embodiments of the present application.

[0176] The above describes a plurality of embodiment schemes provided by the embodiments of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending a plurality of possible embodiment schemes, which can be considered as the embodiments disclosed and disclosed by the embodiments of the present application.

[0177] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of functional verification of a design, characterized by, A general verification component applied to a verification system comprises: determining whether an interrupt occurs to the design under test in a current clock cycle; if the interrupt occurs to the design under test in the current clock cycle, determining interrupt trigger information of the interrupt executed by the design under test, and obtaining register information updated by the design under test in executing the interrupt; generating interrupt retirement information of the design under test based on the interrupt trigger information and the register information, and saving the interrupt retirement information of the design under test into a preset retirement information queue; controlling simulation execution of a reference model based on information saved in the retirement information queue, and obtaining register information updated by the reference model based on the simulation execution, the reference model being a model for co-simulation with the design under test; determining a verification result based on the register information updated by the design under test and the register information updated by the reference model; if the interrupt does not occur to the design under test in the current clock cycle, obtaining a plurality of microcode information retired by the design under test in the current clock cycle, and register information updated by an instruction corresponding to the microcode executed by the design under test; determining boundary microcode information corresponding to an instruction boundary from the plurality of microcode information, wherein the plurality of microcode information has an execution sequence, and the last executed microcode information is the boundary microcode information; generating microcode retirement information of the design under test based on the boundary microcode information and the register information updated by the design under test in executing the instruction, and saving the microcode retirement information of the design under test into the retirement information queue.

2. The method of claim 1, wherein, The information saved in the retirement information queue has an interrupt data field, a microcode data field and a register information data field; wherein the interrupt retirement information uses the interrupt data field to record the interrupt trigger information, uses the register information data field to record the register information, and the microcode data field is empty; the microcode retirement information uses the microcode data field to record the boundary microcode information, uses the register information data field to record the register information, and the interrupt data field is empty.

3. The method according to any of claims 1-2, characterized in that, The controlling simulation execution of the reference model based on the information saved in the retirement information queue, and obtaining register information updated by the reference model based on the simulation execution comprises: in response to the retirement information queue being not empty, extracting information from the retirement information queue; if the extracted information is the interrupt retirement information, controlling the reference model to simulate the interrupt according to the interrupt trigger information in the interrupt retirement information, and obtaining register information updated by the reference model in simulating the interrupt; The determining a verification result based on the register information updated by the design under test and the register information updated by the reference model comprises: comparing the register information updated by the design under test in executing the interrupt with the register information updated by the reference model in simulating the interrupt, and determining the verification result based on a comparison result.

4. The method of claim 1, wherein, The determining interrupt trigger information of the interrupt executed by the design under test comprises: obtaining a microcode entry address corresponding to the interrupt and an interrupt effective signal, and processing the microcode entry address and the interrupt effective signal to obtain the interrupt trigger information of the interrupt executed by the design under test.

5. The method of claim 4, wherein, The obtaining the microcode entry address corresponding to the interrupt and the interrupt effective signal comprises: obtaining the microcode entry address corresponding to the interrupt and the interrupt effective signal from a reorder buffer of the design under test. The obtaining of the register information updated by the execution of the instruction by the design under test comprises: obtaining the register information updated by the execution of the instruction by the design under test from a register stack of the design under test.

6. The method of claim 1 or 2, wherein, The control of the simulation execution of the reference model based on the information stored in the retirement information queue and the obtaining of the register information updated by the simulation execution of the reference model comprise: In response to the retirement information queue being not empty, extracting information from the retirement information queue; if the extracted information is microcode retirement information, controlling the simulation execution of the instruction by the reference model based on the boundary microcode information in the microcode retirement information, and obtaining the register information updated by the simulation execution of the instruction by the reference model; The determination of the verification result based on the register information updated by the design under test and the register information updated by the reference model comprises: Comparing the register information updated by the execution of the instruction by the design under test with the register information updated by the simulation execution of the instruction by the reference model, and determining the verification result based on the comparison result.

7. The method of claim 1 or 2, wherein, The determination of the boundary microcode information corresponding to the instruction boundary from the plurality of microcode information comprises: Judging whether the plurality of microcode information corresponds to the instruction boundary one by one until the boundary microcode information corresponding to the instruction boundary is judged; wherein the last executed microcode in the plurality of microcode obtained by the instruction decoding corresponds to the instruction boundary.

8. The method of claim 1 or 2, wherein, The obtaining of the plurality of microcode information retired by the design under test in the current clock cycle comprises: obtaining the plurality of microcode information retired by the design under test in the current clock cycle from a reorder buffer of the design under test; The obtaining of the register information updated by the execution of the instruction corresponding to the microcode by the design under test comprises: obtaining the register information updated by the execution of the instruction by the design under test from a register stack of the design under test.

9. The method of claim 6, wherein, The microcode retirement information carries a delay signal, and the delay signal is used to indicate whether the instruction delays the update of the segment register; if the delay signal is valid, the update of the segment register is delayed; if the delay signal is invalid, the update of the segment register is not delayed. The comparison of the register information updated by the execution of the instruction by the design under test with the register information updated by the simulation execution of the instruction by the reference model comprises: If the instruction is a normal instruction and the delay signal is invalid, comparing the register information of all registers updated by the execution of the instruction by the design under test with the register information of all registers updated by the simulation execution of the instruction by the reference model; If the instruction is a normal instruction and the delay signal is valid, comparing the register information of all registers except the segment register updated by the execution of the instruction by the design under test with the register information of all registers except the segment register updated by the simulation execution of the instruction by the reference model.

10. The method of claim 3, wherein, The determination of the verification result based on the comparison result comprises: If the comparison result is inconsistent, outputting error information and exiting; if the comparison result is consistent, outputting information that the execution of the design under test is correct, and extracting the next information of the retirement information queue until the number of information for simulation verification extracted from the retirement information queue reaches a set upper limit.

11. The method of claim 6, wherein, The design under test comprises a multi-core multi-thread processor; the microcode retirement information carries a timestamp of an instruction executed by the design under test; and the plurality of microcode retirement information in the retirement information queue is simulated and executed at the reference model in the order of the timestamps.

12. A verification system, comprising: The method comprises: a design under test, a general verification component, and a reference model; The general verification component is configured to determine whether an interrupt occurs in the design under test in a current clock cycle; if an interrupt occurs in the design under test in the current clock cycle, determine interrupt trigger information of the interrupt executed by the design under test, and obtain register information updated by the design under test in executing the interrupt; based on the interrupt trigger information and the register information, generate interrupt retirement information of the design under test, and save the interrupt retirement information of the design under test in a preset retirement information queue; based on the information saved in the retirement information queue, control simulation execution of the reference model, and obtain register information updated by the reference model based on the simulation execution, the reference model being a model for co-simulation with the design under test; based on the register information updated by the design under test and the register information updated by the reference model, determine a verification result. The general verification component comprises a monitor and a scoreboard, and the scoreboard is provided with a retirement information queue; the monitor is configured to, if no interrupt occurs in the design under test in a current clock cycle, obtain a plurality of microcode information retired by the design under test in the current clock cycle, and register information updated by the design under test in executing an instruction corresponding to the microcode; determine boundary microcode information corresponding to an instruction boundary from the plurality of microcode information; based on the boundary microcode information and the register information updated by the design under test in executing the instruction, generate microcode retirement information of the design under test, and save the microcode retirement information of the design under test in the retirement information queue.

13. The verification system of claim 12, wherein, The monitor is specifically configured to determine whether an interrupt occurs in the design under test in a current clock cycle; if an interrupt occurs in the design under test in the current clock cycle, determine interrupt trigger information of the interrupt executed by the design under test, and obtain register information updated by the design under test in executing the interrupt; based on the interrupt trigger information and the register information, generate interrupt retirement information of the design under test, and save the interrupt retirement information of the design under test in a preset retirement information queue; The scoreboard is specifically configured to, based on the information saved in the retirement information queue, control simulation execution of the reference model, and obtain register information updated by the reference model based on the simulation execution; and based on the register information updated by the design under test and the register information updated by the reference model, determine a verification result.

14. The verification system of claim 13, wherein, The information saved in the retirement information queue comprises an interrupt data field, a microcode data field, and a register information data field; the interrupt retirement information uses the interrupt data field to record the interrupt trigger information and uses the register information data field to record the register information, and the microcode data field is empty; and the microcode retirement information uses the microcode data field to record the boundary microcode information and uses the register information data field to record the register information, and the interrupt data field is empty.

15. An authentication electronic device, comprising: comprising at least one memory and at least one processor; the memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to perform the designed function verification method according to any one of claims 1-11.

16. A storage medium, characterized by The storage medium stores one or more computer-executable instructions, and the one or more computer-executable instructions are executed to implement the designed function verification method according to any one of claims 1-11.

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