Programming apparatus, method and novel memory

Abstract

This application provides a programming apparatus, method, and novel memory. It includes: a quantity setting unit, which generates a control clock based on the total programming current of the current cycle to determine the number of valid memory cells configured for programming in the next cycle; a programming control unit, which, in response to the control clock, sequentially selects each valid memory cell in the row to be programmed as the first cell and performs processing until all valid memory cells are programmed; based on the quantity determined by the quantity setting unit for the current cycle, it sequentially selects the first cell and subsequent valid memory cells to configure them for programming; and a programming unit, which programs the valid memory cells configured for programming. This application can adjust the number of cells simultaneously programmed within a programming cycle in real time according to the total programming current, avoiding excessive heat and chip damage due to excessive programming current; and it can move sequentially within a row to achieve traversal of the entire row of cells to be programmed.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and more particularly to a programming device, method, and novel memory. Background Technology

[0002] Memory is a collection of many storage cells arranged in order of cell number. Each cell consists of several binary bits to represent the value stored in the cell. Traditional memory, such as flash memory, stores data "0" and data "1" by injecting charge into the cell to change its threshold voltage and other electrical characteristics. Newer memory, such as resistive random access memory (RRAM), stores data based on the switching of its own resistance between high and low resistance states.

[0003] Taking flash memory as an example, the common practice is to erase the entire memory chip first, and then program each row. Because each flash memory cell consumes relatively little power, an entire row can be programmed simultaneously. Specifically, a row is selected, the data to be written is first stored in a page latch, and then the cells within that row that need to be programmed are written simultaneously.

[0004] However, the above method is not applicable to new types of memory. Due to the differences in programming characteristics of various resistive random access memories, the total programming current is difficult to control, and there is a risk of excessive current and heat that could burn out the chip. Summary of the Invention

[0005] This application provides a programming device, method, and novel memory to solve the programming problem of novel memory and reduce the risk of chip burnout due to excessive current and heat.

[0006] In a first aspect, this application provides a programming apparatus, comprising: a quantity setting unit, a programming control unit, and a programming unit; the quantity setting unit is configured to generate a control clock based on the total programming current of valid memory cells configured to be programmed in the current cycle of an excitation clock, so as to determine the number of valid memory cells configured to be programmed in the next cycle; the programming control unit is configured to, in response to the control clock, sequentially select each valid memory cell in the row to be programmed as the first cell and perform processing until all valid memory cells are programmed; sequentially select the first cell and subsequent valid memory cells according to the number of valid memory cells configured to be programmed in the current cycle and configure them to be programmed; configure the unselected valid memory cells after the first cell to be in a non-programming state; the programming unit is configured to perform programming on the valid memory cells currently configured to be programmed according to a predetermined cycle until all valid memory cells are programmed.

[0007] Secondly, this application provides a programming method applied to a programming device, the programming device including a quantity setting unit, a programming control unit, and a programming unit; the method includes: the quantity setting unit generating a control clock based on the total programming current of the valid memory cells configured as programming cells in the current cycle of the excitation clock, to determine the number of valid memory cells configured as programming cells in the next cycle; the programming control unit responding to the control clock, sequentially taking each valid memory cell in the row to be programmed as the first cell, and performing the following processes until all valid memory cells are programmed: selecting the first cell and subsequent valid memory cells in sequence according to the number of valid memory cells configured as programming cells in the current cycle, and configuring them as programming cells; configuring the unselected valid memory cells after the first cell as non-programming cells; the programming unit performing programming on the currently configured valid memory cells according to a predetermined cycle until all valid memory cells are programmed.

[0008] Thirdly, this application provides a hardware code product, including hardware code, which, when executed by a processor, implements the method as described in the second aspect.

[0009] Fourthly, this application provides a readable storage medium storing hardware code, which, when executed, is used to implement the method as described in the second aspect.

[0010] Fifthly, this application provides an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores hardware code; the processor executes the hardware code stored in the memory to implement the method as described in the second aspect.

[0011] In a sixth aspect, this application provides a novel memory including a plurality of resistive memory cells and a programming device as described in the first aspect; the programming device is used to program the resistive memory cells.

[0012] The programming apparatus, method, and novel memory provided in this application include: a quantity setting unit, a programming control unit, and a programming unit; the quantity setting unit is used to generate a control clock based on the total programming current of the valid memory cells configured to be programmed in the current cycle of the excitation clock, so as to determine the number of valid memory cells configured to be programmed in the next cycle; the programming control unit is used to respond to the control clock by sequentially taking each valid memory cell in the row to be programmed as the first cell and performing processing until all valid memory cells are programmed; according to the number of valid memory cells configured to be programmed in the current cycle, sequentially selecting the first cell and the valid memory cells thereafter and configuring them to be programmed; configuring the unselected valid memory cells after the first cell to be non-programmed; the programming unit is used to perform programming on the valid memory cells currently configured to be programmed according to a predetermined cycle until all valid memory cells are programmed. This application can program only a portion of the cells in the programming row within a single cycle. It can also adjust the number of cells in the programming cycle in real time according to the total programming current to avoid damaging the chip due to excessive heat caused by excessive total programming current. Furthermore, it can move sequentially within a row, replacing programmed cells with unprogrammed cells, and programming them in turn to achieve traversal of the entire row of cells to be programmed. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0014] Figure 1 A schematic diagram of a traditional flash memory array programming structure;

[0015] Figure 2 A schematic diagram of a resistive variable memory array programming structure provided in this application;

[0016] Figure 3 A schematic diagram of the structure of a programming device provided in this application;

[0017] Figure 4 A schematic diagram illustrating the working process of a programming device provided in this application;

[0018] Figure 5 A circuit diagram of a programming control unit provided in this application;

[0019] Figure 6 An external link signal waveform diagram provided in this application;

[0020] Figure 7 A schematic diagram of the structure of a clock generation unit provided in this application;

[0021] Figure 8A schematic diagram of another clock generation unit provided in this application;

[0022] Figure 9 A circuit diagram of a clock generation unit provided in this application;

[0023] Figure 10 A schematic diagram of the structure of an error reporting unit provided in this application;

[0024] Figure 11 A circuit diagram of an error reporting unit provided in this application;

[0025] Figure 12 A schematic diagram of the structure of a quantity setting unit provided in this application;

[0026] Figure 13 A circuit diagram of a quantity setting unit provided in this application;

[0027] Figure 14 A schematic diagram of the structure of a clock control module provided in this application;

[0028] Figure 15 A circuit diagram of a second detection module provided in this application;

[0029] Figure 16 A circuit diagram of a logic calculation module provided in this application;

[0030] Figure 17 A waveform diagram for increasing quantity is provided in this application;

[0031] Figure 18 This application provides a waveform diagram for reducing quantity.

[0032] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0034] First, let me explain the terms used in this application:

[0035] Resistive Random Access Memory (RRAM) is a non-volatile memory that uses the resistance of a non-conductive material to reversibly switch between a high-resistance state and a low-resistance state under the action of an external electric field.

[0036] Memory is a collection of many storage cells arranged in order of cell number. Each cell consists of several binary bits to represent the value stored in the cell. Newer types of memory differ significantly from traditional memory in their storage methods.

[0037] Traditional memories, such as flash memory and dynamic random access memory (DRAM), primarily determine the storage state based on whether or not a cell is injected with charge. Charge injection alters the cell's threshold voltage and other electrical characteristics, allowing the storage data value to be determined by whether the cell is conducting, using an appropriate external voltage load. Newer memories, such as resistive random access memory (RRAM), primarily use the cell's own resistance as the criterion for determining the stored signal.

[0038] Traditional memory typically involves erasing the entire memory chip before reprogramming each row. For example, Figure 1 A schematic diagram of a traditional flash memory array programming structure, such as Figure 1 As shown, the row to be programmed is programmed. Specifically, a row is selected using a row address decoder, the data to be written is first stored in the page latch, and then the cells to be programmed are written simultaneously. Because each flash memory cell consumes relatively low power, an entire row can be programmed at the same time.

[0039] However, due to the different operating methods and characteristics of new types of memory, simply replacing them with the same method of simultaneous programming of the entire row would result in excessive power consumption. For example, in resistive random access memory (RRAM), the programming current of a single RRAM cell is very high; if programming is performed simultaneously, the excessive current could lead to the chip burning out due to overheating.

[0040] To address this issue, consider whether it is possible to program only a portion of the memory cells in a row to be programmed at the same time. Figure 2 This application provides a schematic diagram of a resistive variable memory array programming structure, such as... Figure 2 As shown, programming only a portion of the resistive transformer units within the same time period can effectively control the programming current.

[0041] Furthermore, it's necessary to consider how to determine the number N of selected resistive switching units within the same time period. It is known that the total programming current equals the sum of the currents of all resistive switching units being programmed simultaneously. Therefore, if the programming current of a single unit is known in advance, the number N of selected resistive switching units within the same time period can be calculated based on the safety range set for the total programming current. The value of N can be set via an external link signal before programming.

[0042] In actual manufacturing processes, the programming characteristics of resistive random access memory (RRAM) cells exhibit significant deviations. The programming current may differ between RRAM cells grown on different wafers, and current fluctuations may also exist between different cells within the same wafer. Due to these large deviations, testing the programming characteristics of each cell before programming and determining the value of N would be extremely time-consuming and resource-intensive.

[0043] Therefore, the programming apparatus, method, and novel memory provided in this application offer a programming structure that can adjust the number N of memory cells that can be programmed simultaneously according to the real-time total programming current, thereby solving the above-mentioned technical problems.

[0044] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0045] Example 1

[0046] Figure 3 This application provides a schematic diagram of the structure of a programming device, which includes: a quantity setting unit 50, a programming control unit 10, and a programming unit 20.

[0047] The quantity setting unit 50 is used to generate a control clock based on the total programming current of the valid memory cells configured as programming cells in the current cycle of the excitation clock, so as to determine the number of valid memory cells configured as programming cells in the next cycle; the programming control unit 10 is used to respond to the control clock, sequentially taking each valid memory cell in the row to be programmed as the first cell and performing processing until all valid memory cells are programmed: according to the number of valid memory cells configured as programming cells in the current cycle, sequentially selecting the first cell and the valid memory cells after it and configuring them as programming cells; configuring the unselected valid memory cells after the first cell as non-programming cells; the programming unit 20 is used to perform programming on the valid memory cells currently configured as programming cells according to a predetermined cycle until all valid memory cells are programmed.

[0048] Specifically, the cycle in the quantity setting unit 50 begins upon receiving the first excitation signal of the excitation clock and ends upon receiving the second excitation signal of the excitation clock. Responding to this excitation signal, the quantity setting unit 50 generates a control clock based on the magnitude of the total programming current. This control clock adjusts the number of valid memory cells configured for programming. Responding to this control clock, the programming control unit 10 sequentially selects the corresponding number of valid memory cells and configures them for programming.

[0049] Before programming a memory, an initial quantity value needs to be set via an external link signal. That is, the number of valid memory cells configured for programming in the first cycle is preset; the number in each subsequent cycle is adjusted by the quantity setting unit 50 based on the total programming current of the previous cycle.

[0050] For example, if the quantity setting unit 50 detects that the total programming current is too low, below the set low current threshold, then in the next cycle, an additional valid programming unit is added, i.e., N becomes N+1; if the quantity setting unit 50 detects that the total programming current is too high, above the set high current threshold, then in the next cycle, one valid programming unit is removed, i.e., N becomes N-1; if the quantity setting unit 50 detects that the total programming current is within the set range, then in the next cycle, no change is made to the number of valid programming units.

[0051] If the number of valid memory cells to be configured as programmed in the next cycle is the same as in the current cycle, then the position of the valid memory cells configured as programmed in the next cycle will shift one position relative to the current cycle. The quantity setting unit 50 generates a control clock containing different excitation signals, which are used to control the last valid memory cell, the next valid memory cell, and other non-last valid memory cells configured as programmed in the current cycle among the multiple valid memory cells sequentially configured as programmed in the current cycle, so as to increase or decrease the number of valid memory cells in the programmed state in one cycle.

[0052] Furthermore, the cycle of programming unit 20 is not the same as the cycle of quantity setting unit 50. Unless otherwise specified, the cycle mentioned below refers to the cycle of quantity setting unit 50. The programming unit is used to program valid storage units configured in a programming state. The circuit structure for its cycle control is not the subject of this application, and this application does not make specific limitations or structural analyses.

[0053] Figure 4An exemplary schematic diagram of the operation of a programming device is provided. When programming a row in the memory array, a value is written to the page latch. Here, 1 represents a cell that needs to be programmed, and 0 represents a cell that does not need to be programmed. Figure 4 As shown, in the first row of cells, the cells marked with 1 are the memory units that need to be programmed. Select the units that need to be programmed and arrange them in order to form a chain of valid programming units.

[0054] In actual programming, all programming operations only affect this selected chain of valid programming units. It should be noted that writing values ​​to the page latch is controlled by a separate program or circuit, and is not performed by the programming control unit 10 and programming unit 20 in this application. Since this is not a crucial aspect of the invention, it will not be described in detail here.

[0055] In the above chain of valid programming units, N memory units are selected and configured as programmed units within a single time period. At any given programming time, only N adjacent units are in a programmed state. For example... Figure 4 As shown, the Active cells box contains memory cells configured for programming. Within the first cycle, four valid memory cells are selected and configured for programming within a single time period, while the other valid memory cells are configured for non-programming. Programming unit 20 sequentially programs the first cell among the four selected valid memory cells. After programming the first memory cell in the box, the Active cells box moves backward by 0, 1, or 2 valid memory cells, continuing to program the first memory cell in the current Active cells box. This operation is repeated until the last cell is programmed. Through the pipelined programming control process, the entire row of memory cells to be programmed is traversed.

[0056] Furthermore, such as Figure 4 In the first cycle, N=4. If the total programming current of the four valid memory cells is lower than the preset range, then the number increases by one in the second cycle, N=5. If the total programming current is higher than the preset range in the second cycle, then the number decreases by one in the third cycle, N=4. If the total programming current is within the preset range in the third cycle, then the number remains unchanged in the fourth cycle, N=4. If the total programming current is higher than the preset range in the fourth cycle, then the number decreases by one in the fifth cycle, N=3.

[0057] This application, through a control circuit installed in the programming device, enables the selection of a subset of units for programming at any given time period. Furthermore, during programming in a single line, the units are automatically and sequentially moved in a pipeline manner, replacing programmed units with unprogrammed units, thus traversing the memory units to be programmed. Moreover, based on the total programming current of the current cycle, the number of valid memory units configured for programming in the next cycle is adjusted, achieving real-time and effective control of the total programming current and preventing chip overheating and damage.

[0058] It should be noted that the operation of selecting a number N storage units to be configured into a programming state within a single time period is performed during the initialization phase before programming. One feasible approach is to control the number N by inputting a control clock to the valid programming unit chain via an external link, which will be explained in detail later in conjunction with the circuit structure of the programming control unit 10.

[0059] The structure and operation of the programming device will be described below with reference to the circuit diagram.

[0060] Figure 5 This application provides a circuit diagram of a programming control unit. The programming control unit 10 includes: a programming unit chain consisting of a plurality of flip-flops connected in series; wherein, the plurality of flip-flops correspond one-to-one with the page latches corresponding to each memory cell in the row to be programmed.

[0061] like Figure 5 The diagram illustrates a programming unit chain consisting of four D flip-flops. Each D flip-flop corresponds to a page latch (PL), and each page latch corresponds to a memory cell (Cell). The input of the D flip-flops is the D terminal; the output is the Q terminal; and the clock port is the CLK terminal.

[0062] In this configuration, the clock port of each flip-flop is connected to the control clock via a first switch A, the output of each flip-flop is connected to the input of the next flip-flop via a second switch B, and the input of each flip-flop is connected to the input of the next flip-flop via a third switch E.

[0063] Each memory cell's corresponding page latch is used to control the switching states of the first switch A, the second switch B, and the third switch E of the corresponding flip-flop based on its own stored data, thereby establishing a valid programming cell chain. The memory cell corresponding to the flip-flop in the valid programming cell chain is the valid memory cell. The flip-flop corresponding to a valid memory cell in the programming state is configured as the first logic, and the flip-flop corresponding to a valid memory cell in the non-programming state is configured as the second logic. The following explanation uses an example where the first logic is 1 and the second logic is 0.

[0064] In one example, the programming control unit 10 further includes: multiple inverters; each inverter corresponds to a flip-flop, the input of the inverter is connected to the corresponding page latch, and the output of the inverter is connected to the control terminal of the third switch E of the corresponding flip-flop.

[0065] Specifically, refer to Figure 5 The method for establishing an effective programming unit chain based on its stored data in a page memory is as follows: When the data stored in the page latch is 1, the first switch A and the second switch B are closed; the third switch E is open. Therefore, the clock port of the D flip-flop can receive the control clock through the first switch A, and the output of the current D flip-flop is connected to the input of the next D flip-flop through the second switch B. At this time, the current D flip-flop is connected in the chain. When the data stored in the page latch is 0, the first switch A and the second switch B are open; the third switch E is closed. Therefore, the clock port of the D flip-flop cannot receive the control clock, and the output of the current D flip-flop is disconnected from the input of the next D flip-flop. The next D flip-flop can receive the signal output by the previous D flip-flop through the closed third switch E. At this time, the current D flip-flop is skipped and is not connected in the chain.

[0066] Before programming, some data needs to be written to the valid programming unit chain via an external link. N valid storage units are selected and configured for programming, i.e., initialization is performed, providing an initial quantity N for the first programming cycle. In practical applications, the initial quantity for the first cycle needs to be obtained experimentally or by calculation. If the initial quantity is too large, it will result in a large programming current, and adjusting the quantity setting unit will take some time, which may damage the new type of memory. If the initial quantity is too small, it will affect programming efficiency.

[0067] After the first cycle, the number of valid memory cells in the programming state within each cycle is determined by the quantity setting unit. Furthermore, when programming the entire new memory is nearing completion, if the remaining number of unprogrammed valid memory cells is too small to cause the total programming current to fall below a preset range, the quantity setting unit cannot increase the quantity for the next cycle. Accordingly, the number of valid memory cells in the programming state will decrease sequentially in subsequent cycles until programming of all valid memory cells is complete. The following description covers the intermediate stage of programming the new memory (where the number of unprogrammed valid memory cells is sufficient for adjustment by the quantity setting unit). Unless otherwise specified, the special case of the final stage of programming the new memory is not considered.

[0068] Figure 6 An external link signal waveform diagram provided in this application is shown in reference to... Figure 6 and combined Figure 5The circuit structure shown illustrates a method for configuring N valid memory cells into a programming state.

[0069] like Figure 6 As shown, the programming enable signal Prog_en controls whether the array is in programming mode. Prog_en is always at logic 0, keeping the array out of programming mode, thus allowing initialization via an external link before programming. The link input signal Chain_In inputs a signal to the D terminal of the D flip-flop, and the link control clock signal CLK_O provides the rising edge trigger signal for the D flip-flop.

[0070] This section utilizes the electrical characteristics of D flip-flops, which will be explained below. A D flip-flop is an information storage device with memory function and two stable states. It is the most basic logic unit for constructing various sequential circuits and an important unit circuit in digital logic circuits. There are two triggering methods: level-triggered and edge-triggered. The former can be triggered when the clock pulse = 1, while the latter is usually triggered at the leading edge of the clock pulse (positive transition from 0 to 1). A D flip-flop includes input terminals, a clock port, and an output terminal. The clock port is used to receive the control clock signal.

[0071] Taking an edge-triggered D flip-flop as an example, its function is as follows: when the input is logic 1, after receiving a rising edge excitation signal, the output terminal outputs 1; when the input is logic 0, after receiving a rising edge excitation signal, the output terminal outputs 0.

[0072] The first step of initialization is to write all 1s to the page latch, so that all D flip-flops are in the link.

[0073] The second initialization step: Using an external link clock, all D flip-flops are written to a state that stores logic 0. Specifically, the Chain_In signal is continuously set to logic 0, and a periodic link control clock signal CLK_O is continuously input until all D flip-flops are written to a state that stores logic 0.

[0074] The third initialization step is to store the data to be written in the page latch, so that only the D flip-flops corresponding to the units that need to be programmed are in the chain, thus establishing a valid programming unit chain.

[0075] Initialization step 4: Set the Chain_In signal input to logic 1. The CLK_O signal provides N clock cycles, where N is any integer and can be customized. After N cycles, set the Chain_In signal input to logic 0. The purpose of this operation is to ensure that the first N D flip-flops in the valid programmable cell chain are at logic 1, while the other D flip-flops are at logic 0.

[0076] For example, with Figure 5 Taking four D flip-flops as an example, assume that their corresponding page memories are all 1, meaning that all four D flip-flops are in the link. Also, assume N=2, and the CLK_O signal provides 2 clock cycles, meaning the CLK_O signal has 2 rising edges. Figure 5 In the middle, from left to right, are D i+1 Trigger, D i+2 Trigger, D i+3 Trigger, D i+4 trigger.

[0077] The Chain_In signal input is set to logic 1, D i+1 The input terminal of the trigger is C. i The signal is logic 1, when D i+1 When the trigger receives the first rising edge of the CLK_O signal, D i+1 The output of the flip-flop transitions to logic 1, i.e., C. i+1 Jump to logic 1. At the first rising edge of the CLK_O signal, D i+2 The flip-flop's output remains logic 0 at this moment. When the second rising edge of the CLK_O signal is received, due to C... i+1 Since it is logic 1, therefore D i+2 The output C of the trigger i+2 The signal transitions to logic 1. At the second rising edge of the CLK_O signal, C... i The signal is still logic 1, therefore D i+1 Flip-flop output C i+1 The value remains at logic 1. After two clock cycles of the CLK_O signal are completed, the Chain_In signal input is set to logic 0. The state of the D flip-flops in the valid programmable cell chain will not change further.

[0078] In other words, the CLK_O signal provides two clock cycles, which can set the first two D flip-flops in the effective programming cell chain to 1. Similarly, when the CLK_O signal provides three clock cycles, it can set the first three D flip-flops in the effective programming cell chain to 1.

[0079] Only when both the D flip-flop and the page latch are at logic 1 in the corresponding memory cell column will the electrical conditions for programming be configured, causing the corresponding memory cell to enter the programming state. Therefore, during initialization, only the first N cells that need to be programmed can enter the programming state when the array enters programming mode, ensuring that the number of memory cells in the programming state at any given time will not exceed N.

[0080] After setting the number N of memory cells that can be configured into programming state simultaneously via an external link, the programming enable signal Prog_en switches to logic 1, putting the array into programming mode. In programming mode, the control clock of the programming control unit 10 is based on the internal clock.

[0081] For example, Figure 7 This application provides a schematic diagram of the structure of a clock generation unit. The programming device also includes a clock generation unit 30, used to provide an excitation clock to the quantity setting unit 50, i.e., it has an internal built-in clock. The advantage of the built-in clock is that it does not require an external clock generation circuit to continuously provide an excitation clock during operation.

[0082] Based on the above example, Figure 8 The present application provides a schematic diagram of another clock generation unit. The clock generation unit 30 includes: a first detection module 31 and a generation module 32. The first detection module 31 is used to sequentially detect whether the first valid memory unit currently configured as a programming state has completed programming and output the detection result. The generation module 32 is used to control the excitation clock to generate an excitation signal if the detection result indicates that programming has been completed, otherwise, control the excitation clock not to generate an excitation signal.

[0083] For example, Figure 9 A circuit diagram of a clock generation unit provided in this application. Figure 9 As shown, the first detection module 31 includes: a plurality of fourth switches S and a first comparator; the plurality of fourth switches correspond one-to-one with the memory cells in the row to be programmed; the first terminal of the fourth switch S is connected to the corresponding memory cell, and the second terminal of the fourth switch is connected to the first input terminal of the first comparator; the second input terminal of the first comparator is connected to the first reference voltage Vref1. The fourth switch S is used to select the valid memory cell to be detected by the first detection module 31, and the state of the fourth switch depends on the input and output data of the corresponding flip-flop; the output data of the first comparator indicates whether the currently selected valid memory cell has been programmed.

[0084] Specifically, the fourth switch S i+1 Depends on the corresponding trigger input data C i and output data C i+1 In a chain of valid programmable cells, all flip-flops have a stored value C of logic 0, except for N consecutive flip-flops that are logic 1. Therefore, there is only one scenario in the entire chain where the previous flip-flop's stored value C is logic 0, and the current memory's stored value C is logic 1. This scenario occurs in the first valid memory cell configured for programming. The corresponding flip-flop's output data will always be logic 1, i.e., C... i+1 The value is 1. And its input data C iSince this is the output data of the previous trigger, it must be logic 0. Therefore, the first detection module 31 detects the first valid memory unit currently in the programming state.

[0085] It should be noted that, in order to correctly determine the programming state of the valid memory cell corresponding to the flip-flop with the stored value C1, there is an additional D flip-flop at the very front of the D flip-flop chain that does not correspond to a column in the array. This flip-flop is used to store the value C0, and its logical value is 0.

[0086] Furthermore, the first comparator operates as follows: when the voltage received at its first input terminal is higher than the reference voltage Vref1, the output detection result CO is high; otherwise, it is low. In this embodiment, when the detected unit has completed programming, CO is logic 1 (high); when programming has not been completed, CO is logic 0.

[0087] Reference Figure 9 The first detection module 31 further includes: a first enable switch F1; the first enable switch F1 is disposed between the fourth switch and the first comparator; after the programming unit 20 starts programming, the first enable switch F1 is in a closed state; before the programming unit 20 starts programming, the first enable switch F1 is in an open state. The first enable switch F1 is controlled by an external link signal, such as... Figure 6 The Prog_en signal is shown. After Prog_en transitions to logic 1, the array enters the programming state.

[0088] Reference Figure 9 The generation module 32 includes: a first AND gate, a first OR gate, a first delay unit, and a first inverter. The first input of the first AND gate is connected to the output of the first detection module 31, receiving the detection result CO output by the first detection module 31. The output of the first AND gate is connected to the first input of the first OR gate; the output of the first OR gate is connected to the input of the first delay unit; the output of the first delay unit is connected to the input of the first inverter; the output of the first inverter is connected to the second input of the first AND gate; wherein, the second input of the first OR gate receives a first control signal Turn-off; based on the first control signal and the output signal of the first AND gate, the output of the first OR gate outputs the initial excitation clock CLK_Internal.

[0089] Specifically, the comparator's output CO can serve as a decision flag for the link's self-moving clock transition. CO does not directly control the clock CLK_Internal; instead, it performs a logical operation with its own delay logic before outputting the clock. The control process is as follows: When CO = 0, Delay is 1, the first AND gate outputs 0, the first OR gate outputs 0, and CLK_Internal is 0. When CO transitions to 1, Delay is 1, the first AND gate outputs 1, the first OR gate outputs 1, meaning CLK_Internal transitions to 1. When CO remains 1, Delay is 0, the first AND gate outputs 0, the first OR gate outputs 0, meaning CLK_Internal transitions to 0. By controlling the first delay unit, the rising and falling edge interval of CLK_Internal is controlled, avoiding circuit logic risks caused by excessively short intervals. CO generates its own delay signal through the first AND gate, the first OR gate, the first delay unit, and the first inverter, and is output after logical operation by the first AND gate.

[0090] Furthermore, the clock generation unit 30 also includes a delay module 33; the delay module 33 includes a second delayer for delaying the initial excitation clock CLK_Internal to generate the excitation clock CLK_dff.

[0091] Furthermore, the clock generation unit 30 also includes: a second enable switch F2; the second enable switch F2 is connected to the output terminal of the second delay unit; after the programming unit 20 starts programming, the second enable switch is in a closed state; before the programming unit 20 starts programming, the second enable switch is in an open state. The second enable switch F2 is controlled by an external link signal, such as... Figure 6 The Prog_en signal is shown.

[0092] Figure 10 This application provides a schematic diagram of the structure of an error reporting unit 40. The programming device further includes: an error reporting unit 40; the error reporting unit 40 is used to control the excitation clock CLK_dff output by the clock generation unit 30 to generate an excitation signal if the currently detected valid memory cell has not been programmed after a preset time. When a valid memory cell fails and cannot be programmed, the excitation clock output by the clock generation unit 30 will be continuously low. In order to continue programming subsequent valid memory cells, the error reporting unit forces a rising edge to be generated in the excitation clock output by the generation module, skipping the faulty cell and continuing subsequent programming. Furthermore, the error reporting unit 40 is also used to output an error signal err, provided to external circuitry as a judgment flag for cell abnormality.

[0093] Figure 11This application provides a circuit diagram of an error reporting unit 40. The error reporting unit 40 includes: a second inverter, a fifth switch G1, a sixth switch G2, a first capacitor, and a second comparator. The non-inverting input of the second comparator is connected to the first terminal of the first capacitor and one terminal of the sixth switch G2. The first terminal of the first capacitor is connected to the power supply signal Lin through the fifth switch G1. The inverting input of the second comparator is connected to a second reference voltage Vref2. The second terminal of the first capacitor is grounded. The other terminal of the sixth switch G2 is grounded. The input of the second inverter is connected to the initial excitation clock CLK_Internal, and the output of the second inverter is connected to the control terminal of the fifth switch G1. The control terminal of the sixth switch G2 is connected to the initial excitation clock CLK_Internal. The output of the second comparator outputs a first control signal Turn-off. Specifically, the first control signal Turn-off is used to control the initial excitation clock CLK_Internal output by the generation module 32 to generate a rising edge, thereby causing the excitation clock CLK_dff output by the delay module 33 to generate a rising edge.

[0094] Specifically, when a programming error occurs and the program cannot be completed for an extended period, the initial excitation clock CLK_Internal remains low for an extended period. Consequently, the fifth switch G1 is turned on, and the sixth switch G2 is turned off. Figure 11 The Lin signal continuously charges the first capacitor, causing the voltage at the non-inverting input of the second comparator to rise continuously. When it exceeds the second reference voltage Vref2, the first control signal Turn-off output by the second comparator is set to 1. This causes the first OR gate to output 1, generating a rising edge for the initial excitation clock CLK_Internal, skipping the faulty cell and continuing subsequent programming. Simultaneously, this first control signal Turn-off can also serve as an error signal err, acting as a flag to determine if a cell is faulty.

[0095] After the array enters the programming state, based on the internal clock CLK_Internal, up to N cells can be programmed simultaneously in each clock cycle, but only the first cell in sequence will be judged to determine whether programming is complete. Specifically, the programming circuit in the array will collect the stored data from the D flip-flops and page latches of each column. Only columns where both are logic 1 will be configured with the electrical conditions for programming, and the cells in that column can be in the programming state. After the judgment is completed, CLK_Internal will automatically generate a rising edge (i.e., enter the next cycle) to judge the next cell.

[0096] Figure 12 A schematic diagram of the structure of a quantity setting unit 50 provided in this application. Figure 13A circuit diagram of a quantity setting unit 50 provided in this application is shown. The quantity setting unit 50 includes a clock control module 51 and a clock selection module 52. The clock control module 51 is used to output a first control clock CLK_dff_D, a second control clock CLK_dff_N, and a third control clock CLK_dff_O based on the relationship between the total programming current of the effective memory cells in the current cycle and a predetermined range.

[0097] Specifically, such as Figure 13 The CLK_CTRL module shown receives the excitation clock CLK_dff and outputs the first control clock CLK_dff_D, the second control clock CLK_dff_N, and the third control clock CLK_dff_O.

[0098] Case 1: When the total programming current of the current cycle is lower than a predetermined range, the number of excitation signals for the first control clock CLK_dff_D increases compared to the number of excitation signals for the excitation clock. The second control clock CLK_dff_N and the third control clock CLK_dff_O are synchronized with the excitation clock. This setting is used to increase the total programming current for the next cycle by one based on the number of valid memory cells in the programming state during the current cycle, thereby improving programming efficiency.

[0099] Scenario 2: When the total programming current of the current cycle exceeds a predetermined range, the number of excitation signals for the second control clock CLK_dff_N is reduced compared to the number of excitation signals for the excitation clock. The first control clock CLK_dff_D and the third control clock CLK_dff_O are synchronized with the excitation clock. This setting reduces the number of valid memory cells in the programming state within the current cycle by one, thereby lowering the total programming current for the next cycle, protecting the chip from prolonged high-current operation, and preventing damage from high heat.

[0100] Case 3: When the total programming current of the current cycle is within the predetermined range, the first control clock CLK_dff_D, the second control clock CLK_dff_N, and the third control clock CLK_dff_O are synchronized with the excitation clock. The above settings do not change the number of valid memory cells in the programming state in the next cycle, and can largely maintain the total programming current within the predetermined range. It is understandable that even if the number from the previous cycle is used, the total programming current may not be within the predetermined range due to differences in the programming of individual resistive switching cells. In this case, the number of valid memory cells in the programming state should be adjusted according to Cases 1 and 2.

[0101] like Figure 13 As shown, the clock selection module 52 includes multiple seventh switches H1, multiple eighth switches H2, and multiple ninth switches H3. Figure 13 The example shows the seventh switch H1 corresponding to the left-hand trigger.i+1 Eighth switch H2 i+1 Ninth switch H3 i+1 The subscript indicates the (i+1)th flip-flop. Multiple seventh switches H1, multiple eighth switches H2, and multiple ninth switches H3 each correspond one-to-one with multiple flip-flops.

[0102] Furthermore, one end of the seventh switch H1, the eighth switch H2, and the ninth switch H3 is connected to the clock port of the corresponding flip-flop via the first switch. The other end of the seventh switch H1 is connected to the first control clock CLK_dff_D; the other end of the eighth switch H3 is connected to the second control clock CLK_dff_N; and the other end of the ninth switch H3 is connected to the third control clock CLK_dff_O. Specifically, only one of the three switches corresponding to each flip-flop is turned on at any given time. That is, each flip-flop receives only one excitation clock.

[0103] Within each cycle, the eighth switch H2 corresponding to the last flip-flop in the valid memory cell in the programming state is turned on, and the seventh switch H1 and the ninth switch H3 corresponding to that flip-flop are turned off; the seventh switch H1 corresponding to the next flip-flop in the valid memory cell in the programming state is turned on, and the eighth switch H2 and the ninth switch H3 corresponding to that flip-flop are turned off; the ninth switch H3 corresponding to the other flip-flops in the valid memory cell in the programming state (excluding the last flip-flop) is turned on, and the seventh switch H1 and the eighth switch H2 corresponding to those other flip-flops are turned off.

[0104] To achieve the above control effect, refer to Figure 13 In terms of circuit logic control, the seventh switch H1 is turned on only when the corresponding flip-flop outputs logic 0 and the preceding flip-flop outputs logic 1; the eighth switch H2 is turned on only when the corresponding flip-flop outputs logic 1 and the following flip-flop outputs logic 0; the ninth switch H3 is turned on when neither the seventh nor the eighth switch H2 is turned on. In this way, for each flip-flop, only one of the three switches is turned on at any given time.

[0105] Each cycle contains N valid memory cells in the programming state. At any given time, only one of the eighth switch H2 and the seventh switch H1 is turned on, corresponding to the last valid memory cell among these N valid memory cells and the first valid memory cell adjacent to these N valid memory cells, respectively.

[0106] Figure 14This application provides a schematic diagram of the structure of a clock control module 51. The clock control module 51 includes a second detection module 53 and a logic calculation module 54. The second detection module 53 is used to output a second control signal, a third control signal, and a fourth control signal based on the relationship between the total programming current of the effective memory cells in the current cycle and a predetermined range. The second control signal, the third control signal, and the fourth control signal characterize the relationship between the total programming current of the current cycle and the predetermined range. The logic calculation module 54 is connected to the second detection module 53 and is used to output a first control clock CLK_dff_D, a second control clock CLK_dff_N, and a third control clock CLK_dff_O under the control of the second control signal, the third control signal, and the fourth control signal.

[0107] Specifically, the second control signal indicates that the total programming current of the effective memory cells in the current cycle is lower than the low parameter value in the predetermined range; the third control signal indicates that the total programming current of the effective memory cells in the current cycle is higher than the high parameter value in the predetermined range; and the fourth control signal indicates that the total programming current of the effective memory cells in the current cycle is within the predetermined range.

[0108] The following section, in conjunction with the circuit diagram, explains how the control signals (including the second, third, and fourth control signals) control the generation of the control clock (including the first control clock CLK_dff_D, the second control clock CLK_dff_N, and the third control clock CLK_dff_O).

[0109] Figure 15 This application provides a circuit diagram of a second detection module 53. The second detection module 53 includes multiple tenth switches T, a third comparator, a fourth comparator, a first flip-flop, a second flip-flop, and a third inverter. Figure 15 As shown, multiple tenth switches T correspond one-to-one with the memory cells in the row to be programmed; the first end of the tenth switch T is connected to the corresponding memory cell, and the second end of the tenth switch T is connected to the inverting input of the third comparator and the non-inverting input of the fourth comparator respectively; the non-inverting input of the third comparator is connected to the low parameter value in the predetermined range; the inverting input of the fourth comparator is connected to the high parameter value in the predetermined range.

[0110] The state of the tenth switch T depends on the output data of the corresponding flip-flop and the stored data of the corresponding page latch, so as to control the tenth switch T corresponding to the valid memory cell configured in the programming state to be turned on, and the tenth switch T corresponding to the valid memory cell in other non-programming states to be turned off.

[0111] Specifically, the state of the tenth switch T is determined by the AND logic of the output data of the corresponding flip-flop and the stored data of the corresponding page latch. For example, when the tenth switch T... i+1The corresponding output data (i.e., its stored value) C of the trigger. i+1 and the corresponding page latch storage data P i+1 If both are logic 1, then their AND operation results in a logic 1, and the tenth switch Ti+1 is turned on. For each valid memory cell configured in the programming state within each cycle, the stored data in its corresponding page latch must be logic 1, and the output data of its corresponding flip-flop must also be 1. Therefore, its corresponding tenth switch T is turned on. In other words, the tenth switch Ti+1 corresponding to all valid memory cells configured in the programming state within each cycle is turned on, thus allowing the total programming current to be obtained.

[0112] It should be noted that since the comparator input is a voltage value, the current values ​​of each selected column need to be linearly converted into a voltage value by summing them through a reasonable circuit. The circuit structure for summing currents and converting them into voltages is not the subject of this patent, and therefore will not be analyzed in detail.

[0113] The acquired total programming current is converted into a total programming voltage value, which is then input into the third and fourth comparators for comparison, and the comparison results CO are output respectively. L CO H For the third comparator, its non-inverting input is a low voltage value Vref_L, and its inverting input is the total programming voltage value. When the total programming voltage value is lower than Vref_L, then CO... L The signal is 1; when the total programming voltage is higher than Vref_L, then CO L The signal is 0. For the fourth comparator, its inverting input is a low voltage value Vref_H, and its non-inverting input is the total programming voltage value. When the total programming voltage value is lower than Vref_H, then CO... H The signal is 1; when the total programming voltage is higher than Vref_H, then CO L The signal is 0.

[0114] Furthermore, the output of the third comparator is connected to the input of the first flip-flop; the first output of the first flip-flop outputs the first parameter O. L The second output of the first flip-flop outputs the NOT logic parameter of the first parameter. The fourth comparator is connected to the output of the input of the second flip-flop; the first output of the second flip-flop outputs the second parameter O. H The second output of the second flip-flop outputs the NOT logic parameter of the second parameter. First parameter O L Second parameter O H The combination of these signals forms the second, third, and fourth control signals.

[0115] Specifically, the input signal CO of the first trigger LThe second trigger input signal CO H The first trigger outputs the first parameter O. L With CO L The logic values ​​are the same. The second flip-flop outputs the first parameter O. H With CO H The logical values ​​are the same. Combining the comparison results of the third and fourth comparators, the first and second parameters have three possible combinations:

[0116] (1) When the total programming voltage is lower than the predetermined range, the total programming voltage is lower than Vref_L, and therefore must also be lower than Vref_H, then CO L =1, CO H =1, corresponding O L =1, O H =1, which is the second control signal.

[0117] (2) When the total programming voltage value is higher than the predetermined range, the total programming voltage value is higher than Vref_H, and therefore must also be higher than Vref_L, then CO L =0, CO H =0, corresponding O L =0, O H =0, which is the third control signal.

[0118] (3) When the total programming voltage is within the predetermined range, if the total programming voltage is higher than Vref_L and lower than Vref_H, then CO L =0, CO H =1, corresponding O L =0, O H =1, which is the fourth control signal.

[0119] Furthermore, the clock ports of both the first and second flip-flops are connected to the output of the third inverter, and the input of the third inverter is connected to the fourth control clock CLK_ds. That is, the first and second flip-flops are controlled by the inverted signal of the fourth control clock CLK_ds.

[0120] Figure 16 A circuit diagram of a logic calculation module 54 provided in this application. (Combined with...) Figure 16 The process of controlling the output of the first control clock CLK_dff_D, the second control clock CLK_dff_N, and the third control clock CLK_dff_O by three control signals, as well as the generation process of the fourth control clock CLK_ds, are described.

[0121] like Figure 16As shown, the logic calculation module 54 includes: a third delay unit, a first XOR gate, an eleventh switch M1, a twelfth switch M2, a thirteenth switch M3, and a fourteenth switch M4. The control terminal of the eleventh switch M1 is connected to the first parameter O. L The control terminal of the twelfth switch M2 is connected to the NOT logic parameter of the first parameter. The control terminal of the thirteenth switch M3 is connected to the second parameter O. H The control terminal of the fourteenth switch M4 is connected to the non-logic parameter of the second parameter.

[0122] The input of the third delay is connected to the excitation clock CLK_dff; the output of the third delay outputs the fourth control clock CLK_ds.

[0123] The above settings are used to control the response timing of each device. The first and second flip-flops are delayed for a certain time interval before they take effect. This time interval is used for the flip-flops, fourth switch S, tenth switch T, third comparator and fourth comparator in the programming control module 20 to take effect in response to the excitation clock CLK_dff.

[0124] The first input of the first XOR gate is connected to the output of the third delay; the second input of the first XOR gate is connected to the excitation clock CLK_dff; the output of the first XOR gate is connected to the first terminal of the eleventh switch M1; the second terminal of the eleventh switch M1 is connected to the output of the first control clock CLK_dff_D.

[0125] The above settings, where the excitation clock CLK_dff is XORed with its own delay signal, will generate one more rising edge compared to the excitation clock CLK_dff. In the second control signal (O... L =1, O H =1), the eleventh switch M1 is turned on, and the twelfth switch M2 is turned off. The output first control clock CLK_dff_D has one more rising edge than the excitation clock CLK_dff, which can be used to add an extra valid memory cell to be configured into programming state.

[0126] The first terminal of the twelfth switch M2 is connected to the excitation clock CLK_dff; the second terminal of the twelfth switch M2 is connected to the output terminal of the first control clock CLK_dff_D.

[0127] The above settings, in the third control signal (O) L =0, O H =0) and the fourth control signal (O) L =0, O H =1), the eleventh switch M1 is closed and the twelfth switch M2 is open. The output first control clock CLK_dff_D is consistent with the excitation clock CLK_dff.

[0128] The first terminal of the thirteenth switch M3 is connected to the excitation clock CLK_dff; the first terminal of the fourteenth switch M4 is grounded; the second terminals of both the thirteenth switch M3 and the fourteenth switch M4 are connected to the output terminal of the second control clock CLK_dff_N.

[0129] The above settings, in the second control signal (O) L =1, O H =1) and the fourth control signal (O) L =0, O H =1), the thirteenth switch M3 is turned on, and the fourteenth switch M4 is turned off. The output second control clock CLK_dff_N is consistent with the excitation clock CLK_dff. Under the third control signal (O) L =0, O H When M3 is open (=0), the thirteenth switch M3 is open and the fourteenth switch M4 is open. The output second control clock CLK_dff_N is grounded and does not generate a rising edge, which can be used to reduce the number of valid memory cells configured for programming.

[0130] The output of the third control clock CLK_dff_O is connected to the excitation clock CLK_dff. This setting ensures that CLK_dff_O is always synchronized with the excitation clock CLK_dff under all three control signals.

[0131] Figure 17 A waveform diagram for increasing quantity is provided in this application. Combined with... Figure 17 The process of configuring an additional valid memory unit into a programmed state is described. The excitation signal CLK_dff consists of two rising edges, each representing the start of a cycle.

[0132] The initial excitation clock CLK_Internal generates the excitation signal CLK_dff through the second delay. The excitation signal CLK_dff generates the fourth control clock CLK_ds through the third delay. The rising edge of the inverted signal of the fourth control clock CLK_ds corresponds to the falling edge of the fourth control clock CLK_ds. Figure 17 The Delay shown is the inverted delay signal of the signal CO output by the first inverter of the generation module 32.

[0133] When the total programming current is detected to be lower than the preset range, the output signal CO of the third comparator is activated. L =1. The first flip-flop outputs signal O on the first falling edge of the fourth control clock CLK_ds. LWhen the switch changes to 1, the eleventh switch M1 is turned on, and the twelfth switch M2 is turned off. The output first control clock CLK_dff_D has one more rising edge than the excitation clock CLK_dff, such as... Figure 17 The third rising edge of CLK_dff_D.

[0134] When the total programming current is lower than the preset range, the output signal CO of the fourth comparator... H =1, the second flip-flop outputs signal O H =1, the thirteenth switch M3 is turned on, the fourteenth switch M4 is turned off, and the second control clock CLK_dff_N is consistent with the excitation clock CLK_dff.

[0135] As is known from the foregoing, the seventh switch H1 is turned on only when the corresponding flip-flop outputs logic 0 and the preceding flip-flop outputs logic 1, and is connected to the first control clock CLK_dff_D. Figure 17 In the middle, at the second rising edge of CLK_dff, for the (i+1)th flip-flop, its output C i+1 =0, the output C of the i-th flip-flop i =1, so the (i+1)th flip-flop receives the first control clock CLK_dff_D.

[0136] As is known from the foregoing, the eighth switch H2 is turned on when the corresponding flip-flop outputs logic 1 and the next flip-flop outputs logic 0, and is connected to the second control clock CLK_dff_N. Figure 17 In the above, for the i-th flip-flop, its output C i =1, the output C of the (i+1)th flip-flop i+1 =0, so the i-th flip-flop receives the second control clock CLK_dff_N.

[0137] exist Figure 17 At the second rising edge of CLK_dff_D, the i-th flip-flop changes to 1. At this time, the (i+1)-th flip-flop still outputs 0. Figure 17 At the third rising edge of CLK_dff_D, the (i+1)th flip-flop outputs 1. Because... Figure 17 The third rising edge of CLK_dff_D falls between the second rising edge and the second falling edge of CLK_dff, so the output C of the (i+1)th flip-flop... i+1 It will jump to 1 at the third rising edge of CLK_dff_D.

[0138] It should be noted that when the output C of the flip-flop corresponding to the valid memory cell is 1, it is configured into a programming state. Therefore, when the output C of the (i+1)th flip-flop... i+1If the value is 1, then it is configured in a programmed state. Therefore, based on the above adjustment process, an additional quantity is added, and the (i+1)th flip-flop becomes the last flip-flop in this cycle, and the number of valid memory cells in the programmed state in this cycle is equal to the number in the previous cycle plus one. If no additional quantity is added, then the ith flip-flop is the last flip-flop in this cycle, and the number of valid memory cells in the programmed state in this cycle is equal to the number in the previous cycle.

[0139] Specifically, if no additional quantity is added, Figure 17 If CLK_dff_D does not have a third rising edge, then the (i+1)th flip-flop will always output 0. This situation corresponds to the case where the total programming current is within the preset range: the output signal CO of the third comparator. L =0, the output signal CO of the fourth comparator H =1, corresponding to Figure 16 In this cycle, switch M1 is open, switch M2 is on, switch M3 is on, and switch M4 is open. Therefore, the second control clock CLK_dff_D and the third control clock CLK_dff_N are both synchronized with the excitation clock CLK_dff. Consequently, the number of valid memory cells in the programming state in this cycle is the same as the number in the previous cycle.

[0140] In addition, it can be observed Figure 17 CO L The total programming current was detected to be below the preset range during the cycle preceding the first rising edge of CLK_dff, resulting in an output of 1. However, no adjustment was made to the quantity during the cycle starting at the first rising edge of CLK_dff. This is a possible extreme case, as current changes can occur at any point during the process, although CO... L The total programming current was detected to be below the preset range within the cycle preceding the first rising edge of CLK_dff, resulting in an output of 1. However, O L The output is determined by the falling edge of CLK_ds, so there may be a situation where the adjustment is delayed by one cycle, that is, the adjustment begins in the cycle starting at the second rising edge of CLK_dff. In this case, the total programming current may already be within the preset range in the cycle starting at the first rising edge of CLK_dff, but it will still be adjusted.

[0141] Figure 18 A waveform diagram for reducing quantity is provided in this application. (Combined with...) Figure 18 The process of reducing the number of available memory units configured into a programmed state is described. Figure 18 The values ​​shown are CLK_Internal, Delay, CLK_dff, and CLK_ds. Figure 17The same applies as shown, so I will not repeat it again.

[0142] When the total programming current is detected to be higher than the preset range, the output signal CO of the fourth comparator is activated. H =0. The second flip-flop outputs signal O on the first falling edge of the fourth control clock CLK_ds. H When the value changes to 0, the thirteenth switch M3 is off, and the fourteenth switch M4 is on. The output second control clock CLK_dff_N is grounded without generating a rising edge. Figure 18 CLK_dff_N does not have a second rising edge compared to CLK_dff.

[0143] When the total programming current is detected to be higher than the preset range, the output signal CO of the third comparator is activated. L =0, output signal O L =0, the eleventh switch M1 is open, and the twelfth switch M2 is on. The output first control clock CLK_dff_D is consistent with the excitation clock CLK_dff.

[0144] Through the Figure 17 Analysis reveals that the i-th flip-flop receives the second control clock CLK_dff_N, and the (i+1)-th flip-flop receives the first control clock CLK_dff_D. Figure 18 The same applies in the middle, because structurally, in each cycle, among the N valid memory cells configured in the programming state, the last valid memory cell corresponds to the eighth switch H2 being turned on, connected to the second control clock CLK_dff_N; the first valid memory cell after these N valid memory cells corresponds to the seventh switch H1 being turned on, connected to the first control clock CLK_dff_D. What remains unchanged is the connection between the output ports of these three excitation clocks and their corresponding flip-flops; what changes are the excitation signals of these three excitation clocks.

[0145] When the total programming current is higher than the preset range, the excitation signals of the first control clock CLK_dff_D and the excitation clock CLK_dff are consistent; the second control clock CLK_dff_N is grounded and does not generate a rising edge, thus reducing the excitation signal compared to the excitation clock CLK_dff.

[0146] At the second rising edge of CLK_dff, CLK_dff_N has no rising edge, so the output C of the i-th flip-flop... i =0. Because C i =0, the (i+1)th flip-flop is triggered by the rising edge of the first control clock CLK_dff_D (reference). Figure 18 Under the excitation of CLK_dff (as shown), its output C i+1 =0.

[0147] Based on the above adjustment process, if the number is reduced, the (i-1)th trigger becomes the last trigger in that cycle. If the number is not reduced, the ith trigger becomes the last trigger in that cycle.

[0148] In addition, it can be observed Figure 18 CO H The total programming current was detected to be higher than the preset range during the cycle prior to the first rising edge of CLK_dff, resulting in an output of 0. However, no adjustment was made to the quantity during the cycle starting at the first rising edge of CLK_dff. This is a possible extreme case, as current changes can occur at any point during the process, although CO... H The total programming current was detected to be below the preset range within the cycle preceding the first rising edge of CLK_dff, resulting in an output of 0. However, O H The output is determined by the falling edge of CLK_ds, so there may be a situation where the adjustment is delayed by one cycle. That is, the cycle CLK_dff_N, which starts at the second rising edge of CLK_dff, may not have a rising edge. In this case, the total programming current in the cycle starting at the first rising edge of CLK_dff may already be within the preset range, but it will still be adjusted.

[0149] The programming apparatus provided in this application includes: a quantity setting unit 50, a programming control unit 10, and a programming unit 20; the quantity setting unit 50 is used to generate a control clock based on the total programming current of the valid memory cells configured to be programmed in the current cycle of the excitation clock, so as to determine the number of valid memory cells configured to be programmed in the next cycle; the programming control unit 10 is used to respond to the control clock, sequentially taking each valid memory cell in the row to be programmed as the first cell and performing processing until all valid memory cells are programmed: according to the number of valid memory cells configured to be programmed in the current cycle, sequentially selecting the first cell and the valid memory cells thereafter and configuring them to be programmed; configuring the unselected valid memory cells after the first cell to be non-programmed; the programming unit 20 is used to perform programming on the valid memory cells currently configured to be programmed according to a predetermined cycle until all valid memory cells are programmed. This application can program only a portion of the cells in the programming row within a single cycle. It can also adjust the number of cells in the programming cycle in real time according to the total programming current to avoid damaging the chip due to excessive heat caused by excessive total programming current. Furthermore, it can move sequentially within a row, replacing programmed cells with unprogrammed cells, and programming them in turn to achieve traversal of the entire row of cells to be programmed.

[0150] Example 2

[0151] This application provides a programming method applied to the aforementioned programming apparatus, which includes a programming control unit 10, a programming unit 20, and a quantity setting unit 50. The method includes: the quantity setting unit 50 generating a control clock based on the total programming current of the valid memory cells configured as programming cells in the current cycle of the excitation clock, to determine the number of valid memory cells configured as programming cells in the next cycle; the programming control unit 10, in response to the control clock, sequentially takes each valid memory cell in the row to be programmed as the first cell and performs the following processing until all valid memory cells are programmed: selecting the first cell and subsequent valid memory cells sequentially according to the number of valid memory cells configured as programming cells in the current cycle, and configuring them as programming cells; configuring the unselected valid memory cells after the first cell as non-programming cells; and the programming unit 20 performing programming on the currently configured valid memory cells according to a predetermined cycle until all valid memory cells are programmed.

[0152] The above programming method can program only a portion of the cells in the row to be programmed within a cycle. At the same time, it can adjust the number of cells in the programming cycle in real time according to the total programming current to avoid excessive heat damage to the chip due to excessive total programming current. Furthermore, it can move sequentially within a row, replacing programmed cells with unprogrammed cells, and programming them in turn to achieve traversal of the entire row of cells to be programmed.

[0153] In one example, the programming method further includes: the programming control unit 10 configuring each flip-flop in the programming unit chain as second logic; and the programming control unit 10 configuring the first predetermined number of flip-flops in the effective programming unit chain as first logic based on the input first logic and in response to a predetermined number of external stimulus signals.

[0154] Before programming unit 20, initialization is performed by writing some data to the valid programming unit chain externally, selecting N valid storage units and configuring them to the programming state, providing an initial quantity N for the first cycle, such as... Figure 6 As shown. The input signals include the link input signal Chain_in and the link control clock signal CLK_O, and their main function is to determine the number N of memory cells that are in the programming state at the same time.

[0155] The first step of initialization is to write all 1s to the page latch, so that all D flip-flops are in the link.

[0156] The second initialization step: Using an external link clock, all D flip-flops are written to a state that stores logic 0. Specifically, the Chain_In signal is continuously set to logic 0, and a periodic link control clock signal CLK_O is continuously input until all D flip-flops are written to a state that stores logic 0.

[0157] The third initialization step is to store the data to be written in the page latch, so that only the D flip-flops corresponding to the units that need to be programmed are in the chain, thus establishing a valid programming unit chain.

[0158] Initialization step 4: Set the Chain_In signal input to logic 1. The CLK_O signal provides N clock cycles, where N is any integer and can be customized. After N cycles, set the Chain_In signal input to logic 0. The purpose of this operation is to ensure that the first N D flip-flops in the valid programmable cell chain are at logic 1, while the other D flip-flops are at logic 0.

[0159] The programming method provided in this application programs only a portion of the cells in the row to be programmed within one cycle. At the same time, the number of cells in the programming cycle can be adjusted in real time according to the total programming current to avoid damage to the chip due to excessive total programming current and heat. Furthermore, it can move sequentially within a row, replacing programmed cells with unprogrammed cells, and programming them in turn to achieve traversal of the entire row of cells to be programmed.

[0160] This application also provides a hardware code product, including hardware code, which, when executed by a processor, implements the methods provided in the above embodiments.

[0161] This application also provides a readable storage medium storing hardware code, which, when executed, is used to implement the methods provided in the above embodiments.

[0162] This application also provides an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores hardware code; the processor executes the hardware code stored in the memory to implement the method provided in the above embodiments.

[0163] This application also provides a novel memory, including a plurality of resistive memory cells and a programming device as provided in the foregoing embodiments; the programming device is used to program the resistive memory cells. The novel memory may be a resistive-change memory, a phase-change memory, or a magnetic-change memory.

[0164] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0165] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A programming device, characterized in that, include: Quantity setting unit, programming control unit, and programming unit; The quantity setting unit is used to generate a control clock based on the total programming current of the effective memory cells configured as programmed in the current cycle of the excitation clock, so as to determine the number of effective memory cells configured as programmed in the next cycle. The programming control unit is configured to respond to the control clock by sequentially selecting each valid memory cell in the row to be programmed as the first cell and performing processing until all valid memory cells are programmed: based on the number of valid memory cells configured to be programmed in the current cycle, sequentially selecting the first cell and the valid memory cells thereafter and configuring them to be programmed; configuring the unselected valid memory cells after the first cell to be non-programmed. The programming unit is configured to program the currently configured valid storage units according to a predetermined period until all valid storage units are programmed. The programming control unit includes a programming unit chain consisting of multiple flip-flops connected in series; wherein each of the multiple flip-flops corresponds one-to-one with a page latch corresponding to each memory unit in the row to be programmed.

2. The apparatus according to claim 1, characterized in that, The clock port of each of the flip-flops is connected to the control clock via a first switch, the output of each of the flip-flops is connected to the input of the next flip-flop via a second switch, and the input of each of the flip-flops is connected to the input of the next flip-flop via a third switch. The page latch corresponding to each storage unit is used to control the switching states of the first switch, the second switch, and the third switch of the corresponding trigger based on its own stored data, so as to establish a valid programming unit chain; wherein, the storage unit corresponding to the trigger in the valid programming unit chain is the valid storage unit; Specifically, the trigger corresponding to the valid storage unit configured in a programmed state is configured as the first logic, and the trigger corresponding to the valid storage unit configured in a non-programmed state is configured as the second logic.

3. The apparatus according to claim 2, characterized in that, The programming control unit also includes: multiple inverters; The plurality of inverters correspond one-to-one with the plurality of flip-flops. The input terminal of the inverter is connected to the corresponding page latch, and the output terminal of the inverter is connected to the control terminal of the third switch of the corresponding flip-flop.

4. The apparatus according to claim 3, characterized in that, The device further includes: a clock generation unit; The clock generation unit is used to provide the excitation clock to the quantity setting unit.

5. The apparatus according to claim 4, characterized in that, The clock generation unit includes: a first detection module and a generation module; The first detection module is used to sequentially detect whether the first valid storage unit currently configured as a programming state has completed programming, and output the detection result; The generation module is configured to control the excitation clock to generate an excitation signal if the detection result characterization is completed and programming is completed; otherwise, it controls the excitation clock not to generate the excitation signal.

6. The apparatus according to claim 5, characterized in that, The first detection module includes: multiple fourth switches and a first comparator; The plurality of fourth switches correspond one-to-one with the memory cells in the row to be programmed; the first end of the fourth switch is connected to the corresponding memory cell, and the second end of the fourth switch is connected to the non-inverting input of the first comparator; the inverting input of the first comparator is connected to the first reference voltage. The fourth switch is used to select the valid storage unit that the first detection module is currently detecting, and the state of the fourth switch depends on the input data and output data of the corresponding trigger. The output data of the first comparator indicates whether the currently selected valid memory cell has been programmed.

7. The apparatus according to claim 6, characterized in that, The first detection module further includes: a first enable switch; The first enable switch is disposed between the fourth switch and the non-inverting input of the first comparator; After the programming unit starts programming, the first enable switch is in a closed state; before the programming unit starts programming, the first enable switch is in a closed state.

8. The apparatus according to claim 5, characterized in that, The generation module includes: a first AND gate, a first OR gate, a first delay unit, and a first inverter; The first input terminal of the first AND gate is connected to the output terminal of the first detection module to receive the detection result output by the first detection module; The output of the first AND gate is connected to the first input of the first OR gate; the output of the first OR gate is connected to the input of the first delay unit; the output of the first delay unit is connected to the input of the first inverter; the output of the first inverter is connected to the second input of the first AND gate. The second input terminal of the first OR gate is connected to the first control signal; based on the first control signal and the output signal of the first AND gate, the output terminal of the first OR gate outputs the initial excitation clock.

9. The apparatus according to claim 8, characterized in that, The clock generation unit further includes: a delay module; The delay module includes a second delayer for delaying the initial excitation clock to generate the excitation clock.

10. The apparatus according to claim 9, characterized in that, The clock generation unit further includes: a second enable switch; the second enable switch is connected between the output terminal of the second delay unit and the programming control unit; After the programming unit starts programming, the second enable switch is in a closed state; before the programming unit starts programming, the second enable switch is in a closed state.

11. The apparatus according to claim 9, characterized in that, The device further includes: an error reporting unit; The error reporting unit is used to control the excitation clock output by the clock generation unit to generate the excitation signal if the currently detected valid storage unit has not completed programming after a preset time.

12. The apparatus according to claim 11, characterized in that, The error reporting unit includes: a second inverter, a fifth switch, a sixth switch, a first capacitor, and a second comparator; The non-inverting input of the second comparator is connected to the first terminal of the first capacitor and one terminal of the sixth switch; the first terminal of the first capacitor is connected to the power supply signal through the fifth switch; the inverting input of the second comparator is connected to the second reference voltage; the second terminal of the first capacitor is grounded; the other terminal of the sixth switch is grounded. The input terminal of the second inverter is connected to the initial excitation clock, and the output terminal of the second inverter is connected to the control terminal of the fifth switch; the control terminal of the sixth switch is connected to the initial excitation clock. The output of the second comparator outputs the first control signal.

13. The apparatus according to claim 3, characterized in that, The quantity setting unit includes: a clock control module and a clock selection module; The clock control module is used to output a first control clock, a second control clock, and a third control clock based on the relationship between the total programming current and a predetermined range in the current cycle. Specifically, when the total programming current is below the predetermined range, the number of excitation signals for the first control clock increases compared to the number of excitation signals for the excitation clock, and the second and third control clocks are synchronized with the excitation clock; when the total programming current is above the predetermined range, the number of excitation signals for the second control clock decreases compared to the number of excitation signals for the excitation clock, and the first and third control clocks are synchronized with the excitation clock; when the total programming current is within the predetermined range, the first, second, and third control clocks are synchronized with the excitation clock. The clock selection module includes multiple seventh switches, multiple eighth switches, and multiple ninth switches; The plurality of seventh switches, the plurality of eighth switches, and the plurality of ninth switches correspond one-to-one with the plurality of triggers. One end of each of the seventh, eighth, and ninth switches is connected to the clock port of the corresponding trigger through the first switch; the other end of the seventh switch is connected to the first control clock; the other end of the eighth switch is connected to the second control clock; and the other end of the ninth switch is connected to the third control clock. Within each cycle, the eighth switch corresponding to the last trigger in the valid memory cell configured in the programming state is turned on, and the seventh and ninth switches corresponding to that trigger are turned off; the seventh switch corresponding to the next trigger in the valid memory cell configured in the programming state is turned on, and the eighth and ninth switches corresponding to that trigger are turned off; the ninth switch corresponding to the other triggers in the valid memory cell configured in the programming state (excluding the last trigger) is turned on, and the seventh and eighth switches corresponding to those other triggers are turned off.

14. The apparatus according to claim 13, characterized in that, The clock control module includes a second detection module and a logic calculation module; The second detection module is used to output a second control signal, a third control signal, and a fourth control signal based on the relationship between the total programming current and a predetermined range in the current cycle; the second control signal, the third control signal, and the fourth control signal characterize the relationship between the total programming current and the predetermined range in the current cycle. The logic calculation module is connected to the second detection module and is used to output the first control clock, the second control clock, and the third control clock under the control of the second control signal, the third control signal, and the fourth control signal.

15. The apparatus according to claim 14, characterized in that, The second detection module includes multiple tenth switches, a third comparator, a fourth comparator, a first flip-flop, a second flip-flop, and a third inverter; The plurality of tenth switches correspond one-to-one with the memory cells in the row to be programmed; the first end of the tenth switch is connected to the corresponding memory cell, and the second end of the tenth switch is connected to the inverting input of the third comparator and the non-inverting input of the fourth comparator respectively; the non-inverting input of the third comparator is connected to the low parameter value in the predetermined range; The inverting input of the fourth comparator is connected to a high parameter value within the predetermined range; The state of the tenth switch depends on the output data of the corresponding trigger and the storage data of the corresponding page latch, so as to control the tenth switch corresponding to the valid memory cell configured in the programming state to be turned on, and the tenth switch corresponding to the other valid memory cells to be turned off. The output of the third comparator is connected to the input of the first flip-flop; the first output of the first flip-flop outputs a first parameter; the second output of the first flip-flop outputs the NOT parameter of the first parameter; the fourth comparator is connected to the output of the input of the second flip-flop; the first output of the second flip-flop outputs a second parameter; the second output of the second flip-flop outputs the NOT parameter of the second parameter; the combination of the first parameter and the second parameter forms the second control signal, the third control signal, and the fourth control signal; The clock ports of the first flip-flop and the second flip-flop are both connected to the output of the third inverter, and the input of the third inverter is connected to the fourth control clock.

16. The apparatus according to claim 15, characterized in that, The logic calculation module includes: a third delay unit, a first XOR gate, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch; The control terminal of the eleventh switch is connected to the first parameter; the control terminal of the twelfth switch is connected to the non-logic parameter of the first parameter; the control terminal of the thirteenth switch is connected to the second parameter; the control terminal of the fourteenth switch is connected to the non-logic parameter of the second parameter. The input terminal of the third delay unit is connected to the excitation clock; the output terminal of the third delay unit outputs the fourth control clock. The first input terminal of the first XOR gate is connected to the output terminal of the third delay unit; the second input terminal of the first XOR gate is connected to the excitation clock; the output terminal of the first XOR gate is connected to the first terminal of the eleventh switch; the second terminal of the eleventh switch is connected to the output terminal of the first control clock. The first terminal of the twelfth switch is connected to the excitation clock; the second terminal of the twelfth switch is connected to the output terminal of the first control clock. The first terminal of the thirteenth switch is connected to the excitation clock; the first terminal of the fourteenth switch is grounded; the second terminals of both the thirteenth and fourteenth switches are connected to the output terminal of the second control clock. The output of the third control clock is connected to the excitation clock.

17. A programming method, characterized in that, Applied to a programming device, the programming device includes a quantity setting unit, a programming control unit, and a programming unit; The programming control unit includes: a programming unit chain consisting of multiple flip-flops connected in series; wherein, each of the multiple flip-flops corresponds one-to-one with a page latch corresponding to each memory cell in the row to be programmed; the method includes: The quantity setting unit generates a control clock based on the total programming current of the effective memory cells configured as programmed in the current cycle of the excitation clock, so as to determine the number of effective memory cells configured as programmed in the next cycle. In response to the control clock, the programming control unit sequentially selects each valid memory cell in the row to be programmed as the first cell and performs the following process until all valid memory cells are programmed: based on the number of valid memory cells configured to be programmed in the current cycle, the first cell and the valid memory cells thereafter are selected sequentially and configured to be programmed; the unselected valid memory cells after the first cell are configured to be non-programmed. The programming unit performs programming on the currently configured programming state of the valid storage units according to a predetermined cycle, until all the valid storage units are programmed.

18. A novel memory, characterized in that, It includes a plurality of resistive memory cells and a programming device as described in any one of claims 1-16; the programming device is used to program the memory cells.

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