Preparation method of RC-IGBT cell and RC-IGBT chip

Abstract

The present application provides a method for fabricating an RC-IGBT cell and an RC-IGBT chip. The fabrication method includes: processing a semiconductor substrate and forming a gate composed of an oxide layer and polysilicon thereon; etching a plurality of hole regions in the middle of the gate; injecting N+ emitters in the hole regions through a photomask with a preset structure, wherein the region where the N+ emitters are injected is the IGBT region, and the region where the N+ emitters are not injected is the FRD region. The fabrication method provided by the present application segments the strip gate, etches a plurality of hole regions in the middle of the gate, and uses a photomask with a preset structure to rationally layout the positions of the N+ emitters in the hole regions, enabling the diode part not short-circuited by the channel to enter the conductivity modulation state first, effectively reducing VF, and optimizing VF-shift.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing an RC-IGBT cell and an RC-IGBT chip. Background Art

[0002] In a reverse conducting-insulated gate bipolar transistor (RC-IGBT) module, since a fast recovery diode (FRD) is integrated in parallel inside the chip, the power level of the module can be greatly improved. The RC-IGBT has the ability to conduct in the forward and reverse directions. When conducting in the forward direction, the RC-IGBT operates in the IGBT mode, and when conducting in the reverse direction, the device operates in the FRD mode.

[0003] When a general IGBT module operates, an optimized gate control method is usually adopted to obtain the lowest power loss. That is, opposite gate voltage signals are provided for the low-voltage side and the high-voltage side of the device respectively, and a blanking time is required to ensure that the two switches cannot conduct simultaneously to avoid device short-circuit. For the RC-IGBT, when it operates in the FRD mode, the gate of the device needs to be grounded or a negative gate voltage signal is required to ensure low FRD conduction loss, because a positive gate voltage will cause the MOS channel to invert and short-circuit with the P-well (i.e., the anode of the FRD), thereby greatly reducing the hole injection efficiency of the FRD anode. When the FRD conducts in the forward direction, the conduction voltage drop (VF, Forward or Voltage) increases significantly. That is, when the RC-IGBT operates in the FRD mode, the conduction voltage drop VF of the FRD under a positive gate voltage is different from that under a negative gate voltage, and VF is larger under a positive gate voltage than under a negative gate voltage. This will lead to an increase in the loss of the FRD under a positive gate voltage. This phenomenon of different VF values under positive and negative gate voltages is called VF-shift.

[0004] In related technologies, to solve the problem of large VF-shift, efforts are made from the outside to optimize the gate control signal. When the diode conducts unipolarity at the initial stage of operation, although there is a problem of large VF, there is no reverse recovery process during turn-off, so the reverse recovery loss is extremely small; after the diode undergoes the conductivity modulation effect, although VF is large, the reverse recovery loss also increases. The optimization principle of the drive control signal is as Figure 1As shown, when the diode operates during the freewheeling stage of the module, the driver applies a negative gate voltage to the gate, preventing the channel from conducting and allowing the diode to directly enter the bipolar operation mode. When the device is about to finish freewheeling, the gate voltage is changed to a positive gate voltage in advance, causing the channel to open, reducing the hole injection efficiency in the P region and the holes in the drift region. When the IGBT is turned on, the reverse recovery loss of the diode is greatly reduced. This method can, to a certain extent, solve the problem of excessive VF-shift in reverse-conducting IGBTs, but it poses higher requirements for the driver. Therefore, it is necessary to improve one or more problems existing in the above-related technical solutions.

[0005] It should be noted that this part aims to provide background or context for the technical solutions of the present invention stated in the claims. The description herein is not admitted to be prior art merely because it is included in this part. Summary of the Invention

[0006] In view of the above problems, the present application provides a method for manufacturing an RC-IGBT cell and an RC-IGBT chip.

[0007] The present application first provides a method for manufacturing an RC-IGBT cell, the method comprising:

[0008] Processing a semiconductor substrate and forming a gate composed of an oxide layer and polysilicon thereon;

[0009] Etching a plurality of hole regions in the middle of the gate;

[0010] Injecting N+ emitters into the hole regions through a photomask having a preset structure, wherein the region where the N+ emitters are injected is the IGBT region, and the region where the N+ emitters are not injected is the FRD region.

[0011] In some embodiments, each of the hole regions includes a first etched region and a second etched region distributed around the first etched region.

[0012] In some embodiments, the number of the hole regions is at least two.

[0013] In some embodiments, the photomask includes: a plate body and a plurality of hole bodies disposed on the plate body;

[0014] Wherein, the hole bodies are arranged in sequence along the length direction of the gate, and the positions of the hole bodies correspond one-to-one to the positions of the IGBT regions.

[0015] In some embodiments, when performing the implantation of the N+ emitter, the position of each hole body of the photomask corresponds to one of the hole regions respectively, and the aperture of each hole body is smaller than the length of the corresponding hole region. The spacing positions between the hole bodies correspond to the tail of the previous hole region and the head of the next hole region, and the positions of the head and tail hole bodies to the edge of the photomask correspond to the head or tail of a hole region respectively.

[0016] In some embodiments, when performing the implantation of the N+ emitter, the position of each hole body of the photomask corresponds to one or more complete hole regions respectively, the spacing positions between the hole bodies correspond to one or more complete hole regions respectively, and the positions of the head and tail hole bodies to the edge of the photomask also correspond to one or more complete hole regions respectively.

[0017] In some embodiments, when performing the implantation of the N+ emitter, the position of each hole body of the photomask corresponds to the middle of one of the hole regions. The spacing between the hole bodies includes a first spacing and a second spacing. Among them, the position of the first spacing corresponds to the tail of the previous hole region and the head of the next hole region, and the position of the second spacing corresponds to a complete hole region and the heads and tails of the hole regions adjacent to this hole region before and after. The positions of the head and tail hole bodies to the edge of the photomask correspond to the head or tail of a hole region respectively.

[0018] In some embodiments, the total length range of the cell is 10 - 1000 μm.

[0019] In some embodiments, the total length range of the cell is 1 - 100 μm.

[0020] The embodiment of the present application also provides an RC-IGBT chip. The RC-IGBT cells prepared by the method of any one of the above embodiments are arranged in the active region of the chip in an array form.

[0021] A method for preparing an RC-IGBT cell and an RC-IGBT chip provided by the present application can effectively reduce VF and optimize VF-shift by etching a plurality of hole regions in the middle of the gate and rationally arranging the position of the N+ emitter in the hole regions by using a photomask with a preset structure, so that the diode part not short-circuited by the channel enters the conductivity modulation state first. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Hereinafter, the present application will be described in more detail based on embodiments and with reference to the drawings.

[0023] Figure 1 It is a schematic diagram of the optimization principle of a driving control signal of a prior art provided in the background art of the present application;

[0024] Figure 2 Schematic diagram of the implementation process of a preparation method for an RC-IGBT cell provided by an embodiment of the present application;

[0025] Figure 3 Planar schematic diagram of a segmented strip gate cell provided by an embodiment of the present application;

[0026] Figure 4 Schematic diagram of the position of a photomask and a segmented strip gate cell provided by an embodiment of the present application;

[0027] Figure 5 Another schematic diagram of the position of a photomask and a segmented strip gate cell provided by an embodiment of the present application;

[0028] Figure 6 Another schematic diagram of the position of a photomask and a segmented strip gate cell provided by an embodiment of the present application;

[0029] Figure 7 Planar schematic diagram of an RC-IGBT cell array provided by an embodiment of the present application.

[0030] Reference numerals: 100, active region; 200, gate; 300, hole region; 400, first scribe region; 500, second scribe region; 600, photomask; 610, hole body; 620, spacing between hole bodies; 630, portion of the hole body away from the edge of the photomask.

[0031] In the drawings, like parts are denoted by like reference numerals, and the drawings are not drawn to actual scale. Detailed implementation manners

[0032] The following will describe in detail the implementation manners of the present disclosure in conjunction with the drawings and embodiments, so as to fully understand how the present disclosure uses technical means to solve technical problems and the implementation process of achieving corresponding technical effects and implement accordingly. Each feature in the embodiments of the present disclosure and the embodiments can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. Like reference numerals denote like elements throughout.

[0033] It should be understood that, although the terms “first”, “second”, “third”, etc. may be used to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below may be denoted as a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0034] It should be understood that spatial relationship terms such as “above”, “on top of”, “below”, “beneath”, etc. may be used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be appreciated that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as “below” other elements or features will be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “beneath” can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms “a”, “an” and “the” are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0036] Embodiments of the present disclosure are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions shown herein but include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.

[0037] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0038] To fully understand the present disclosure, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0039] An embodiment of the present disclosure provides a method for fabricating an RC-IGBT cell, with reference to Figure 2 As shown, the method includes steps S1-S3. Among them:

[0040] Step S1: Process a semiconductor substrate and form a gate composed of an oxide layer and polysilicon thereon.

[0041] Step S2: Etch a plurality of hole regions in the middle of the gate.

[0042] Step S3: Inject N+ emitters into the hole regions through a photomask with a preset structure. The region where the N+ emitters are injected is the IGBT region, and the region where the N+ emitters are not injected is the FRD region.

[0043] A method for fabricating an RC-IGBT cell provided by the present application can effectively reduce VF and optimize VF-shift by etching a plurality of hole regions in the middle of the gate and reasonably arranging the positions of N+ emitters in the hole regions using a photomask with a preset structure, enabling the diode part not short-circuited by the channel to enter the conductivity modulation state first.

[0044] Next, a method for fabricating an RC-IGBT cell provided by the present application will be described in detail with reference to Figures 2 to 6 For step S1, in one embodiment, an N-type single-crystalline silicon material or an N-type epitaxial silicon material can be used as the material of the semiconductor substrate and serve as the drift region of the RC-IGBT cell. After steps such as etching the active region 100, depositing an oxide layer, P-body implantation, and annealing on the drift region according to existing manufacturing methods, a layer of polysilicon is deposited again on the surface of the above-generated structure, or polysilicon is deposited and doped to form N-type polysilicon. For example, in a specific embodiment, N-type polysilicon can be formed by depositing polysilicon on the surface of the semiconductor substrate 100 through a high-temperature furnace tube and performing in-situ doping. The thickness of the polysilicon is 1-2 μm, and the concentration is 1E20 cm

[0045] -3 ​; Then, the polysilicon is subjected to high-temperature activation at a temperature of 950 °C for 30 minutes. Finally, a gate 200 composed of an oxide layer and polysilicon is formed.

[0046] For step S2, in one embodiment, referring to Figure 3 as shown, at least two hole regions 300 can be formed on the gate 200 through photolithography and etching of the gate 200. In this way, compared with the structure having only one hole region in the middle, there is still a gate in the gap portion between the multiple hole regions 300. During the signal transmission process, it is beneficial for the signal to reach the gates on both the upper and lower sides of the hole region 300 simultaneously, and the effect of enhancing the gate signal consistency can be achieved.

[0047] Of course, the present disclosure does not limit the number of hole regions 300. In one embodiment, only 2 hole regions 300 can be formed on one gate 200. In another embodiment, 3, 4, 5 or more hole regions 300 can also be formed on one gate 200. Compared with a single hole region, these structures all achieve the effect of enhancing the gate signal consistency.

[0048] In one embodiment, as Figure 3 shown, each of the above hole regions 300 includes a first etched opening region 400 and a second etched opening region 500 distributed around the first etched opening region 400. Specifically, the first etched opening region 400 is a hole etched to the bare silicon, while the second etched opening region 500 is a hole etched to the polysilicon layer. During etching, the same specific photomask can be used to form the first etched opening region 400 and the second etched opening region 500 at one time.

[0049] For step S3, in one embodiment, a photomask 600 with a preset structure can be designed in advance. The photomask 600 includes a plate body and a plurality of hole bodies 610 provided on the plate body. Specifically, the hole bodies 610 on the photomask 600 can be circular, rectangular or other shapes. The present disclosure does not limit the shape of the hole bodies 610 as long as the N+ emitter implantation can be performed. In one embodiment, the hole bodies 610 on the photomask 600 are arranged in sequence along the length direction of the gate 200, and the positions of the hole bodies 610 correspond one-to-one to the positions of the IGBT regions.

[0050] In this way, during ion implantation, N+ emitter implantation can be performed in each hole region 300 through multiple hole bodies 610. Specifically, N+ emitters can be formed at the positions of the hole regions 300 corresponding to the hole bodies 610 on the photomask 600, while N+ emitters will not be formed at the positions of the hole gaps on the photomask 600 and the hole regions 300 corresponding to the periphery of the photomask 600. Then, the regions without N+ emitters do not conduct during the IGBT operating mode, but can enhance hole injection during the FRD operating mode, and are not affected by the gate voltage, thereby effectively reducing VF and optimizing VF-shift.

[0051] In one embodiment, the implanted ions of the N+ emitter are high-energy arsenic ions and are subjected to high-temperature push traps. For example, the implantation dose of arsenic ions is 1E15 - 8E15 cm -2 , and the implantation energy is 80 - 120 Kev.

[0052] In one embodiment, when performing the implantation of the N+ emitter, the position of each hole body 610 of the photomask 600 corresponds to a hole region 300 respectively, and the aperture of each hole body 610 is smaller than the length of the hole region 300 it corresponds to. The spacing positions 620 between the hole bodies correspond to the tail of the previous hole region 300 and the head of the next hole region 300, and the portions 630 of the head and tail hole bodies to the edge of the photomask correspond to the head or tail of a hole region 300 respectively. In this design, there is no independent FRD region and IGBT region, and the two regions are alternately distributed within the same ring.

[0053] For example, referring to Figure 4 shown, Figure 4 the segmented strip gate cell in has 4 hole regions 300. When implanting the N+ emitter, a photomask 600 with 4 rectangular hole bodies 610 is used. Then, the 4 hole bodies 610 on the photomask 600 correspond to the middle positions of the 4 hole regions 300 respectively, and the side length of each rectangular hole body 610 along the length direction of the gate 200 in the photomask 600 is smaller than the length of the hole region 300 it corresponds to. The distances between the 4 rectangular hole bodies 610 can be equal or unequal, as long as the positions of these distances can exactly cover the tail of the previous hole region 300 and the head of the next hole region 300. And Figure 4 the right edge of the photomask in covers the right end of the rightmost hole region 300, and the left edge of the photomask covers the left end of the leftmost hole region 300. Of course, for segmented strip gate cells with other numbers of hole regions 300, when performing the implantation of the N+ emitter with this design, the structure of the photomask is similar and will not be elaborated here.

[0054] In one embodiment, when performing the implantation of the N+ emitter, the position of each hole body 610 of the photomask 600 corresponds to one or more complete hole regions 300 respectively, the position of the spacing 620 between the hole bodies corresponds to one or more complete hole regions 300 respectively, and the portions 630 of the head and tail hole bodies to the edge of the photomask also correspond to one or more complete hole regions 300 respectively. In this design, there are independent FRD regions and IGBT regions, and the two regions are continuously distributed.

[0055] For example, referring to Figure 5 as shown in Figure 5 the split bar gate cell in has 4 hole regions 300. When implanting the N+ emitter, a photomask 600 with 1 rectangular hole body 610 is used. Then, the 1 hole body 610 on the photomask 600 corresponds to 2 complete hole regions 300 respectively. The right edge of the photomask covers the rightmost complete hole region 300, and the left edge of the photomask covers the leftmost complete hole region 300. Of course, in other embodiments, the hole body 610 on the photomask 600 can also correspond to only 1 complete hole region 300. The design method is similar and will not be elaborated here.

[0056] In one embodiment, when performing the implantation of the N+ emitter, the position of each hole body 610 of the photomask 600 corresponds to the middle of one of the hole regions 300 respectively. The spacing 620 between the hole bodies includes a first spacing and a second spacing. Among them, the position of the first spacing corresponds to the tail of the previous hole region 300 and the head of the next hole region 300, and the position of the second spacing corresponds to a complete hole region 300 and the heads and tails of the hole regions 300 adjacent to the hole region 300 before and after it. The portions 630 of the head and tail hole bodies to the edge of the photomask correspond to the head or tail of one hole region 300 respectively. In this design, there are independent FRD regions and IGBT regions, and the two regions are alternately distributed.

[0057] For example, referring to Figure 6 as shown in Figure 6The split bar gate cell therein has 4 hole regions 300. During the N+ emitter implantation, a photomask 600 with 3 rectangular apertures 610 is used. The 3 apertures 610 on the photomask 600 respectively correspond to the middle positions of 3 of the hole regions 300. In the structure of this photomask 600, the spacings between the 3 rectangular apertures 610 are not equal. Among them, the spacing between the first rectangular aperture and the second rectangular aperture from left to right is larger, covering a complete hole region 300 and the tails and heads of the hole regions 300 adjacent to the front and back of this hole region 300, while the spacing between the second rectangular aperture and the third rectangular aperture from left to right is smaller, only covering the tail of the previous hole region 300 and the head of the subsequent hole region 300. And Figure 6 the right edge of the photomask in covers the right end of the rightmost hole region 300, and the left edge of the photomask covers the left end of the leftmost hole region 300. Of course, for split bar gate cells with other numbers of separating bars, when performing the implantation of the N+ emitter with this kind of design, the structure of the photomask is similar and will not be elaborated here.

[0058] In one embodiment, in order to further reduce VF, the total length range of the cell can be designed to be 10 - 1000 μm.

[0059] In one embodiment, in order to further reduce VF, the total width range of the cell can be designed to be 1 - 100 μm. And the gate width between the hole regions 300 should be smaller so that the adjacent P-channels under the polysilicon can be combined together, thus not conducting current.

[0060] This application also provides an RC-IGBT chip. The RC-IGBT cells in this RC-IGBT chip are prepared by the method described in any of the above embodiments. And, as shown in Figure 7 reference , multiple RC-IGBT cells are arranged in an array in the active region of this RC-IGBT chip. Regarding the technical effects brought by the relevant structure of this RC-IGBT chip, they are the same as those described when preparing the RC-IGBT cells above and will not be elaborated here.

[0061] In summary, a method for preparing an RC-IGBT cell and an RC-IGBT chip provided by this application, by segmenting the bar gate, reasonably arranging the position of the N+ emitter in the cell by using a photomask with a preset structure, enabling the diode part not short-circuited by the channel to enter the conductivity modulation state first, can effectively reduce VF and optimize VF-shift.

[0062] The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. For those skilled in the art, various changes and modifications can be made to the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure. Although the disclosed embodiments of the present disclosure are as above, the content is only an embodiment adopted for the convenience of understanding the present disclosure and is not used to limit the present disclosure. Any person skilled in the art within the technical field to which the present disclosure pertains can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the protection scope of the present disclosure shall still be subject to the scope defined by the appended claims.

Claims

1. A method for fabricating an RC-IGBT cell, characterized in that, the method comprises: processing a semiconductor substrate and forming a gate composed of an oxide layer and polysilicon thereon; etching a plurality of hole regions in the middle of the gate; each of the hole regions includes a first etched region and a second etched region distributed around the first etched region; wherein, the first etched region is a hole etched into the semiconductor substrate, and the second etched region is a hole etched into the polysilicon layer; injecting N+ emitters in the hole regions through a photomask with a preset structure, wherein the region where the N+ emitters are injected is the IGBT region, and the region where the N+ emitters are not injected is the FRD region; the photomask includes: a plate body and a plurality of hole bodies arranged on the plate body; wherein, the hole bodies are arranged in sequence along the length direction of the gate, and the positions of the hole bodies correspond one-to-one to the positions of the IGBT regions.

2. The fabrication method according to claim 1, characterized in that, the number of the hole regions is at least two.

3. The fabrication method according to claim 1, characterized in that, when injecting the N+ emitters, the position of each hole body of the photomask corresponds to one of the hole regions respectively, and the aperture of each hole body is smaller than the length of the corresponding hole region, the spacing positions between the hole bodies correspond to the tail of the previous hole region and the head of the next hole region, and the positions of the head and tail hole bodies to the edge of the photomask correspond to the head or tail of a hole region respectively.

4. The fabrication method according to claim 1, characterized in that, when injecting the N+ emitters, the position of each hole body of the photomask corresponds to one or more complete hole regions respectively, the spacing positions between the hole bodies correspond to one or more complete hole regions respectively, and the positions of the head and tail hole bodies to the edge of the photomask also correspond to one or more complete hole regions respectively.

5. The fabrication method according to claim 1, characterized in that, when injecting the N+ emitters, the position of each hole body of the photomask corresponds to the middle of one of the hole regions respectively, the spacing between the hole bodies includes a first spacing and a second spacing, wherein, the position of the first spacing corresponds to the tail of the previous hole region and the head of the next hole region, the position of the second spacing corresponds to a complete hole region and the heads and tails of the hole regions adjacent to the hole region before and after it, and the positions of the head and tail hole bodies to the edge of the photomask correspond to the head or tail of a hole region respectively.

6. The fabrication method according to claim 1, characterized in that, the total length range of the cell is 10 - 1000 μm.

7. The fabrication method according to claim 1, characterized in that, the total width range of the cell is 1 - 100 μm.

8. An RC-IGBT chip, characterized in that, RC-IGBT cells fabricated based on the method according to any one of claims 1 - 7 are arranged in an array in the active region of the chip.

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