A memory chip packaging method and structure

Abstract

The application discloses a Memory chip packaging method and structure, a non-functional structure layer is generated by extending in the width direction of the long strip-shaped chip, support bumps are arranged at the bottom of the non-functional structure layer, the support bumps formed by the array are consistent with the height of the functional bumps at the bottom of the long strip-shaped chip, the long strip-shaped chip is supported by the support bumps and the functional bumps, then the long strip-shaped chip with the non-functional structure layer is attached to the pins of the substrate by the flip chip method, the long strip-shaped chip, the support bumps at the bottom of the non-functional structure layer and the pins of the substrate are simultaneously soldered by reflow soldering, and the long strip-shaped chip is integrally packaged and formed, the support bumps are soldered with the pins, the packaging stress is dispersed to the support bumps on the non-functional structure layer, the functional bumps are prevented from falling off due to stress, the influence of the stress on the functional bumps at the bottom of the long strip-shaped chip is greatly reduced, and the mounting stability of the long strip-shaped chip structure is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of packaging, and relates to a method for increasing support of a Memory chip to reduce packaging stress, in particular to a Memory chip packaging method and structure. BACKGROUND

[0002] With the rapid development of electronic information technology, the demand for storage chips is increasing in AI intelligence, Internet of Things and high-performance processor products, and the proportion of storage chip shipments in consumer electronic products is increasing year by year. With the increasing integration of chips, the size of storage chips is gradually increasing, and due to the special design of storage chips, that is, the chip is generally in the form of a long strip, the traditional flip chip technology has no technical difficulties in packaging long strip-shaped chips. Compared with the traditional wire bonding technology, the flip chip technology has great advantages in terms of electrical signal transmission, heat dissipation, signal crosstalk, ultra-thin and ultra-small packaging size and manufacturing cycle. Therefore, the introduction of flip chip packaging for storage chips has become a trend. However, for flip chip packaging technology, the influence of storage chip packaging stress is significantly increased, which causes stress on the chip, thereby reducing the reliability and yield of the product. SUMMARY

[0003] The purpose of the present application is to provide a Memory chip packaging method and structure to overcome the shortcomings of the prior art. The present application reduces the influence of packaging stress by adding non-functional bumps for support on the extension surface of the long strip-shaped chip, thereby increasing the product reliability and yield.

[0004] A Memory chip packaging method, comprising the following steps:

[0005] Generating a non-functional structure layer in the width direction of the long strip-shaped chip, supporting bumps on the bottom of the non-functional structure layer, the supported bumps formed by the array are consistent in height with the functional bumps on the bottom of the long strip-shaped chip, then the long strip-shaped chip with the extended non-functional structure layer is attached to the pins of the substrate by flip chip method, and the long strip-shaped chip and the supported bumps on the bottom of the non-functional structure layer are simultaneously soldered to the pins of the substrate by reflow soldering, thereby completing the packaging of the long strip-shaped chip.

[0006] Further, the non-functional structure layer is generated in the width direction of the long strip-shaped chip, and the overall width of the long strip-shaped chip in the original width direction after extension is not greater than 1.5 times the original length of the long strip-shaped chip.

[0007] Further, the non-functional structure layer is generated in the width direction of the long strip-shaped chip, and the overall width of the long strip-shaped chip in the original width direction after extension is equal to the original length of the long strip-shaped chip.

[0008] Further, the non-functional structure layer is generated in the width direction of the long strip-shaped chip by wafer manufacturing process.

[0009] Further, the thickness of the non-functional structure layer generated by extending in the width direction of the long strip-shaped chip is greater than the thickness of the long strip-shaped chip, and the upper surface of the long strip-shaped chip is flush with the upper surface of the non-functional structure layer.

[0010] Further, the non-functional structure layer is connected to the support bumps at the bottom thereof through the chip surface protection layer.

[0011] A Memory chip packaging structure is fixed to the non-functional structure layers on both sides of the long strip-shaped chip, the bottom of the non-functional structure layer is arrayed with support bumps, the support bumps at the bottom of the non-functional structure layer are in the same height as the functional bumps at the bottom of the long strip-shaped chip, and the support bumps at the bottom of the functional structure layer and the functional bumps at the bottom of the long strip-shaped chip are both welded to the pins on the substrate.

[0012] Further, the thickness of the non-functional structure layer generated by extending in the width direction of the long strip-shaped chip is greater than the thickness of the long strip-shaped chip, and the upper surface of the long strip-shaped chip is flush with the upper surface of the non-functional structure layer.

[0013] Further, the width of the long strip-shaped chip and the width of the non-functional structure layers on both sides thereof are not greater than 1.5 times the length of the long strip-shaped chip.

[0014] Further, the non-functional structure layer is connected to the support bumps at the bottom thereof through the chip surface protection layer.

[0015] Compared with the prior art, the present application has the following beneficial technical effects:

[0016] The present application is a Memory chip packaging method, which generates a non-functional structure layer by extending in the width direction of the long strip-shaped chip to form an integral whole with the long strip-shaped chip, then arraying support bumps at the bottom of the non-functional structure layer, the support bumps formed by the arraying are in the same height as the functional bumps at the bottom of the long strip-shaped chip, and can be simultaneously welded to avoid interference caused by the process or the short distance; the long strip-shaped chip as a whole is supported by the support bumps cooperating with the functional bumps, then the long strip-shaped chip extended with the non-functional structure layer is attached to the pins of the substrate by the flip chip method, and the long strip-shaped chip and the support bumps at the bottom of the non-functional structure layer are simultaneously welded to the pins of the substrate by reflow soldering, so as to be integrally packaged and formed, the support bumps are welded to the pins, the packaging stress is dispersed to the support bumps on the non-functional structure layer, the functional bumps are prevented from falling off due to the stress, the influence of the stress on the functional bumps at the bottom of the long strip-shaped chip is greatly reduced, and the installation stability of the long strip-shaped chip structure is improved.

[0017] Further, the long strip-shaped chip is extended in the width direction to form a non-functional structure layer, and the overall width of the long strip-shaped chip in the original width direction after the extension is equal to the original length of the long strip-shaped chip, so that stable support is formed in the length and width directions of the long strip-shaped chip, and the influence of excessive stress is avoided.

[0018] A Memory chip packaging structure is provided, in which a non-functional structure layer is fixedly arranged on both sides of the width of the long strip-shaped chip, the long strip-shaped chip is supported as a whole by support bumps cooperating with functional bumps, the support bumps are welded with pins, and the packaging stress is dispersed to the support bumps on the non-functional structure layer, so that the functional bumps are prevented from falling off due to stress, and the influence of stress on the functional bumps at the bottom of the long strip-shaped chip is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic view of the cross section of the long strip-shaped chip and the extended chip bump support in the embodiment of the present application.

[0020] Figure 2 is a layout view of the long strip-shaped chip and the extended chip bump support in the embodiment of the present application.

[0021] In the figure, 1 is a long strip-shaped chip, 2 is a functional bump of the long strip-shaped chip, 3 is a non-functional area of the long strip-shaped chip extending to the right, 4 is a first column of support bumps of the non-functional area, 5 is a second column of support bumps of the non-functional area, 6 is an edge support bump of the non-functional area, 7 is a non-functional area of the long strip-shaped chip extending to the left, 8 is a substrate, 9 is a pin of the substrate, 10 is a chip surface protection layer, and 11 is a circuit metal layer of the long strip-shaped chip. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the protection scope of the present application.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] The present invention will now be described in further detail with reference to the accompanying drawings:

[0025] A memory chip packaging method involves extending the length of a rectangular chip to the size of a square chip on both sides, and creating non-functional bumps on the extended chip for support. The packaging stress is then distributed to these non-functional bumps, reducing the stress on the functional bumps of the memory chip. The stress primarily originates from the high and low temperature thermal shock during reflow soldering, the impact force of the molding injection pressure, and the warpage stress after molding. The method specifically includes the following steps:

[0026] For packaging elongated chips, a non-functional structure layer is extended along the width of the chip. Support bumps are arrayed at the bottom of this non-functional structure layer. The height of these support bumps is the same as the height of the functional bumps at the bottom of the chip, meaning they are in the same plane. The elongated chip with the extended non-functional structure layer is then bonded to the leads of a substrate using a flip-chip method. Reflow soldering is then used to simultaneously solder the elongated chip and the support bumps at the bottom of its non-functional structure layer to the leads of the substrate, completing the packaging of the elongated chip. The packaging of the elongated chip generates stress... The stress mainly comes from the high and low temperature thermal shock during reflow soldering, the pressure impact of molding injection, and the warping stress after molding. Because the long side of the elongated chip is relatively long, the solder joint between the bumps and the substrate pins is prone to cracking during reflow soldering, which can easily lead to significant warping of the long side of the chip body. By generating a non-functional structure layer on each side of the elongated chip in the width direction, forming a whole with the elongated chip, and then setting support bumps at the bottom of the non-functional structure layer, the entire elongated chip is supported by the support bumps, distributing the packaging stress to the support bumps on the non-functional structure layer, which greatly reduces the stress on the bumps at the bottom of the elongated chip.

[0027] The memory chip package structure is formed using the methods described above, such as... Figure 1 , Figure 2As shown, the thickness of the non-functional structure layer generated by extending the width of the elongated chip is greater than the thickness of the elongated chip. The upper surface of the elongated chip is flush with the upper surface of the non-functional structure layer. The non-functional structure layer is used to support the elongated chip at the bottom, and the stress is dispersed on the non-functional structure layer, which can effectively prevent the elongated chip from warping.

[0028] For the packaging of a long strip chip, non-functional structural layers are generated on both sides of the width direction of the long strip chip. The width of the non-functional structural layers generated on both sides of the width direction of the long strip chip is the same. Non-functional structural layers are extended in the width direction of the long strip chip. After the extension, the overall width of the long strip chip in its original width direction is not greater than 1.5 times the original length of the long strip chip. That is, the sum of the width of the extended structural layer and the width of the long strip chip is not greater than 1.5 times the original length of the long strip chip.

[0029] To improve the packaging accuracy, efficiency, and economy of elongated chips, the surface structure of the elongated chip is made square after extension. That is, the length of the non-functional structure layer is extended on both sides of the original elongated chip, and the elongated chip becomes a square chip after extension; the extension length on both sides of the elongated chip is the same.

[0030] like Figure 1 , Figure 2 As shown, a non-functional region 7 extending to the left and a non-functional region 3 extending to the right of the elongated chip are formed on both sides of the elongated chip. The non-functional structural layers formed by the extension on both sides of the elongated chip are formed by wafer manufacturing process. The elongated chip 1, the non-functional region 7 extending to the left of the elongated chip and the non-functional region 3 extending to the right of the elongated chip are combined into a whole.

[0031] Multiple sets of support bumps are arrayed at the bottom of the non-functional area 7 extending to the left of the elongated chip and the non-functional area 3 extending to the right of the elongated chip to form a stable support structure. Pins corresponding to the support bumps are provided on the substrate, and each support bump contacts a pin. The support bumps are soldered to the pins by reflow soldering.

[0032] Depending on the chip structure of different lengths, different numbers of support bumps are set. For chip structures with an aspect ratio greater than 2, two rows of support bumps are arrayed at the bottom of the single-sided extended structural layer; for example... Figure 2 As shown, on the non-functional area extending to the left of the elongated chip, there are arrays of the first column of support bumps 4, the second column of support bumps 5, and the edge support bumps 6. The first column of support bumps 4, the second column of support bumps 5, and the edge support bumps 6 are arranged at intervals, and the support bumps serve to support the chip.

[0033] The non-functional structure layer is connected to the support bumps at its bottom through a chip surface protective layer 10. The chip surface protective layer 10 serves as a buffer layer and adhesive layer, improving the connection stability between the support bumps and the non-functional structure layer. The elongated memory chip functional bumps 2 at the bottom of the elongated chip are distributed at the bottom edge of the elongated chip. The elongated memory chip circuit metal layer 11 at the bottom of the elongated chip generates the elongated chip functional bumps 2 through a bump fabrication process. The elongated chip functional bumps 2 are soldered to the substrate pins 9.

[0034] This application extends non-functional structural layers on both sides of the width of the elongated chip to form an integral structure. Then, by using support bumps and pins on the substrate to cooperate with the connection pins at the bottom of the elongated chip, a stable support structure is formed. The structural packaging stress is distributed to the support bumps at the bottom of the non-functional structural layers, which greatly reduces the stress on the functional bumps at the bottom of the elongated chip. This avoids the problem of cracks in the welding junction between the functional bumps and the substrate pins caused by high and low temperature thermal shock during reflow soldering, molding pressure, and warping stress after molding, as well as the problem of warping of the long side of the elongated memory chip caused by stress.

Claims

1. A method of packaging a Memory chip, characterized by, The method comprises the following steps: The long strip-shaped chip is pasted onto the pins of the substrate base through the flip chip method, the long strip-shaped chip and the support bumps at the bottom of the non-functional structure layer are simultaneously soldered to the pins of the substrate base through reflow soldering, and the packaging of the long strip-shaped chip is completed.

2. The method of claim 1, wherein the Memory chip package is a BGA package. The thickness of the non-functional structure layer generated in the width direction of the long strip-shaped chip is greater than the thickness of the long strip-shaped chip, and the upper surface of the long strip-shaped chip is flush with the upper surface of the non-functional structure layer.

3. The method of claim 1, wherein the Memory chip package is a BGA package. The non-functional structure layer and the support bumps at the bottom thereof are connected through a chip surface protection layer.

4. A Memory chip package structure based on the method of any one of claims 1 to 3, characterized in that, The long strip-shaped chip is pasted onto the pins of the substrate base through the flip chip method, the long strip-shaped chip and the support bumps at the bottom of the non-functional structure layer are simultaneously soldered to the pins of the substrate base through reflow soldering, and the packaging of the long strip-shaped chip is completed.

5. The Memory chip package structure of claim 4, wherein, The thickness of the non-functional structure layer generated in the width direction of the long strip-shaped chip is greater than the thickness of the long strip-shaped chip, and the upper surface of the long strip-shaped chip is flush with the upper surface of the non-functional structure layer.

6. The Memory chip package structure of claim 4, wherein, The width of the long strip-shaped chip and the width of the non-functional structure layer on both sides thereof are not greater than 1.5 times the length of the long strip-shaped chip.

7. The Memory chip package structure of claim 4, wherein, The non-functional structure layer and the support bumps at the bottom thereof are connected through a chip surface protection layer. The long strip-shaped chip is pasted onto the pins of the substrate base through the flip chip method, the long strip-shaped chip and the support bumps at the bottom of the non-functional structure layer are simultaneously soldered to the pins of the substrate base through reflow soldering, and the packaging of the long strip-shaped chip is completed.

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