An SOI substrate and a manufacturing method thereof, an SOI substrate having an isolation structure

Abstract

This application provides an SOI substrate and its manufacturing method, and an SOI substrate with an isolation structure. The method includes: providing a substrate, the substrate including a substrate and an insulating layer formed on the substrate; etching the insulating layer to form a first trench in the insulating layer exposing the substrate; depositing an amorphous material layer on the insulating layer, the amorphous material layer contacting the substrate through the first trench; and performing laser annealing on the amorphous material layer to transform the amorphous material layer into an epitaxial layer. In the SOI substrate manufacturing method provided in this application, the use of laser annealing can quickly transform the amorphous material layer into an epitaxial layer, effectively reducing the thermal budget. Furthermore, the above SOI substrate manufacturing method does not require ion implantation, which simplifies the manufacturing process and reduces manufacturing costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to an SOI substrate and its manufacturing method, and an SOI substrate with an isolation structure. Background Technology

[0002] Silicon on Insulator (SOI) substrates are used for integrated circuit manufacturing. Compared to the widely used bulk silicon substrates, SOI substrates offer many advantages: integrated circuits fabricated on SOI substrates have lower parasitic capacitance, higher integration density, less short-channel effect, and higher speed. Furthermore, they can achieve dielectric isolation of components within the integrated circuit, eliminating the parasitic latch-up effect present in bulk silicon integrated circuits. Typically, an SOI substrate consists of three layers: a top silicon layer for forming transistor devices, an insulating layer, and a silicon substrate that provides mechanical support.

[0003] Although SOI substrates offer advantages in device performance such as reduced parasitic capacitance, increased operating speed, elimination of latch-up effects, and reduced leakage current, existing SOI substrate manufacturing processes are complex, time-consuming, and costly. Summary of the Invention

[0004] In view of this, the present application provides an SOI substrate and its manufacturing method, and an SOI substrate with an isolation structure, in order to solve at least one technical problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0006] In a first aspect, embodiments of this application provide a method for manufacturing an SOI substrate, the method comprising:

[0007] A substrate is provided, the substrate including a substrate and an insulating layer formed on the substrate;

[0008] The insulating layer is etched to form a first trench in the insulating layer that exposes the substrate;

[0009] An amorphous material layer is deposited on the insulating layer, and the amorphous material layer is in contact with the substrate through the first trench;

[0010] The amorphous material layer is subjected to laser annealing to transform it into an epitaxial layer.

[0011] According to one embodiment of this application, the method further includes:

[0012] A second trench is formed in the epitaxial layer to expose the substrate.

[0013] According to one embodiment of this application, the method further includes:

[0014] The second trench is filled to form an isolation structure;

[0015] Transistors are formed between the isolation structures.

[0016] According to one embodiment of this application, the second trench and the first trench are formed through the same mask plate.

[0017] According to one embodiment of this application, the laser energy density used in the laser annealing process is in the range of 0.7 to 1.2 J / cm². 2 .

[0018] According to one embodiment of this application, the laser annealing process is performed in an inert atmosphere.

[0019] According to one embodiment of this application, the substrate is a silicon substrate; the epitaxial layer is a silicon epitaxial layer.

[0020] Secondly, embodiments of this application provide an SOI substrate, the SOI substrate comprising:

[0021] A substrate, the substrate including a substrate and an insulating layer located on the substrate; a first trench is formed in the insulating layer;

[0022] An epitaxial layer is formed on the insulating layer and is in contact with the substrate through the first trench.

[0023] According to one embodiment of this application, the substrate is a silicon substrate; the epitaxial layer is a silicon epitaxial layer.

[0024] Thirdly, embodiments of this application provide an SOI substrate with an isolation structure, comprising:

[0025] The substrate includes a substrate, an insulating layer on the substrate, and an epitaxial layer on the insulating layer;

[0026] An isolation structure comprising a second trench located in a substrate and an insulating material filling the second trench; the second trench extends through the insulating layer and the epitaxial layer.

[0027] According to one embodiment of this application, the substrate is a silicon substrate; the epitaxial layer is a silicon epitaxial layer.

[0028] This application provides an SOI substrate and its manufacturing method, and an SOI substrate with an isolation structure. The method includes: providing a substrate, the substrate including a substrate and an insulating layer formed on the substrate; etching the insulating layer to form a first trench in the insulating layer exposing the substrate; depositing an amorphous material layer on the insulating layer, the amorphous material layer contacting the substrate through the first trench; and performing laser annealing on the amorphous material layer to transform the amorphous material layer into an epitaxial layer. The SOI substrate manufacturing method provided in this application, after forming the first trench exposing the substrate in the insulating layer, deposits an amorphous material layer on the insulating layer, the amorphous material layer contacting the substrate through the first trench, and performs laser annealing on the amorphous material layer, causes the amorphous material layer to crystallize from the portion in contact with the substrate, thereby transforming it into an epitaxial layer. In the above SOI substrate manufacturing method, the use of laser annealing can quickly transform the amorphous material layer into an epitaxial layer, effectively reducing the thermal budget. Furthermore, the above SOI substrate manufacturing method does not require ion implantation, which simplifies the manufacturing process and reduces manufacturing costs. Attached Figure Description

[0029] Figure 1 A schematic cross-sectional view of the substrate in the SOI substrate provided in the embodiments of this application;

[0030] Figure 2 A schematic cross-sectional view of an SOI substrate including a first trench, provided for an embodiment of this application;

[0031] Figure 3A and Figure 3B A partial top view of an SOI substrate including a first trench, provided for an embodiment of this application;

[0032] Figure 4 A schematic cross-sectional view of an SOI substrate including an amorphous material layer, provided for an embodiment of this application;

[0033] Figure 5 A schematic cross-sectional structure diagram of an SOI substrate including an epitaxial layer provided for an embodiment of this application;

[0034] Figure 6 A schematic cross-sectional view of an SOI substrate including a second trench, provided for an embodiment of this application;

[0035] Figure 7A and Figure 7B A partial top view of an SOI substrate including a second trench, provided for an embodiment of this application;

[0036] Figure 8 A schematic cross-sectional view of another SOI substrate including a second trench, provided for an embodiment of this application;

[0037] Figure 9 A schematic cross-sectional view of an SOI substrate with an isolation structure provided in an embodiment of this application;

[0038] Figure 10 A flowchart illustrating the manufacturing method of the SOI substrate provided in this application embodiment;

[0039] The figure includes: 10-substrate; 11-substrate; 12-insulating layer; H2 is the thickness of the insulating layer; 20, 201, 202-first trench; W1 is the width of the first trench; 30-amorphous material layer; H1 and H3 are the thicknesses of the amorphous material layer at different positions; 40-epitaxy layer; 50, 50', 501, 502-second trench; W2 is the width of the second trench; 601-isolation structure. Detailed Implementation

[0040] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0042] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0047] SOI technology isolates transistor components from each other by introducing an insulating layer between two silicon substrates. Currently, there are three relatively common SOI manufacturing methods.

[0048] The first SOI manufacturing method is the oxygen implantation (separation by ion-implanted oxygen, SIMOX) process. First, a milled silicon wafer is prepared, including a front and a back side. Next, the silicon wafer is heated to approximately 500°C, and oxygen ions are implanted into the interior of the silicon wafer via ion implantation to form an oxygen ion implantation layer. Finally, in an inert gas environment, heat treatment is performed at a high temperature exceeding 1300°C to transform the oxygen ion implantation layer formed inside the silicon wafer into an oxide film layer. This high-temperature heat treatment process also reduces implantation defects, thereby producing SOI.

[0049] As mentioned above, the process of fabricating SOI using the SIMOX process requires high ion implantation (IMP) energy to implant a high dose of oxygen ions. However, a large number of oxygen ions passing through the surface of the silicon wafer can damage the wafer, easily leading to the generation of high-density through-dislocations during subsequent high-temperature heat treatment. Therefore, fabricating SOI using the SIMOX process not only requires high-dose ion implantation, increasing the manufacturing cost, but also necessitates prolonged heat treatment at high temperatures, resulting in excessively long manufacturing times and even difficulty in obtaining SOI of good quality.

[0050] The second SOI manufacturing method is direct wafer bonding. First, the surface of a silicon wafer is thermally oxidized to form an oxide film. Then, this silicon wafer with the oxide film is directly bonded to another silicon wafer. Annealing can be used to enhance the bonding strength and reduce defects at the bonding interface. Finally, chemical mechanical polishing (CMP) is used to thin the wafer to the required thickness to form SOI.

[0051] As mentioned above, the process of manufacturing SOI using direct bonding technology requires prolonged heat treatment at high temperatures, which undoubtedly leads to excessively long manufacturing time for SOI.

[0052] The third SOI manufacturing method is the smart-cut process. First, a substrate wafer and a bonding wafer are prepared. Next, the bonding wafer undergoes thermal oxidation to form an oxide film layer on its surface. Then, hydrogen ions are implanted into the bonding wafer with the oxide film layer to form a hydrogen ion implantation layer parallel to its surface within the bonding wafer. Next, the substrate wafer is superimposed on the bonding wafer with the hydrogen ion implantation layer, separated by the oxide film layer, so that the substrate wafer and the bonding wafer are in contact and bonded together. Finally, a low-temperature heat treatment step is performed using the hydrogen ion implantation layer as a boundary, and high-temperature annealing is used to enhance the bonding strength between the substrate wafer and the bonding wafer. The surface of the bonding wafer is then planarized to obtain the SOI.

[0053] As mentioned above, the process of manufacturing SOI using the smart lift-off process requires high-dose hydrogen ion implantation, followed by high-temperature heat treatment to improve the bonding strength between the substrate wafer and the bonding wafer. Therefore, manufacturing SOI using the smart lift-off process not only requires high-dose ion implantation but also high-temperature heat treatment, which makes the SOI manufacturing process complex, time-consuming, and costly.

[0054] In view of this, embodiments of this application provide a method for manufacturing an SOI substrate. (See reference...) Figure 10 , Figure 10 A flowchart illustrating a method for manufacturing an SOI substrate according to an embodiment of this application. Figure 10 As shown, the method includes:

[0055] S1001. A substrate is provided, the substrate including a substrate and an insulating layer formed on the substrate.

[0056] refer to Figure 1 , Figure 1 This is a schematic cross-sectional view of the substrate in an SOI substrate provided in an embodiment of this application. (See attached diagram.) Figure 1 As shown, a substrate 10 is provided, which includes a substrate 11 and an insulating layer 12 located on the substrate 11.

[0057] The substrate can be a single-element semiconductor material substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, etc. Here, the substrate is the bottom layer structure of SOI, used to provide mechanical support for the two layers above it. Therefore, in the three-layer structure of SOI, the substrate has the largest thickness. The technical solution of this application does not limit the shape and size of the substrate. The substrate can be circular, with dimensions of 100nm, 200nm, 300nm, or larger. The substrate can also be square, with dimensions of 100nm*100nm, 200nm*200nm, 300nm*300nm, or larger.

[0058] The insulating layer can be made of silicon dioxide, silicon nitride, aluminum oxide, or other insulating materials, or combinations thereof. In one embodiment of this application, the insulating layer can be made of silicon dioxide, deposited using one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to form the insulating layer. In another embodiment of this application, the insulating layer can be made of silicon dioxide, formed by oxidizing the substrate using an oxidation method. The insulating layer is primarily used to achieve mutual isolation between transistor components, and its thickness can range from 900 to 1100 nm.

[0059] S1002, Etch the insulating layer to form a first trench in the insulating layer that exposes the substrate.

[0060] refer to Figure 2 , Figure 2 A schematic cross-sectional view of an SOI substrate including a first trench, provided for an embodiment of this application. (See attached diagram.) Figure 2 As shown, the insulating layer 12 is etched to form a first trench 20 exposing the substrate 11. The width of the first trench 20 is W1, and the thickness of the insulating layer 12 is the same as the depth of the first trench 20, which is H2. The first trench penetrates both the upper and lower surfaces of the insulating layer, with its opening facing upwards. The bottom surface of the first trench is formed of the substrate material, and the sides of the first trench are formed of the insulating layer material.

[0061] In some embodiments of this application, the etching of the insulating layer stops on the substrate, i.e., the substrate serves as an etching stop layer for etching the insulating layer.

[0062] In some embodiments of this application, the first trench is a rectangular groove that penetrates the insulating layer, and the insulating layer has a plurality of rectangular grooves arranged in parallel to each other.

[0063] refer to Figure 3A , Figure 3A A partial top view of an SOI substrate including a first trench, provided for an embodiment of this application. (See attached image.) Figure 3A As shown, the first trench 201 penetrates the upper and lower surfaces of the insulating layer 12, and the first trench 201 penetrates two opposite sides of the insulating layer 12. The insulating layer 12 has a plurality of first trenches 201 arranged in parallel with each other. Figure 3A This is a partial top view of the first trench. Figure 2 Can be used as along Figure 3AA schematic diagram of the cross-sectional structure along the AA' direction. The dimensions of the first groove in this application are not limited and can be set according to the needs of SOI.

[0064] In some embodiments of this application, the first trench is a through hole penetrating the insulating layer, and the insulating layer has a plurality of through holes distributed in an array.

[0065] refer to Figure 3B , Figure 3B A partial top view of an SOI substrate including a first trench, provided for an embodiment of this application. (See attached image.) Figure 3B As shown, the first trench 202 is a through hole that penetrates the upper and lower surfaces of the insulating layer, and the through holes are distributed in an array in the insulating layer. Figure 3B This is a partial top view of the first trench. Figure 2 It can also be used as a line Figure 3B A schematic diagram of the cross-sectional structure along the BB' direction. The technical solution of this application does not limit the size of the through-hole; it can be set according to the needs of SOI.

[0066] S1003. An amorphous material layer is deposited on the insulating layer, and the amorphous material layer is in contact with the substrate through the first trench.

[0067] refer to Figure 4 , Figure 4 A schematic cross-sectional view of an SOI substrate including an amorphous material layer, provided for an embodiment of this application. (See attached diagram.) Figure 4 As shown, an amorphous material layer 30 is deposited on the insulating layer 12, and the amorphous material layer 30 contacts the substrate 11 through a first trench 20. In other words, the amorphous material layer fills the first trench, and the upper surface of the amorphous material layer is higher than the upper surface of the insulating layer. The material of the amorphous material layer may include amorphous silicon (α-Si). In one embodiment of this application, the material of the amorphous material layer may be amorphous silicon, and the amorphous silicon may be deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof, to form the amorphous material layer. The thickness of the amorphous material layer may range from 10 to 200 nm.

[0068] S1004. The amorphous material layer is subjected to laser annealing to transform the amorphous material layer into an epitaxial layer.

[0069] refer to Figure 5 , Figure 5 This is a schematic cross-sectional view of an SOI substrate including an epitaxial layer, provided for an embodiment of this application. Figure 5As shown, the amorphous material layer 30 undergoes laser annealing to transform it into an epitaxial layer 40. Specifically, laser annealing utilizes an excimer laser to uniformly irradiate the amorphous material layer located on the insulating layer, generating a large amount of energy in an extremely short time. This causes the amorphous material layer to melt at high temperatures, and the molten amorphous material then recrystallizes from the substrate to become an epitaxial layer. Because the laser is pulsed, with laser pulses on the order of tens of nanoseconds, the total action time of the laser annealing process is very short, thus enabling the conversion of the amorphous material layer into an epitaxial layer while minimizing damage to the substrate. The most critical process parameter in laser annealing is the laser energy density. Only when the laser energy density reaches its optimal value can the crystal quality of the epitaxial layer be improved. Here, the crystal quality can be characterized by the size and uniformity of the crystal grains.

[0070] In actual production, the crystallization quality is affected not only by the laser energy density but also by the thickness of the amorphous material layer. Different locations within the same amorphous material layer have different thicknesses, requiring different laser energy values. Using different laser energy values ​​for amorphous material layers of varying thicknesses can improve the crystallization quality.

[0071] Still referencing Figure 4 H1 and H2 represent the thicknesses of the amorphous material layer at different locations. Specifically, the thickness of the amorphous material layer 30 above the first trench 20 is H3, and the thickness of the amorphous material layer 30 above the insulating layer 12 is H1. Different laser energy values ​​can be selected based on the thickness of the amorphous material layer at different locations. Then, a laser with the corresponding energy value is used to irradiate the corresponding locations on the amorphous material layer, making the crystallization degree at different locations of the amorphous material layer more uniform. This results in uniform grain size at different locations after the amorphous material layer is converted into an epitaxial layer, thereby obtaining a high-quality epitaxial layer.

[0072] Considering the thickness difference (H3-H1) at different locations of the amorphous material layer, where H2 represents the thickness of the insulating layer (which is relatively small), it means the thickness difference at different locations of the amorphous material layer is not significant. Therefore, high-quality epitaxial layers can be obtained by irradiating different locations of the amorphous material layer with the same laser energy.

[0073] Typically, a laser annealing apparatus includes a laser generator located above and a process chamber located below. The laser generated by the laser generator anneals the amorphous material layer to be treated within the process chamber. The amorphous material layer to be treated is situated on a substrate, which is located on a worktable capable of moving in three-dimensional space. The movement of the worktable drives the movement of the substrate to complete the annealing of the amorphous material layer. The process chamber can also be connected to a gas module, allowing inert gas to be introduced into the process chamber during the laser annealing process.

[0074] The laser annealing process used in this application embodiment includes lasers generated by the laser generator, which may include, but are not limited to, argon fluoride (ArF) lasers with a wavelength of 193 nm, krypton fluoride (KrF) lasers with a wavelength of 248 nm, xenon chloride (XeCl) lasers with a wavelength of 308 nm, xenon fluoride (XeF) lasers with a wavelength of 352 nm, and YAG (Y3Al5O) lasers with a wavelength of 532 nm. 12 (Yttrium aluminum garnet crystal) laser.

[0075] In some embodiments of this application, the thickness of the epitaxial layer 40 ranges from 10 nm to 200 nm. In other embodiments, the thickness of the epitaxial layer 40 may be greater than 200 nm.

[0076] The SOI substrate manufacturing method provided in this application involves forming a first trench in an insulating layer to expose the substrate, then depositing an amorphous material layer on the insulating layer. The amorphous material layer contacts the substrate through the first trench. After laser annealing, the amorphous material layer crystallizes from the portion in contact with the substrate, thus transforming into an epitaxial layer. In the above SOI substrate manufacturing method, laser annealing can quickly transform the amorphous material layer into an epitaxial layer. More specifically, nanosecond laser annealing can be used; for example, the amorphous silicon layer can be transformed into a polycrystalline silicon layer within 250 ns, saving cycle time and effectively reducing the thermal budget. Furthermore, the above SOI substrate manufacturing method eliminates the need for ion implantation, simplifying the manufacturing process and reducing manufacturing costs.

[0077] In some embodiments of this application, the laser energy density used in the laser annealing process is in the range of 0.7–1.2 J / cm². 2 .

[0078] In some embodiments of this application, the laser annealing process is performed in an inert atmosphere. For example, the laser annealing process can be performed in a nitrogen or argon atmosphere.

[0079] In one specific embodiment of this application, the substrate is a silicon substrate; the epitaxial layer is a silicon epitaxial layer. The substrate includes a silicon substrate and an insulating layer located on the silicon substrate. The insulating layer is etched to form a first trench exposing the silicon substrate. An amorphous silicon layer is deposited on the insulating layer, and the amorphous silicon layer contacts the silicon substrate through the first trench. The amorphous silicon layer is then subjected to laser annealing to transform it into an epitaxial layer. In this case, the epitaxial layer can be a monocrystalline silicon layer or a polycrystalline silicon layer.

[0080] In some embodiments of this application, the method further includes:

[0081] The epitaxial layer is etched to form a second trench in the epitaxial layer that exposes the substrate.

[0082] refer to Figure 6 , Figure 6 A schematic cross-sectional view of an SOI substrate including a second trench, provided for an embodiment of this application. (See attached diagram.) Figure 6 As shown, the epitaxial layer 40 is etched to form a second trench 50 exposing the substrate 11 in the epitaxial layer 40. At this time, the width of the second trench 50 is W1 and the depth of the second trench 50 is H3. The second trench penetrates the upper and lower surfaces of the epitaxial layer and the insulating layer, the opening of the second trench faces upward, the bottom surface of the second trench is formed by the substrate material, and the side surface of the second trench is formed by the epitaxial layer material and the insulating layer material.

[0083] In some embodiments of this application, the etching of the epitaxial layer and the insulating layer is stopped on the substrate, that is, the substrate serves as an etching stop layer for etching the epitaxial layer and the insulating layer.

[0084] In some embodiments of this application, the second trench and the first trench are formed using the same mask. In other words, the dimensions of the first trench and the second trench are the same. For example, the width of the first trench is the same as the width of the second trench.

[0085] Still referencing Figure 6 The width of the second trench is the same as the width of the first trench, both being W1. The same mask can be used to etch both the first and second trenches. This saves on the cost of forming the SOI substrate.

[0086] In some embodiments of this application, the second trench is a rectangular trench that penetrates the insulating layer, and the epitaxial layer has a plurality of rectangular trenches arranged in parallel to each other.

[0087] refer to Figure 7A , Figure 7A A partial top view of an SOI substrate including a second trench, provided for an embodiment of this application. (See attached image.) Figure 7A As shown, the second trench 501 penetrates the upper and lower surfaces of the epitaxial layer and the insulating layer, and the second trench 501 penetrates the two opposite sides of the epitaxial layer and the insulating layer. The epitaxial layer 40 has a plurality of second trenches 501 arranged in parallel with each other. Figure 7A This is a partial top view of the second trench. Figure 6 Can be used as along Figure 7A A schematic diagram of the cross-sectional structure along the CC' direction. The dimensions of the second trench are not limited in this application and can be set according to the needs of SOI.

[0088] In some embodiments of this application, the second trench is a through-hole penetrating the insulating layer, and the epitaxial layer has a plurality of through-holes distributed in an array.

[0089] refer to Figure 7B , Figure 7B A partial top view of an SOI substrate including a second trench, provided for an embodiment of this application. (See attached image.) Figure 7B As shown, the second trench 502 is a through-hole that penetrates the upper and lower surfaces of the epitaxial layer and the insulating layer, and the through-hole is distributed in an array in the epitaxial layer. Figure 7B This is a partial top view of the second trench. Figure 6 It can also be used as a line Figure 7B A schematic diagram of the cross-sectional structure along the DD' direction. The technical solution of this application does not limit the size of the through-hole; it can be set according to the needs of SOI.

[0090] In some other embodiments of this application, the dimensions of the first trench are different from those of the second trench. Specifically, the width of the first trench is different from the width of the second trench.

[0091] refer to Figure 8 , Figure 8 A schematic cross-sectional view of another SOI substrate including a second trench, provided as an embodiment of this application. (See attached diagram.) Figure 8 As shown, the epitaxial layer 40 is etched to form a second trench 50' exposing the substrate 11 in the epitaxial layer 40. The width of the second trench 50' is W2, and the depth of the second trench 50' is H3. Here, the width W2 of the second trench is greater than the width W1 of the first trench. The second trench penetrates the upper and lower surfaces of the epitaxial layer and the insulating layer, with the opening of the second trench facing upwards. The bottom surface of the second trench is formed by the substrate material, and the sides of the second trench are formed by the epitaxial layer material and the insulating layer material.

[0092] In some embodiments of this application, the method further includes: filling the second trench to form an isolation structure; and forming transistors between the isolation structures.

[0093] refer to Figure 9 , Figure 9 This is a schematic cross-sectional view of an SOI substrate with an isolation structure provided in an embodiment of this application. Figure 9 As shown, the second trench 50 is filled to form an isolation structure 601, and transistors are formed between the isolation structures 601. More specifically, the transistors are located on an insulating layer and within an epitaxial layer. Isolation between adjacent transistors can be achieved through the isolation structures and insulating layers, effectively reducing current leakage.

[0094] This application embodiment also provides an SOI substrate, the SOI substrate comprising:

[0095] A substrate, the substrate including a substrate and an insulating layer located on the substrate; a first trench is formed in the insulating layer;

[0096] An epitaxial layer is formed on the insulating layer and is in contact with the substrate through the first trench.

[0097] Still referencing Figure 5 The SOI substrate includes: a substrate 10, which includes a substrate 11 and an insulating layer 12 located on the substrate 11; a first trench 20 is formed in the insulating layer 12; and an epitaxial layer 40, which is formed on the insulating layer 12 and contacts the substrate 11 through the first trench 20.

[0098] In one specific embodiment of this application, the substrate is a silicon substrate; the epitaxial layer is a silicon epitaxial layer.

[0099] This application embodiment also provides an SOI substrate with an isolation structure, including:

[0100] The substrate includes a substrate, an insulating layer on the substrate, and an epitaxial layer on the insulating layer;

[0101] An isolation structure comprising a second trench located in a substrate and an insulating material filling the second trench; the second trench extends through the insulating layer and the epitaxial layer.

[0102] Still referencing Figure 9The SOI substrate includes: a substrate 10, which includes a substrate 11, an insulating layer 12 on the substrate 11, and an epitaxial layer 40 on the insulating layer 12; and an isolation structure 601, which includes a second trench 50 in the substrate and an insulating material filling the second trench 50; the second trench 50 penetrates the insulating layer 12 and the epitaxial layer 40.

[0103] In one specific embodiment of this application, the substrate is a silicon substrate; the epitaxial layer is a silicon epitaxial layer.

[0104] This application provides an SOI substrate and its manufacturing method, and an SOI substrate with an isolation structure. The method includes: providing a substrate, the substrate including a substrate and an insulating layer formed on the substrate; etching the insulating layer to form a first trench in the insulating layer exposing the substrate; depositing an amorphous material layer on the insulating layer, the amorphous material layer contacting the substrate through the first trench; and performing laser annealing on the amorphous material layer to transform the amorphous material layer into an epitaxial layer. The SOI substrate manufacturing method provided in this application, after forming the first trench exposing the substrate in the insulating layer, deposits an amorphous material layer on the insulating layer, the amorphous material layer contacting the substrate through the first trench, and performs laser annealing on the amorphous material layer, causes the amorphous material layer to crystallize from the portion in contact with the substrate, thereby transforming it into an epitaxial layer. In the above SOI substrate manufacturing method, the use of laser annealing can quickly transform the amorphous material layer into an epitaxial layer, effectively reducing the thermal budget. Furthermore, the above SOI substrate manufacturing method does not require ion implantation, which simplifies the manufacturing process and reduces manufacturing costs.

[0105] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0106] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method of manufacturing an SOI substrate, characterized by, The method includes: A substrate is provided, the substrate including a substrate and an insulating layer formed on the substrate; The insulating layer is etched to form a first trench in the insulating layer that exposes the substrate; An amorphous material layer is deposited on the insulating layer, and the amorphous material layer is in contact with the substrate through the first trench; The amorphous material layer is subjected to laser annealing to transform it into an epitaxial layer. The epitaxial layer is etched to form a second trench exposing the substrate, the second trench penetrating the insulating layer and the epitaxial layer; The second trench is filled to form an isolation structure; A transistor is formed between the isolation structures, the transistor being located on the insulating layer and the transistor being located in the epitaxial layer.

2. The method as described in claim 1, characterized in that, The second trench and the first trench are formed through the same mask plate.

3. The method of claim 1, wherein, The laser energy density range used in the laser annealing process is 0.7 to 1.2 J / cm 2 .

4. The method of claim 1, wherein, The laser annealing process is performed in an inert atmosphere.

5. The method of claim 1, wherein, The substrate is a silicon substrate; the epitaxial layer is a silicon epitaxial layer.

6. An SOI substrate having an isolation structure, characterized by, include: The substrate includes a substrate, an insulating layer on the substrate, and an epitaxial layer on the insulating layer; An isolation structure, the isolation structure comprising a second trench located in a substrate and an insulating material filling the second trench; The second trench penetrates the insulating layer and the epitaxial layer, and the isolation structure is in contact with the substrate; A transistor located between the isolation structures, the transistor being located on the insulating layer and the transistor being located in the epitaxial layer.

7. The SOI substrate with an isolation structure according to claim 6, wherein the buried oxide layer is formed by thermal oxidation of the silicon layer. The substrate is a silicon substrate; the epitaxial layer is a silicon epitaxial layer.

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