A display structure and a manufacturing method thereof

Abstract

The present application discloses a display structure and a manufacturing method thereof, and relates to the field of LED display technology. The manufacturing method comprises the steps of: arranging a plurality of bare crystal IC arrays on a substrate; the bare crystal IC has a solid crystal surface and a pin surface facing opposite directions, and the solid crystal surface of the bare crystal IC faces the substrate; the arrangement spacing of the bare crystal IC is greater than or equal to the longest side dimension of the bare crystal IC; performing at least one conductive circuit generation process on the side of the substrate where the bare crystal IC is arranged to obtain a circuit structure with a substrate; peeling off the substrate to expose the solid crystal surface of the bare crystal IC; placing the corresponding RGB chip at the pad position of the solid crystal surface of the bare crystal IC, and then packaging to obtain a display structure with a built-in bare crystal IC. In the present application, a circuit structure with a substrate is obtained from a bare crystal IC, and then the substrate is peeled off, which not only does not require additional IC packaging, but also makes the obtained main circuit structure thinner and closer to the characteristics of a flexible circuit board, thereby realizing a high-density flexible display.

Description

Technical Field

[0001] The present application relates to the technical field of LED displays, and particularly relates to a display structure and a manufacturing method thereof. Background Art

[0002] Currently, a micro-pitch display is an array based on small inorganic semiconductor light-emitting diodes, and a passive or active matrix display is obtained by transferring sliced LED (Light-Emitting Diode) microchips.

[0003] As the pitch in micro-pitch displays continues to decrease, the size of flip-chip dies becomes smaller and smaller, the electrode pitch and the pad channel pitch also become smaller, while the accuracy of screen printing, printing or etching becomes higher and higher. Among them, the bare die IC needs to be encapsulated before use, and the volume of the encapsulated IC is several times larger than that of the bare die IC. Due to the limited display area, there are relatively large problems in the arrangement of ICs in micro-pitch displays. Currently, the existing rigid circuit boards have problems such as low etching accuracy, large line tolerances, and high manufacturing costs.

[0004] LED flexible screens can be made into products such as LED bar screens, wavy LED screens, fan-shaped LED display screens, and flowing water-shaped LED floor tiles according to the shape. Such display screens can bring high stability and high brightness to high-resolution displays. However, in the flexible substrate technology, the lines on the flexible circuit board are formed by screen printing, and the mass production process can only achieve a line width of 50 μm, which cannot meet the requirement of a line width less than 20 μm for the wiring on the pad surface. Therefore, the requirement for the display pitch is restricted. Summary of the Invention

[0005] Aiming at the defects existing in the prior art, the purpose of the present application is to provide a display structure and a manufacturing method thereof, so as to solve the problems of high manufacturing difficulty and high cost of the display structure in the related art.

[0006] The first aspect of the present application provides a manufacturing method of a display structure, which includes the steps of:

[0007] Arranging a plurality of bare die ICs in an array on a substrate; the above bare die ICs have a die-bonding surface and a pin surface with opposite orientations, and the die-bonding surface of the above bare die ICs faces the above substrate; the arrangement pitch of the above bare die ICs is greater than or equal to the longest side dimension of the above bare die ICs;

[0008] Performing at least one conductive line generation process on the surface of the substrate on which the bare die ICs are arranged to obtain a circuit structure with a substrate;

[0009] Peeling the above substrate to expose the die-bonding surface of the above bare die ICs;

[0010] After placing the corresponding RGB chips at the pad positions on the die-bonding surface of the above-mentioned bare die IC, encapsulation is carried out to obtain a display structure with a built-in bare die IC.

[0011] In some embodiments, the above-mentioned conductive line generation process specifically includes:

[0012] Spin-coat a photoresist on the side of the above-mentioned substrate where the bare die IC is arranged to form a photoresist layer;

[0013] After patterning the above-mentioned photoresist layer by photolithography, a transparent conductive material is used as the printing material and printed onto the patterned area of the above-mentioned photoresist layer and cured to form a patterned conductive line.

[0014] In some embodiments, the above-mentioned transparent conductive material is nano silver, carbon nanotubes or indium tin oxide ITO.

[0015] In some embodiments, before arranging the multiple bare die ICs in an array on the substrate, it further includes:

[0016] Form a metal thin film layer on the side of the above-mentioned substrate where the bare die IC is to be arranged.

[0017] In some embodiments, the above-mentioned metal thin film layer is formed on the above-mentioned substrate by evaporation.

[0018] In some embodiments, the above-mentioned peeling of the substrate specifically includes:

[0019] Put the above-mentioned circuit structure with the substrate into an electrolytic cell, and electrolyze the above-mentioned metal thin film layer to dissolve and disappear the metal thin film layer, so as to peel off the above-mentioned substrate and obtain the main circuit structure.

[0020] In some embodiments, a physical peeling method is used to peel the above-mentioned substrate from the circuit structure with the substrate to obtain the main circuit structure.

[0021] In some embodiments, the above-mentioned encapsulation to obtain a display structure with a built-in bare die IC specifically includes:

[0022] Form a plastic encapsulation structure on the side of the above-mentioned main circuit structure where the above-mentioned RGB chips are placed and around the above-mentioned main circuit structure;

[0023] The above-mentioned RGB chips include a red LED chip, a green LED chip and a blue LED chip.

[0024] In some embodiments, the above-mentioned substrate is a glass substrate or a flexible PI film.

[0025] In the second aspect of the present application, a display structure is provided, and the above-mentioned display structure is obtained by the above-mentioned manufacturing method.

[0026] The beneficial effects brought by the technical solution provided in this application include:

[0027] For the display structure and its manufacturing method of this application, after arranging multiple bare die IC arrays on a substrate, at least one conductive line generation process is performed on the side of the substrate where the bare die ICs are arranged to obtain a circuit structure with a substrate. Then, the substrate in the circuit structure with a substrate is peeled off to expose the die bonding surface of the bare die IC. Corresponding RGB chips can be placed at the pad positions on the die bonding surface of the bare die IC and encapsulated to obtain a display structure with a built-in bare die IC. In this application, by reversely manufacturing the traditional circuit board structure, a circuit structure with a substrate is obtained from the bare die IC, and then the substrate is peeled off. Not only is no additional IC packaging required, but the obtained main circuit structure is thinner and closer to the characteristics of a flexible circuit board, realizing high-density flexible display. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 It is a schematic structural diagram of a bare die IC in an embodiment of this application;

[0030] Figure 2 It is a schematic cross-sectional view of conductive line generation in an embodiment of this application;

[0031] Figure 3 It is a top view of a circuit structure with a substrate in an embodiment of this application;

[0032] Figure 4 It is a schematic cross-sectional view of substrate peeling in an embodiment of this application;

[0033] Figure 5 It is a schematic cross-sectional view of encapsulation in an embodiment of this application.

[0034] Reference Signs:

[0035] 1. Bare die IC; 11. Pin; 12. Die bonding pad; 2. Substrate; 3. Photoresist layer; 31. First photoresist layer; 32. Second photoresist layer; 33. Third photoresist layer; 4. Conductive line; 41. First conductive line; 42. Second conductive line; 43. Third conductive line; 5. RGB chip; 6. Main circuit structure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] An embodiment of the present application provides a method for manufacturing a display structure, which can solve the problems of high manufacturing difficulty and high cost of display structures in related technologies.

[0038] The method for manufacturing a display structure according to an embodiment of the present application includes the following steps:

[0039] S1. Arrange a plurality of bare die IC (Integrated Circuit) 1s in an array on a substrate 2. The above bare die IC 1 has a die bonding surface and a lead surface facing in opposite directions, and the die bonding surface of the above bare die IC 1 faces the above substrate 2; the arrangement pitch of the above bare die IC 1 is greater than or equal to the longest side dimension of the above bare die IC 1. Wherein, taking the direction from the die bonding surface to the lead surface as the height direction, taking the long side direction of the die bonding surface or the lead surface as the length direction, and taking the short side direction of the die bonding surface or the lead surface as the width direction, the longest side dimension of the above bare die IC 1 is the long side dimension of the die bonding surface or the lead surface.

[0040] As Figure 1 shown, in this embodiment, the above bare die IC 1 has an upward die bonding surface and a downward lead surface. The lead surface of the bare die IC 1 is provided with leads 11, and the die bonding surface of the bare die IC 1 is provided with die bonding pads 12. Therefore, when arranging the bare die IC 1s in an array on the substrate 2, the bare die ICs are in a flip-chip structure, that is, they are arranged on the substrate 2 with the die bonding surface facing down and the lead surface facing up, and the arrangement pitch of the bare die ICs determines the display dot pitch of the display structure.

[0041] S2. Perform at least one conductive line generation process on the side of the substrate 2 on which the bare die IC 1s are arranged to obtain a circuit structure with a substrate.

[0042] S3. Peel the above substrate 2 to expose the die bonding surface of the above bare die IC 1.

[0043] S4. After placing corresponding RGB chips 5 at the pad positions on the die bonding surface of the above bare die IC 1, perform encapsulation to obtain a display structure with a built-in bare die IC.

[0044] The manufacturing method of the display structure of this embodiment is as follows: After arranging multiple bare die ICs in an array on a substrate, at least one conductive line generation process is performed on the side of the substrate where the bare die ICs are arranged to obtain a circuit structure with the substrate. Then, the substrate in the circuit structure with the substrate is peeled off to expose the die bonding surface of the bare die IC1. Corresponding RGB chips can be placed at the pad positions on the die bonding surface of the bare die IC and packaged to obtain a display structure with a built-in bare die IC. In this application, by reverse manufacturing the traditional circuit board structure, a circuit structure with a substrate is obtained from the bare die IC, and then the substrate is peeled off. This not only eliminates the need for additional IC packaging but also makes the obtained main circuit structure thinner and closer to the characteristics of a flexible circuit board, realizing high-density flexible display.

[0045] As Figure 2 shown, based on the above embodiment, in this embodiment, the conductive line generation process in step S2 specifically includes the following steps:

[0046] First, spin-coat a photoresist on the side of the above substrate 2 where the bare die IC1 is arranged to form a photoresist layer 3, so as to protect the bare die IC during the subsequent photolithography process.

[0047] Then, perform photolithographic patterning on the above photoresist layer 3, that is, perform photolithography according to the required circuit pattern to etch out the pins on the bare die IC that need to be connected to other circuits, forming a patterned area of the photoresist layer 3.

[0048] Finally, use a 3D printer to print a transparent conductive material as the printing material onto the patterned area of the above photoresist layer 3 according to the above circuit pattern and cure it to form a patterned conductive line 4.

[0049] Optionally, perform a conductive line generation process on the side of the above substrate 2 where the bare die IC1 is arranged once to obtain a circuit structure with the substrate.

[0050] In other embodiments, since each bare die IC has three pins, for convenient wire connection, three conductive line generation processes can be performed, specifically including:

[0051] S21. Spin-coat a photoresist on the side of the above substrate 2 where the bare die IC1 is arranged to form a first photoresist layer 31. Then, after performing photolithographic patterning on the first photoresist layer 31 to form the required circuit pattern of the first layer, use a 3D printer to print a transparent conductive material as the printing material onto the patterned area of the above first photoresist layer and cure it to form a first conductive line 41;

[0052] S22. Spin-coat a photoresist on the side where the first conductive circuit 41 is formed to form a second photoresist layer 32. Then, after performing photolithographic patterning on the second photoresist layer 32 to form the circuit pattern of the required second layer, use a 3D printer to print a transparent conductive material as the printing material onto the patterned area of the second photoresist layer according to the circuit pattern of the second layer, and cure and mold it to form a second conductive circuit 42;

[0053] S23. Spin-coat a photoresist on the side where the second conductive circuit 42 is formed to form a third photoresist layer 33. Then, after performing photolithographic patterning on the third photoresist layer 33 to form the circuit pattern of the required third layer, use a 3D printer to print a transparent conductive material as the printing material onto the patterned area of the third photoresist layer according to the circuit pattern of the third layer, and cure and mold it to form a third conductive circuit 43. Thus, a multi-layer circuit structure is formed.

[0054] As Figure 3 shown, each pin of the bare die IC includes a pin positive electrode, a pin negative electrode, and a pin signal line. The pin positive electrode connection line, the pin negative electrode connection line, and the signal line connection line of each bare die IC each occupy one layer of the conductive circuit.

[0055] As Figure 4 shown, after peeling the substrate 2 from the above multi-layer circuit structure, the main circuit structure 6 can be obtained.

[0056] In this embodiment, the line width of the above conductive circuit varies with the viewing distance. Preferably, for a viewing distance of 2 - 3m, the preferred conductive line width is 10um.

[0057] In other embodiments, if the spacing between adjacent bare die IC1s is controlled to be large enough, such as the spacing between adjacent bare die ICs being greater than the sum of three wire diameters and three wire pitches, then a circuit structure with a substrate can be obtained through one conductive circuit generation process, that is, wiring can be achieved on the same layer.

[0058] Preferably, the above transparent conductive material can be nano silver, carbon nanotubes, or indium tin oxide ITO. In this embodiment, the above transparent conductive material is a nano silver material.

[0059] In this embodiment, the bottom substrate 2 serves as a support structure. After arranging the bare die ICs thereon, the fixing and gap filling effects can be achieved through the photoresist, so that in the subsequent substrate peeling process, only chemical or physical peeling is required to separate the substrate from the first photoresist layer.

[0060] Preferably, in the above step S1, before arranging multiple bare die IC1s in an array on the substrate 2, the following steps are further included:

[0061] Form a metal thin film layer on the side of the above substrate 2 where the bare die IC1s are to be arranged.

[0062] Preferably, the metal thin film layer is formed by evaporation on one side of the substrate 2 where the bare die IC1 is to be arranged.

[0063] Based on the above embodiments, in this embodiment, in step S3, the substrate 2 is peeled off, which specifically includes the following steps:

[0064] Put the circuit structure with the substrate into an electrolytic cell, and electrolyze the metal thin film layer to dissolve and disappear the metal thin film layer, so as to peel off the substrate 2 and obtain the main circuit structure 6.

[0065] Optionally, the electrolytic cell includes an anode and a cathode, and an electrolyte is accommodated in the electrolytic cell. Among them, the anode and the cathode are arranged in the electrolyte in the electrolytic cell. In this embodiment, the electrolyte is a copper sulfate solution.

[0066] In other embodiments, a physical peeling method can also be used to peel off the substrate 2 from the circuit structure with the substrate to obtain the main circuit structure 6.

[0067] In this embodiment, the hardness of the bare die IC1 can be pre-judged, and when the hardness of the bare die IC1 is greater than the hardness threshold, there is no need to form a metal thin film layer on the substrate 2, and the substrate can be peeled off only by a physical peeling method.

[0068] As Figure 5 shown, after placing the corresponding RGB chips 5 at the pad positions on the die bonding surface of the above bare die IC1 to complete die bonding, encapsulation can be carried out.

[0069] Furthermore, in step S4, encapsulation is carried out to obtain a display structure with a built-in bare die IC, which specifically includes the following steps:

[0070] A plastic encapsulation structure is formed on one side of the main circuit structure 6 where the RGB chips 5 are placed and around the main circuit structure 6.

[0071] In this embodiment, according to the full-color RGB display substrate, each pixel requires 3 chips, namely red, green, and blue. That is, the above RGB chips 5 include a red LED chip, a green LED chip, and a blue LED chip. After placing each red LED chip, green LED chip, and blue LED chip at the corresponding die bonding pad positions of the corresponding bare die ICs respectively, encapsulation can be carried out.

[0072] Among them, the distance between each pixel is usually calculated by the center distance between the same-color chips of adjacent pixels to define the dot pitch of the display module. Therefore, by arranging multiple bare die ICs according to the corresponding pitch, the dot pitch of the same-color chips can meet the set pitch.

[0073] In this embodiment, the above-mentioned substrate 2 serves as a support structure and can be a glass substrate or a flexible PI film.

[0074] The manufacturing method of this embodiment does not require a high-precision etching process, nor does it require additional IC packaging. By using the die bonding pads on the bare die IC, high-density flexible display can be achieved to solve the problem that it is difficult to reduce the volume of existing IC packaging. In addition, the pads on the bare die IC have high precision, which can reduce the RGB chip pitch and better achieve the light mixing effect of the RGB three colors.

[0075] In an embodiment of the present application, a display structure is further provided, and the above-mentioned display structure is manufactured by the above-mentioned manufacturing method.

[0076] The display structure of this embodiment is applicable to the manufacturing methods of the above-mentioned display structures, can achieve high-density flexible display, and achieve a better light mixing effect of the RGB three colors. In addition, since the pin pitch on the pin surface of the bare die IC is greater than the pad pitch on the die bonding surface, this structure can achieve a larger via lead pin pitch, about 1.5 - 2 times larger, under the same pad pitch condition. In the subsequent processing, high-precision alignment is not required either.

[0077] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application. Unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0078] It should be noted that in this application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0079] The above are only specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to these embodiments shown herein, but rather will conform to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for manufacturing a display structure, characterized in that, It includes the steps of: Arranging a plurality of bare die ICs (1) in an array on a substrate (2); the bare die IC (1) has a die bonding surface and a pin surface facing opposite directions, and the die bonding surface of the bare die IC (1) faces the substrate (2); the arrangement pitch of the bare die ICs (1) is greater than or equal to the longest side dimension of the bare die IC (1); taking the direction of the long side of the die bonding surface or the pin surface as the length direction, the longest side dimension is the long side dimension of the die bonding surface or the pin surface; Performing at least one conductive line generation process on the side of the substrate (2) where the bare die ICs (1) are arranged to obtain a circuit structure with a substrate; Peeling the substrate (2) to expose the die bonding surface of the bare die IC (1); After placing corresponding RGB chips (5) at the pad positions on the die bonding surface of the bare die IC (1), performing encapsulation to obtain a display structure with a built-in bare die IC; Before arranging the plurality of bare die ICs (1) in an array on the substrate (2), it further includes: Forming a metal thin film layer on the side of the substrate (2) where the bare die ICs (1) are to be arranged; Peeling the substrate (2) specifically includes: Putting the circuit structure with a substrate into an electrolytic cell, and electrolyzing the metal thin film layer to dissolve and disappear the metal thin film layer, so as to peel the substrate (2) to obtain a main circuit structure (6); Performing at least one conductive line generation process specifically includes: performing three conductive line generation processes in sequence to form three layers of conductive lines, and the positive lead connection, negative lead connection, and signal line connection of each bare die IC each occupy one layer of conductive line.

2. The method for manufacturing a display structure according to claim 1, characterized in that, The conductive line generation process specifically includes: Spin-coating a photoresist on the side of the substrate (2) where the bare die ICs (1) are arranged to form a photoresist layer (3); After performing photolithographic patterning on the photoresist layer (3), printing a transparent conductive material as a printing material onto the patterned area of the photoresist layer (3) and curing it to form a patterned conductive line (4).

3. The method for manufacturing a display structure according to claim 2, characterized in that: The transparent conductive material is nano silver, carbon nanotubes, or indium tin oxide ITO.

4. The method for manufacturing a display structure according to claim 1, characterized in that: Forming the metal thin film layer on the substrate (2) by evaporation coating.

5. The method for manufacturing a display structure according to claim 1, characterized in that, Performing the encapsulation to obtain a display structure with a built-in bare die IC specifically includes: Forming a plastic encapsulation structure on one side of the main circuit structure (6) where the RGB chips (5) are placed and around the main circuit structure (6); The RGB chip (5) includes a red LED chip, a green LED chip, and a blue LED chip.

6. The method for manufacturing a display structure according to claim 1, characterized in that: The substrate (2) is a glass substrate or a flexible PI film.

7. A display structure, characterized in that, The display structure is obtained by the manufacturing method according to any one of claims 1-6.

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