Semiconductor device

Abstract

The semiconductor device of the embodiment includes a first nitride semiconductor layer having a first surface and a second surface; a first source electrode provided on the first surface; a first drain electrode provided on the first surface; a first gate electrode provided on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer provided on the second surface, having a third surface and a fourth surface, and having a smaller band gap than the first nitride semiconductor layer, the third surface being opposite to the second surface; and a first semiconductor device provided on the fourth surface, having a fifth surface opposite to the fourth surface and having a size smaller than the fourth surface, and including a first semiconductor material having a larger band gap than the second nitride semiconductor layer.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2020-151229 (filed on September 9, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation methods mainly involve semiconductor devices. Background Technology

[0004] As materials for next-generation power semiconductor devices, group III nitrides such as GaN (gallium nitride) semiconductors are anticipated. Compared to silicon (Si), GaN-based semiconductors have a larger band gap. Therefore, GaN-based semiconductor devices can achieve smaller and higher voltage-rated power semiconductor devices compared to Si (silicon) semiconductor devices. Furthermore, this reduces parasitic capacitance, thus enabling high-speed driven power semiconductor devices.

[0005] In GaN-based transistors, HEMT (High Electron Mobility Transistor) structures, which use two-dimensional electron gas (2DEG) as charge carriers, are generally used. Typical HEMTs are normally-on transistors that conduct even when no gate voltage is applied. Therefore, there is a difficulty in realizing normally-off transistors that do not conduct unless a gate voltage is applied.

[0006] In power supply circuits requiring high voltages of hundreds of volts to 1,000 volts, safety is paramount, necessitating normally-off operation. Therefore, a circuit structure has been proposed that connects normally-on GaN transistors and normally-off Si transistors via a cascode connection to achieve normally-off operation. Summary of the Invention

[0007] Embodiments of the present invention provide miniaturized semiconductor devices.

[0008] The semiconductor device of this embodiment includes: a first nitride semiconductor layer having a first surface and a second surface; a first source electrode disposed on the first surface; a first drain electrode disposed on the first surface; a first gate electrode disposed on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer disposed on the second surface having a third surface facing the second surface; and a fourth surface having a smaller bandgap ratio compared to the first nitride semiconductor layer; and a first semiconductor device disposed on the fourth surface having a fifth surface that is smaller than or equal to the fourth surface and facing the fourth surface, comprising a first semiconductor material having a smaller bandgap ratio compared to the second nitride semiconductor layer. Attached Figure Description

[0009] Figure 1 This is a schematic top view of the semiconductor device according to the first embodiment.

[0010] Figures 2A to 2C This is a schematic diagram of the main parts of the nitride semiconductor device according to the first embodiment.

[0011] Figure 3 This is an example of a schematic cross-sectional view of a semiconductor device according to the first embodiment.

[0012] Figure 4 This is another example of a schematic cross-sectional view of a semiconductor device according to the first embodiment.

[0013] Figure 5 This is another example of a schematic cross-sectional view of a semiconductor device according to the first embodiment.

[0014] Figure 6 This is a schematic cross-sectional view of the main part of the MOSFET in the first embodiment.

[0015] Figure 7 This is an example of a circuit diagram constructed from a semiconductor device according to the first embodiment.

[0016] Figure 8 This is another example of a circuit diagram constructed from a semiconductor device according to the first embodiment.

[0017] Figure 9 This is a schematic diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment.

[0018] Figure 10 This is a schematic diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment.

[0019] Figure 11 This is a schematic diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment.

[0020] Figure 12 This is a schematic diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment.

[0021] Figure 13 This is a schematic diagram of a semiconductor device used for comparison.

[0022] Figure 14 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0023] Figure 15 This is a schematic cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment.

[0024] Figure 16 This is a schematic cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment.

[0025] Figure 17 This is a schematic top view of the semiconductor device according to the third embodiment. Detailed Implementation

[0026] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same reference numerals will be used to denote the same parts, and descriptions of parts that have already been described once will be omitted as appropriate.

[0027] In this specification, to indicate the positional relationship of components, the upper direction in the accompanying drawings is described as "upper," and the lower direction is described as "lower." In this specification, the concepts of "upper" and "lower" do not necessarily refer to their relationship with the direction of gravity.

[0028] The following explanation will be based on the case where the first conductivity type is n-type and the second conductivity type is p-type.

[0029] In the following explanation, n + n, n - and p + p, p - The expression represents the relative levels of impurity concentration for each conductivity type. That is, n + This indicates that the impurity concentration of type n is relatively high compared to type n. - This indicates that the impurity concentration of the n-type is relatively low compared to the n-type. Additionally, p... + This indicates that the impurity concentration of p-type is relatively high compared to p-type. - This indicates that the impurity concentration of p-type is relatively low compared to p-type. Additionally, sometimes n-type is used... + type, n - Type abbreviated as n-type, p-type + Type, p - The type is abbreviated as p-type.

[0030] (First Implementation)

[0031] Figure 1 This is a schematic diagram of the semiconductor device 100 according to this embodiment. Figures 2A to 2C This is a schematic diagram of the main parts of the nitride semiconductor device 30 in this embodiment.

[0032] Figure 3 The semiconductor device 100 includes the first source electrode 14a, the field plate electrode 20a, the wiring 14c, and the first via 24a. Figure 2B ) through section A-A' ( Figure 1 An example of a schematic sectional view in (). Figure 4 The semiconductor device 100 includes the first drain electrode 16a, wiring 16c, wiring 16e, and third via 26a. Figure 2B The section A-A' passing through ( Figure 1 An example of a schematic sectional view in (). Figure 5 The semiconductor device 100 is in the first gate electrode 18a and wiring 18d ( Figure 2B The section A-A' passing through ( Figure 1 An example of a schematic sectional view in ). Additionally, as mentioned above, regarding section A-A' ( Figure 1 Assuming multiple types of sectional views, therefore, they are divided into Figure 3 , Figure 4 and Figure 5 A diagram is provided.

[0033] use Figures 1 to 5 The semiconductor device 100 of this embodiment will be described.

[0034] The semiconductor device 100 in this embodiment is a device formed by electrically connecting a nitride semiconductor device 30 and a MOSFET (an example of a first semiconductor device) 80 in series.

[0035] The insulating substrate 2 is, for example, a substrate for forming circuits, etc.

[0036] Here, the X direction, the Y direction perpendicular to the X direction, and the Z direction perpendicular to both the X and Y directions are defined. The insulating substrate 2 is arranged parallel to the XY plane.

[0037] A lead frame 4 is disposed above the insulating substrate 2. The lead frame 4 is used for electrical connection between an external circuit (not shown) and the semiconductor device 100. The lead frame 4 is formed, for example, from Cu (copper) or Al (aluminum).

[0038] A fourth conductive layer 46 is disposed above the lead frame 4. The fourth conductive layer 46 electrically connects the lead frame 4 to the nitride semiconductor device 30. The fourth conductive layer 46 is, for example, solder or silver paste used as a chip bonding material. However, the material used for the fourth conductive layer 46 is not limited to these.

[0039] A conductive second substrate 42 is disposed above the fourth conductive layer 46 and is electrically connected to the fourth conductive layer 46. The second substrate 42 is, for example, a conductive Si (silicon) substrate doped with impurities, but is not limited to this.

[0040] A third conductive layer 45 is disposed above the second substrate 42 and is electrically connected to the second substrate 42. The third conductive layer 45 preferably contains, for example, an Au (gold) / Sn (tin) alloy. However, the material used for the third conductive layer is not limited to this.

[0041] The nitride semiconductor device 30 is disposed above the third conductive layer 45. The nitride semiconductor device 30 is, for example, a HEMT (High Electron Mobility Transistor).

[0042] The nitride semiconductor device 30 has a first nitride semiconductor layer 10, a second nitride semiconductor layer 12, a first source electrode 14, a first drain electrode 16, a first gate electrode 18, a field plate electrode 20, an interlayer insulating film 22, a second conductive layer 44, a third via 26, a first via 24, a conductive material 32, wiring 47, and a second via 48.

[0043] The first nitride semiconductor layer 10 has a first surface 10a and a second surface 10b. The first nitride semiconductor layer 10 is configured with the first surface 10a facing downwards. The first nitride semiconductor layer 10 is, for example, undoped Al. Y Ga 1-Y N (0 < Y ≤ 1, X < Y). More specifically, the first nitride semiconductor layer 10 is, for example, undoped Al. 0.2 Ga 0.8 N. The thickness of the first nitride semiconductor layer 10 is, for example, 15 nm or more and 50 nm or less.

[0044] The second nitride semiconductor layer 12 has a third surface 12a and a fourth surface 12b. The third surface 12a is disposed on the second surface 10b, opposite to the second surface 10b, and in contact with the second surface 10b. The band gap of the second nitride semiconductor layer 12 is smaller than the band gap of the first nitride semiconductor layer. The second nitride semiconductor layer 12 is, for example, Al. X Ga 1-X N (0 ≤ X < 1). Furthermore, the second nitride semiconductor layer 12 may also contain, for example, aluminum gallium nitride (Al₂O₃). W Ga 1-W A multilayer structure of N (0 < W < 1). More specifically, the first nitride semiconductor layer 10 is, for example, GaN. The thickness of the second nitride semiconductor layer 12 is, for example, 0.5 μm or more and 10 μm or less.

[0045] A heterojunction interface is formed between the first nitride semiconductor layer 10 and the second nitride semiconductor layer 12. When the nitride semiconductor device 30 is turned on, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface and becomes a charge carrier.

[0046] A first source electrode 14 is disposed on a first surface 10a. A first drain electrode 16 is disposed on the first surface 10a. A first gate electrode 18 is disposed on the first surface 10a between the first source electrode 14 and the first drain electrode 16. The first source electrode 14, the first drain electrode 16, and the first gate electrode 18 are, for example, metal electrodes. The metal electrodes used for the first source electrode 14, the first gate electrode 18, or the first drain electrode 16 have, for example, a Ti (titanium) and Al stacked structure, or a Ni (nickel) and Au (gold) stacked structure. Furthermore, an insulating film containing, for example, silicon nitride (SiN), silicon oxide (SiO2), or aluminum oxide (Al2O3) may be disposed between the first nitride semiconductor layer 10 and the first gate electrode 18. Additionally, a nitride semiconductor layer containing p-type impurities may be disposed between the first nitride semiconductor layer 10 and the first gate electrode 18.

[0047] The field plate electrode 20 is disposed below the first source electrode 14 and is electrically connected to the first source electrode 14. The field plate electrode 20 is used to mitigate the electric field within the nitride semiconductor device 30.

[0048] An interlayer insulating film 22 is disposed between the first surface 10a and the third conductive layer 45. The interlayer insulating film 22 may contain, for example, polyimide, BCB (benzocyclobutene), SiN or SiO2, but is not limited to these.

[0049] The second conductive layer 44 is disposed between the interlayer insulating film 22 and the third conductive layer 45. The second conductive layer 44 is, for example, a conductive layer of a conductive material containing a metal such as Al, W (tungsten) or Cu.

[0050] The third through-hole 26 is disposed between the second conductive layer 44 and the first drain electrode 16, electrically connecting the second conductive layer 44 and the first drain electrode 16. The third through-hole 26 is, for example, a through-hole made of a conductive material containing metals such as Al, W, or Cu.

[0051] The first via 24 is electrically connected to the first source electrode 14 and penetrates the first nitride semiconductor layer 10 and the second nitride semiconductor layer 12. The first via 24 is, for example, a via made of a conductive material containing metals such as Al, W, or Cu.

[0052] A conductive material (an example of the first conductive layer) 32 is disposed above the second nitride semiconductor layer 12 and is electrically connected to the first via 24. A bonding material (an example of the first conductive layer) 34 is disposed above the conductive material 32 and is electrically connected to the conductive material 32. The conductive material 32 may include, for example, a conductive material such as a metal, and may be formed simultaneously with the first via 24. Alternatively, the conductive material 32 may not be formed simultaneously with the first via 24. The bonding material 34 may be, for example, solder or silver paste used as a chip bonding material.

[0053] The first gate pad 33 is disposed above the second nitride semiconductor layer 12 and, as described later, is electrically connected to the first gate electrode 18 of the nitride semiconductor device 30. The first gate pad 33 is electrically connected to the pad 6d disposed above the insulating substrate 2, for example, using a bonding wire 8d containing Au (gold) or Cu.

[0054] MOSFET 80 is disposed above bonding material 34. MOSFET 80 has a fifth surface 80b, which is smaller than or equal to the fourth surface 12b and faces the fourth surface 12b. A second source pad 82, a second Kelvin pad 84, and a second gate pad 86 are disposed on the upper surface of MOSFET 80. The second source pad 82 is electrically connected to pad 6a disposed above insulating substrate 2, for example, using bonding wire 8a. The second Kelvin pad 84 is electrically connected to pad 6b disposed above insulating substrate 2, for example, using bonding wire 8b. The second gate pad 86 is electrically connected to pad 6c disposed above insulating substrate 2, for example, using bonding wire 8c.

[0055] Next, use Figures 2A to 2C Please provide an explanation. Figure 2B This is a schematic bottom view of the nitride semiconductor device 30 of this embodiment. Figure 2A yes Figure 2B A schematic cross-sectional view of the nitride semiconductor device 30 of this embodiment in section B-B'. Figure 2C This is a schematic cross-sectional view showing the connection configuration between wiring 18d and the first gate pad 33. Additionally, in Figure 2A The field plate electrode 20 and the interlayer insulating film 22 shown in the figure are in Figure 2B Not shown in the image.

[0056] The nitride semiconductor device 30 of this embodiment, for example, has a multi-finger structure. A first drain electrode 16a, serving as a first drain electrode 16, is disposed between the first source electrode 14a and the first source electrode 14b, which serve as the first source electrode 14. Furthermore, a first gate electrode 18a, serving as a first gate electrode 18, is disposed between the first source electrode 14a and the first drain electrode 16a. Additionally, a first gate electrode 18b, serving as the first gate electrode 18, is disposed between the first source electrode 14b and the first drain electrode 16a. A first gate electrode 18c, serving as the first gate electrode 18, is disposed between the first source electrode 14b and the first drain electrode 16b. A field plate electrode 20a, serving as a field plate electrode 20, is electrically connected to the first source electrode 14a. A field plate electrode 20b, serving as a field plate electrode 20, is electrically connected to the first source electrode 14b.

[0057] Wiring 14c is electrically connected to the first source electrode 14a and the first source electrode 14b. Additionally, first vias 24a and 24b, serving as first vias 24, are connected to wiring 14c. Thus, the first source electrode 14 is electrically connected to the first via 24. Wiring 16c is electrically connected to the first drain electrode 16a. Wiring 16d is electrically connected to the first drain electrode 16b. Wiring 16e is electrically connected to wiring 16c and 16d. Third vias 26a and 26b, serving as third vias 26, are connected to wiring 16e. Thus, the first drain electrode 16 is electrically connected to the third via 26. Wiring 18d is electrically connected to the first gate electrode 18a, the first gate electrode 18b, and the first gate electrode 18c. Wiring 18d is connected, for example, to a second via 48 made of a conductive material including a metal such as Al, W, or Cu. The second via 48 penetrates the first nitride semiconductor layer 10 and the second nitride semiconductor layer 12. The second via 48 is electrically connected to the first gate pad 33. Thus, the first gate pad 33 is electrically connected to the first gate electrode 18. Furthermore, Figure 2B The area shown by the dashed line is the active area of ​​the nitride semiconductor device 30.

[0058] Figure 6 This is a schematic cross-sectional view of the main part of the MOSFET 80 in this embodiment. The MOSFET 80 in this embodiment is, for example, a vertical trench-type Si (silicon) MOSFET. In addition, Si is an example of a first semiconductor material with a smaller bandgap compared to the second nitride semiconductor layer 12.

[0059] The second drain electrode 56 is disposed above the bonding material 34 and is electrically connected to the bonding material 34. The second drain electrode 56 is an electrode that functions as the drain electrode of the MOSFET 80. The second drain electrode 56 may contain a conductive material such as a metal.

[0060] A drain layer (an example of a first semiconductor layer) 58 is disposed above the second drain electrode 56. The drain layer 58 functions as the drain of the MOSFET 80. The drain layer 58, for example, contains n... + Si of type.

[0061] A drift layer (an example of a second semiconductor layer) 60 is disposed above the drain layer 58. The drift layer 60 functions as the drift layer of the MOSFET. The drift layer 60, for example, contains n... - Si of type.

[0062] A substrate region (an example of a first semiconductor region) 62 is disposed above the drift layer 60. The substrate region 62 functions as the substrate of the MOSFET 80. The substrate region 62 is a region where a channel is formed when a voltage is applied to the second gate electrode 70 (described later), allowing carriers to flow between the source region 64 and the drain layer 58 (described later). The substrate region 62 may contain, for example, p-type Si.

[0063] A source region (an example of a second semiconductor region) 64 is disposed above the substrate region 62. The source region 64 functions as the source of the MOSFET 80. When an appropriate voltage is applied to the second gate electrode 70, charge carriers flow between the source region 64 and the drain layer 58. The source region 64, for example, contains n + Si of type.

[0064] Contact region 66 is disposed above substrate region 62 and electrically connected to substrate region 62 and source region 64. Contact region 66 is provided to improve electrical contact between substrate region 62 and source region 64 and the second source electrode 74, described later. Contact region 66, for example, includes p... + Si of type.

[0065] The trench 50 is configured to extend from above the source region 64 to the drift layer 60.

[0066] An insulating film 52 is disposed within the trench 50. For example, the insulating film 52 is disposed such that it covers the field plate electrode 54 described later. For example, the insulating film 52 contains SiO2. x (Silicon oxide).

[0067] A gate insulating film 68 is disposed above the insulating film 52 within the trench 50. Additionally, the gate insulating film 68 is disposed between the second gate electrode 70 and the substrate region 62. The gate insulating film 68 may contain, for example, SiO2. x (Silicon oxide).

[0068] The field plate electrode 54 is disposed opposite to the drift layer 60 within the trench 50 via an insulating film 52. For example, the field plate electrode 54 and the drift layer 60 are disposed side-by-side. The field plate electrode 54, for example, is located in... Figure 6 The portion (not shown) provided in the depth direction has an upwardly extending portion. Furthermore, the field plate electrode 54 uses this upwardly extending portion to be electrically connected to the second source electrode 74, which will be described later.

[0069] An interlayer insulating film 72 is disposed above the gate insulating film 68 and the second gate electrode 70. The interlayer insulating film 72 may contain, for example, SiO₂. x (Silicon oxide).

[0070] The second source electrode 74 is disposed above the source region 64, the interlayer insulating film 72, and the contact region 66. The second source electrode 74 comprises a conductive material such as a metal.

[0071] The second source pad 82 is disposed above the second source electrode 74 and is electrically connected to the second source electrode 74. The second source pad 82 contains conductive materials such as metal.

[0072] Additionally, the second gate pad 86 ( Figure 1 For example, it is electrically connected to the second gate electrode 70.

[0073] Furthermore, the semiconductor device 100 may include both MOSFET 80 and control circuit 90, or either MOSFET 80 or control circuit 90.

[0074] Figure 7 This is an example of a circuit diagram constructed from the semiconductor device 100 of this embodiment. Figure 7 This circuit represents the circuit where the drain electrode 112 of the normally off transistor 110 and the source electrode 121 of the normally open transistor 120 are connected by a common source and common gate. The normally off transistor 110 and the normally open transistor 120 are connected in series, thereby achieving the normally off operation.

[0075] Normally off transistor 110 has a source electrode 111, a drain electrode 112, and a gate electrode 113. Normally off transistor 110 is equivalent to MOSFET 80 (e.g., Figure 1 The normally off transistor 110 has a voltage rating of, for example, 10V or higher and 30V or lower.

[0076] A wiring 142 is connected to the source electrode 111. The wiring 142 is connected to the source terminal 102. The source terminal 102 is, for example, equivalent to the second source pad 82.

[0077] Additionally, wiring 144 is connected to the source electrode 111. Wiring 144 is connected to terminal 103. Terminal 103, for example, corresponds to the second Kelvin pad 84.

[0078] Normally open transistor 120 has a source electrode 121, a drain electrode 122, and a gate electrode 123. Normally open transistor 120 corresponds to nitride semiconductor device 30 (e.g., Figure 1 The voltage rating of a normally open transistor 120 is, for example, above 600V and below 1200V.

[0079] The capacitor 185 has a first end 186 and a second end 187. The first end 186 is electrically connected to the gate electrode 123.

[0080] The diode 180 has an anode 181 and a cathode 182. The anode 181 is electrically connected to a first terminal 186 and a gate electrode 123. The cathode 182 is electrically connected to a source electrode 121.

[0081] Resistor 175 has end 176 and end 177. End 176 is electrically connected to gate electrode 113.

[0082] Diode 170 has an anode 171 and a cathode 172. Anode 171 is electrically connected to terminal 177. Cathode 172 is electrically connected to gate electrode 113 and terminal 176. Diode 170 is connected in parallel with resistor 175.

[0083] The gate drive circuit 196 is electrically connected to the second end 187, the end 177, and the anode 171. The gate drive circuit 196 outputs signals for driving the normally off transistor 110 and the normally open transistor 120.

[0084] Figure 7 The operation of the circuit shown is described, for example, in Japanese Patent No. 6392458.

[0085] Figure 8 This is another example of a circuit diagram constructed from the semiconductor device 100 of this embodiment. The gate drive circuit 196 is connected to the gate electrode 113 but not to the gate electrode 123. In addition, the source electrode 111 and the gate electrode 123 are connected by wiring 150. Figure 8 This is another example of a circuit in which the source electrode 111 of a normally off transistor 110 and the gate electrode 123 of a normally open transistor 120 are connected by a common source and a common gate.

[0086] Figures 9 to 12 This is a schematic diagram illustrating the manufacturing process of the semiconductor device according to this embodiment. Additionally, a top view is shown in the center. A cross-sectional view along line C-C' is shown above. A bottom view is shown below.

[0087] First, a second nitride semiconductor layer 12 and a first nitride semiconductor layer 10 are formed on the first substrate 40, for example, by metal-organic chemical vapor deposition (MOCVD). Furthermore, a first source electrode 14, a first drain electrode 16, a first gate electrode 18, a field electrode 20, an interlayer insulating film 22, and a third via 26 are formed. The first substrate 40 is, for example, a Si substrate or a sapphire substrate. Figure 9 ).

[0088] Next, a second conductive layer 44 is formed on the interlayer insulating film 22. Figure 10 ).

[0089] Next, a third conductive layer 45, for example, comprising an Au / Sn alloy, is formed above the second conductive layer 44. Then, the second substrate 42 and the second conductive layer 44 are connected via the third conductive layer 45. Next, the first substrate 40 is removed. If the first substrate 40 is a Si substrate, it is removed, for example, by chemical etching using an aqueous potassium hydroxide (KOH) solution. If the first substrate 40 is a sapphire substrate, it is removed, for example, by laser lift-off. Next, the semiconductor device in the middle of manufacturing is reversed (vertically). Figure 11 ).

[0090] Next, a first via 24 electrically connected to the first source electrode 14 and penetrating the first nitride semiconductor layer 10 and the second nitride semiconductor layer 12, a second via 48 electrically connected to the first gate electrode 18, a conductive material 32 disposed above the second nitride semiconductor layer 12 and electrically connected to the first via 24, and a first gate pad 33 disposed on the second nitride semiconductor layer 12 and electrically connected to the second via 48 are formed. Figure 12 ).

[0091] Next, the second substrate 42 of the semiconductor device in the manufacturing process is thinned into a thin film by back-side grinding and monolithically formed into a chip. Next, the second substrate 42 is bonded to the lead frame 4 by the fourth conductive layer 46. Next, the MOSFET 80 is bonded on top of the bonding material 34, the control circuit 90 and the bonding line 8 are appropriately bonded, and the semiconductor device 100 of this embodiment is obtained by appropriate sealing and encapsulation cutting based on molding resin.

[0092] Next, the effects of the semiconductor device in this embodiment will be described.

[0093] Figure 13 This is a schematic diagram of a semiconductor device 800 used for comparison. Both the nitride semiconductor device 30 and the MOSFET 80 are arranged in the same XY plane. Terminal 806 and the drain terminal 810 of the nitride semiconductor device 30 are electrically connected via bonding wire 808. The source terminal 812 of the nitride semiconductor device 30 is electrically connected to a metal plate 832 via bonding wire 816. A MOSFET 80 (not shown) is disposed above the metal plate 832, and its drain electrode is electrically connected to the metal plate 832. The source electrode 840 disposed on the upper surface of the MOSFET 80 is electrically connected to terminal 856 via bonding wire 866.

[0094] The gate electrode 814 of the nitride semiconductor device 30 is electrically connected to the terminal 850 via a bonding wire 860. The gate electrode 842 of the MOSFET 80 is electrically connected to the terminal 852 via a bonding wire 862.

[0095] The source electrode 840 is electrically connected to terminal 854 via bonding wire 864. Terminal 854 is used, for example, for a Kelvin connection.

[0096] In a circuit that achieves normally-off operation by connecting a normally-on nitride semiconductor device 30 and a normally-off MOSFET 80 via a common-source, common-gate connection, two transistors are used. Therefore, if both the nitride semiconductor device 30 and the MOSFET 80 are mounted in the XY plane, there is a problem of increased package size.

[0097] Furthermore, if both the nitride semiconductor device 30 and the MOSFET 80 are mounted in the XY plane, the resistance of the bonding wire connecting the nitride semiconductor device 30 and the MOSFET 80 increases, resulting in a problem of increased on-resistance as a semiconductor device. For example, to extend the surface distance between terminal 806 and drain terminal 810, a distance is preferably set, therefore, it is preferable to extend the length of the bonding wire 808. Thus, the problem of increased on-resistance as a semiconductor device exists.

[0098] In addition, due to the electromotive force generated by the inductance of the junction wire, there are problems that are prone to occur, such as delays in the rise or fall speed of the semiconductor device, and transients in the drain current or source voltage that change drastically over time.

[0099] Furthermore, the potential on the bottom side of the nitride semiconductor device 30 is the same as the source potential of a typical semiconductor device. On the other hand, the potential on the bottom side of the MOSFET 80 in the semiconductor device 800, i.e., the potential of the metal plate 832, becomes the potential of the drain electrode of the MOSFET 80. Therefore, since the bottom side has different potentials depending on its location, there is a problem of finding countermeasures such as making a portion of it float.

[0100] Therefore, the semiconductor device 100 of this embodiment includes: a first nitride semiconductor layer 10 having a first surface 10a and a second surface 10b; a first source electrode 14 disposed on the first surface 10a; a first drain electrode 16 disposed on the first surface 10a; a first gate electrode 18 disposed on the first surface 10a between the first source electrode 14 and the first drain electrode 16; a second nitride semiconductor layer 12 disposed on the second surface 10b having a fourth surface 12b and a third surface 12a opposite to the second surface 10b, having a smaller band gap than the first nitride semiconductor layer 10; and a MOSFET 80 disposed on the fourth surface 12b having a fifth surface 80b that is smaller than or equal to the fourth surface 12b and opposite to the fourth surface 12b, and containing a first semiconductor material with a smaller band gap than the second nitride semiconductor layer 12.

[0101] According to this structure, since the nitride semiconductor device 30 and the MOSFET 80 are stacked, a miniaturized semiconductor device can be provided. In particular, since the nitride semiconductor device 30 requires a high breakdown voltage, it is preferable to set the distance between the first source electrode 14, the first drain electrode 16, and the first gate electrode 18 to a certain extent, thus making it easier to increase the size. On the other hand, the MOSFET 80 has a low breakdown voltage, so its size is smaller. Furthermore, in the manufacturing process, the MOSFET 80 is bonded above the bonding material 34, but if the fifth surface 80b is smaller than or equal to the size of the fourth surface 12b, it is easier to align the MOSFET 80 above the bonding material 34. Therefore, the fifth surface 80b of the MOSFET 80 is smaller than or equal to the size of the fourth surface 12b of the nitride semiconductor device 30.

[0102] The semiconductor device 100 also includes: a first via 24 that passes through the first nitride semiconductor layer 10 and the second nitride semiconductor layer 12 and is electrically connected to the first source electrode 14; and a conductive material 32 disposed between the fourth surface 12b and the fifth surface 80b and electrically connected to the first via 24, thereby facilitating the stacking of the nitride semiconductor device 30 and the MOSFET 80.

[0103] MOSFET 80 is preferably a vertical MOSFET. This is because, due to the second drain electrode 56 on the back side, it is easy to form a circuit based on a stacked cascode connection.

[0104] Furthermore, by using the second conductive layer 44 and the third conductive layer 45, the third through-hole 26 can be easily bonded to the second substrate 42.

[0105] The material containing Au (gold) and Sn (tin), preferably used as the third conductive layer 45, can be bonded at a relatively low temperature, thus reducing the warpage of the first substrate 40 and the second substrate 42. Furthermore, it reduces the thermal budget applied to the semiconductor device during the manufacturing process. Additionally, even with minor process changes, performance degradation is less likely to occur in the manufactured semiconductor device.

[0106] In addition, in order to electrically connect the third via 26 to the third conductive layer 45, it is preferable to first form a second conductive layer 44 connected to the third via 26, and then electrically connect the third via 26 to the third conductive layer 45 via the second conductive layer 44, rather than directly connecting the third via 26 to the third conductive layer 45.

[0107] The semiconductor device according to this embodiment can provide a miniaturized semiconductor device.

[0108] (Second Implementation)

[0109] The semiconductor device 105 of this embodiment differs from the semiconductor device of the first embodiment in that it includes a first substrate 40 disposed between the fourth surface and the MOSFET 80. Descriptions that are repeated in the first embodiment will be omitted here.

[0110] Figure 14 This is a schematic cross-sectional view of the semiconductor device 105 according to the second embodiment. The first substrate 40, which is removed during the manufacturing process in the semiconductor device of the first embodiment, is not removed. As the first substrate 40, a Si substrate doped with impurities is conductive, and therefore preferred. On the other hand, the semiconductor device 105 does not include a second substrate 42. Furthermore, the semiconductor device 105 also does not include a third conductive layer 45.

[0111] Figure 15 as well as Figure 16 This is a schematic cross-sectional view showing the manufacturing process of the semiconductor device 105 in this embodiment. Figure 15 and Figure 16 The process shown is the same as Figure 9 and Figure 10 The process shown is the same. However, the first substrate 40 is not removed thereafter. Furthermore, bonding with the second substrate 42 is not performed. Subsequent manufacturing processes are omitted.

[0112] The semiconductor device according to this embodiment does not require removal of the first substrate 40 or bonding with the second substrate 42, thus enabling easy manufacturing. Furthermore, the semiconductor device of this embodiment also provides a miniaturized semiconductor device.

[0113] (Third Implementation)

[0114] The semiconductor device of this embodiment differs from the semiconductor devices of the first and second embodiments in that it also includes a control circuit (an example of a second semiconductor device) 90. Descriptions that are repeated in the first and second embodiments are omitted here.

[0115] Figure 17 This is a schematic top view of the semiconductor device 106 in this embodiment.

[0116] A control circuit (an example of a second semiconductor device) 90 is disposed, for example, above the bonding material 34 and the first gate pad 33. The control circuit 90 is disposed on the fourth surface 12b of the second nitride semiconductor layer 12 via the conductive material 32 and the bonding material 34. The control circuit 90 has a sixth surface 90b, smaller than or equal to the fourth surface 12b, opposite to the fourth surface 12b. The sixth surface 90b is the bottom surface of the control circuit 90. The control circuit 90 includes a gate drive circuit 196 (…). Figure 7 , Figure 8For example, a predetermined control signal is input to the first gate electrode 18 and the second gate electrode 70. The control circuit 90 is an IC in which multiple components are monolithically assembled, or an electronic circuit board with multiple electronic components configured, containing Si (silicon) (an example of a second semiconductor material) with a smaller bandgap compared to the second nitride semiconductor layer 12.

[0117] For example, the gate drive circuit 196, diode 170, resistor 175, capacitor 185, and diode 180 can be assembled in the control circuit 90. Alternatively, a portion of the gate drive circuit 196, diode 170, resistor 175, capacitor 185, and diode 180 can also be assembled, and the contents of the components assembled in the control circuit 90 are not particularly limited.

[0118] The control circuit 90 is electrically connected to pad 6b, for example, via bonding line 8g. Additionally, the control circuit 90 is electrically connected to pad 6c, for example, via bonding line 8e. Furthermore, the control circuit 90 is electrically connected to pad 6d, for example, via bonding line 8d. Additionally, the control circuit 90 is electrically connected to the second gate pad 86, for example, via bonding line 8f. For example, gate signals are input to the control circuit 90 using pads 6c and 6d. Moreover, the gate drive circuit 196 assembled in the control circuit 90 can be used, for example, to control the nitride semiconductor device 30 and the MOSFET 80.

[0119] The semiconductor device described in this embodiment can also provide a miniaturized semiconductor device.

[0120] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims.

Claims

1. A semiconductor device comprising: a first nitride semiconductor layer having a first surface and a second surface; and a first source electrode provided on the first surface. a first drain electrode provided on the first surface; a first gate electrode provided on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer provided on the second surface, having a third surface and a fourth surface, and having a smaller band gap than the first nitride semiconductor layer, the third surface being opposite to the second surface; a first semiconductor device provided on the fourth surface, having a fifth surface which is opposite to the fourth surface and has a size smaller than the fourth surface, and including a first semiconductor material having a smaller band gap than the second nitride semiconductor layer, a first via hole penetrating the first nitride semiconductor layer and the second nitride semiconductor layer and electrically connected to the first source electrode, and a first conductive layer provided between the fourth surface and the fifth surface, electrically connected to the first via hole, the first semiconductor device having a second drain electrode electrically connected to the first conductive layer, a first semiconductor layer of a first conductivity type provided above the second drain electrode, a first semiconductor region of a second conductivity type provided above the first semiconductor layer, and a second semiconductor region of the first conductivity type provided above the first semiconductor region; a second gate electrode provided above the first semiconductor layer; and a second source electrode provided above the second semiconductor region.

2. The semiconductor device according to claim 1, wherein The second substrate is provided below the first source electrode, below the first drain electrode, and below the first gate electrode, and is electrically connected to the first drain electrode.

3. The semiconductor device according to claim 2, wherein The second semiconductor device is provided on the fourth surface, has a sixth surface which is opposite to the fourth surface and has a size smaller than the fourth surface, and includes a second semiconductor material having a smaller band gap than the second nitride semiconductor layer.

4. The semiconductor device according to claim 1, wherein The second semiconductor device includes a control circuit which inputs a prescribed control signal to the first gate electrode.

5. The semiconductor device according to claim 4, wherein The control circuit has a capacitor having a first end portion electrically connected to the first gate electrode and a second end portion, a diode having an anode electrically connected to the first gate electrode and the first end portion and a cathode electrically connected to the first source electrode, and a gate drive circuit electrically connected to the second end portion.

6. The semiconductor device according to claim 5, wherein ​

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