Semiconductor device and method of manufacturing the same

Abstract

Various embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. In a semiconductor device including a split-gate MONOS memory mixed together in a semiconductor device and a trench capacitor element having an upper electrode partially embedded in a trench formed in a main surface of a semiconductor substrate, flatness of a top surface of the upper electrode embedded in the trench is improved. A polysilicon film formed over the semiconductor substrate to form a control gate electrode of a memory cell forming the MONOS memory is embedded in the trench formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby forming an upper electrode including the polysilicon film in the trench.

Description

[0001] DIVISION

[0002] This application is a divisional application of Chinese invention patent application No. 201610091368.2, filed on February 18, 2016, entitled "Semiconductor Device and Manufacturing Method Thereof".

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] The publication of Japanese Patent Application No. 2015-048719, filed on March 11, 2015, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0005] This invention relates to a semiconductor device and a method for manufacturing the same. The invention can be applied, for example, to the manufacture of semiconductor devices having non-volatile memory and capacitor elements. Background Technology

[0006] EEPROM (Electrically Erasable and Programmable Read-Only Memory) has been widely used as an electrically writable / erasable non-volatile semiconductor memory device. This type of memory device has a conductive floating gate electrode surrounded by an oxide film or a trapping insulating film beneath the gate electrode of a MISFET. The memory device uses the charge accumulation state at the floating gate or trapping insulating film as stored information and reads this information as the threshold of the transistor.

[0007] A capture insulating film refers to an insulating film capable of accumulating charge. As an example, this insulating film can be made of silicon nitride film. Injecting / draining charge into this charge accumulation region causes each MISFET to shift at a threshold and operate as a storage element. Non-volatile memory devices using capture insulating films include discrete gate cells using MONOS (metal oxide nitride oxide semiconductor) films.

[0008] However, a known method for forming the gate electrode is the so-called gate-last process, in which a dummy gate electrode is formed on the substrate and then replaced with a metal gate electrode or the like. When using the gate-last process, it is difficult to form a capacitor element in which the lower electrode is formed at the same height as the gate electrode, and the upper electrode is formed above the lower electrode.

[0009] In contrast, a capacitor element in which a semiconductor substrate is used as a lower electrode and an upper electrode is formed at the same height as that of a gate electrode can be mixed with a memory element or the like formed over the semiconductor substrate by using a gate-last process. In this capacitor element, the upper electrode is partially embedded in a trench formed in a main surface of the semiconductor substrate, so that the facing area of the upper electrode and the semiconductor substrate can be increased. This can increase the capacitance.

[0010] Patent Document 1 (Japanese Patent Application Publication No. 2001-85633) describes a capacitor element in which a capacitance is generated between a substrate and a first gate over the substrate, and further, a capacitance is generated between the first gate and a second gate over the first gate.

[0011] Patent Document 2 (Japanese Patent Application Publication No. 2003-309182) describes that, in a capacitor element for generating a capacitance between a substrate and an electrode over the substrate, the electrode is partially embedded in a trench in a top surface of the substrate.

[0012] Patent Document 3 (Japanese Patent Application Publication No. 2013-154790) describes that a memory cell is formed by using a gate-last process.

[0013] [Patent Document 1] Japanese Patent Application Publication No. 2001-85633

[0014] [Patent Document 2] Japanese Patent Application Publication No. 2003-309182

[0015] [Patent Document 3] Japanese Patent Application Publication No. 2013-154790 SUMMARY

[0016] In a capacitor element in which a trench is formed in a main surface of a semiconductor substrate and an electrode is partially embedded in the trench, when the electrode has a small film thickness, the embedding is incomplete. This results in generation of a residue, a foreign matter, or the like.

[0017] Other objects and novel features will become apparent from the following description and the accompanying drawings.

[0018] The contents of representative inventions among the inventions disclosed in this application will be briefly described below.

[0019] For a method for manufacturing a semiconductor device of one embodiment, a control gate electrode of a MONOS memory and an upper electrode in a trench of a trench capacitor element are formed of the same conductor film.

[0020] Further, in the semiconductor device of another embodiment, the control gate electrode of the MONOS memory and the upper electrode formed so as to form a trench capacitor element and fill the inside of the trench are formed by the same layer of film.

[0021] According to the embodiments, it is possible to improve the reliability of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0022] FIG. 1 is a cross-sectional view of the semiconductor device of the first embodiment during a manufacturing step;

[0023] FIG. 2 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 1

[0024] FIG. 3 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 2

[0025] FIG. 4 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 3

[0026] FIG. 5 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 4

[0027] FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 5

[0028] FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 6

[0029] FIG. 8 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 7

[0030] FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 8

[0031] FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 9

[0032] FIG. 11 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 10

[0033] FIG. 12 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 11 ​​​​​​​​​​Cross-sectional view during a subsequent manufacturing step;

[0034] FIG. 13 is a semiconductor device during a manufacturing step; FIG. 12 Cross-sectional view during a subsequent manufacturing step;

[0035] FIG. 14 is a semiconductor device during a manufacturing step; FIG. 13 Cross-sectional view during a subsequent manufacturing step;

[0036] FIG. 15 is a semiconductor device during a manufacturing step; FIG. 14 Cross-sectional view during a subsequent manufacturing step;

[0037] FIG. 16 is a semiconductor device during a manufacturing step; FIG. 15 Plan view during a subsequent manufacturing step;

[0038] FIG. 17 is a semiconductor device during a manufacturing step; FIG. 15 Cross-sectional view during a subsequent manufacturing step;

[0039] FIG. 18 is a semiconductor device during a manufacturing step;

[0040] FIG. 19 is a semiconductor device during a manufacturing step; FIG. 18 Cross-sectional view during a subsequent manufacturing step;

[0041] FIG. 20 is a semiconductor device during a manufacturing step;

[0042] FIG. 21 is a semiconductor device during a manufacturing step;

[0043] FIG. 22 is a semiconductor device during a manufacturing step;

[0044] FIG. 23 is a semiconductor device during a manufacturing step;

[0045] FIG. 24 is a semiconductor device during a manufacturing step; FIG. 23 Cross-sectional view during a subsequent manufacturing step;

[0046] FIG. 25 is a semiconductor device during a manufacturing step; FIG. 24 Cross-sectional view during a subsequent manufacturing step;

[0047] FIG. 26is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 25 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0048] FIG. 27 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 26 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0049] FIG. 28 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0050] FIG. 29 is a planar layout of the semiconductor device during a manufacturing step after

[0051] FIG. 30 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 28 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0052] FIG. 31 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0053] FIG. 32 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 31 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0054] FIG. 33 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 32 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0055] FIG. 34 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 33 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0056] FIG. 35 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 34 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0057] FIG. 36 is a cross-sectional view of the semiconductor device during a manufacturing step after FIG. 35 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0058] FIG. 37 is a planar layout of the semiconductor device during a manufacturing step after

[0059] FIG. 38 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0060] FIG. 39 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0061] FIG. 40 is a cross-sectional view of the semiconductor device during a manufacturing step after

[0062] FIG. 41 is a table showing an example of conditions under which voltages are applied to respective positions of selected memory cells at the time of "writing", "erasing", and "reading out". DETAILED DESCRIPTION

[0063] Hereinafter, each of the embodiments will be described in detail with reference to the corresponding drawings. Incidentally, in all the drawings used to describe each of the embodiments, components having the same function are denoted by the same reference characters and numerals, and repeated explanation thereof will be omitted. Further, in each of the embodiments below, explanation of the same or similar parts will be omitted in principle except when particularly required.

[0064] First Embodiment

[0065] Each of the semiconductor devices of the present embodiment and the following embodiments is a semiconductor device including a nonvolatile memory (a nonvolatile memory element, a flash memory, or a nonvolatile semiconductor memory device) and a capacitor element. In the present embodiment and the following embodiments, a nonvolatile memory will be described with reference to a memory cell based on an n-channel MISFET (MISFET: Metal Insulator Semiconductor Field Effect Transistor).

[0066] Further, the polarity (the polarity of each of the applied voltages and the polarity of the carrier for writing / erasing / reading out) in the present embodiment and the following embodiments is used to describe the operation in the case of a memory cell based on an n-channel MISFET. When the memory cell is based on a p-channel MISFET, the same operation can be obtained in principle by reversing the polarity of all the applied potentials, the conduction type of the carrier, and the like.

[0067] <Method for manufacturing semiconductor device>

[0068] The method for manufacturing a semiconductor device of the present embodiment will be described with reference to FIGS. 1-17

[0069] FIGS. 1-15 and FIG. 17 Each of the cross-sectional views in Figs. 1A to 1C is a cross-sectional view of the semiconductor device of the present embodiment during the manufacturing steps. FIG. 16 Fig. 1D is a plan layout of the semiconductor device of the present embodiment during the manufacturing steps. FIGS. 1-15 and FIG. 17 ​Each of FIGS. 1A to 1C sequentially shows a cross-sectional view of a memory cell region 1A, a peripheral circuit region 1B, and a capacitor element region 1C from the left side to the right side of each drawing. The respective drawings show how to form a memory cell of a nonvolatile memory in the memory cell region 1A, how to form a low-breakdown-voltage MISFET in the peripheral circuit region 1B, and how to form a trench-type capacitor element in the capacitor element region 1C, respectively. The memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C are regions arranged in a direction along a main surface of a semiconductor substrate.

[0070] Incidentally, the operation of the nonvolatile memory also requires a high-breakdown-voltage MISFET. However, the high-breakdown-voltage MISFET is not different from the low-breakdown-voltage MISFET, except that the gate insulating film of the high-breakdown-voltage MISFET is the same in film thickness as the insulating film of the trench-type capacitor element, and except that various implementation conditions can be different for respective optimizations. Therefore, the following description of the high-breakdown-voltage MISFET will be omitted in principle.

[0071] Here, a case where an n-channel type MISFET (control transistor and memory transistor) is formed in the memory cell region 1A will be described. However, by reversing the conductivity type, a p-channel type MISFET (control transistor and memory transistor) can also be formed in the memory cell region 1A.

[0072] Similarly, here, a case where an n-channel type MISFET is formed in the peripheral circuit region 1B will be described. However, by reversing the conductivity type, a p-channel type MISFET can also be formed in the peripheral circuit region 1B. Alternatively, both an n-channel type MISFET and a p-channel type MISFET, that is, a CMISFET (complementary metal insulator semiconductor), can also be formed in the peripheral circuit region 1B.

[0073] Similarly, here, a case where a capacitor element is formed in the capacitor element region 1C will be described, the capacitor element including a lower electrode (first electrode) including an n-type well in a main surface of a semiconductor substrate, and an upper electrode (second electrode) formed by an n-type semiconductor film formed on the semiconductor substrate. However, a capacitor element including a lower electrode including a p-type well, and an upper electrode formed by a p-type semiconductor film can also be formed.

[0074] In the manufacturing steps of the semiconductor device, first, as shown in FIG. 1A, a p-type well 2 is formed in a main surface of a semiconductor substrate 1. Next, as shown in FIG. 1B, an n-type well 3 is formed in the p-type well 2. Next, as shown in FIG. 1C, a trench-type capacitor element 4 is formed in the n-type well 3. Next, as shown in FIG. 1D, a low-breakdown-voltage MISFET 5 is formed in the p-type well 2. Next, as shown in FIG. 1E, a memory cell of a nonvolatile memory 6 is formed in the n-type well 3. FIG. 1As shown, a semiconductor substrate (semiconductor wafer) SB is prepared, which is formed of, for example, P-type single-crystal silicon (Si) having a specific resistance of about 1 Ωcm to 10 Ωcm. Subsequently, for example, heat treatment is performed to form an insulating film IF1 formed of a silicon oxide film over the entire main surface of the semiconductor substrate SB. Then, an insulating film IF2 formed of, for example, a silicon nitride film is formed over the insulating film IF1 by using, for example, a CVD (Chemical Vapor Deposition) method.

[0075] Then, as shown in FIG. 1B, the insulating film IF2 and the insulating film IF1, and the top surface of the semiconductor substrate SB are partially removed by using a photolithography technique and a dry etching method. In other words, openings are formed through the laminated film formed of the insulating film IF2 and the insulating film IF1 at a plurality of portions. Thereby, a portion of the top surface of the semiconductor substrate SB directly below the openings is removed. As a result, a plurality of trenches (recesses or depressions) D1 and a plurality of trenches D2 are formed in the top surface of the semiconductor substrate SB. The trenches D1 are formed in the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C, respectively, and the trenches D2 are formed only in the capacitor element region 1C. FIG. 2 Each of the trenches D2 extends in a first direction along the main surface of the semiconductor substrate SB. The plurality of trenches D2 are arranged side by side along the main surface of the semiconductor substrate SB and in a second direction orthogonal to the first direction. In other words, the plurality of trenches D2 are formed in a strip shape. Incidentally, the layout of the trenches D2 is not limited to the strip shape, but can have a dot shape, a parallel cross shape, or the like.

[0076] The trenches D1 and D2 are recesses formed in the same step and reach a depth at a certain halfway of the semiconductor substrate SB. At this time, the top surface of the semiconductor substrate SB adjacent to the trenches D1 and the top surface of the semiconductor substrate SB adjacent to the trenches D2 are located at the same height. Here, it can be considered that a corner of a boundary between a bottom surface and a side wall of each of the trenches D1 and D2 has a roundness. However, the roundness of the corner is small.

[0077] Incidentally, here, the insulating film IF2 and the insulating film IF1, and the semiconductor substrate SB are processed by one etching step, respectively. However, the following steps are also acceptable: for example, after the insulating film IF2 is processed by a dry etching method, the insulating film IF1 is processed by a wet etching; as a result, the top surface of the semiconductor substrate SB is exposed; subsequently, the trenches D1 and D2 are formed by using a dry etching method.

[0078] Then, as shown in FIG. 1C, a conductive film 10 is formed over the semiconductor substrate SB. The conductive film 10 is formed of, for example, a polysilicon film. The conductive film 10 is formed by using, for example, a CVD method. The conductive film 10 is formed so as to fill the trenches D1 and D2. In other words, the conductive film 10 is formed so as to cover the top surface of the semiconductor substrate SB and the side walls of the trenches D1 and D2. The conductive film 10 is formed so as to have a thickness of, for example, about 100 nm to 300 nm.

[0079] FIG. 3 ​As shown, the corresponding sidewalls of trenches D1 and D2 are oxidized. Then, a silicon oxide film is formed on the semiconductor substrate SB using, for example, a CVD method, and this silicon oxide film completely fills the corresponding interiors of trenches D1 and D2. Subsequently, a heat treatment is performed to densify the silicon oxide film. Then, the top surface of the silicon oxide film is polished by a CMP (chemical mechanical polishing) method, thereby exposing the top surface of the insulating film IF2. As a result, the silicon oxide films embedded in the corresponding interiors of the multiple trenches D1 and D2 are separated from each other.

[0080] Then, the top surface of the silicon oxide film is etched back, thereby retracting it. However, the height of each top surface of the silicon oxide film embedded within the respective trenches D1 and D2 is higher than the position of the main surface of the semiconductor substrate SB. In each trench D1, a device isolation region EI formed by the silicon oxide film is formed. In each trench D2, a dummy device isolation region DEI formed by the silicon oxide film is formed. The dummy device isolation region DEI is an insulating film to be removed in a later step.

[0081] Then, as FIG. 4 As shown, a photoresist film PR1 is patterned on a semiconductor substrate SB using photolithography. The photoresist film PR1 is a mask pattern that covers the memory cell region 1A and the peripheral circuit region 1B, and partially exposes the capacitor element region 1C. In the capacitor element region 1C, the element isolation region EI is covered by the photoresist film PR1, and the dummy element isolation region DEI is exposed from the photoresist film PR1. The photoresist film PR1 terminates directly above the insulating film IF1 between the adjacent element isolation regions EI and the dummy element isolation region DEI in the capacitor element region 1C.

[0082] Then, as FIG. 5 As shown, in the state where the device isolation region EI is covered by the photoresist film PR1, dry etching is performed by using the photoresist film PR1 and insulating films IF1 and IF2 as masks. As a result, the dummy device isolation region DEI is removed. Then, the photoresist film PR1 is removed by ashing or the like. However, the etching step removes the insulating films IF1 and IF2, which serve as masks in the region near the area between adjacent trenches D2 in trench D2. Therefore, the top surface of the semiconductor substrate SB in this region is exposed. In this embodiment, the dummy device isolation region DEI is removed, and the sidewalls and bottom surface of trench D2 are exposed. Therefore, the dummy device isolation region DEI can be regarded as a pseudo device isolation region.

[0083] The insulating films IF1 and IF2 in the vicinity of the trench D2 are removed. As a result, the corner portion of the interface between the side wall of the trench D2 and the main surface of the semiconductor substrate SB in this range is cut and rounded by etching. However, the central portion of the bottom surface of the trench D2 in the direction along the main surface of the semiconductor substrate SB (which can be referred to as the lateral direction hereinafter) is more easily etched than the end portion of the bottom surface near the side wall of the trench D2. Therefore, the corner portion of the interface between the side wall and the bottom surface of the trench D2 is greatly rounded, so that the surface between the side wall and the bottom surface of the trench D2 is smoothly connected.

[0084] Therefore, the corner portion of the bottom surface of the trench D2 is more rounded than the corner portion of the bottom surface of the trench D1. Meanwhile, the corner portion of the upper end of the side wall of the trench D2 is more rounded than the corner portion of the upper end of the side wall of the trench D1. In other words, the radius of curvature of the corner portion of the bottom surface end of the trench D2 is larger than the radius of curvature of the corner portion of the bottom surface end of the trench D1. Meanwhile, the radius of curvature of the corner portion of the upper end of the side wall of the trench D2 is larger than the radius of curvature of the corner portion of the upper end of the side wall of the trench D1.

[0085] Further, by the etching step, the top surface of the semiconductor substrate SB between the adjacent trenches D2 is etched back, and thereby the main surface of the semiconductor substrate SB in this region is lower in height than in other regions (for example, the region adjacent to the trench D1). Similarly, the bottom surface of the trench D2 is etched back by the etching step. Therefore, the height of the bottom surface of the trench D2 is lower than the height of the bottom surface of the trench D1. In other words, the trench D2 is deeper than the trench D1.

[0086] In other words, with reference to the position of the main surface of the semiconductor substrate SB between the adjacent trenches D1 in the memory cell region 1A, the top surface of the semiconductor substrate SB between the adjacent trenches D2 is located below the reference position in the direction perpendicular to the main surface of the semiconductor substrate SB (which can be simply referred to as the vertical direction hereinafter). However, the distance in the vertical direction between the reference position and the position of the bottom surface of the trench D2 is larger than the distance in the vertical direction between the reference position and the position of the bottom surface of the trench D1. In other words, the position of the main surface of the semiconductor substrate SB in the vicinity of the trench D2 is lower than the position of the main surface of the semiconductor substrate SB in the vicinity of the trench D1; and the position of the bottom surface of the trench D2 is lower than the position of the bottom surface of the trench D1.

[0087] Incidentally, the layer laminate of the insulating films IF1 and IF2 exposed from the photoresist film PR1 in the vicinity of the photoresist film PR1 (see FIG. 4The insulating film IF2, located at the point where the photoresist film PR1 is exposed between the adjacent device isolation regions EI and DEI, is not completely removed, its thickness is reduced, and it remains after the etching. This is because performing the dry etching step under these conditions makes it easier to remove the dummy device isolation regions DEI formed by the silicon oxide film and more difficult to remove the insulating film IF2 formed by the silicon nitride film.

[0088] Here, for example, near the photoresist film PR1, the top surface of the insulating film IF2, formed of silicon nitride, in the area exposed from the photoresist film PR1, is moved back, but a portion of the insulating film IF2 in that area is retained. In this case, the insulating films IF2 and IF1 protect the top surface of the semiconductor substrate SB between the adjacent element isolation regions EI and dummy element isolation regions DEI from dry etching. Therefore, damage to the top surface can be prevented.

[0089] Furthermore, in the dry etching used to remove the dummy element isolation region DEI in trench D2, insulating films IF2 and IF1 are used as masks. Thus, etching is stopped when the dummy element isolation region DEI and insulating films IF1 and IF2 near trench D2, exposed from the photoresist film PR1, have been removed in capacitor element region 1C. Therefore, for most of the etching time, the top surface of the semiconductor substrate SB between adjacent trenches D2 is protected by insulating films IF2 and IF1. As a result, the top surface of the semiconductor substrate SB between adjacent trenches D2 can be prevented from being damaged by dry etching.

[0090] Then, as FIG. 6 As shown, the insulating film IF2 is selectively removed by wet etching. In other words, first, sacrificial oxidation is performed to form an oxide film on the sidewalls and bottom surface of trench D2. Then, a cleaning process is performed. As a result, the oxide film covering the sidewalls of trench D2 is retained, and the silicon oxide film (not shown) on top of the insulating film IF2 is removed. Subsequently, the insulating film IF2 is removed by thermal phosphoric acid.

[0091] Subsequently, a cleaning process is performed to remove the sacrificial oxide film covering the side walls and the bottom surface of the trench D2, and the insulating film IF1 covering the main surface of the semiconductor substrate SB. As a result, the main surface of the semiconductor substrate SB is exposed. In other words, the surface of the semiconductor substrate SB, except for the side walls and the bottom surface of the trench Dl covered by the element isolation region El, is exposed. Then, a sacrificial oxidation is performed to form a thin sacrificial oxide film (not shown) covering the surface of the semiconductor substrate SB.

[0092] Then, ion implantation is performed to form p-type wells WLl and WL2, and a p-type well WL3 in the main surface of the semiconductor substrate SB in the memory cell region IA, the peripheral circuit region IB, and the capacitor element region IC, respectively. Here, the wells WLl and WL2 are formed by implanting a p-type impurity (e.g., B (boron)) at a low concentration. Here, the well WL3 is formed by implanting an n-type impurity (e.g., As (arsenic) or P (phosphorus)) at a low concentration. Incidentally, although not shown and not specifically described, in the region where the p-type well MISFET is formed, an n-type impurity (e.g., As (arsenic) or P (phosphorus)) is ion implanted into the main surface of the semiconductor substrate SB to form an n-type well.

[0093] The respective formation depths of the wells WLl, WL2, and WL3 are deeper than the formation depths of the trenches Dl and D2. Here, the wells WLl, WL2, and WL3 are formed by different ion implantation steps by using a photolithography technique, respectively, to allow the wells WLl, WL2, and WL3 to have different impurity concentrations. Subsequently, the semiconductor substrate SB is heat treated to diffuse the impurities in the wells WLl, WL2, and WL3. Then, the thin sacrificial oxide film is removed. As a result, the main surface of the semiconductor substrate SB, and the side walls and the bottom surface of the trench D2 are exposed.

[0094] Subsequently, the following steps are performed. As a result, the respective top surfaces of the memory cell region IA, the peripheral circuit region IB, and the capacitor element region IC are covered by an insulating film formed of a silicon oxide film. However, the insulating film IF3 formed in the memory cell region IA and the peripheral circuit region IB is different in film thickness from the insulating film IF4 formed in the capacitor element region IC. The film thickness of the insulating film IF4 is, for example, 15 nm.

[0095] That is, the exposed surface of the semiconductor substrate SB is oxidized, resulting in formation of the insulating film IF4 having a larger film thickness. As a result, the sidewalls and the bottom surface of the trench D2 are covered with the insulating film IF4 in addition to the main surface of the semiconductor substrate SB. The insulating film IF4 is formed by, for example, an ISSG (in-situ steam generation) oxidation method, that is, a thermal oxidation method. Then, the insulating film IF4 in the memory cell region 1A and the peripheral circuit region 1B is removed by using a photolithography technique and an etching method. As a result, the main surface of the semiconductor substrate SB in the memory cell region 1A and the peripheral circuit region 1B is exposed.

[0096] Subsequently, a thermal oxidation or the like is performed, thereby forming the insulating film IF3 having a smaller film thickness at the exposed top surface of the semiconductor substrate SB. As a result, the respective top surfaces of the semiconductor substrate SB in the memory cell region 1A and the peripheral circuit region 1B are covered with the insulating film IF3. In this way, it is possible to form the insulating films having different thicknesses in the memory cell region 1A and the peripheral circuit region 1B and in the capacitor element region 1C, respectively.

[0097] Subsequently, the polysilicon film PS1 is formed over the entire main surface of the semiconductor substrate SB by using, for example, a CVD method. As a result, the respective top surfaces of the insulating films IF3 and IF4 are covered with the polysilicon film PS1. In this step, the film thickness of the polysilicon film PS1 is large enough with respect to the width in the lateral direction of the trench D2. Therefore, the trench D2 is completely covered with the insulating film IF4 and the polysilicon film PS1. In addition, the top surface of the polysilicon film PS1 is hardly recessed directly above the trench D2. In other words, the inside of the trench D2 is filled with the polysilicon film PS1 via the insulating film IF4. Then, the insulating film IF5 formed of a silicon nitride film is formed over the polysilicon film PS1 by using, for example, a CVD method.

[0098] Here, the following steps are also possible: during deposition, the polysilicon film PS1 is formed as an amorphous silicon film; then, the amorphous silicon film is changed to the polysilicon film PS1 formed of a polysilicon film by a subsequent heat treatment. The polysilicon film PS1 is not doped with impurities during deposition. After deposition, impurity ions are injected. The impurities are diffused by a subsequent heat treatment, thereby producing a low-resistance semiconductor film.

[0099] The impurities injected by the ion injection step can also be diffused into the polysilicon film PS1 in the trench D2 by a heat treatment. In other words, the impurities can also be doped into the polysilicon film PS1 at the bottom of the inside of the trench D2. Therefore, when the capacitor element including the upper electrode including the polysilicon film PS1 in the trench D2 is formed in a later step, it is possible to prevent formation of a depletion layer in the upper electrode of the trench D2.

[0100] Here, n-type impurities (e.g., As (arsenic) or P (phosphorus)) are implanted into the polysilicon film PS1 in the capacitor element region 1C. This is for the purpose of making the conductivity type uniform between the lower electrode formed of the well WL3 in the top surface of the semiconductor substrate SB and the upper electrode formed of the polysilicon film PS1 directly above the lower electrode when the capacitor to be formed later is formed. In this way, in the present embodiment, an n-type capacitor element is formed. However, when a p-type capacitor element is formed, the well WL3 is formed as a p-type semiconductor region, and the polysilicon film PS1 is made into a p-type semiconductor film by ion implantation.

[0101] The polysilicon film PS1 partially fills the trench D2. However, the polysilicon film PS1 has a film thickness large enough. Therefore, no large undercuts are formed in the top surface of the polysilicon film PS1 directly above the trench D2.

[0102] Then, as shown in FIG. 6, the insulating film IF5, the polysilicon film PS1, and the insulating film IF3 in the memory cell region 1A are processed by using a photolithography technique and an etching method. This results in formation of the control gate electrode CG formed of the polysilicon film PS1, and the gate insulating film GIl formed of the insulating film IF3. Incidentally, the following steps are also possible: first, the insulating film IF5 in the memory cell region 1A is processed by using a photolithography technique and a dry etching method; then, the polysilicon film PS1 and the insulating film IF3 in the memory cell region 1A are processed with the insulating film IF5 serving as a mask. FIG. 7 Alternatively, here, the following steps are also possible: the polysilicon film PS1 in the peripheral circuit region IB and the capacitor element region 1C is not processed; however, the polysilicon film PS1 in the capacitor element region 1C is processed in the etching step. When the polysilicon film PS1 in the capacitor element region 1C is processed, as described later with reference to FIG. 8, the portion of the polysilicon film PS1 in and near the trench D2 is left, and the portion of the polysilicon film PS1 aside from the trench D2 is removed.

[0103] FIG. 10 Alternatively, here, the following steps are also possible: the polysilicon film PS1 in the peripheral circuit region IB and the capacitor element region 1C is not processed; however, the polysilicon film PS1 in the capacitor element region 1C is processed in the etching step. When the polysilicon film PS1 in the capacitor element region 1C is processed, as described later with reference to FIG. 8, the portion of the polysilicon film PS1 in and near the trench D2 is left, and the portion of the polysilicon film PS1 aside from the trench D2 is removed.

[0104] Then, as shown in FIG. 6, the insulating film IF5, the polysilicon film PS1, and the insulating film IF3 in the memory cell region 1A are processed by using a photolithography technique and an etching method. This results in formation of the control gate electrode CG formed of the polysilicon film PS1, and the gate insulating film GIl formed of the insulating film IF3. Incidentally, the following steps are also possible: first, the insulating film IF5 in the memory cell region 1A is processed by using a photolithography technique and a dry etching method; then, the polysilicon film PS1 and the insulating film IF3 in the memory cell region 1A are processed with the insulating film IF5 serving as a mask. FIG. 8

[0105] ​​Here, the lamination structure of the lamination film forming the ONO film ON is not shown for easy understanding of the drawing. In other words, here, the boundary between the respective films forming the ONO film ON is not shown. The ONO film ON is an insulating film having a charge accumulation portion inside thereof. Specifically, the ONO film ON is formed of a lamination film of a first silicon oxide film (a bottom oxide film) formed over the semiconductor substrate SB, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film (a top oxide film) formed over the silicon nitride film. The silicon nitride film serves as the charge accumulation portion.

[0106] The first silicon oxide film and the second silicon oxide film can be formed by, for example, an oxidation treatment (thermal oxidation treatment) or a CVD method or a combination thereof. In this step, oxidation can also be performed using ISSG oxidation. The silicon nitride film can be formed by, for example, a CVD method. The thickness of each of the first silicon oxide film and the second silicon oxide film can be set to, for example, about 2 nm to 10 nm. The thickness of the silicon nitride film can be set to, for example, about 5 nm to 15 nm.

[0107] Subsequently, a polysilicon film PS2 is formed over the entire main surface of the semiconductor substrate SB in a manner covering the surface of the ONO film ON by using, for example, a CVD method. As a result, the side wall and the top surface of the ONO film ON exposed in the memory cell region 1A are covered with the polysilicon film PS2. In other words, the polysilicon film PS2 is formed via the ONO film ON at the side wall of the control gate electrode CG. The film thickness of the polysilicon film PS2 is smaller than the film thickness of the polysilicon film PS1.

[0108] The polysilicon film PS2 can also be formed in the following manner. The film is formed as an amorphous silicon film during deposition, and made into a polysilicon film by a subsequent heat treatment. The polysilicon film PS2 is, for example, a film doped with an n-type impurity (for example, phosphorus (P)) at a higher concentration. The polysilicon film PS2 is a film used for forming the memory gate electrode MG described later.

[0109] The film thickness referred to here indicates, in the case of a particular film, the thickness of the film in a direction perpendicular to the surface of an underlying layer. For example, when the polysilicon film PS2 is formed over a surface along the main surface of the semiconductor substrate SB and along a surface such as the top surface of the ONO film ON, the film thickness of the polysilicon film PS2 indicates the film thickness of the polysilicon film PS2 in a direction perpendicular to the main surface of the semiconductor substrate SB. However, in the case where the polysilicon film PS2 is formed in contact with a wall perpendicular to the main surface of the semiconductor substrate SB such as a side wall of the ONO film ON at a portion thereof, the film thickness of the polysilicon film PS2 indicates the thickness of the polysilicon film PS2 in a direction perpendicular to the side wall.

[0110] Then, as FIG. 9As shown, the polysilicon film PS2 is etched back by a dry etching method, thereby exposing a top surface of the ONO film ON. In the etch-back step, the polysilicon film PS2 is anisotropically etched (etched back). As a result, the polysilicon film PS2 is left in a sidewall shape over each of the opposite sidewalls of the laminated film formed by the gate insulating film GIl, the control gate electrode CG, and the insulating film IF5 via the ONO film ON.

[0111] This results in formation of a memory gate electrode MG formed of the polysilicon film PS2 left in a sidewall shape at one of the sidewalls of the laminated film in the memory cell region IA via the ONO film ON. The etch-back exposes the top surface of the ONO film ON in the peripheral circuit region IB and the capacitor element region IC. The film thickness of the polysilicon film PS2 is smaller than the film thickness of the polysilicon film PS 1. Therefore, the film thickness (gate length) of the memory gate electrode MG formed of the polysilicon film PS2 in contact with the sidewall of the control gate electrode CG in the lateral direction is smaller than the film thickness of the control gate electrode CG formed of the polysilicon film PS 1 in the vertical direction.

[0112] Subsequently, a photoresist pattern (not shown) is formed over the semiconductor substrate SB by using a photolithography technique, which covers the memory gate electrode MG adjacent to one sidewall of the control gate electrode CG and exposes the polysilicon film PS2 adjacent to the other sidewall of the control gate electrode CG. Then, etching is performed by using the photoresist pattern as an etching mask, which removes the polysilicon film PS2 formed across the control gate electrode CG opposite to the memory gate electrode MG. Then, the photoresist pattern is removed. In this step, the memory gate electrode MG is covered with the photoresist pattern and thus left without being etched.

[0113] Subsequently, a portion of the ONO film ON not covered by the memory gate electrode MG and exposed is removed by etching (e.g., wet etching). In this step, in the memory cell region IA, a portion of the ONO film ON directly below the memory gate electrode MG is left without being removed. Similarly, a portion of the ONO film ON between the memory gate electrode MG and the laminated film including the gate insulating film GIl, the control gate electrode CG, and the insulating film IF5 is left without being removed. A portion of the ONO film ON in other regions is removed. Therefore, a top surface of the semiconductor substrate SB in the memory cell region IA is exposed. However, a top surface of the insulating film IF5 in the memory cell region IA, the peripheral circuit region IB, and the capacitor element region IC is exposed. Further, a sidewall of the control gate electrode CG not adjacent to the memory gate electrode MG is exposed.

[0114] In this manner, the memory gate electrode MG is formed on the semiconductor substrate SB via an ONO film ON having a charge accumulation portion therein, adjacent to the control gate electrode CG.

[0115] Then, as FIG. 10 As shown, polysilicon film PS1 and insulating films IF3, IF4, and IF5 are patterned in peripheral circuit region 1B and capacitor element region 1C using photolithography and etching techniques. As a result, a dummy gate electrode DG formed by polysilicon film PS1 and a gate insulating film GI2 formed by insulating film IF3 are formed in peripheral circuit region 1B. Simultaneously, an upper electrode UE formed by polysilicon film PS1 is formed in capacitor element region 1C. Further, in capacitor element region 1C, the insulating film IF4 on the semiconductor substrate SB in the area exposed from the upper electrode UE is removed. As a result, the main surface of semiconductor substrate SB between adjacent element isolation regions EI is exposed in capacitor element region 1C.

[0116] The dummy gate electrode DG is a semiconductor film to be removed in a later step. A laminate consisting of a gate insulating film GI2, a dummy gate electrode DG, and an insulating film IF5 is formed on the main surface of the semiconductor substrate SB between adjacent element isolation regions EI.

[0117] Then, as FIG. 11 As shown, multiple n-type electrons are formed by using methods such as ion implantation. - The n-type semiconductor region (impurity diffusion region) EX. That is, using insulating films IF4 and IF5, the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG, the ONO film ON, and the top electrode UE as masks (ion implantation suppression masks), n-type impurities (such as arsenic (As) or phosphorus (P)) are doped into the main surface of the semiconductor substrate SB via ion implantation. As a result, multiple n-type impurities are formed. - Type semiconductor region EX. In forming n - Before the semiconductor region EX, there are offset spacers covering the sidewalls of the structure formed by the control gate electrode CG and the memory gate electrode MG, as well as the corresponding sidewalls of the dummy gate electrode DG, which can be formed, for example, by a silicon nitride film or a silicon oxide film or a laminate thereof.

[0118] In memory cell region 1A, n is formed on the top surface of this portion of the semiconductor substrate SB, which is located on the side of the structure including the control gate electrode CG and the memory gate electrode MG. -n-type semiconductor regions EX pair, respectively formed in portions of source / drain regions of control transistors and memory transistors in a memory cell region 1A formed later. In a peripheral circuit region 1B, n - n-type semiconductor regions EX pair, respectively formed in portions of source / drain regions of MISFETs in the peripheral circuit region 1B formed later. In the memory cell region 1A and the peripheral circuit region 1B, corresponding n - n-type semiconductor regions EX pair, respectively formed in portions of source / drain regions of MISFETs in the peripheral circuit region 1B formed later. In the memory cell region 1A and the peripheral circuit region 1B, corresponding n

[0119] Subsequently, side walls SW are formed which cover the side walls on opposite sides of a structure including the control gate electrode CG, the memory gate electrode MG, the gate insulating film GIl, the insulating film IF5 and the ONO film ON in the memory cell region 1A. However, by the same step, the side walls SW are formed in the peripheral circuit region 1B which cover the side walls on opposite sides of a laminate film formed by the gate insulating film GI2, the insulating film IF5 and the dummy gate electrode DG. Further, by the same step, the side walls SW are formed in the capacitor element region 1C which cover the side walls on opposite sides of a laminate film including the upper electrode UE and the insulating films IF4 and IF5.

[0120] The side walls SW can be formed in a self-aligned manner in the following manner: by sequentially forming a silicon oxide film and a silicon nitride film over the semiconductor substrate SB by using, for example, a CVD method; and then, partially removing the silicon oxide film and the silicon nitride film by anisotropic etching so as to expose the top surface of the semiconductor substrate SB and the top surface of the insulating film IF5. In other words, it can be considered that the side walls SW are formed by a laminate film. However, in the drawings, the boundaries between the respective films of the laminate film are not shown. Incidentally, the formation method of the laminate film can be improved so as to provide an optimum side wall width for the respective element characteristics. However, the description thereof is omitted.

[0121] Subsequently, a plurality of n + type semiconductor regions (impurity diffusion regions) DF are formed in the memory cell region 1A, the peripheral circuit region 1B and the capacitor element region 1C by using an ion implantation method or the like. That is, by the ion implantation method, n + type semiconductor regions DF are formed in the memory cell region 1A, the peripheral circuit region 1B and the capacitor element region 1C by using an ion implantation method or the like. That is, by the ion implantation method, n +The n-type semiconductor region DF has a higher impurity concentration than the n-type semiconductor region EX, and has a larger junction depth (formation depth) than the n-type semiconductor region EX. - The n-type semiconductor region DF has a higher impurity concentration than the n-type semiconductor region EX, and has a larger junction depth (formation depth) than the n-type semiconductor region EX. - The n-type semiconductor region DF has a higher impurity concentration than the n-type semiconductor region EX, and has a larger junction depth (formation depth) than the n-type semiconductor region EX. Incidentally, the n-type semiconductor region DF can be formed to have a smaller junction depth than the n-type semiconductor region EX. + The n-type semiconductor region DF has a higher impurity concentration than the n-type semiconductor region EX, and has a larger junction depth (formation depth) than the n-type semiconductor region EX. Incidentally, the n-type semiconductor region DF can be formed to have a smaller junction depth than the n-type semiconductor region EX. - The n-type semiconductor region DF has a higher impurity concentration than the n-type semiconductor region EX, and has a larger junction depth (formation depth) than the n-type semiconductor region EX. Incidentally, the n-type semiconductor region DF can be formed to have a smaller junction depth than the n-type semiconductor region EX.

[0122] This results in the formation of source / drain regions in the memory cell region 1A and the peripheral circuit region 1B, which are formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures. - The n-type semiconductor region DF has a higher impurity concentration than the n-type semiconductor region EX, and has a larger junction depth (formation depth) than the n-type semiconductor region EX. - The n-type semiconductor region DF has a higher impurity concentration than the n-type semiconductor region EX, and has a larger junction depth (formation depth) than the n-type semiconductor region EX. + The n-type semiconductor region DF has a higher impurity concentration than the n-type semiconductor region EX, and has a larger junction depth (formation depth) than the n-type semiconductor region EX. Incidentally, the n-type semiconductor region DF can be formed to have a smaller junction depth than the n-type semiconductor region EX.

[0123] The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures. + The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures. + The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures. + The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures.

[0124] The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures. + The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures. + The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures.

[0125] Subsequently, activation annealing is performed, which is a heat treatment for activating impurities doped into the semiconductor regions (n-type semiconductor regions EX and n-type semiconductor regions DF) for source regions and drain regions, etc. - The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures. + The n-type semiconductor region DF in the portion of the semiconductor substrate SB top surface that is laterally outside the structure including the control gate electrode CG, the memory gate electrode MG, and the sidewall SW in the memory cell region 1A is formed of the n-type semiconductor region EX and the n-type semiconductor region DF, which are formed in the semiconductor substrate SB, and which have LDD (Lightly Doped Drain) structures.

[0126] Subsequently, a silicide layer S1 is formed. The silicide layer S1 can be formed by performing a so-called self-aligned silicide process. Specifically, the silicide layer S1 can be formed in the following manner.

[0127] That is, firstly, on the entire main surface of the semiconductor substrate SB, including n + A metal film for forming a silicide layer S1 is formed (deposited) on the top surface of the semiconductor region DF and on the top surface of the memory gate electrode MG. This metal film can be made of a single metal (pure metal film) or an alloy film. The metal film is formed, for example, of a cobalt (Co) film, a nickel (Ni) film, or a nickel-platinum alloy film, and can be formed using methods such as sputtering.

[0128] Then, the semiconductor substrate SB is subjected to heat treatment (heat treatment for forming the silicide layer S1). As a result, n + The corresponding surface layer portions of the semiconductor region DF and the memory gate electrode MG react with the metal film. This results in... + A silicide layer S1 is formed at the respective top of the semiconductor region DF and the memory gate electrode MG. Then, unreacted portions of the metal film are removed by wet etching or the like, thereby creating a silicide layer on top of the semiconductor region DF and the memory gate electrode MG. FIG. 11 The structure shown in the figure.

[0129] The silicide layer S1 can be formed, for example, as a cobalt silicide layer, a nickel silicide layer, or a nickel-platinum silicide layer. Incidentally, the respective top surfaces of the control gate electrode CG, the dummy gate electrode DG, and the upper electrode UE are covered by the insulating film IF5 of the capping film. Therefore, no silicide layer S1 is formed at the top of each top surface. Incidentally, the top of the memory gate electrode MG, which is sidewall-shaped, is exposed. Therefore, a silicide layer S1 is formed at the exposed portion. However, the silicide layer S1 can be completely removed by a polishing step using a CMP (chemical mechanical polishing) method performed in a later step.

[0130] Then, as FIG. 12 As shown, an interlayer insulating film IF1 is formed over the entire main surface of the semiconductor substrate SB, covering the control gate electrode CG, the memory gate electrode MG, the sidewall SW, the dummy gate electrode DG, and the top electrode UE. The interlayer insulating film IF1 is formed from a single film, such as a silicon oxide film, and can be formed using, for example, a CVD method. Here, the interlayer insulating film IF1 is formed to have a film thickness greater than, for example, the thickness of the control gate electrode CG.

[0131] Then, as FIG. 13As shown, the top surface of the interlayer insulating film IL1 is polished using methods such as CMP. As a result, the respective top surfaces of the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG in the peripheral circuit region 1B, and the upper electrode UE in the capacitor element region 1C are exposed. In other words, in this polishing step, the interlayer insulating film IL1 is polished until the respective top surfaces of the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG, and the upper electrode UE are exposed. As a result, the insulating film IF5 is removed, thereby also partially removing the top of each sidewall SW.

[0132] This step removes the silicide layer S1 above the memory gate electrode MG along with a portion of the top surface of the memory gate electrode MG. Furthermore, in this step, it is difficult to... FIG. 12 Polishing stops when the top surfaces of the dummy gate electrode DG and the control gate electrode CG are exposed from the insulating film IF5. Therefore, as shown... FIG. 13 As shown, polishing removes the corresponding top surfaces of the dummy gate electrode DG, control gate electrode CG, and upper electrode UE, thereby causing them to recede. In other words, polishing reduces the corresponding film thicknesses of the dummy gate electrode DG, control gate electrode CG, and upper electrode UE.

[0133] As a result, the top of each electrode is retracted through a polishing step. Therefore, a memory cell MC is formed in the memory cell region 1A, the memory cell MC including a control gate electrode CG and a memory gate electrode MG, and source / drain regions formed in the main surface of the semiconductor substrate SB to its side. That is, in the memory cell region 1A, the control gate electrode CG and the source / drain regions formed in the top surface of the semiconductor substrate SB to the side of the control gate electrode CG form a control transistor. The gate insulating film GI1 directly below the control gate electrode CG forms the gate insulating film of the control transistor.

[0134] Furthermore, in memory cell region 1A, a memory gate electrode MG and a source / drain region pair formed in the top surface of the semiconductor substrate SB on the side of the memory gate electrode MG form a memory transistor. The ONO film ON below the memory gate electrode MG forms the gate insulating film of the memory transistor. In this way, the control transistor and the memory transistor have a shared source / drain region pair. The control transistor and the memory transistor form the memory cell MC.

[0135] Furthermore, through a polishing step, the top surface of the upper electrode UE in the capacitor element region 1C is retracted. This results in the formation of a capacitor element CE, which includes the upper electrode UE and a lower electrode formed by a semiconductor substrate SB directly below the upper electrode UE. An insulating film IF4 is interposed between the upper electrode UE and the semiconductor substrate SB. This separates the upper electrode UE from the lower electrode, and they are insulated from each other by the insulating film IF4.

[0136] Even after the polishing step has been performed, the film thickness (gate length) of the memory gate electrode MG in the lateral direction, which is in contact with the sidewall of the control gate electrode CG, is less than the film thickness of the control gate electrode CG in the vertical direction.

[0137] Then, as FIG. 14 As shown, an insulating film IF6 is formed on the interlayer insulating film IL1 using, for example, a CVD method. Then, the insulating film IF6 is processed using photolithography and etching methods. As a result, the insulating film IL6 is retained in the memory cell region 1A and the capacitor element region 1C. In other words, the insulating film IF6 covers the corresponding top surfaces of the control gate electrode CG, the memory gate electrode MG, and the upper electrode UE, and exposes the dummy gate electrode DG. The insulating film IF6 is formed of a silicon oxide film or a silicon nitride film.

[0138] Then, the dummy gate electrode DG is etched and removed. Here, the dummy gate electrode DG is removed by wet etching, for example, with an alkaline aqueous solution, using the insulating film IF6 as a mask to protect the control gate electrode CG, the memory gate electrode MG, and the upper electrode UE. Removing the dummy gate electrode DG results in the formation of a trench (recess or depression) on the gate insulating film GI2. The trench D3 on the gate insulating film GI2 in the peripheral circuit region 1B is the region from which the dummy gate electrode DG has been removed. The sidewalls on each opposite side of the trench D3 are formed by sidewalls SW, and the bottom surface of the trench D3 is formed by the top surface of the gate insulating film GI2.

[0139] Then, as FIG. 15 As shown, an insulating film HK is formed on the semiconductor substrate SB, that is, on the interlayer insulating film IL1, including on the bottom surface and sidewalls of the trench D3. Then, on the semiconductor substrate SB, that is, on the insulating film HK, metal films ME1 and ME2 are sequentially formed as conductive films for the gate electrode in such a way that the trench D3 is completely filled.

[0140] In the formation step of the insulating film HK and the metal film ME1, the inside of the trench D3 is incompletely filled. By forming the metal film ME2 over the metal film ME1, the trench D3 is completely filled. Further, the metal film formed of the metal films ME1 and ME2 is also formed over the interlayer insulating film IL1.

[0141] The insulating film HK is an insulating film for a gate insulating film to be formed in the peripheral circuit region IB. The metal film is a conductor film for a gate electrode. Specifically, the insulating film HK is a film that forms a gate insulating film of a low-breakdown-voltage MISFET to be formed later in the peripheral circuit region IB. The insulating film HK is a film of an insulating material higher in dielectric constant (relative dielectric constant) than any of silicon oxide and silicon nitride, a so-called high-k film (high-dielectric-constant film).

[0142] As the insulating film HK, a metal oxide film such as a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a tantalum oxide film, or a lanthanum oxide film can be used. Further, these metal oxide films can further contain one or both of nitrogen (N) and silicon (Si). The insulating film HK can be formed by, for example, an ALD (atomic layer deposition) method. The film thickness of the insulating film HK is, for example, 1.5 nm. When a high-dielectric-constant film (here, the insulating film HK) is used for a gate insulating film, the physical film thickness of the gate insulating film can be increased more than when a silicon oxide film is used. This can provide an advantage that a leakage current can be reduced.

[0143] As the metal films ME1 and ME2, a metal film such as a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium carbide (TiC) film, a tantalum carbide (TaC) film, a tungsten carbide (WC) film, a tantalum carbonitride (TaCN) film, a titanium (Ti) film, a tantalum (Ta) film, a titanium aluminide (TiAl) film, or an aluminum (Al) film can be used. Incidentally, the metal film referred to here means a conductor film that exhibits metallic conductivity, and is assumed to include not only a single metal film (pure metal film) or an alloy film but also a metal compound film that exhibits metallic conductivity. The metal film can be formed by using, for example, a sputtering method.

[0144] Here, for example, the metal film ME1 is formed of a titanium nitride (TiN) film, and the metal film M2 over the titanium nitride film is formed of an aluminum (Al) film. In this step, the aluminum film is preferably made thicker than the titanium nitride film. The aluminum film is low in resistance, which makes it possible to reduce the resistance of the gate electrode to be formed later.

[0145] Subsequently, unnecessary portions of the metal films ME1 and ME2 and the insulating film HK outside the trench D3 are polished and removed by a CMP method or the like. As a result, the insulating film HK and the metal films ME1 and ME2 are left in the trench TR3. In this step, the insulating film IF6 is also removed. As a result, the respective top surfaces of the control gate electrode CG, the memory gate electrode MG, and the upper electrode UE are exposed. The metal films ME1 and ME2 in the trench D3 over the gate insulating film GI2 embedded in the peripheral circuit region IB form the gate electrode G1.

[0146] As a result, in the peripheral circuit region IB, the low-breakdown-voltage MISFET Q1 is formed. The MISFET Q1 is a field effect transistor having the gate electrode G1 and the source / drain region laterally to the gate electrode G1. The gate insulating film GI2 directly below the gate electrode G1 and the insulating film HK form the gate insulating film of the MISFET Q1. The gate electrode G1 is a metal gate electrode. In the present embodiment, the dummy gate electrode DG is removed, and the dummy gate electrode DG is replaced with the gate electrode G1. Therefore, the dummy gate electrode DG is a pseudo gate electrode, and can be regarded as a gate electrode for replacement.

[0147] Further, in the present embodiment, the metal film is used to form the gate electrode G1. The respective electrode is formed as a metal gate electrode. This can provide an advantage such that it is possible to reduce the size of the transistor element (reduce the thickness of the gate insulating film).

[0148] In the peripheral circuit region IB, the gate electrode G1 is adjacent to the insulating film HK over the gate insulating film GI2 at its bottom surface and the sidewall. In other words, the gate insulating film GI2 and the insulating film HK intervene between the gate electrode G1 and the semiconductor substrate SB; and at least the insulating film HK intervenes between the gate electrode G1 and the sidewall SW.

[0149] Subsequently, over the interlayer insulating film IL1, the insulating film IF7 is formed by using, for example, a CVD method. Then, the insulating film IF7 is processed by using a lithography technique and an etching method. As a result, the insulating film IF7 is left in the peripheral circuit region IB. In other words, the insulating film IF7 covers the top surface of the gate electrode G1, and does not cover the respective top surfaces of the control gate electrode CG, the memory gate electrode MG, and the upper electrode UE. The insulating film IF7 is formed of a silicon oxide film or a silicon nitride film.

[0150] Subsequently, the same process as the process described with reference to FIG. 11The self-aligned silicide process is identical to the steps described. As a result, a silicide layer S2 is formed at the corresponding top surfaces of the control gate electrode CG, memory gate electrode MG, and upper electrode UE exposed from the insulating film IF7. Here, the insulating film IF7 covers the top surface of the gate electrode G1 as follows: In the self-aligned silicide process, when removing the unreacted portion of the metal film after heat treatment, it prevents the gate electrode G1 of the metal gate electrode from being removed along with the metal film. In other words, the insulating film IF7 is a protective film for the gate electrode G1.

[0151] Then, as FIG. 16 and FIG. 17 As shown, this forms an interlayer insulating film, multiple contact plugs, and multiple wiring connections. Incidentally, in... FIG. 16 The planar layout shown only illustrates trenches D1 and D2 in the component isolation region 1C, the upper electrode UE, the component isolation region EI, the well WL3, and n. + The semiconductor region DF and the contact plug CP. Further, in FIG. 16 In the diagram, dashed lines indicate the outlines of trenches D1 and D2, well WL3, and the component isolation region EI at the portion covered by the upper electrode UE. Here, the same dashed lines indicate the outlines of the component isolation region EI and trench D1. FIG. 17 The capacitor element region 1C is along FIG. 16 The cross section of line AA.

[0152] Here, firstly, as FIG. 17 As shown, the interlayer insulating film IL2 covering the entire top surface of the semiconductor substrate SB (including the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C) is formed using, for example, a CVD method. The interlayer insulating film IL2 is formed of, for example, a silicon oxide film and covers the respective top surfaces of the control gate electrode CG, the memory gate electrode MG, the gate electrode G1, the upper electrode UE, the insulating film IF7, and the interlayer insulating film IL1.

[0153] Subsequently, dry etching is performed on the interlayer insulating films IL1, IL2, and IF7 using a photoresist pattern (not shown) formed on the interlayer insulating film IL2 using photolithography as an etching mask. This results in the formation of multiple contact holes (openings or vias) through the interlayer insulating films IL1 and IL2 and multiple contact holes through the interlayer insulating films IL2 and IF7. At the bottom of each contact hole, the n-th layer of the silicide layer S1 on the main surface of the semiconductor substrate SB is... +A portion of the surface of the p-type semiconductor region DF, a portion of the silicide layer S2 above the surface of the control gate electrode CG, a portion of the silicide layer S2 above the surface of the memory gate electrode MG, a portion of the gate electrode G1, a portion of the silicide layer S2 above the surface of the upper electrode UE, and the like are exposed.

[0154] Subsequently, a plurality of conductive contact plugs CP formed of tungsten (W) or the like are formed so as to be coupled to the conductors in the respective contact holes. For example, in order to form the contact plugs CP, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof) is formed on the interlayer insulating film IL2, including inside the contact holes. Then, a main conductor film formed of a tungsten film or the like is formed on the barrier conductor film in such a manner as to completely fill the inside of each contact hole. Then, unnecessary portions of the main conductor film and the barrier conductor film outside the contact holes are removed by a CMP method, a back-etching method, or the like. As a result, the contact plugs CP can be formed. Incidentally, in order to simplify the drawing, the barrier conductor film and the main conductor film (tungsten film) that form the contact plugs CP are integrally shown in FIG. 6. FIG. 17

[0155] The contact plugs CP are formed so as to be respectively electrically coupled to the n + The contact plugs CP are formed so as to be respectively electrically coupled to the n + The top surfaces of the silicide layer S1 above the p-type semiconductor region DF, the silicide layer S2 above the control gate electrode CG, the silicide layer S2 above the memory gate electrode MG, the top surface of the gate electrode G1, the top surface of the silicide layer S2 above the upper electrode UE, and the like are coupled.

[0156] Incidentally, FIG. 17 The cross-sectional view of FIG. 6 does not show the respective contact holes and the contact plugs CP above the control gate electrode CG, the memory gate electrode MG, and the gate electrode G1. In other words, in the region not shown, the contact plugs CP are respectively coupled to the control gate electrode CG, the memory gate electrode MG, and the gate electrode G1 that extend in the gate width direction.

[0157] ​Subsequently, over the interlayer insulating film IL2, including over the contact plugs CP embedded therein, a first wiring layer including first layer wiring Ml is formed. The wiring Ml can be formed by using a so-called single damascene technique. The first wiring layer has an interlayer insulating film IL3, and the first layer wiring Ml passing through the interlayer insulating film IL3. The bottom surface of the wiring Ml is coupled with the top surface of the contact plug CP. Although not shown in subsequent steps, over the first wiring layer, a second wiring layer, a third wiring layer, and so on are sequentially formed to form a laminated wiring layer; then, the semiconductor wafer is singulated by a dicing step, thereby producing a plurality of semiconductor chips.

[0158] The semiconductor device of the present embodiment is manufactured in the manner mentioned so far. Incidentally, here has been explained as an example the so-called high-k last manufacturing method in which the insulating film HK is formed after the dummy gate electrode is removed. However, it is also possible to use the so-called high-k first manufacturing method in which the insulating film HK is formed before the dummy gate electrode is removed. The memory cell MC of the present embodiment uses a high voltage for the write / erase operation. The power supply voltage generation circuit requires a large-scale capacitor element CE for charge accumulation and smoothing. In the capacitor element CE, the portion of the upper electrode UE is embedded in the trench D2, resulting in an increase in the capacitance per unit area. This makes it possible to reduce the size of the semiconductor chip.

[0159] As shown in Fig. 1, in the capacitor element region 1C, a plurality of trenches D2 each including a portion of the upper electrode UE embedded therein, extend in the first direction, respectively, and are arranged side by side with each other in the second direction. The annular trench Dl is formed in the manner of surrounding the region including the plurality of trenches D2 formed therein. In the trench Dl, the annular element isolation region El is formed. In the plan view, the upper electrode UE covers all of the trenches D2 surrounded by the element isolation region El, and covers the end portion of the inside of the annular element isolation region El. FIG. 16 The plurality of contact plugs CP are coupled with the top surface of the upper electrode UE and the top surface of the n + type semiconductor region DF outside the element isolation region El. Each of the contact plugs CP is coupled with the top surface of the upper electrode UE directly above the element isolation region El. In the capacitor element region 1C, the contact plugs CP coupled with the top surface of the n + type semiconductor region DF of the main surface of the semiconductor substrate SB (see

[0160] ), are coupling conductors for supplying a potential to the lower electrode of the capacitor element CE (i.e., the semiconductor substrate SB (well WL3) directly below the upper electrode UE). FIG. 17

[0161] ​In this embodiment, the upper electrode UE is partially embedded in a plurality of trenches D2, which increases the face area between the upper electrode UE and the lower electrode (semiconductor substrate). In other words, the capacitance of the capacitor element CE can be increased more than when the upper electrode is formed on a flat semiconductor substrate (lower electrode) via an insulating film.

[0162] <Regarding the operation of non-volatile memory>

[0163] Then, refer to FIG. 41 An example of operating a non-volatile memory is described.

[0164] FIG. 41 This is a table illustrating an example of the conditions under which voltage is applied to the corresponding location of the selected memory cell during "write", "erase" and "read" operations in this embodiment. FIG. 41 The table shows the voltage Vmg applied to the memory gate electrode MG of the memory cell MC, the voltage Vs applied to the source region, the voltage Vcg applied to the control gate electrode CG, the voltage Vd applied to the drain region, and the base voltage Vc applied to the p-type well in the top surface of the semiconductor substrate at the corresponding times of "write," "erase," and "read." The term "select memory cell" here refers to the memory cell selected as the target for "write," "erase," or "read." Incidentally, in FIG. 17 In the example of the non-volatile memory shown, the active region to the right of the memory gate electrode MG is the source region, and the active region to the left of the control gate electrode CG is the drain region.

[0165] Incidentally, in FIG. 41 The voltages shown in the table are preferred examples of voltage application conditions and are not exclusive; various changes can be made if necessary. Further, in this embodiment, electrons are injected into the insulating film ONO of the memory transistor (see...). FIG. 17 The charge accumulation portion of the silicon nitride film is defined as "writing", and the hole injection is defined as "erasing".

[0166] Furthermore, in FIG. 41 In the table, row A corresponds to the case where the write method is SSI and the erase method is BTBT; row B corresponds to the case where the write method is SSI and the erase method is FN; row C corresponds to the case where the write method is FN and the erase method is BTBT; and row D corresponds to the case where the write method is FN and the erase method is FN.

[0167] The SSI method can be regarded as an operation method for writing to a memory cell by injecting hot electrons into a silicon nitride film. The BTBT method can be regarded as an operation method for erasing a memory cell by injecting hot holes into a silicon nitride film. The FN method can be regarded as an operation method for writing or erasing by tunneling of electrons or holes. The FN method can also be expressed as follows: the writing of the FN method can be regarded as an operation method for writing to a memory cell by injecting electrons into a silicon nitride film using the FN tunneling effect; and the erasing of the FN method can be regarded as an operation method for erasing a memory cell by injecting holes into a silicon nitride film using the FN tunneling effect. Hereinafter, specific descriptions will be made.

[0168] The writing method includes a writing method (hot electron injection writing method) for writing by hot electron injection by source side injection, which is called a so-called SSI (source side injection) method, and a writing method (tunneling writing method) for writing by FN (Fowler Nordheim) tunneling, which is called a so-called FN method.

[0169] For the writing of the SSI method, for example, a voltage (Vmg = 10 V, Vs = 5 V, Vcg = 1 V, Vd = 0.5 V, and Vb = 0 V) shown in "writing operation voltage" of row A or row B of the table of FIG. 10 is applied to the respective positions of the selected memory cells, and writing is performed; thereby, electrons are injected into the silicon nitride film in the ONO film ON of the selected memory cell, and writing is performed. FIG. 41

[0170] In this step, hot electrons are generated in the channel region (between the source and the drain) under and between the two gate electrodes (the memory gate electrode MG and the control gate electrode CG). Thereby, hot electrons are injected into the silicon nitride film as the charge accumulation portion in the ONO film ON under the memory gate electrode MG. The injected hot electrons (electrons) are trapped in the trap energy levels in the silicon nitride film in the ONO film ON. As a result, the threshold voltage of the memory transistor is increased. That is, the memory transistor is caused to enter a written state.

[0171] For the writing of the FN method, for example, a voltage (Vmg = 10 V, Vs = 5 V, Vcg = 1 V, Vd = 0.5 V, and Vb = 0 V) shown in "writing operation voltage" of row A or row B of the table of FIG. 10 is applied to the respective positions of the selected memory cells, and writing is performed; thereby, electrons are injected into the silicon nitride film in the ONO film ON of the selected memory cell, and writing is performed. FIG. 41 ​the voltage (Vmg = -12 V, Vs = 0 V, Vcg = 0 V, Vd = 0 V, and Vb = 0 V) indicated by "Write operation voltage" of row C or row D of the table of FIG. 12, to perform writing; whereby, in the selected memory cell, electrons tunnel from the memory gate electrode MG and are injected into the silicon nitride film in the ONO film ON, thereby performing writing. In this step, electrons tunnel from the memory gate electrode MG through the second silicon oxide film (top oxide film) by FN tunneling (FN tunneling effect), are injected into the ONO film ON, and are trapped in the trap energy levels in the silicon nitride film in the ONO film ON. As a result, the threshold voltage of the memory transistor increases. That is, the memory transistor is caused to enter the written state.

[0172] Incidentally, in the writing of the FN method, writing can also be performed in such a manner that electrons tunnel from the semiconductor substrate SB and are injected into the silicon nitride film in the ONO film ON. In this case, the write operation voltage can be set to, for example, the voltage obtained by reversing the sign of the "Write operation voltage" in row C or row D of the table of FIG. 12. FIG. 41

[0173] The erasing method includes an erasing method (hot hole injection erasing method) that performs erasing by hot hole injection due to the action of BTBT (band-to-band tunneling phenomenon), which is called the so-called BTBT method, and an erasing method (tunneling erasing method) that performs erasing by FN (Fowler Nordheim) tunneling, which is called the so-called FN method.

[0174] For erasing of the BTBT method, holes generated by BTBT are injected into the charge accumulation portion (silicon nitride film in the ONO film ON), thereby performing erasing. For example, the voltage indicated by "Erase operation voltage" of row A or row C of the table of FIG. 12 (Vmg = -6 V, Vs = 6 V, Vcg = 0 V, Vd = off, and Vb = 0 V) is applied to the corresponding position of the selected memory cell. As a result, holes are generated by the BTBT phenomenon and are accelerated under an electric field. Thereby, the holes are injected into the silicon nitride film in the ONO film ON of the selected memory cell. This decreases the threshold voltage of the memory transistor. That is, the memory transistor is caused to enter the erased state. FIG. 41

[0175] For erasing of the FN method, for example, the voltage indicated by "Erase operation voltage" of row A or row C of the table of FIG. 12 (Vmg = -6 V, Vs = 6 V, Vcg = 0 V, Vd = off, and Vb = 0 V) is applied to the corresponding position of the selected memory cell. As a result, holes are generated by the FN tunneling phenomenon and are accelerated under an electric field. Thereby, the holes are injected into the silicon nitride film in the ONO film ON of the selected memory cell. This decreases the threshold voltage of the memory transistor. That is, the memory transistor is caused to enter the erased state. FIG. 41 ​​The erase operation is performed using the voltages (Vmg = 12V, Vs = 0V, Vcg = 0V, Vd = 0V, and Vb = 0V) shown in row B or row D of the table. This causes holes to tunnel from the memory gate electrode MG and be injected into the silicon nitride film within the ONO film ON, thus performing the erase. In this step, holes tunnel from the memory gate electrode MG through the second silicon oxide film (top oxide film) via FN tunneling (FN tunneling effect), are injected into the ONO film ON, and are trapped in the trap levels within the silicon nitride film ON. This reduces the threshold voltage of the memory transistor, causing the memory transistor to enter the erase state.

[0176] Incidentally, in the FN method of erasure, erasure can also be performed as follows: holes are tunneled from the semiconductor substrate SB and injected into the silicon nitride film in the ONO film ON. In this case, the erasure operation voltage can be set, for example, by reversing the voltage at... FIG. 41 The voltage is obtained by the sign of the "Erase Operation Voltage" in row B or row D of the table.

[0177] During reading, for example, applying a force such as in the selected memory cell to the corresponding location. FIG. 41 The read operation is performed using the voltages shown in rows A, B, C, or D of the table, corresponding to the "Read Operation Voltage". The voltage Vmg applied to the memory gate electrode MG during read is set to a value between the threshold voltage of the memory transistor in write mode and the threshold voltage in erase mode. As a result, write and erase states can be distinguished.

[0178] Next, the corresponding applied voltages during operation will be described. The voltage supplied by the external power supply to the product chip is, for example, 1.5V for a low breakdown voltage MISFET and 5V for a high breakdown voltage MISFET. In memory operation, other voltages besides these are generated by a voltage generation circuit within the chip. For example, a 10V voltage used for Vmg during higher voltage SSI writes is generated by a voltage generation circuit formed by a high breakdown voltage MISFET. In the voltage generation circuit, charge accumulation, voltage smoothing, etc., are required as follows: FIG. 17 The capacitor element is shown in capacitor element region 1C.

[0179] <Regarding the effects of this embodiment>

[0180] Hereinafter, the problems of the comparative example of the semiconductor device, i.e., the semiconductor device having the split-gate type MONOS memory and the memory element including the capacitor having the upper electrode with a small film thickness embedded in the trench in the top surface of the semiconductor substrate will be described. Thereby, the effects of the present embodiment will be described. Here, FIGS. 38-40 Each of FIGS. 1A to 1C shows a cross-sectional view of the semiconductor device of the comparative example.

[0181] In each of the semiconductor device of the present embodiment and the comparative example, as described with reference to FIGS. 1-15 , the MISFET Q1 in the peripheral circuit region IB is formed by using a back gate process. In other words, in the present embodiment and the comparative example, a dummy gate electrode DG (see FIG. 10 ) is formed, and the dummy gate electrode DG is covered with an interlayer insulating film IL1; then, a polishing step exposes the top surface of the dummy gate electrode DG; then, the dummy gate electrode DG is replaced with a metal gate electrode.

[0182] In this back gate process, a polishing step of polishing the top of each gate electrode is performed. Therefore, it is difficult to form a capacitor element formed of a laminate film of a first conductor film (lower electrode) and a second conductor film (upper electrode) formed over the semiconductor substrate. This is because that even when the second conductor film is formed over the first conductor film, the polishing step removes the second conductor film. In this case, in the present embodiment and the following comparative examples, a capacitor element is formed in which the semiconductor substrate is provided as a lower electrode, and a polysilicon film over the semiconductor substrate is provided as an upper electrode.

[0183] Further, in the present embodiment and the following comparative examples, a trench is formed in the main surface of the semiconductor substrate by a dry etching method; and the upper electrode is partially embedded in the trench. This results in an increase in the facing area between the upper electrode and the semiconductor substrate, which makes it possible to increase the capacitance. In the present application, this element can be referred to as a trench capacitor element.

[0184] As the comparative example, FIG. 38 a cross-sectional view of the semiconductor device including the split-gate type MONOS memory in the memory cell region IA, the MISFET Q1 in the peripheral circuit region IB, and the capacitor element CE1 in the capacitor element region IC is shown. The capacitor element CE1 includes an upper electrode UEa partially embedded in a trench D2 formed in the main surface of the semiconductor substrate SB, and a lower electrode formed of the semiconductor substrate SB directly below.

[0185] As FIG. 38As shown, the capacitor element CE1 is covered with interlayer insulating films IL1 and IL2 at its top portion. Here, the semiconductor device of the comparative example differs from the semiconductor device of the present embodiment in that the film thickness of the upper electrode UEa of the capacitor element CE1 is smaller. For example, the upper electrode UEa is formed of the polysilicon film PS2 (see FIG. 8 ) for forming the memory gate electrode MG. In other words, the film thickness of the polysilicon film PS2 for forming the memory gate electrode MG is smaller than the film thickness of the polysilicon film PS1 (see FIG. 6 ) for forming the control gate electrode CG. Therefore, the film thickness of the upper electrode UEa of the comparative example is smaller than the thickness of the control gate electrode CG.

[0186] The reason why the gate length of the memory gate electrode MG, i.e., the film thickness of the polysilicon film PS2 (see FIG. 8 ) for forming the memory gate electrode MG, is smaller is as follows.

[0187] The split-gate type MONOS memory has a structure in which two transistors are coupled to each other. When a current flows from a drain region on the side of the control gate electrode CG of the memory cell MC forming the MONOS memory to a source region on the side of the memory gate electrode MG, the channel resistance of the memory transistor including the memory gate electrode MG is high (the gate length of the memory gate electrode MG is large). Thereby, a voltage drop is caused. As a result, the source potential of the control transistor including the control gate electrode CG increases, causing a decrease in the voltage between the gate and the source of the control transistor. Therefore, the current value is suppressed on the side of the control gate electrode CG.

[0188] On the other hand, when the channel resistance under the control gate electrode CG is large, a voltage drop is caused, but the gate-source voltage of the memory transistor is unlikely to decrease. That is, the drain voltage of the memory transistor is affected by the voltage drop, and decreases. However, in a saturation region, even when the drain voltage slightly decreases, almost no change in current is caused. Therefore, even when the gate length of the control gate electrode CG is larger than the gate length of the memory gate electrode MG, the influence on the characteristics of the memory cell is small. From the explanation mentioned so far, it is required that the memory gate electrode MG be formed of the polysilicon film PS2 having a film thickness smaller than the polysilicon film PS1 for forming the control gate electrode CG.

[0189] From the perspective of preventing voltage drop and improving the operating speed of memory cells, a smaller gate length is desirable for the memory gate electrode MG. Therefore, it is possible to reduce the thickness of the polysilicon film PS2 used to form the memory gate electrode MG, thereby reducing the gate length of the memory gate electrode MG through miniaturization of semiconductor devices. Here, when the polysilicon film PS2 used to form the memory gate electrode MG is processed as in the comparative example to form the upper electrode UEa of the capacitor element CE1, the thickness of the polysilicon film PS2 becomes less than half the opening width of the trench D2. As a result, the trench D2 may not be completely filled by the polysilicon film PS2.

[0190] In this case, such as FIG. 38 As shown, the upper electrode UEa is partially formed in each trench D2 along the sidewall and bottom surface of the trench D2; and a deep recess is formed directly above the trench D2 in the top surface of the upper electrode UEa. That is, the top surface of the upper electrode UEa cannot be formed to be nearly flat. Therefore, even when performing the reference... FIG. 13 During the described polishing step, the recess is also retained in the top surface of the upper electrode UEa. Incidentally, when the film thickness of the upper electrode UEa is less than the thickness of the control gate electrode CG formed after the polishing step, the top surface of the upper electrode UEa is not polished during the polishing step. In other words, even when polishing is performed, the top surface of the upper electrode UEa is not exposed and remains covered by the interlayer insulating film IL1.

[0191] In this case, in reference FIG. 15 In the described step of forming the silicide layer S2, it is impossible to form the silicide layer S2 at the top surface of the upper electrode UEa. Therefore, even when the contact plug is coupled to the top surface of the upper electrode UEa, the coupling resistance between the contact plug and the upper electrode UEa cannot be reduced. This adversely degrades the characteristics of the capacitor element CE1.

[0192] However, when a deep recess is formed directly above the trench D2 in the top surface of the upper electrode UEa as described above, a residue RD can be generated inside the recess during the sidewall SW formation step. In this case, the residue RD can subsequently be peeled off, thereby creating a foreign object. The formation of this foreign object leads to defects in the semiconductor device.

[0193] In contrast, in this embodiment, the control gate electrode CG and the upper electrode UE are made of the same polycrystalline silicon film PS1 (see...). FIG. 6 ) is formed. Therefore, in reference FIG. 13 Following the described polishing steps, the control gate electrode CG and the upper electrode UE have the same height and are exposed from the interlayer insulating film IL1. Therefore, in reference... FIG. 15In the second self-alignment silicide process described, a silicide layer S2 is formed at the top surface of the upper electrode UE.

[0194] Therefore, as in the comparative example, due to the influence of the small film thickness of the upper electrode, a silicide layer is not formed at the top surface of the upper electrode. This can prevent an increase in the coupling resistance between the upper electrode and the contact plug. Thereby, it is possible to prevent the capacitor element from stopping operating normally due to the influence of the increase in the coupling resistance. This can improve the reliability of the semiconductor device.

[0195] That is, in the present embodiment, even in the case where the polishing step described with reference to FIG. 13 After the polishing step described, the control gate electrode CG and the upper electrode UE have the same film thickness. Therefore, the top surface of the upper electrode UE is not covered with the interlayer insulating film ILl. Therefore, the silicide layer S2 is formed in a manner contacting the top surface of the upper electrode UE. As FIG. 17 indicated, the top surface of the upper electrode UE is not covered with the interlayer insulating film ILl, and is covered with the interlayer insulating film IL2. In other words, in a plan view, the interlayer insulating film ILl and the upper electrode UE do not overlap each other.

[0196] Further, it is possible to prevent a deep recess from being formed in the top surface of the upper electrode UE. This can prevent the following situation: a residue RD (see FIG. 38 ) is left in the recess, and, subsequently, the residue RD peels off, becomes a foreign matter, which leads to a defect of the semiconductor device.

[0197] As described above, the polysilicon film PSl (see FIG. 11 ) for forming the control gate electrode CG has a large film thickness. Therefore, the polysilicon film PSl can completely fill the trench D2. The first reason why the polysilicon film PSl has a large film thickness is as follows: in order to prevent the transistor characteristics of the memory cell MC from being deviated, the polysilicon film PSl is formed to have a large film thickness to some extent.

[0198] In other words, the control gate electrode CG before the polishing step is required to have a sufficient height (thickness) to prevent impurities for forming n - -type semiconductor regions EX and n + -type semiconductor regions DF from being injected through the gate electrode, and into the portion in which a channel is formed. That is, in the ion implantation step described with reference to FIG. 11 , when impurity ions pass through the control gate electrode CG, and are doped into the main surface of the semiconductor substrate SB, the characteristics of the transistor are changed. Therefore, in order to prevent this, the control gate electrode CG before the polishing step, that is, the polysilicon film PSl (see FIG. 6 ), is required to be formed to have a thickness equal to or greater than a prescribed thickness.

[0199] Specifically, at the time of ion implantation described with reference to FIG. 11 to the n - type semiconductor region EX and the n + type semiconductor region DF, any one of the thickness (depth) of the control gate electrode CG is required to be greater than the thickness (depth) of the n

[0200] Meanwhile, the second reason why the polysilicon film PSl has a large film thickness is as follows: As described with reference to FIG. 13 , in the case of employing the gate-last process, when the top surface of the interlayer insulating film ILl is polished, over-polishing by which the top surface of the control gate electrode CG is partially removed by polishing is performed; therefore, the film thickness of the polysilicon film PSl that forms the control gate electrode CG is set to be greater in advance.

[0201] In other words, in the gate-last process, the dummy gate electrode DG and the control gate electrode CG shown in FIG. 12 are filled with the interlayer insulating film ILl. Then, as described with reference to FIG. 13 , the top surface of the interlayer insulating film ILl is polished by using a CMP method or the like. In this step, it is difficult to perform the following: by precisely controlling the polishing amount, the top surface of the dummy gate electrode DG is not removed, and the top surface is exposed from the interlayer insulating film ILl and the insulating film IF5 (see FIG. 12 ). Therefore, at the time of polishing, when the top surface of the dummy gate electrode DG is removed to a certain degree by polishing, the polishing is stopped. As a result, the top surface of the dummy gate electrode DG is exposed.

[0202] In this step, when the film thickness of the control gate electrode CG and the dummy gate electrode DG becomes too small, the control transistor and the MISFET Ql that are formed later can stop operating normally. Therefore, the polysilicon film PSl that is used to form the control gate electrode CG and the dummy gate electrode DG is required to ensure a large film thickness in advance.

[0203] Further, as described with reference to FIG. 15 , the gate electrode Gl of the metal gate electrode is formed in the peripheral circuit region IB. Then, in order to reduce the resistance of the control gate electrode CG and the memory gate electrode MG, it is desirable to cause the respective top surfaces of the control gate electrode CG and the memory gate electrode MG to be silicided, thereby providing a silicide layer S2. However, as described with reference to FIG. 13In the polishing step described, when the control gate electrode CG becomes too thin, the silicide layer S2 comes into contact with the gate insulating film GIl. Thereby, it is conceivable that the materials of the gate insulating film GIl and the gate electrode react with each other. In this case, a phenomenon called Fermi level pinning occurs, and the effective work function of the control gate electrode CG changes. This disadvantageously leads to an increase in the absolute value of the threshold voltage of the MOSFET.

[0204] Therefore, when the control gate electrode CG is too thin, and the film thickness of the silicide layer S2 formed differs between the respective memory cells MC, the memory cells MC in which the control gate electrode CG is silicided to the position where it comes into contact with the top surface of the gate insulating film GIl, and the memory cells MC in which the control gate electrode CG formed of a silicon film remains between the silicide layer S2 and the gate electrode GIl, can be mixed together. In this case, a plurality of memory cells MC differ from each other in performance. In this case, in order to avoid such a deviation in performance, it is required that the polysilicon film PS 1 for forming the control gate electrode CG be formed thick in advance.

[0205] Incidentally, it is also conceivable to separately deposit the polysilicon film for forming the control gate electrode CG and the polysilicon film for forming the dummy gate electrode DG according to the manufacturing method. In this case, it is also conceivable that a difference in film thickness between the polysilicon films results. However, even when the control gate electrode CG and the dummy gate electrode DG are thereby formed of different polysilicon films, in order to maintain uniformity in height between the interlayer insulating film ILl and the respective top surfaces of the respective gate electrodes in the polishing step, it is required that the polysilicon films have a uniform film thickness. Therefore, in the gate-last process, the polysilicon film PS 1 for forming the control gate electrode CG has a large film thickness.

[0206] Further, in the removal step of the dummy element isolation region DEI described with reference to FIG. 4 and FIG. 5 , dry etching is performed using the laminated film of the insulating films IF 1 and IF2 remaining on the semiconductor substrate SB between the adjacent trenches D2. However, when dry etching is performed after the insulating films IF 1 and IF2 shown in FIG. 4 are removed, the top surface of the semiconductor substrate SB is greatly damaged. In other words, the surface of the semiconductor substrate SB between the adjacent trenches D2 is exposed, and is thereby damaged by the plasma of the dry etching. Therefore, the quality of the upper electrode UE (see FIG. 17 ) formed subsequently is poor, which disadvantageously reduces the reliability of the semiconductor device.

[0207] However, when the film covering the top surface of the semiconductor substrate SB between trenches D2 is merely a silicon oxide film, this silicon oxide film is removed during the initial stage of dry etching. Therefore, similarly, the surface of the semiconductor substrate SB is damaged, which adversely reduces the reliability of the semiconductor device.

[0208] In contrast, in this embodiment, during dry etching, each insulating film IF2 and insulating film IF1, formed from a more difficult-to-remove polycrystalline silicon film, is used as a mask. This prevents the top surface of the semiconductor substrate SB between adjacent trenches D2 from being damaged by dry etching.

[0209] Furthermore, to avoid the damage described above, it is advisable to perform the reference etching using wet etching instead of dry etching. FIG. 5 The described steps involve removing the dummy element isolation region DEI. However, in this case, each of the corners at the end of the bottom surface of trench D2 and the corners at the top of the sidewalls of trench D2 is angular in shape. This adversely causes leakage current to flow between the upper and lower electrodes in the capacitor element.

[0210] That is, as in FIG. 39 and FIG. 40 As shown in the comparative example, when the dummy element isolation region is removed by wet etching, the trench capacitor element includes the upper electrode NUE embedded therein (see...). FIG. 39 ) or PUE (see FIG. 40 The groove D2a has an angular shape at both its bottom surface end and the upper end of its sidewall. The corresponding corners at the bottom surface end and the upper end of the sidewall of the groove D2a are almost not rounded, as shown in... FIG. 4 The bottom surface end of the groove D1 shown is the same as the corresponding corner of the upper end of the sidewall. Therefore, in FIG. 39 and FIG. 40 At the corners shown, electric field concentration becomes more likely.

[0211] Incidentally, FIG. 39 and FIG. 40 Each of these is a cross-sectional view showing a comparative example semiconductor device, and each shows the portion near the trench of the trench capacitor element at an enlarged scale. FIG. 39 In the process, an n-type well NWL is formed on the main surface of the semiconductor substrate SB, which forms the lower electrode of the trench capacitor element; and an upper electrode NUE, formed of an n-type polycrystalline silicon film, is formed on the semiconductor substrate SB via an insulating film IF4. FIG. 40 In the semiconductor substrate SB, a p-type well PWL is formed on the main surface of the lower electrode of the trench capacitor element; and an upper electrode PUE formed of a p-type polycrystalline silicon film is formed on the semiconductor substrate SB via an insulating film IF4.

[0212] As FIG. 39 shown in FIG. 12, in the trench capacitor element formed of the n-type upper electrode NUE and the n-type well NWL, when a positive potential is applied to the n-type upper electrode NUE, electric field concentration occurs in the well NWL at the corner of the upper end of the trench D2a. As a result, the electrons, which are the majority carriers of the n-type semiconductor, flow from the well NWL to the upper electrode NUE side at the corner. Therefore, the leakage current shortens the lifetime of the insulating film IF4 and the like in the vicinity of the corner. This disadvantageously lowers the reliability of the capacitor element and the like. In FIG. 39 , the position from which the electrons flow out for the foregoing reason is indicated by an arrow.

[0213] Further, as FIG. 40 shown in FIG. 13, in the trench capacitor element formed of the p-type upper electrode PUE and the p-type well PWL, when a negative potential is applied to the upper electrode PUE, electric field concentration occurs in the well PWL at the corner of the upper end of the trench D2a. As a result, the holes, which are the majority carriers of the p-type semiconductor, flow from the well PWL to the upper electrode PUE side at the corner. Therefore, the leakage current shortens the lifetime of the insulating film IF4 and the like in the vicinity of the corner. This disadvantageously lowers the reliability of the capacitor element and the like. In FIG. 40 , the position from which the electrons flow out for the foregoing reason is indicated by an arrow.

[0214] Further, as FIG. 40 shown in FIG. 14, in the trench capacitor element formed of the p-type upper electrode PUE and the p-type well PWL, when the electric field applied to the electrodes of the capacitor element is large, the electrons, which are the minority carriers on the upper electrode PUE, flow toward the well PWL due to the bending of the energy band. In this step, the flow of the electrons becomes particularly noticeable due to the effect of the electric field concentration at the upper electrode PUE at the bottom surface end of the trench D2a (i.e., the corner of the upper electrode PUE). The leakage current shortens the lifetime of the insulating film IF4 and the like in the vicinity of the corner. In FIG. 40 , the position from which the electrons flow out for the foregoing reason is indicated by an arrow.

[0215] Thus, disadvantageously, in the n-type trench capacitor element, the leakage current tends to be caused due to the shape of the upper end of the trench D2a; and in the p-type trench capacitor element, the leakage current tends to be caused due to the shapes of the upper end and the bottom surface end of the trench D2a.

[0216] In contrast to this, in the present embodiment, as FIG. 4 and FIG. 5 shown in FIGS. 15 and 16, the dummy element isolation region DEI is removed by using dry etching instead of wet etching. As a result, the corner of the top of the sidewall of the trench D2 is cut and rounded by the dry etching. However, the central portion of the bottom surface of the trench D2 is cut by the dry etching. Therefore, the bottom surface end of the trench D2 is rounded. Thus, asFIG. 17 As shown, when a voltage is applied to each electrode of the capacitor element CE with the upper electrode UE embedded in the trench D2, the electric field generated in the well WL3 at the bottom surface end of the upper electrode in the trench D2 and in the side wall upper end of the trench D2 can be moderated.

[0217] Therefore, the concentration of the electric field at the corner of the trench capacitor element's trench D2 can be prevented. Therefore, the generation of the leakage current between the lower electrode and the upper electrode UE can be prevented, and the shortening of the life of the insulating film IF4 interposed between the lower electrode and the upper electrode UE can be prevented. Therefore, the reduction in the reliability of the semiconductor device due to the generation of the leakage current or the shortening of the life of the capacitor element CE can be prevented.

[0218] Further, as shown in FIG. 6 In the present embodiment, the step of forming a sacrificial oxide layer at the side wall and the bottom surface of the trench D2 by oxidation treatment and then removing the sacrificial oxide layer is repeatedly performed twice. Therefore, the damage caused to the side wall and the bottom surface of the trench D2 can be removed by referring to the dry etching step described in FIG. 5 Therefore, the reliability of the semiconductor device can be improved.

[0219] Further, when the dummy element isolation region is removed by wet etching, it is necessary to prevent the element isolation region EI in the trench Dl (see FIG. 4 ) from being removed by wet etching. This creates the necessity of securing a large space between the trench Dl and the trench D2, which disadvantageously hinders the miniaturization of the semiconductor device. In other words, the insulating film IFl and the like on the main surface of the semiconductor substrate SB are removed by the chemicals used in wet etching (isotropic etching) in addition to the dummy element isolation region DEI. Thus, it can be considered that the insulating film IFl exposed from the photoresist film PRl retreats to the element isolation region EI in the region covered by the photoresist film PRl. In this case, the chemicals reach the element isolation region EI, so that the element isolation region EI can also be removed. Therefore, in order to prevent this, it becomes necessary to expand the distance between the trench D2 and the trench Dl.

[0220] On the contrary, in the present embodiment, the dummy element isolation region is removed by the dry etching step. Therefore, the element isolation region EI is not removed. Therefore, the distance between the trench D2 and the trench Dl can be reduced, which can contribute to the miniaturization of the semiconductor device.

[0221] <Regarding the first modified example>

[0222] Hereinafter, the first modified example will be described with reference to FIG. 18 and FIG. 19A first modification example of the semiconductor device of this embodiment will be described. FIG. 18 Each of FIG. 19 is a cross-sectional view for illustrating a method for manufacturing the semiconductor device of the first modification example of this embodiment. As with FIGS. 1-15 and FIG. 17 , FIG. 18 and FIG. 19 each show a cross section of the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C.

[0223] In this modification example, it will be explained that the dummy element isolation region is removed by wet etching (isotropic etching) in a case where no problem is caused in terms of reliability at the corner portion of the trench of the trench capacitor element.

[0224] In the manufacturing steps of this modification example, first, the steps described with reference to FIGS. 1-3 are performed. Then, as shown in FIG. 18 , the insulating film IF2 is removed. Subsequently, a cleaning step of the main surface of the semiconductor substrate SB is performed. Subsequently, a sacrificial oxide film is formed at the surface of the semiconductor substrate SB. Then, ion implantation is selectively performed for each region, thereby forming the wells WL1 to WL3. Then, heat treatment is performed, thereby diffusing impurities in the wells WL1 to WL3.

[0225] Then, a photoresist film PR2 is formed over the main surface of the semiconductor substrate SB. Here, as compared with the photoresist film PR1 described with reference to FIG. 4 , the termination portion of the photoresist film PR2 between the trenches D1 and D2 in the capacitor element region 1C is more separated from the end portion of the trench D1. Further, here, the difference from the structure of FIG. 4 is that the trench D1 and the trench D2 in the capacitor region 1C are greatly separated from each other.

[0226] This is for the following reason: it is necessary to prevent the element isolation region EI in the trench D1 from being removed by wet etching in order for the removal of the dummy element isolation region DEI to be performed next. That is, it is necessary to prevent the following case: the insulating film IF1 is isotropically etched by wet etching and is retracted to the trench D1; as a result, in the capacitor element region 1C, the element isolation region EI in the trench D1 covered with the photoresist film PR2 is removed. Therefore, here, in order to prevent the insulating film IF1 from being retracted to the trench D1, a large width of the insulating film IF1 adjacent to the trench D1 to be covered with the photoresist film PR2 is ensured near the termination portion of the photoresist film PR2.

[0227] The subsequent steps are not specifically shown. However, wet etching is performed by using the photoresist film PR2 as a mask. Thereby, the insulating film IF1 and the dummy element isolation region DEI exposed from the photoresist film PR2 are removed. As a result, the side wall and the bottom surface of the trench D2 are exposed. Subsequently, after the photoresist film PR2 is removed, the sacrificial oxide film is removed. Then, the insulating films IF3 and IF4, the polysilicon film PS1, and the insulating film IF5 are formed in the same manner as the steps described with reference to FIG. 6 However, the two sacrificial oxidation steps described with reference to FIG. 6 are not performed here.

[0228] Then, the steps described with reference to FIGS. 7-17 are performed. As a result, the semiconductor device of the present modified example shown in FIG. 19 is completed. Here, the dummy element isolation region DEI is removed by wet etching. Therefore, the respective corners of the bottom surface end and the top of the side wall of the trench D2 are hardly rounded, as in the trench D1.

[0229] As in the present modified example, the leakage current in the trench capacitor element as described with reference to FIGS. 39-40 is hardly caused, and no problem is caused. In this case, even when the dummy element isolation region DEI is removed by wet etching (see FIG. 18 ), the reliability of the semiconductor device is not reduced. As in the present modified example, when the dummy element isolation region DEI is removed by wet etching, the following effects can be obtained.

[0230] That is, the dummy element isolation region DEI in the trench D2 is not removed by dry etching. This can prevent plasma damage to the surface of the semiconductor substrate SB, including to the side wall and the bottom surface of the trench D2, due to dry etching.

[0231] Further, the surface of the semiconductor substrate SB is not subjected to plasma damage as described above. Therefore, after the dummy element isolation region DEI is removed, it is not required to perform the two sacrificial oxidation steps described with reference to FIG. 6 . When the sacrificial oxidation steps are performed, it is required to perform the ion implantation steps of forming the wells WL1 to WL3 after the sacrificial oxide film is formed. However, in the present modified example, the sacrificial oxidation steps are not performed. Therefore, the wells WL1 to WL3 can be formed before the removal step of the dummy element isolation region DEI shown in FIG. 18 , in other words, before the photoresist film PR2 is formed.

[0232] Here, when ion implantation is performed on the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C respectively under different conditions, thereby forming the wells WL1 to WL3, a photoresist pattern is formed / removed for each ion implantation for forming each well. If this formation / removal step of the photoresist pattern is repeated after the dummy element isolation region DEI is removed, it can become difficult to completely remove the photoresist pattern in the trench D2. In this case, there is a problem of an increase in manufacturing cost due to cleaning, or a problem of a decrease in reliability of the semiconductor device due to a partial remaining of the photoresist film in the trench D2.

[0233] In contrast to this, in the present modified example, the wells WL1 to WL3 can be formed with the use of the trench D2 filled with the dummy element isolation region DEI. Therefore, the formation / removal of the photoresist pattern for differently forming the respective wells can be easily performed.

[0234] Further, in the present modified example, like the embodiment described with reference to FIGS. 1-17 the upper electrode UE for filling the trench D2 is formed by using the polysilicon film for forming the control gate electrode CG. Therefore, compared to the comparative example shown in FIG. 38 , the flatness of the top surface of the upper electrode UE can be improved. As a result, it is possible to prevent defective deposition from occurring due to the influence of the recesses in the top surface of the upper electrode UE. Further, it is possible to prevent the following cases: recesses are formed in the top surface of the upper electrode UE, thereby causing a residue or a cavity to be generated in each recess. Also, it is possible to prevent the top surface of the upper electrode UE from being reduced in height. Therefore, it is possible to form the silicide layer S2 over the upper electrode UE.

[0235] <Regarding the Second Modified Example>

[0236] Hereinafter, a second modified example of the semiconductor device of the present embodiment will be described with reference to FIG. 20 . FIG. 20 is a cross-sectional view for illustrating a method for manufacturing the semiconductor device of the second modified example of the present embodiment. Like FIGS. 1-15 and FIG. 17 , a cross section of the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C is shown. FIG. 20

[0237] In the present modified example, the following will be explained: before the dummy element isolation region is completely removed, the dry etching for removing the dummy element isolation region described with reference to FIG. 5 is stopped; as a result, an insulating film is left at the bottom of the trench in which the upper electrode of the capacitor element is embedded.

[0238] ​In the manufacturing steps of this modified example, first, the same steps as described with reference to FIGS. 1-5 are performed. However, in the dry etching step described with reference to FIG. 5 , the dummy element isolation region DEI (see FIG. 4 ) is not completely removed, and at the bottom inside each trench D2, the insulating film IF8 formed by the dummy element isolation region DEI is left. In other words, the insulating film IF8 in contact with the bottom surface of each trench D2 is left.

[0239] Accordingly, the bottom surface of the trench D2 is not exposed. However, the corners of the top of the side wall of the trench D2 are rounded, as described with reference to FIG. 5 . However, the bottom surface of the trench D2 is not dry etched. Accordingly, the end of the bottom surface is not rounded, and thus is angular, as are the corners of the end of the bottom surface of the trench Dl. Accordingly, the respective bottom surfaces of the trenches Dl and D2 are equal in height. However, the top surface of the semiconductor substrate SB between adjacent trenches D2 is lower than the top surface of the location of the main surface of the semiconductor substrate SB in the region adjacent to the trench Dl.

[0240] Then, the insulating films IF3 and IF4, the polysilicon film PS1, and the insulating film IF5 are formed, as described with reference to FIG. 6 . Here, the insulating film IF4 in the capacitor element region 1C is formed by an oxidation step, and thus is not formed at the bottom surface of the trench D2 and the lower portion of the side wall of the trench D2 covered by the insulating film IF8. In other words, in the trench D2, the insulating film IF4 is formed only over the insulating film IF8. Then, the steps described with reference to FIGS. 7-17 are performed. As a result, the semiconductor device of this modified example shown in FIG. 20 is completed.

[0241] In this modified example, the following effects can be obtained. That is, when the insulating film IF4 is formed in the trench D2 by an oxidation method such as thermal oxidation, at the bottom of the trench D2, or at the corners of that bottom, the film thickness of the insulating film IF4 can decrease due to the influence of stress caused by the shape, such as the depth of the trench D2. When the insulating film IF4 is thus partially reduced in thickness, the insulating properties of the insulating film IF4 decrease, which disadvantageously reduces the reliability of the semiconductor device.

[0242] In contrast, in this modified example, as shown in FIG. 20 , the dummy element isolation region DEI (see FIG. 4Partially retained at the bottom of trench D2. This prevents the formation of an insulating film IF4 with a small film thickness at the bottom of trench D2. Therefore, leakage current can be prevented between the upper electrode UE and the lower electrode of capacitor element CE. Thus, the reliability of semiconductor devices can be improved.

[0243] Furthermore, in this modified example, the corners of the bottom surface of trench D2 are not rounded. Therefore, the effect of suppressing leakage current generated due to the rounding of the corners of the bottom surface of trench D2 cannot be achieved. However, as another effect, the same as in the reference example can be obtained. FIGS. 1-17 The effects described in the embodiments are roughly the same.

[0244] <Regarding the third modification example>

[0245] Below, we will refer to FIG. 21 A third modification example of the semiconductor device in this embodiment will be described. FIG. 21 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third modified example of this embodiment. FIGS. 1-15 and FIG. 17 Same, FIG. 21 Cross-sections of memory cell region 1A, peripheral circuit region 1B, and capacitor element region 1C are shown.

[0246] In this modified example, compared with the reference FIG. 6 The difference in the method for forming the described insulating film IF4 lies in that the deposited film, formed by a deposition method such as CVD, forms the insulating film for isolating the electrodes of the capacitor element. Other manufacturing steps are the same as those described above. FIGS. 1-17 The manufacturing steps described are the same. In this modified example, the following effects can be achieved.

[0247] That is, as described in the second modified example, at the bottom of trench D2, an insulating film IF4 (see [example missing]) is formed by an oxidation method. FIG. 6 The film thickness may be reduced. This adversely reduces the reliability of semiconductor devices.

[0248] In this modified example, instead of oxidation, CVD or similar methods are used. FIG. 21 An insulating film IF9, formed of silicon oxide, is deposited and formed on the bottom surface and sidewalls of trench D2 as shown. This prevents a decrease in reliability due to a reduction in the thickness of the insulating film at the bottom of trench D2. Furthermore, in this modified example, the same as in the reference... FIGS. 1-17 The effects described in the embodiments are roughly the same.

[0249] <Regarding the fourth modification example>

[0250] Hereinafter, a fourth modification example of the semiconductor device of the present embodiment will be described with reference to FIG. 22 A fourth modification example of the semiconductor device of the present embodiment will be described. FIG. 22 is a cross-sectional view for illustrating a method for manufacturing the semiconductor device of the fourth modification example of the present embodiment. As with FIGS. 1-15 and FIG. 17 , FIG. 22 a cross section of the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C is shown.

[0251] In the present modification example, the method for forming the insulating film IF4 described with reference to FIG. 6 differs in that the laminated film of the two insulating films formed by the thermal oxidation method and the deposition method, respectively, is formed for establishing insulation between the upper electrode UE and the lower electrode of the capacitor element CE. That is, as described with reference to FIG. 6 , after the insulating film IF4 is formed by the thermal oxidation method, the insulating film IF9 is formed by a deposition method such as a CVD method. The laminated film of the insulating films IF4 and IF9 formed in this way is left as the insulating film for establishing insulation between the upper electrode UE and the lower electrode of the capacitor element CE. The other manufacturing steps are the same as described with reference to FIGS. 1-17 In the present modification example, the following effects can be obtained.

[0252] That is, when the insulating film for establishing insulation between the upper electrode and the lower electrode of the capacitor element is deposited and formed by a CVD method or the like, the insulating film can be inferior in reliability in insulating properties or the like to the insulating film formed by an oxidation method such as a thermal oxidation method. In contrast to this, in the present modification example, the laminated film of the insulating film IF4 formed by the oxidation method and the insulating film IF9 formed by the deposition method establishes insulation between the upper electrode UE and the lower electrode.

[0253] In this case, it is possible to consider reducing the thickness of the insulating film IF4 of the lower side thermal oxide film at the bottom surface or the bottom surface corner of the trench D2. However, the insulating film IF9 formed of a silicon oxide film having a uniform film thickness is stacked thereon. Therefore, it is possible to prevent a decrease in reliability of the insulating film for establishing insulation between the upper electrode UE and the lower electrode of the capacitor element CE. Further, in the present modification example, the same effects as in the fourth modification example of the semiconductor device of the present embodiment described with reference to FIGS. 1-17The effects in the described embodiments are roughly the same effects. Incidentally, over the semiconductor substrate SB, a high-breakdown-voltage MISFET (not shown) for input / output of a semiconductor device or the like is formed. Thereby, it can be considered that, for each gate insulating film of the high-breakdown-voltage MISFET in the present modification example and the third modification example, a film formed by the same step as a step of establishing insulation between the upper electrode UE and the lower electrode of the capacitor element CE is used.

[0254] Second Embodiment

[0255] Hereinafter, the manufacturing steps of the semiconductor device of the second embodiment will be described with reference to FIGS. 23-27 The manufacturing steps of the semiconductor device of the second embodiment will be described with reference to FIGS. 23-27 Each of FIGS. 1A to 1C is a cross-sectional view for illustrating a method for manufacturing the semiconductor device of the present embodiment. As with FIGS. 1-15 and FIG. 17 the same, FIGS. 23-27 Each of FIGS. 1A to 1C shows a cross section of the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C.

[0256] In the first embodiment, it has been described that, after the dummy element isolation region DEI (see FIG. 4 ) is removed, the insulating film IF2 (see FIG. 4 ) serving as a mask so as to form a trench in which an element isolation region and a trench capacitor element are embedded is removed. In contrast to this, hereinafter, a step in which, after an insulating film formed of a silicon nitride film serving as a mask so as to form a trench is removed, the dummy element isolation region is removed will be described. Further, in the present embodiment, instead of using a back gate process, a step of forming a gate electrode before forming a source / drain region of a MISFET in the peripheral circuit region, that is, a so-called front gate process is used.

[0257] In the manufacturing steps of the present modification example, first, the steps described with reference to FIGS. 1-3 are performed. Then, as shown in FIG. 23 , the insulating film IF2 is removed by wet etching. Then, over the main surface of the semiconductor substrate SB, a photoresist film PR1 is formed. The layout of the photoresist film PR1 is the same as the layout of the photoresist film PR1 described with reference to, for example, FIG. 24 .

[0258] Then, as shown in FIG. 5 , dry etching is performed by using PR1 as a mask, thereby removing the dummy element isolation region DEI and the insulating film IF1. Then, the photoresist film PR1 is removed. In this step, unlike the first embodiment, the silicon nitride film (see FIG. 23) formed is used as a mask. Therefore, in the early stage of etching, the insulating film IF1 is removed. Therefore, until the dummy element isolation region DEI is completely removed, the main surface of the semiconductor substrate SB in the vicinity of the trench D2 is recessed more than in the case of the first embodiment. Specifically, the height of the top surface of the semiconductor substrate SB between adjacent trenches D2 is significantly reduced. In other words, in the region in which the plurality of trenches D2 are arranged, the height of the main surface of the semiconductor substrate SB is significantly reduced.

[0259] By the way, the region in which the trenches D2 are arranged referred to here is a region exposed from the photoresist film PR1 in order to be removed by the steps described with reference to FIG. 16 In other words, the region in which the trenches D2 are arranged represents a region surrounded by the ring element isolation region EI in the layout shown in FIG. 23 , that is, a region (active region) for generating a capacitance between the semiconductor substrate of the lower electrode and the upper electrode UE, in which the resist is opened in the steps described with reference to FIG. 25 The end portion of the upper electrode UE is located directly above the element isolation region EI, and surrounds the region in which the trenches D2 are arranged.

[0260] Then, as shown in FIG. 6 , the same steps as those described with reference to FIG. 6 are performed, thereby forming the insulating films IF3 and IF4, and the polysilicon film PS1. However, here, the insulating film IF5 that caps the insulating films is not formed (see FIG. 24 ). Here, in the region in which the plurality of trenches D2 are formed, the height of the main surface of the semiconductor substrate SB is low. Therefore, the height of the top surface of the polysilicon film PS1 formed on this region is lower than the height of the top surface of the polysilicon film PS1 in other regions.

[0261] Here, before the insulating films IF3 and IF4 are formed, the surface of the semiconductor substrate SB is sacrificially oxidized, thereby forming a sacrificial oxide film in contact with the surface of the semiconductor substrate SB. Then, before the insulating films IF3 and IF4 are formed, a step of removing the sacrificial oxide film is performed. As a result, damage to the surface of the semiconductor substrate SB due to dry etching described with reference to FIG. 26 can be removed.

[0262] Then, as shown in FIGS. 7-11 , the same steps as those described with reference to FIG. 6The same steps as described above are performed, thereby forming the memory cell MC, the MISFET Q2, and the capacitor element CE. In other words, the memory cell MC includes a control transistor including the control gate electrode CG and a memory transistor including the memory gate electrode MG. The capacitor element CE is formed of the upper electrode UE having a top surface partially recessed in a wide range and the lower electrode formed of the semiconductor substrate SB directly below the upper electrode UE. In the peripheral circuit region IB, the replacement with the metal gate electrode is not performed. Therefore, the MISFET Ql has the gate electrode G2 formed of the polysilicon film PS 1.

[0263] Here, the insulating film IF5 (see FIG. 11 ) is not formed. Therefore, by the self-alignment silicide process described above with reference to FIG. 13 , a silicide layer SI is formed at the respective top surfaces of the control gate electrode CG, the memory gate electrode MG, the gate electrode G2, and the upper electrode UE. Further, as in the gate-last process, the replacement of the dummy gate electrode with another gate electrode is not required. Therefore, the polishing step described above with reference to FIG. 24 is not performed.

[0264] Subsequently, the interlayer insulating film ILl is formed in a manner covering the memory cell MC, the MISFET Q2, and the capacitor element CE. Here, the top surface of the interlayer insulating film ILl is influenced by the shape of each gate electrode, the upper electrode UE, and the like, and has non-uniformity. In other words, for example, directly above the gate electrode G2, the top surface of the interlayer insulating film ILl rises in a convex form. The height of the top surface of the interlayer insulating film ILl at the convex portion is greater than the height of the top surface of the interlayer insulating film ILl in the region laterally thereof in the height of the top surface. Similarly, directly above the upper electrode UE, the top surface of the interlayer insulating film ILl rises in a convex form and is greater than the top surface of the interlayer insulating film ILl in the region laterally thereof in the height of the top surface.

[0265] However, directly above the region in which the trench D2 is arranged, the top surface of the upper electrode UE is lower in height than the top surface of the end portion of the upper electrode UE in the lateral direction. Therefore, moreover, the portion of the convexly rising portion of the top surface of the interlayer insulating film ILl directly above the upper electrode UE, which is directly above the region in which the trench D2 is arranged, is low in the height of the top surface thereof. Here, the region in which the trench D2 is arranged has a very large area in a plan view in order to secure the capacitance of the capacitor element CE. Therefore, in a large region except for the end portion of the region directly above the upper electrode UE, the top surface of the interlayer insulating film ILl directly above the upper electrode UE is lower in the height of the top surface.

[0266] In other words, the height of the top surface of the interlayer insulating film ILl directly above the region in which the trench D2 is arranged (the active region) is lower than the height of the interlayer insulating film IL directly above the end portion of the upper electrode UE, and is higher than the height of the top surface of the main surface of the semiconductor substrate SB in the region aside from the upper electrode UE side (for example, the n-type semiconductor region in the capacitor element region 1C, for example, the p-type semiconductor region DF) in the plan view. + The height of the top surface of the interlayer insulating film ILl directly above the region in which the trench D2 is arranged (the active region) is lower than the height of the interlayer insulating film IL directly above the end portion of the upper electrode UE, and is higher than the height of the top surface of the main surface of the semiconductor substrate SB in the region aside from the upper electrode UE side (for example, the n-type semiconductor region in the capacitor element region 1C, for example, the p-type semiconductor region DF) in the plan view.

[0267] When the top surface of the interlayer insulating film ILl is polished in a subsequent step by, for example, a CMP method, the shape of the top surface of the interlayer insulating film ILl is advantageous from the viewpoint of improving the flatness of the top surface. That is, when the top surface of the interlayer insulating film ILl is raised directly above a region occupying a large area such as the region in which the trench D2 is arranged, it is difficult to planarize the top surface of the interlayer insulating film ILl in such a region and the top surface of the interlayer insulating film ILl in other regions.

[0268] In other words, when the top surface of the interlayer insulating film ILl directly above the region in which the trench D2 is arranged, and the top surface of the interlayer insulating film ILl directly above the end portion of the upper electrode UE, have equal heights, it becomes difficult to planarize by the polishing step. As a result, it becomes impossible to normally perform deposition / treatment of the interlayer insulating film, wiring, and the like formed on the interlayer insulating film ILl.

[0269] In contrast, in the present embodiment, in the dry etching step described with reference to FIG. 27 , etching is performed without using a silicon nitride film as a mask. This results in the height of the top surface of the main surface of the semiconductor substrate SB in the region in which the trench D2 is arranged being lower. Therefore, as shown in FIG. 27 , the upper electrode UE and the interlayer insulating film ILl formed directly above this region are low in the height of the top surface over a wide range. This can produce an effect of facilitating planarization of the top surface of the interlayer insulating film ILl by the polishing step to be performed next. That is, it is possible to suppress the generation of a step difference at the top surface of the interlayer insulating film ILl. Even if it is not possible to completely planarize the top surface of the interlayer insulating film ILl, it is possible to reduce the size of the step difference at the top surface of the interlayer insulating film ILl.

[0270] Then, as shown in FIG. 17 , the top surface of the interlayer insulating film ILl is polished by, for example, a CMP method. Then, the same process as described with reference to FIG. 15The same steps as described herein are performed to complete the semiconductor device of this embodiment. However, in the polishing step, the control gate electrode CG, the memory gate electrode MG, and the upper electrode UE, as well as their respective overlying silicide layers S1, are not exposed. Further, the same steps as described with reference to 17 are performed. However, the formation of the interlayer insulating film IL2 is not required. Therefore, the interlayer insulating film IL3 and the wiring M1 are not formed over the interlayer insulating film IL1 via the interlayer insulating film IL2. Further, the silicide layer S1 has already been formed over the respective top surfaces of the control gate electrode CG, the memory gate electrode MG, and the upper electrode UE. This eliminates the need to perform the second self-aligned silicide process described in the first embodiment (see...). FIG. 6 The necessity of ).

[0271] Incidentally, here we have already discussed IF5, which does not form an insulating film (see...). FIG. 6 The situation described above is as follows. However, the following steps are also acceptable: when performing the reference... FIGS. 1-17 In the described steps, after forming the insulating film IF5, patterning is performed so that the insulating film IF5 is only retained directly above the control gate electrode CG. In this case, the top surface of the control gate electrode CG in the completed semiconductor device remains covered by the insulating film IF5, except for the feed portion to the control gate electrode CG.

[0272] In this embodiment, as described above, the top surface of the interlayer insulating film IL1 can be easily planarized via a polishing step. This reduces the cost required for the manufacturing steps of the semiconductor device. Furthermore, the flatness of the top surface of the interlayer insulating film IL1 directly above the upper electrode UE can be easily improved. Therefore, it is possible to prevent the inability to properly perform deposition / processing on the interlayer insulating film, wiring, etc., formed on the interlayer insulating film IL1.

[0273] Furthermore, this modified example can generate a version similar to the referenced version. FIG. 23 The described embodiments have roughly the same effect. However, in reference to FIG. 24 and FIG. 4 In the described dry etching step, the main surface of the semiconductor substrate SB is not coated with a silicon nitride film (see... FIG. 5 and FIG. 25 The insulating film IF2 formed provides protection. Therefore, the damage to the semiconductor substrate SB surface exposed by dry etching from the photoresist film in the capacitor element region 1C is greater than the damage in the first embodiment. However, this can be mitigated by forming insulating films IF3 and IF4 (see... FIG. 28 The previously performed steps of forming and removing the sacrificial oxide film are used to remove the damage.

[0274] <Regarding the modification example>

[0275] Hereinafter, the modification example of the semiconductor device of the present embodiment will be described with reference to FIG. 28 A modification example of the semiconductor device of the present embodiment will be described. FIG. 27 is a cross-sectional view for illustrating a method for manufacturing the semiconductor device of the modification example of the present embodiment. As with FIG. 28 , FIG. 23 a cross-section of the memory cell region 1A, the peripheral circuit region IB and the capacitor element region 1C is shown.

[0276] In the present modification example, as with the manufacturing steps described with reference to FIG. 24 and FIG. 4 , dry etching is performed under the protection of the insulating film IF2 formed of the silicon nitride film (see FIG. 6 ). As a result, the height of the top surface of the semiconductor substrate SB in the region in which the trench D2 is arranged is reduced. This facilitates planarization of the top surface of the interlayer insulating film ILl (see FIG. 28 ). However, here, the MISFET Ql (see FIGS. 23-25 ) in the peripheral circuit region IB is formed by a gate-last process.

[0277] In other words, as with the manufacturing steps of the present modification example, the same steps as those described with reference to FIG. 6 are performed. Then, on the polysilicon film PS 1, an insulating film IF5 (see FIGS. 7-17 ) is formed. Then, the same steps as those described with reference to FIG. 28 are performed. As a result, the semiconductor device of the present modification example shown in FIG. 13 is completed.

[0278] Here, the polishing step described with reference to FIG. 6 reduces the height of the top surface of the upper electrode UE. However, the top surface of the upper electrode UE directly above the region in which the trench D2 is arranged is lower than the top surface of the end portion of the upper electrode UE, i.e., the height of the top surface of the upper electrode UE directly above the element isolation region El in the capacitor element region 1C. In other words, the position of the top surface of the upper electrode UE directly above the trench D2 is lower than the position of the top surface of the upper electrode UE directly above the element isolation region El in the capacitor element region 1C.

[0279] Therefore, the same steps as those described with reference to FIG. 28The insulating film IF5 formed in the described step remains directly above the portion of the upper electrode UE. In other words, the insulating film IF5 is formed directly above the active region of the capacitor element CE between the upper electrode UE and the interlayer insulating film IL. The insulating film IF5 is not formed between the end portion of the upper electrode UE and the interlayer insulating film IL2. In other words, the top surface of the end portion of the upper electrode UE is not covered with the insulating film IF5. However, when the step difference is even larger, it is possible not only to retain the insulating film IF5 but also the interlayer insulating film IL1 thereon. Incidentally, FIG. 15 A state in which only the insulating film IF5 is retained is shown.

[0280] In this case, in the second self-alignment silicide process described above with reference to FIGS. 23-28 the insulating film IF5 covers the top surface of the upper electrode UE at the portion where the trench D2 is arranged. Therefore, even if the silicide layer S2 is not formed, there is no problem. In other words, the contact plug CP for supplying a potential to the upper electrode UE is coupled to the top surface of the silicide layer S2 covering the top surface of the end portion of the upper electrode UE. This can suppress the contact resistance between the contact plug CP and the upper electrode UE to a low level.

[0281] In addition, in the present modified example, roughly the same effect as in the embodiment described above with reference to FIG. 29 can be obtained.

[0282] Third Embodiment

[0283] Below, the manufacturing steps of the semiconductor device of the third embodiment will be described with reference to FIG. 30 and FIG. 29 . FIG. 30 is a planar layout for illustrating a method for manufacturing the semiconductor device of the present embodiment. FIG. 30 is a cross-sectional view for illustrating a method for manufacturing the semiconductor device of the present embodiment. FIG. 29 shows a cross-sectional view along the line B-B of FIGS. 1-15 in the capacitor element region 1C. As in FIG. 17 and FIG. 30 , FIG. 29 shows a cross-section of the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C.

[0284] The planar layout shown in FIG. 29 shows only the trenches D1 and D2, the first upper electrode UE1, the second upper electrode UE2, the element isolation region EI, the well WL3, the n +a semiconductor region DF, and a contact plug CP. Further, in FIGS. 1-5 the middle, the outlines of the trenches Dl and D2, the well WL3, and the element isolation region El at the portions thereof covered by the first upper electrode UE1 and the second upper electrode UE2 are indicated by dotted lines. Further, the outline of the first upper electrode UE1 covered by the second upper electrode UE2 is also shown by dotted lines.

[0285] According to the present embodiment, each MISFET is formed by a gate-first process, and on the upper electrode (first upper electrode) of the capacitor element, another upper electrode (second upper electrode) is provided. Incidentally, hereinafter, the following steps will be described: after the first upper electrode is formed, a polysilicon film for forming the memory gate electrode and the second upper electrode is formed.

[0286] In the manufacturing steps of the semiconductor device of the present embodiment, first, the same steps as those described with reference to FIG. 6 are executed. Then, as in the steps described with reference to FIG. 6 , the insulating films IF3 and IF4 and the polysilicon film PS1 are formed. However, here, the insulating film IF5 is not formed (see FIG. 7 ). Then, the same steps as those described with reference to FIG. 7 are executed, thereby forming the control gate electrode CG.

[0287] However, here, patterning is executed, thereby forming the control gate electrode CG. In addition, the polysilicon film PS1 in the capacitor element region 1C is processed (see FIG. 8 ), thereby forming the first upper electrode UE1. The structure of the first upper electrode UE1 is the same as that of the upper electrode described in the first embodiment. Then, the steps described with reference to FIG. 8 are executed. As a result, the control gate electrode CG and the first upper electrode UE1 are covered by the ONO film ON and the polysilicon film PS2 (see FIG. 9 ).

[0288] Subsequently, with the polysilicon film PS2 directly above the first upper electrode UE1 covered by the photoresist film, a dry etching step is executed as described with reference to FIG. 30 . As a result, the corresponding portions of the polysilicon film PS2 and the ONO film ON are removed, thereby forming the memory gate electrode MG in the memory cell region 1A. Then, the photoresist film is removed.

[0289] Here, in the region protected from dry etching by the photoresist film, i.e., directly above the first upper electrode UE1, the second upper electrode UE2 formed of the polysilicon film PS2 is formed via the ONO film ON (see FIG. 11). However, in the peripheral circuit region IB, the polysilicon film PSl is exposed from the ONO film ON and the polysilicon film PS2.

[0290] Then, the polysilicon film PSl is processed, so that the gate electrode G2 formed of the polysilicon film PSl is formed in the peripheral circuit region IB. In the present embodiment, the gate-last process is not performed, and the gate electrode is not replaced with a metal gate electrode. Therefore, here in the peripheral circuit region IB, which forms the MISFET to be formed later, is not a dummy gate electrode, but the gate electrode G2.

[0291] Then, the same steps as those described with reference to FIG. 12 and FIG. 13 are performed. As a result, the top of each semiconductor element is covered with the interlayer insulating film ILl. Then, the top surface of the interlayer insulating film ILl is polished. The gate-last process is not performed. Therefore, in the subsequent steps, the polishing step described with reference to FIG. 14 and the replacement of the gate electrode described with reference to FIG. 15 and FIG. 11 are not performed. Further, in the steps described with reference to FIG. 16 , the silicide layer S 1 is formed at the respective exposed top surfaces of the control gate electrode CG, the memory gate electrode MG, the first upper electrode UE1 and the second upper electrode UE2, respectively. The polishing step is not performed, and therefore the silicide layer S 1 and the second upper electrode UE2 are left, i.e., not removed even in the later steps.

[0292] Then, the steps described with reference to FIG. 17 and FIG. 29 are performed. As a result, the semiconductor device of the present embodiment shown in FIG. 30 and FIG. 17 is completed. Here, the interlayer insulating film IL2 is not formed (see FIG. 30 ). Therefore, on the interlayer insulating film ILl, the first wiring layer is formed without via the interlayer insulating film IL2. In the region not shown in FIG. 29 , as shown in FIG. 6 , the contact plug CP is electrically coupled with the top surface of the second upper electrode UE2 formed on the semiconductor substrate SB without via the first upper electrode UE1.

[0293] Incidentally, when the top surface of the control gate electrode CG is partially covered with the cap insulating film, in the steps described with reference to FIG. 7 , the insulating film IF5 is formed on the polysilicon film PSl. Then, in the steps described with reference to ​The described steps leave the insulating film IF5 directly above the control gate electrode CG, and remove portions of the insulating film IF5 in other areas. As a result, the insulating film IF5 is not left between the first upper electrode UE1 and the second upper electrode UE2, which are formed later.

[0294] As Figure 29 illustrated, the layout of the capacitor element CE differs from the layout of the first embodiment (see Figure 16 ) in that the second upper electrode UE2 is formed on the first upper electrode UE1. In a plan view, a portion of the second upper electrode UE2 overlaps with an area in which the trench D2 is arranged, and other portions of the first upper electrode UE1 and the second upper electrode UE2 overlap with the element isolation region EI. In an area directly above the element isolation region EI, and in which the second upper electrode UE2 and the first upper electrode UE1 do not overlap with each other, a top surface of an end portion of the second upper electrode UE2 is coupled with the contact plug CP.

[0295] This embodiment can produce roughly the same effects as in the first embodiment. However, here, the step of polishing the top surface of the first upper electrode UE1, and the step of forming the silicide layer S2 on the first upper electrode UE1 by the second self-aligned silicide process (see Figure 15 ) are not performed. This prevents the problem of not forming the silicide layer at the top surface of the upper electrode due to the small film thickness of the upper electrode, as in the comparative example described with reference to Figure 38 . Therefore, this embodiment does not produce the effect of preventing an increase in the coupling resistance between the upper electrode and the contact plug, among the effects described in the first embodiment.

[0296] Further, in this embodiment, the back gate process is not performed. In other words, the polishing step described with reference to Figure 13 is not performed. Therefore, the second upper electrode UE2 formed on the first upper electrode UE1 via the ONO film ON can be left as is. Therefore, the capacitor element CE is formed of the lower electrode (first electrode) formed of the semiconductor substrate SB, the first upper electrode (second electrode) UE1, and the second upper electrode (third electrode) UE2. This can generate a capacitance at two locations, between the lower electrode and the first upper electrode UE1, and between the first upper electrode UE1 and the second upper electrode UE2. Therefore, it is possible to form a capacitor element CE that has a small footprint in a plan view and has a large capacitance.

[0297] By the way, here, the case has been described that the first upper electrode UE1 is formed by patterning and then the polysilicon film PS2 is formed, and subsequently, the second upper electrode UE2 is formed. However, it is also possible to form the first upper electrode UE1 by forming the second upper electrode UE2, and then by patterning the polysilicon film PS2.

[0298] Fourth Embodiment

[0299] Hereinafter, the manufacturing steps of the semiconductor device of the fourth embodiment will be described with reference to Figures 31 to 36 The manufacturing steps of the semiconductor device of the fourth embodiment will be described with reference to Figures 31 to 36 Each of FIGS. 1A to 1C is a cross-sectional view for illustrating a method for manufacturing the semiconductor device of the present embodiment. As with Figures 1 to 15 and Figure 17 the same, Figures 31 to 36 Each of FIGS. 1A to 1C illustrates a cross section of the memory cell region 1A, the peripheral circuit region 1B, and the capacitor element region 1C.

[0300] In the first embodiment, the case has been described that the polysilicon film for forming the memory gate electrode of the MONOS memory fills the inside of each trench of the trench capacitor element, thereby forming the upper electrode of the capacitor element. However, in the present embodiment, the polysilicon film for forming the memory gate electrode of the MONOS memory fills the trench, thereby forming the upper electrode.

[0301] In the first embodiment, the solution to the problem due to the recess in the top surface of the upper electrode formed directly above the trench, which is caused when the film thickness of the polysilicon film for forming the memory gate electrode is small, has been described. In contrast, in the present embodiment, the manufacturing steps that can be performed in the case where the film thickness of the polysilicon film for forming the memory gate electrode can be set to be large, the trench width of the trench capacitor element can be realized to be narrow, and the like, and the case where the problem associated with the recess does not occur, will be described.

[0302] In the manufacturing steps of the semiconductor device of the present embodiment, first, as shown in Figure 31 , a plurality of trenches D1 and a plurality of trenches D2 are formed in the top surface of the semiconductor substrate SB. Then, an element isolation region EI is formed in each of the trenches D1, and a dummy element isolation region DEI is formed in each of the trenches D2. Unlike the steps described with reference to Figures 1 to 3 , the insulating film IF2 (see Figure 3 ) formed is removed before the later dummy element isolation region DEI removal step.

[0303] Then, as shown in Figure 32As shown, the insulating film IF1 is removed. Subsequently, ion implantation is performed to form wells WL1, WL2, and WL3 in the memory cell region 1A, peripheral circuit region 1B, and capacitor element region 1C, respectively. Then, the main surface of the semiconductor substrate SB is oxidized. As a result, an insulating film IF3 is formed at the top surface of the semiconductor substrate SB exposed from the element isolation region EI and the dummy element isolation region DEI in the memory cell region 1A, peripheral circuit region 1B, and capacitor element region 1C. Then, a polycrystalline silicon film PS1 and an insulating film IF5 are sequentially formed on the main surface of the semiconductor substrate SB using, for example, a CVD method.

[0304] Subsequently, insulating film IF5, polysilicon film PS1, and insulating film IF3 are processed using photolithography and etching methods. As a result, in memory cell region 1A, a control gate electrode CG formed from polysilicon film PS1 is formed via gate insulating film GI1 on the main surface of semiconductor substrate SB. Further, insulating film IF5, polysilicon film PS1, and insulating film IF3 are removed from capacitor element region 1C by etching. As a result, element isolation region EI, dummy element isolation region DEI, and semiconductor substrate SB are exposed. Here, etching is performed on peripheral circuit region 1B protected by photoresist film (not shown). As a result, polysilicon film PS1 and the like in peripheral circuit region 1B are not processed and are retained.

[0305] Then, as Figure 33 As shown, a pattern formed by a photoresist film PR2 on the main surface of a semiconductor substrate SB covers the memory cell region 1A and the peripheral circuit region 1B. In the capacitor element region 1C, a portion of the main surface of the semiconductor substrate SB and multiple dummy element isolation regions DEI are exposed from the photoresist film PR2. In other words, the pattern shape of the photoresist film PR2 is similar to that of a reference... Figure 4 The described photoresist film PR1 has the same shape and does not cover the area in which the trenches D2 are arranged.

[0306] Subsequently, dry etching is performed using the photoresist film PR2 as a mask to remove the dummy element isolation region DEI. This exposes the corresponding sidewalls and bottom surfaces of the multiple trenches D2. However, the main surface of the semiconductor substrate SB near the trenches D2 is dry etched, thus reducing its height by a receding form. Furthermore, both the top corners of the sidewalls of the trenches D2 and the corners of the bottom surfaces of the trenches D2 are rounded.

[0307] Then, as Figure 34As shown, the photoresist film PR2 is removed. Then, an ONO film ON and a polysilicon film PS2 are sequentially formed on the semiconductor substrate SB using, for example, a CVD method. As a result, in the memory cell region 1A, the sidewalls and top surface of the laminate formed by the gate insulating film GI1, the control gate electrode CG, and the insulating film IF5 are covered by the ONO film ON and the polysilicon film PS2. However, in the peripheral circuit region 1B, the top surface of the insulating film IF5 is covered by the ONO film ON and the polysilicon film PS2. Furthermore, the corresponding top surfaces of the semiconductor substrate SB and the element isolation region EI in the memory cell region 1A and the peripheral circuit region 1B are covered by the ONO film ON and the polysilicon film PS2.

[0308] However, in capacitor element region 1C, the top surface of each element isolation region EI and the top surface of the semiconductor substrate SB, including the sidewalls and bottom surface of each trench D2, are covered by an ONO film ON and a polycrystalline silicon film PS2. The ONO film ON does not completely fill the trench D2. The ONO film ON and the polycrystalline silicon film PS2 completely fill the trench D2. In other words, compared with the reference... Figure 38 The difference in the comparative examples described is that the polycrystalline silicon film PS2 has a film thickness that is greater than or equal to half the opening width of the trench D.

[0309] Therefore, the depressions in the top surface of the polycrystalline silicon film PS2 formed directly above each trench D2 are smaller and shallower compared to when the polycrystalline silicon film PS2 cannot completely fill the trench D2.

[0310] Then, as Figure 35 As shown, corresponding portions of the polysilicon film PS2 and the ONO film ON were removed using photolithography and dry etching methods. As a result, in the memory cell region 1A, the memory gate electrode MG was formed with a reference... Figure 9 The structure described. In the peripheral circuit region 1B, the polysilicon film PS2 and the ONO film ON are removed, thereby exposing the top surface of the insulating film IF5.

[0311] In capacitor element region 1C, an upper electrode UE is formed by a polycrystalline silicon film PS2 partially embedded in multiple trenches D2. As a result, in capacitor element region 1C, a capacitor element CE is formed including the upper electrode UE and a lower electrode formed by a semiconductor substrate SB (well WL3) directly below the upper electrode UE. In other words, in capacitor element region 1C, an ONO film ON and a polycrystalline silicon film PS2 (see [reference needed]) are formed directly above the region where trenches D2 are arranged. Figure 34The ONO film ON and the polysilicon film PS2 are retained in other areas; and the top surface of the element isolation region EI and the top surface of the semiconductor substrate SB are partially exposed from the ONO film ON and the polysilicon film PS2.

[0312] In capacitor element region 1C, the laminated film of ONO film ON and upper electrode UE terminates directly above the element isolation region EI adjacent to trench D2. The sidewalls and bottom surface of each trench D2 remain covered by the laminated film. Between element isolation region EI and another element isolation region EI adjacent to it, the main surface of semiconductor substrate SB is exposed from the laminated film.

[0313] Then, as Figure 36 As shown, a laminated film formed from insulating film IF3, polysilicon film PS1, and insulating film IF5 in peripheral circuit region 1B is processed using photolithography and etching methods. This results in the formation of a dummy gate electrode, which is formed from gate insulating film GI2 formed from insulating film IF3 and polysilicon film PS1. Then, the process is performed in accordance with reference to... Figures 11 to 17 The same steps described are used to complete the semiconductor device of this embodiment. In other words, the MISFET Q1 in the peripheral circuit region 1B is formed using a post-gate process.

[0314] When following the steps described so far... Figure 13 When performing the polishing step in the same manner as described, the corresponding top surfaces of the control gate electrode CG, the dummy gate electrode, and the upper electrode UE are polished and exposed. Here, in this embodiment, the polycrystalline silicon film PS2 (see...) Figure 34 The polycrystalline silicon film PS2 has a relatively large thickness. Therefore, the upper electrode UE formed from the polycrystalline silicon film PS2 has a sufficient thickness to be exposed from the interlayer insulating film IL1 during the polishing step. This prevents the upper electrode UE from being exposed from the interlayer insulating film IL1 during the polishing step, and prevents the formation of a silicide layer S2 at the top surface of the upper electrode UE.

[0315] Here, the upper electrode UE is exposed from the element isolation region EI directly above it. In other words, a silicide layer S2 is formed on the surface of the upper electrode UE directly above the element isolation region EI. The silicide layer S2 is coupled to the contact plug CP. Conversely, in the active region of the semiconductor region CE, i.e., the region where the trench D2 is arranged, by referring to... Figure 33 The described dry etching step reduces the height of the top surface of the semiconductor substrate SB and forms a small recess in the top surface of the upper electrode UE embedded in the trench D2. As a result, the top surface of the upper electrode UE directly above this region is covered by an interlayer insulating film IL1.

[0316] That is, above the region, the interlayer insulating film IL1 intervenes between the upper electrode UE and the interlayer insulating film IL2. In other words, in the polishing step described with reference to Figure 13 the top surface of the upper electrode UE in the region is not exposed from the interlayer insulating film IL1. Therefore, the suicide layer S2 is not formed at the top surface of the upper electrode UE in the region. However, the top surface of the upper electrode UE above the region in which the trench D2 is arranged is not a position for ensuring coupling with the contact plug CP. Therefore, even if the suicide layer S2 is not formed, there is no problem.

[0317] As described so far, in the case where the film thickness of the polysilicon film PS2 used for forming the memory gate electrode MG (see Figure 34 ) can be increased, or in other cases, even when the upper electrode UE is formed of the polysilicon film PS2, the trench D2 can be completely filled, and the suicide layer S2 can be formed at at least part of the top surface above the upper electrode UE. Therefore, the flatness of the top surface of the upper electrode UE can be improved. Further, the recesses are increased in depth, which can prevent formation of a residue or a cavity in each of the recesses. Therefore, roughly the same effect as that of the first embodiment can be obtained. This can prevent a decrease in the reliability of the semiconductor device.

[0318] <Regarding a modification example>

[0319] Figure 37 A planar layout of the capacitor element CE as a modification example of the present embodiment is shown. The layout shown in Figure 37 differs from the layout shown in Figure 16 , specifically, the layout of the region in which the trench D2 is arranged (i.e., the active region of the capacitor element CE) has a width greater than the width of the upper electrode UE in the lateral direction (the longitudinal direction of the drawing).

[0320] In other words, the top surface of the portion of the active region surrounded by the ring element isolation region EI is exposed from the upper electrode UE. The top surface of the exposed portion of the well WL3 formed in the active region is coupled with the plurality of contact plugs CP for feeding current to the lower electrode. Incidentally, in the plan view, the top surface of the n + type semiconductor region DF outside the ring element isolation region EI is also coupled with the plurality of contact plugs CP for feeding current to the lower electrode.

[0321] Thereby, not limited to the layout shown in Figure 16 , as Figure 37The active region surrounded by the ring element isolation region EI can also be coupled with the contact plug CP as shown. This layout can also be applied to the first to third embodiments. When this layout is applied to the third embodiment, the coupling region of the contact plug CP to the active region surrounded by the ring element isolation region EI is provided in a region that does not coincide with either of the first upper electrode UE1 and the second upper electrode UE2 (see FIG. 1) in a plan view. Figure 29 ) in a plan view.

[0322] So far, the present application accomplished by the present inventor has been specifically described by the respective embodiments. However, it is obvious that the present application is not limited to these embodiments, and various changes can be made to the present application within the scope not departing from the gist of the present application.

[0323] Further, parts of the contents described in the respective embodiments will be described below.

[0324] (1) A method for manufacturing a semiconductor device, comprising the steps of:

[0325] (a) providing a semiconductor substrate having a first region and a second region arranged along a main surface,

[0326] (b) forming a first trench in the main surface of the semiconductor substrate in the second region,

[0327] (c) covering a side wall and a bottom surface of the first trench with a first insulating film,

[0328] (d) forming a first conductor film over the main surface of the semiconductor substrate in the first region and the second region after the step (c), and thereby embedding the first conductor film in the first trench via the first insulating film,

[0329] (e) processing the first conductor film, and thereby forming a control gate electrode formed of the first conductor film over the main surface of the semiconductor substrate in the first region,

[0330] (f) forming a memory gate electrode via a second insulating film having a charge accumulation portion inside at a side wall of the control gate electrode,

[0331] (g) processing the first conductor film, and thereby forming a first electrode formed of the first conductor film filling the first trench in the second region, and

[0332] (h) forming a first source / drain region pair in the main surface of the semiconductor substrate in the first region after the step (f).

[0333] In the present method, the control gate electrode, the memory gate electrode, and the first source / drain region pair form a memory cell of a nonvolatile memory, and

[0334] The first gate and the semiconductor substrate under the first electrode form a capacitor element.

[0335] (2) In the method for manufacturing a semiconductor device according to clause (1),

[0336] In step (c), the side wall and the bottom surface of the first trench are covered with the first insulating film formed by an oxidation method.

[0337] (3) In the method for manufacturing a semiconductor device according to clause (1),

[0338] In step (c), the side wall and the bottom surface of the first trench are covered with the first insulating film formed by a deposition method.

[0339] (4) In the method for manufacturing a semiconductor device according to clause (1),

[0340] Step (c) includes the following steps:

[0341] (c1) oxidizing the side wall and the bottom surface of the first trench, and forming a sixth insulating film, and

[0342] (c2) depositing a seventh insulating film on the side wall and the bottom surface of the first trench, and thereby covering the side wall and the bottom surface of the first trench with the first insulating film formed by the sixth insulating film and the seventh insulating film.

[0343] (5) The method for manufacturing a semiconductor device according to clause (1), further comprising the following steps:

[0344] (b1) after step (b), embedding the third insulating film in the first trench, and

[0345] (b2) before step (c), removing the third insulating film in the first trench by isotropic etching.

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) providing a semiconductor substrate, the semiconductor substrate having a main surface, the main surface including a memory cell formation region and a capacitor element formation region; (b) forming a first conductor film over the main surface of the semiconductor substrate in the memory cell formation region via a first insulating film; (c) patterning the first conductor film to form a control gate electrode, the control gate electrode being formed of the first conductor film over the main surface of the semiconductor substrate in the memory cell formation region via the first insulating film; (d) after the step (c), forming a trench in the main surface of the semiconductor substrate in the capacitor element formation region; (e) forming a second insulating film on an upper surface of the trench and on the control gate electrode, the second insulating film having a charge accumulation film; (f) after the step (e), forming a second conductor film on the second insulating film to cover the trench and the control gate electrode; (g) subjecting the second conductor film to an etching treatment to form a memory gate electrode and a first electrode, the memory gate electrode being formed of the second conductor film in the memory cell formation region, the first electrode being formed of the second conductor film in the capacitor element formation region; (h) after the step (g), forming a first source / drain region pair in the main surface of the semiconductor substrate defined by the control gate electrode and the memory gate electrode in the memory cell formation region; and (i) forming a first plug over the first electrode and a second plug over the main surface of the semiconductor substrate, the first plug and the second plug being electrically coupled with the first electrode and the main surface of the semiconductor substrate, respectively, wherein the control gate electrode, the memory gate electrode, and the first source / drain region pair form a memory cell of a nonvolatile memory, and wherein the first electrode, the second insulating film, and the semiconductor substrate under the first electrode form a capacitor element.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the second conductor film has a film thickness that is at least half of a dimension of an opening width of the trench.

3. The method for manufacturing a semiconductor device according to claim 1, wherein a film thickness of the second conductor film is smaller than a film thickness of the first conductor film.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the step (f) includes embedding a portion of the second conductor film in the trench. ​

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