Semiconductor device and method of manufacturing the same

Abstract

Embodiments provide a semiconductor device capable of suppressing reliability degradation and a manufacturing method thereof. The semiconductor device of the present embodiment includes a laminate having a plurality of conductive layers and a plurality of first insulating layers alternately laminated in a first direction. The conductive layer includes a first metal layer and a second metal layer. The first metal layer contains a first metal element and a substance that chemically reacts with a material gas containing the first metal element. The second metal layer contains the first metal element, and the content of the substance is less than that of the first metal layer. The first metal layer is disposed between the first insulating layer and the second insulating layer.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims priority to Japanese Patent Application No. 2020-151432 (Filing date: September 9, 2020). This application incorporates by reference the entire contents of the priority application. TECHNICAL FIELD

[0003] The present embodiment relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0004] A semiconductor device (semiconductor storage device) such as a NAND (Not AND) type EEPROM (Electrically Erasable Programmable Read-only Memory) sometimes has a three-dimensional memory cell array in which memory cells are arranged three-dimensionally. Such a memory cell array has a laminate in which a conductive layer functioning as a word line and an insulating layer are alternately laminated.

[0005] However, with miniaturization, the height of the conductive layer decreases, and accordingly, the wiring resistance of the word line increases. In addition, if the barrier film is thinned or omitted in order to reduce the wiring resistance, for example, reliability such as leakage characteristics deteriorates. SUMMARY

[0006] The present application is to provide a semiconductor device and a manufacturing method thereof capable of suppressing deterioration of reliability.

[0007] The semiconductor device of the present embodiment has a laminate having a plurality of conductive layers and a plurality of first insulating layers alternately laminated in a first direction. The conductive layer has a first metal layer and a second metal layer. The first metal layer contains a first metal element and a substance that chemically reacts with a material gas containing the first metal element. The second metal layer contains the first metal element, and the content of the substance is less than that of the first metal layer. The first metal layer is disposed between the first insulating layer and the second insulating layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a view showing one configuration example of a memory cell array in the semiconductor device of the first embodiment.

[0009] Figure 2A is a schematic cross-sectional view illustrating a three-dimensional configuration of a memory cell.

[0010] Figure 2B is a schematic cross-sectional view illustrating a three-dimensional configuration of a memory cell.

[0011] Figure 3This is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.

[0012] Figure 4 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0013] Figure 5 It means succession Figure 4 A cross-sectional view of the manufacturing method of the subsequent semiconductor device.

[0014] Figure 6 It means succession Figure 5 A cross-sectional view of the manufacturing method of the subsequent semiconductor device.

[0015] Figure 7 It means succession Figure 6 A cross-sectional view of the manufacturing method of the subsequent semiconductor device.

[0016] Figure 8 It means succession Figure 7 A cross-sectional view of the manufacturing method of the subsequent semiconductor device.

[0017] Figure 9A It means Figure 8 A schematic diagram of the metal layer formation process in the process.

[0018] Figure 9B It means Figure 8 A schematic diagram of the metal layer formation process in the process.

[0019] Figure 9C It means Figure 8 A schematic diagram of the metal layer formation process in the process.

[0020] Figure 10 This is a cross-sectional view showing the configuration of a comparative example semiconductor device.

[0021] Figure 11 This is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment.

[0022] Figure 12 It means Figure 11 A schematic diagram of nitrogen within the metal layer.

[0023] Figure 13 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment. Detailed Implementation

[0024] Embodiments of the present application will be described below with reference to the accompanying drawings. The present embodiments are not intended to limit the present application. In the following embodiments, the up-down direction of the semiconductor substrate indicates the relative direction when the face on which the semiconductor elements are provided is facing upward, and can be different from the up-down direction according to the gravitational acceleration. The drawings are schematic or conceptual views, and the ratio of each part, etc. is not necessarily the same as that of an actual product. In the specification and drawings, the same elements as those already described above in the drawings are denoted with the same reference numerals, and detailed description thereof will be appropriately omitted.

[0025] (First Embodiment)

[0026] Figure 1 is a view showing one configuration example of a memory cell array in the semiconductor storage device of the first embodiment. The memory cell array MCA is, for example, a three-dimensional memory cell array in which memory cells are three-dimensionally arranged. In addition, in Figure 1 , the illustration of the insulating portions other than the insulating film formed in the memory hole 113 is omitted for easy observation of the drawing. In addition, silicon is exemplified as the semiconductor in the following embodiments, but a semiconductor other than silicon can also be used.

[0027] In addition, in the present specification, an XYZ orthogonal coordinate system is introduced for convenience of explanation. In this coordinate system, two directions parallel to the main face of the substrate 100 and orthogonal to each other are set as the X direction and the Y direction, and a direction orthogonal to both the X direction and the Y direction is set as the Z direction. The plurality of word lines (conductive layers) WL are stacked in the Z direction.

[0028] As shown in Figure 1 , an n-type well region 101 is formed in the semiconductor substrate 100, and a p-type well region 102 is formed on the n-type well region 101. On the p-type well region 102, a plurality of NAND strings NS are formed. Specifically, on the p-type well region 102, a plurality of wiring layers 110 functioning as selection gate lines SGS, a plurality of wiring layers 111 functioning as word lines WL, and a plurality of wiring layers 112 functioning as selection gate lines SGD are formed.

[0029] The wiring layer 110 is formed of, for example, 4 layers, and is electrically connected to the common selection gate line SGS by the plurality of NAND strings NS, and functions as a gate electrode of two selection transistors ST2.

[0030] The wiring layer 111 is formed of, for example, 8 layers, and is electrically connected to the common word line WL for each layer.

[0031] The wiring layer 112 is formed of, for example, 4 layers, and is connected to the selection gate line SGD corresponding to each NAND string NS, and functions as a gate electrode of one selection transistor ST1, respectively.

[0032] The memory hole 113 is formed so as to reach the p-type well region 102 through the wiring layers 110, 111, and 112. On the side surface of the memory hole 113, a barrier insulating film 114, a charge accumulation layer 115 (insulating film), and a gate insulating film 116 are formed in this order. The conductive film 117 is filled in the memory hole 113. The conductive film 117 functions as a current path of the NAND string NS. On the upper end of the conductive film 117, the wiring layer 118 functioning as a bit line BL is formed. Further, the details of the memory hole 113 will be described with reference to FIG. 2. Figure 2A and Figure 2B Hereinafter, the description will be made.

[0033] As described above, on the p-type well region 102, the selection transistor ST2, the plurality of memory cell transistors MT, and the selection transistor ST1 are laminated in this order, and one memory hole 113 corresponds to one NAND string NS.

[0034] In the surface of the p-type well region 102, an n+-type impurity diffusion layer 103 and a p+-type impurity diffusion layer 104 are formed.

[0035] The contact plug 119 is formed on the n+-type impurity diffusion layer 103, and the wiring layer 120 functioning as a source line CELSRC is formed on the contact plug 119. The source line CELSRC is also formed in the M2 layer, and the source line CELSRC of the M2 layer is electrically connected to a voltage generation circuit.

[0036] The contact plug 121 is formed on the p+-type impurity diffusion layer 104, and the wiring layer 122 functioning as a well wiring CPWELL is formed on the contact plug 121.

[0037] The M0 layer in which the wiring layers 120 and 122 are formed is formed above the wiring layer 112 (select gate line SGD) and below the M1 layer in which the wiring layer 118 is formed.

[0038] The above configuration is arranged in the depth direction of the paper face on which Figure 1 One finger is constituted by a set of the plurality of NAND strings NS arranged in a row in the depth direction.

[0039] Further, the wiring layers 110 function as common select gate lines SGS in the same block and are electrically connected to each other. Between the lowermost wiring layer 110 and the p-type well region 102, the gate insulating film 116 is formed. The lowermost wiring layer 110 and the gate insulating film 116 adjacent to the n+-type impurity diffusion layer 103 are formed up to the vicinity of the n+-type impurity diffusion layer 103.

[0040] Thus, in a case where the transistor ST2 is selected to be in an on state, the channel formed connects the storage unit transistor MT0 and the n+ impurity diffusion layer 103. The voltage generation circuit can apply a potential to the conductive film 117 by applying a voltage to the well wiring CPWELL.

[0041] Figure 2A Figure 2B is a schematic cross-sectional view illustrating a storage unit of a three-dimensional structure. A plurality of columns CL are provided in a memory hole 113 (hereinafter referred to as a memory hole MH). The plurality of columns CL each include a semiconductor body 210, a memory film 220, and a core layer 230.

[0042] As shown in Figure 2A Figure 2B The memory hole MH in the X-Y plane has a shape such as a circle or an ellipse, for example. A barrier insulating film 21a, which constitutes a part of the memory film 220, can be provided between the conductive layer 21 and the insulating layer 22. The barrier insulating film 21a is a silicon oxide film or a metal oxide film, for example. One example of the metal oxide is aluminum oxide. The barrier insulating film 21a suppresses reverse tunneling of charges from the conductive layer 21 to the memory film 220 side.

[0043] The semiconductor body 210 has a shape such as a bottomed cylindrical shape, for example. The semiconductor body 210 includes silicon, for example. The silicon is polycrystalline silicon obtained by crystallizing amorphous silicon, for example. The semiconductor body 210 is non-doped silicon, for example. Alternatively, the semiconductor body 210 can be p-type silicon. The semiconductor body 210 becomes a channel of each of the drain-side select transistor STD, the storage unit MC, and the source-side select transistor STS.

[0044] The memory film 220 is provided between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 has a shape such as a cylindrical shape, for example. A plurality of storage units MC have a storage region between the semiconductor body 210 and the conductive layer 21 which becomes a word line WL, and are stacked in the Z-axis direction. The memory film 220 includes a cover insulating film 221, a charge trapping film 222, and a tunnel insulating film 223, for example. The semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 each extend in the Z-axis direction.

[0045] ​​A cover insulating film 221 is provided between the conductive layer 21 and the insulating layer 22 and the charge trapping film 222. The cover insulating film 221 contains, for example, silicon oxide. The cover insulating film 221 protects the charge trapping film 222 from being etched when the sacrificial film (not shown) is replaced with the conductive layer 21 (replacement process). The cover insulating film 221 can also be removed from between the conductive layer 21 and the memory film 220 in the replacement process. In this case, a barrier insulating film 21a is provided between the conductive layer 21 and the charge trapping film 222, for example. Alternatively, the cover insulating film 221 can be omitted when the conductive layer 21 is formed without using the replacement process.

[0046] The charge trapping film 222 is provided between the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 contains, for example, silicon nitride, and has trapping sites for trapping charges in the film. The portion of the charge trapping film 222 sandwiched between the conductive layer 21 serving as a word line WL and the semiconductor body 210 constitutes a memory region of a memory cell MC. The threshold voltage of the memory cell MC varies depending on the presence or absence of a charge in the charge trapping portion, or the amount of the trapped charge in the charge trapping portion. Thus, the memory cell MC stores information.

[0047] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 contains, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. When electrons are injected from the semiconductor body 210 to the charge trapping portion (write operation), and when electron holes are injected from the semiconductor body 210 to the charge trapping portion (erase operation), for example, the electrons and the electron holes pass through the potential barrier (tunnel) of the tunnel insulating film 223, respectively.

[0048] The core layer 230 fills the inner space of the cylindrical semiconductor body 210. The core layer 230 has, for example, a columnar shape. The core layer 230 contains, for example, silicon oxide, and has insulating properties.

[0049] Figure 3 is a cross-sectional view showing the configuration of the semiconductor device of the first embodiment. Furthermore, Figure 3 is also an enlarged view of the memory cell MC and its periphery.

[0050] As explained with reference to Figure 1 and Figure 2A , the semiconductor device has a laminate on the semiconductor substrate 100, the laminate having a plurality of conductive layers 21 and a plurality of insulating layers 22 alternately laminated in the Z direction. In addition, the semiconductor device also has an insulating layer (barrier insulating film 21a) provided between the conductive layer 21 and the insulating layer 22.

[0051] As Figure 3The conductive layer 21 has a metal layer 211 and a metal layer 212 as shown.

[0052] The metal layer 211 contains a first metal element and a substance that chemically reacts with a material gas containing the first metal element. The main component of the metal layer 211 is the first metal element. The first metal element is, for example, tungsten (W). The material gas is, for example, tungsten hexafluoride (WF6) gas. The substance that chemically reacts with the material gas is, for example, silicon (Si). In addition, the substance that chemically reacts with the material gas is volatilized by the reaction. That is, tungsten hexafluoride reduces silicon, and the metal layer 211 as a tungsten film is formed. On the other hand, silicon is oxidized and reacts with fluorine of tungsten hexafluoride to be volatilized as SiF4. x In addition, SiF4 x is not necessarily all volatilized. Therefore, a part of SiF4 x remains in the metal layer 211. Thus, the silicon concentration of the metal layer 211 is higher than that of the metal layer 212.

[0053] The metal layer 211 functions as a base layer or a core formation layer for the metal layer 212 that is different in formation method. The covering property of the metal layer 211 with respect to steps and the like is higher than that of the metal layer 212. Therefore, by providing the metal layer 211, the conductive layer 21 can be more appropriately formed on the barrier insulating film 21a.

[0054] The metal layer 212 is provided in such a manner that the metal layer 211 is disposed between the metal layer 212 and the insulating layer 22. Therefore, as shown in FIG. 2, from the lower insulating layer 22 to the upper insulating layer 22, five layers are provided in the order of the barrier insulating film 21a, the metal layer 211, the metal layer 212, the metal layer 211, and the barrier insulating film 21a in the Z direction. Figure 3

[0055] In addition, the metal layer 212 contains the first metal element, and the content of the substance that chemically reacts with the material gas is less than that of the metal layer 211. The reason for this is that, as described below, the metal layer 212 is formed differently from the metal layer 211, and silicon is not used. In addition, the resistance of the metal layer 212 is lower than that of the metal layer 211.

[0056] In addition, as described with reference to Figure 2A and Figure 2B , the semiconductor device further has a columnar portion (column CL) provided in such a manner as to penetrate the stacked body in the Z direction. The column CL contains a charge trapping film 222 as a charge accumulation layer and a semiconductor body 210 as a semiconductor layer.

[0057] The metal layer 211 is disposed between the metal layer 212 and the charge trapping film 222 and the semiconductor body 210. Therefore, as shown in FIG. 2, the metal layer 211 is disposed between the metal layer 212 and the columnar portion (column CL) provided in such a manner as to penetrate the stacked body in the Z direction. Figure 3 ​As shown, three layers are provided in the Y direction in the order of the barrier insulating film 21a, the metal layer 211, and the metal layer 212, from the cover insulating film 221.

[0058] Next, a method of manufacturing a semiconductor device will be described.

[0059] Figures 4-8 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment.

[0060] First, as shown in Figure 4 , a laminate having a plurality of sacrificial layers 24 and a plurality of insulating layers 22 alternately laminated in the Z direction is formed. In addition, in the example shown in Figure 4 , a memory hole MH is formed in the laminate, and a pillar CL is formed in the memory hole MH.

[0061] Next, as shown in Figure 5 , the sacrificial layers 24 are removed from the laminate. The sacrificial layers 24 are, for example, silicon nitride films. In this case, the sacrificial layers 24 can be selectively removed using an etching liquid containing phosphoric acid. Thus, voids 24a between the insulating layers 22 are formed. In addition, the cover insulating film 221 is exposed through the voids 24a.

[0062] Next, as shown in Figure 6 , the barrier insulating film 21a is formed in a part of the region in which the sacrificial layers 24 are removed (the voids 24a). That is, the barrier insulating film 21a is formed on the insulating layers 22 and the cover insulating film 221.

[0063] Next, as shown in Figure 7 , the reaction layer 213 is formed in a part of the region in which the sacrificial layers 24 are removed. That is, the reaction layer 213 is formed on the barrier insulating film 21a. The reaction layer 213 contains, as a main component, a substance that chemically reacts with a material gas containing a first metal element. The reaction layer 213 is, for example, a silicon layer. The reaction layer 213 is formed, for example, by a CVD (Chemical Vapor Deposition) method using a gas containing silicon such as monosilane (SiH4) or disilane (Si2H6).

[0064] Next, as shown in Figure 8 , a material gas is supplied to the region in which the sacrificial layers 24 are removed. By causing the reaction layer to chemically react with the material gas, the metal layer 211 containing the first metal element and a substance that chemically reacts with the material gas is formed. Details of the formation process of the metal layer 211 will be described later with reference to Figures 9A-9C .

[0065] In Figure 8Following the previous process, a metal layer 212 is formed on the metal layer 211 by filling the area where the sacrificial layer 24 has been removed. The metal layer 212 contains a first metallic element, and the amount of the substance that chemically reacts with the material gas is less than that of the metal layer 211. For example, hydrogen (H2) and tungsten hexafluoride gas are used to form the metal layer 212. Thus, the process is complete. Figure 3 The semiconductor device shown.

[0066] Next, for Figure 8 The details of the formation process of the metal layer 211 in the process are explained.

[0067] Figures 9A-9B It means Figure 8 A schematic diagram of the formation process of metal layer 211 in the process. From Figures 9A to 9C Time passed. Figure 9A express Figure 7 The state. Figure 9C express Figure 8 The state. Figure 9B express Figure 7 and Figure 8 The process between. In Figure 8 In the Z direction, a blocking insulating film 21a (e.g., an aluminum oxide film) is provided on the insulating layer 22 (e.g., a silicon oxide film). On the other hand, in Figure 8 In the Y direction, a blocking insulating film 21a is provided on the covering insulating film 221 (e.g., silicon oxide film).

[0068] Figure 9A This indicates the time point at which the reaction layer 213 is formed by supplying silane. The thickness of the reaction layer 213 is, for example, about 1 nm to about 5 nm.

[0069] Figure 9B This indicates the time point X seconds after the tungsten hexafluoride gas is supplied, which is shorter than Y seconds. A silicon reduction reaction occurs from the surface-side reaction layer 213 towards the barrier insulating film 21a, forming a metal layer 211.

[0070] Figure 9C This indicates the time point Y seconds after the start of tungsten hexafluoride gas supply. For example... Figure 9C As shown, almost all reaction layers 213 react to form a metal layer 211. Furthermore, even when tungsten hexafluoride gas is supplied for more than Y seconds, the thickness of the metal layer 211 (tungsten layer) remains unchanged. Therefore, by stopping the supply of tungsten hexafluoride gas at the point when almost all reaction layers 213 have finished reacting, the effects of residual tungsten hexafluoride gas can be suppressed. Sometimes, residual tungsten hexafluoride can cause adverse effects such as deterioration of leakage characteristics on the barrier insulating film 21a, insulating layer 22, or covering insulating film 221. This is because, for example, fluoride ions diffuse in the oxide film using heat, creating defects.

[0071] That is, by supplying a material gas to the region from which the sacrificial layer 24 is removed for a time corresponding to the thickness of the reaction layer 213, the reaction layer 213 is caused to chemically react with the material gas, and the metal layer 211 is formed. For example, by fixing the reaction conditions such as temperature and gas concentration, which are related to the reaction rate, and investigating in advance the relationship between the gas supply time and the thickness of the metal layer 211, the timing at which substantially all of the reaction layer 213 has reacted (Y seconds) can be found. For example, if the thickness of the reaction layer 213 is halved, the gas supply time can be halved. Thus, by adjusting the gas supply time, the amount of reaction can be adjusted. As a result, the invasion of fluorine into the barrier insulating film 21a and the insulating layer 22 can be suppressed, and the degradation of reliability such as leakage characteristics can be suppressed. Figure 9C

[0072] As described above, according to the first embodiment, the metal layer 211 includes a first metal element and a substance that chemically reacts with a material gas including the first metal element. That is, the metal layer 211 is formed by silicon reduction of tungsten hexafluoride gas with respect to the silicon layer. In addition, the reaction is performed from the surface side of the silicon layer. Thus, at the timing at which substantially all of the silicon layer has reacted, the supply of the tungsten hexafluoride gas can be stopped. Thereby, the influence of fluorine included in the material gas can be suppressed, and the degradation of the leakage characteristics of the insulating layer can be suppressed.

[0073] Figure 10 is a cross-sectional view showing the configuration of a semiconductor device of a comparative example.

[0074] Generally, as shown in Figure 10 , a barrier insulating film 21a and a conductive layer 21 are provided with a barrier film 21b. For example, in the case where the conductive layer 21 is tungsten, the barrier film 21b is, for example, a laminated structure film of titanium nitride (TiN) and titanium (Ti). The barrier film 21b is, for example, provided in order to suppress the degradation of reliability such as leakage characteristics. The manufacturing method of the metal layer 211a of the comparative example is different from that of the metal layer 211 of the first embodiment. The metal layer 211a is, for example, formed by repeatedly performing the supply of tungsten hexafluoride gas and the supply of diborane (B2H6) gas. However, in this case, the remaining tungsten hexafluoride can possibly invade the barrier insulating film 21a, the insulating layer 22, or the cover insulating film 221. Thus, it is necessary to protect the barrier insulating film 21a, the insulating layer 22, and the cover insulating film 221 with the barrier film 21b.

[0075] In contrast to this, in the first embodiment, by adjusting the gas supply time, the supply of tungsten hexafluoride gas can be stopped at the timing at which substantially all of the reaction layer 213 has reacted. Thereby, the invasion of the remaining tungsten hexafluoride into the barrier insulating film 21a, the insulating layer 22, or the cover insulating film 221 can be suppressed. As a result, the barrier film 21b is not necessary, and the number of manufacturing steps can be reduced. Figure 10 ​The fluorine concentration in the barrier insulating film 21a and the insulating layer 22 can be suppressed by about 1 order of magnitude, for example, compared to the comparative example shown in FIG. 6. That is, without using the barrier film 21b, the fluorine diffusion can be suppressed, and thus the reliability degradation such as the leakage characteristics can be suppressed.

[0076] Therefore, in the first embodiment, as shown in FIG. 1, Figure 3 the metal layer (barrier film 21b) including the second metal element different from the first metal element is not provided between the conductive layer 21 and the insulating layer 22. The second metal element is titanium (Ti), for example.

[0077] Figure 3 and Figure 10 The height WLh of the word line WL has a tendency to decrease with miniaturization. The more the height WLh decreases, the more the wiring resistance of the word line WL increases. As a method of reducing the wiring resistance, it is considered to increase the height (volume) of the metal layer 212 which has a relatively low resistance. In the example shown in FIG. 1, the barrier film 21b is omitted. The reason is that, generally, the barrier film 21b has a higher resistance than the conductive layer 21 (metal layer 212). As a result, the height of the metal layer 212 can be increased within the limited height WLh, and thus the wiring resistance of the word line WL can be suppressed. Figure 3

[0078] In addition, in the first embodiment, the barrier film 21b can also be provided. In this case, as compared to the comparative example shown in FIG. 6, the barrier film 21b can also be made thinner, and thus the wiring resistance of the word line WL can be suppressed. Figure 10

[0079] (Second Embodiment)

[0080] Figure 11 is a cross-sectional view showing the configuration of the semiconductor device of the second embodiment. The second embodiment differs from the first embodiment in that the metal layer 211 contains nitrogen.

[0081] The metal layer 211 also contains nitrogen (N). More specifically, the metal layer 211 contains ammonia (NH3) 214. For example, a nitrided layer having a high nitrogen concentration is formed in the vicinity of the interface with the barrier insulating film 21a. With the nitrogen in the metal layer 211, the adhesion between the barrier insulating film 21a and the metal layer 211 (conductive layer 21) can be improved. It is considered that the reason is that, for example, the nitrogen in the metal layer 211 is chemically bonded with tungsten (W-N) and silicon (Si-N) in the metal layer 211, and aluminum (Al-N) in the barrier insulating film 21a.

[0082] Figure 12 is a schematic view showing the nitrogen concentration in the metal layer 211 of Figure 11 .

[0083] As shown in FIG. 2, the metal layer 211 contains nitrogen (N).​​Figure 12 As shown, the nitrogen concentration on the side of the insulating layer 22 in the metal layer 211 is higher than the nitrogen concentration on the side of the metal layer 212. The ammonia 214 concentration in the metal layer 211 is highest near the interface with the barrier insulating film 21a. In addition, in more detail, the nitrogen concentration of the metal layer 211 decreases from the side of the insulating layer 22 toward the side of the metal layer 212. The reason for this is that a portion of the ammonia 214 diffuses from the side of the barrier insulating film 21a toward the side of the metal layer 212.

[0084] Figure 13 is a cross-sectional view showing a manufacturing method of a semiconductor device according to the second embodiment.

[0085] After the barrier insulating film 21a is formed (see FIG. 2A), as shown in FIG. 2B, a region where the sacrificial layer 24 is removed is supplied with a nitrogen-containing gas. The nitrogen-containing gas is, for example, ammonia (NH3). The supply time of the ammonia is, for example, about 10 seconds to about 60 seconds. By this, ammonia 214 is adsorbed on the barrier insulating film 21a. The subsequent processes are the same as those of the first embodiment. Figure 6 Figure 13 Figure 7 Here, the barrier film 21b shown in the comparative example is sometimes used not only to improve the reliability explained in the first embodiment, but also to improve, for example, the adhesion of the conductive layer 21 to the barrier insulating film 21a.

[0086] In contrast to this, in the second embodiment, the adhesion of the conductive layer 21 to the barrier insulating film 21a can be improved using the nitrogen (ammonia 214) contained in the metal layer 211. That is, without using the barrier film 21b, the adhesion of the conductive layer 21 to the barrier insulating film 21a can be improved. Figure 10

[0087]

[0088] The embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made within the scope of the gist of the application. These embodiments or changes thereof are included in the scope or gist of the application, and are also included in the scope of the application and equivalents thereof recited in the claims.

[0089] [Explanation of Symbols]

[0090] 21: conductive layer

[0091] 210: semiconductor body

[0092] 211: metal layer

[0093] 212: metal layer

[0094] 21a: barrier insulating film

[0095] ​​​​21b: Barrier film

[0096] 22: Insulating layer

[0097] 213: Reaction layer

[0098] 214: Ammonia

[0099] 222: Charge trapping film

[0100] 24: Sacrificial layer

[0101] 24a: Void

[0102] CL: Column

Claims

1. A semiconductor device comprising a laminate having a plurality of conductive layers and a plurality of first insulating layers alternately laminated in a first direction, the conductive layer has: a first metal layer containing a first metal element and a substance that chemically reacts with a material gas containing the first metal element; and a second metal layer containing the first metal element and having a smaller content of the substance than the first metal layer; the first metal layer is disposed between the first insulating layer and the second metal layer and contains nitrogen (N), and a nitrogen concentration on the first insulating layer side of the first metal layer is higher than a nitrogen concentration on the second metal layer side.

2. The semiconductor device according to claim 1, wherein a third metal layer containing a second metal element different from the first metal element is not provided between the conductive layer and the first insulating layer.

3. The semiconductor device according to claim 2, wherein the second metal element is titanium (Ti).

4. The semiconductor device according to claim 1, wherein the first metal element is tungsten (W), the material gas is tungsten hexafluoride (WF6) gas, the substance is silicon (Si).

5. The semiconductor device according to claim 1, wherein the nitrogen concentration of the first metal layer decreases from the first insulating layer side toward the second metal layer side.

6. The semiconductor device according to claim 1, wherein the nitrogen concentration of the first metal layer decreases from the first insulating layer side toward the second metal layer side.

7. The semiconductor device according to claim 1, further comprising a columnar portion provided so as to penetrate the laminate in the first direction and containing a charge accumulation layer and a semiconductor layer, the first metal layer is disposed between the second metal layer and the charge accumulation layer and the semiconductor layer.

8. The semiconductor device according to claim 1, further comprising a second insulating layer provided between the conductive layer and the first insulating layer.

9. A method for manufacturing a semiconductor device, comprising the steps of: removing a plurality of sacrificial layers from a laminate having the plurality of sacrificial layers and a plurality of first insulating layers alternately laminated in a first direction; supplying a nitrogen-containing gas to a region from which the sacrificial layers are removed; forming a reaction layer containing a substance that chemically reacts with a material gas containing a first metal element in a part of the region from which the sacrificial layers are removed; forming a first metal layer containing the first metal element and the substance by chemically reacting the reaction layer with the material gas by supplying the material gas to the region from which the sacrificial layers are removed; and forming a second metal layer containing the first metal element and having a smaller content of the substance than the first metal layer on the first metal layer so as to fill the region from which the sacrificial layers are removed.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of forming the first metal layer by chemically reacting the reaction layer with the material gas by supplying the material gas to the region from which the sacrificial layers are removed for a time corresponding to a thickness of the reaction layer.

11. The method for manufacturing a semiconductor device according to claim 9, further comprising the steps of forming a second insulating layer in a part of the region where the sacrificial layer is removed before the reaction layer is formed, and supplying a nitrogen-containing gas to the region where the sacrificial layer is removed.

12. The method for manufacturing a semiconductor device according to claim 10, further comprising the steps of forming a second insulating layer in a part of the region where the sacrificial layer is removed before the reaction layer is formed, and supplying a nitrogen-containing gas to the region where the sacrificial layer is removed.

13. The method for manufacturing a semiconductor device according to claim 9, wherein the nitrogen-containing gas is ammonia (NH3).

14. The method for manufacturing a semiconductor device according to claim 11, wherein the nitrogen-containing gas is ammonia (NH3).

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