Solid-state imaging device

Abstract

A solid-state imaging device can include a first structure, a glass substrate, and a second structure including an output circuit that outputs a pixel signal from a pixel of the first structure, wherein a first multi-layer wiring layer of the first structure is connected to a second multi-layer wiring layer of the second structure in at least one location, and wherein the first structure is directly bonded to the second structure by a first bonding layer of the first structure and a second bonding layer of the second structure, the first multi-layer wiring layer being on the first bonding layer and the second multi-layer wiring layer being on the second bonding layer.

Description

[0001] This application is a divisional application of patent application No. 201680023750.8 with a filing date of May 2, 2016, entitled "Solid-state Imaging Device, Method for Manufacturing the Same, and Electronic Device". TECHNICAL FIELD

[0002] The present application relates to a solid-state imaging device, a method for manufacturing the same, and an electronic device, and more particularly to a solid-state imaging device, a method for manufacturing the same, and an electronic device that can further reduce the device size. BACKGROUND

[0003] By proposing a configuration in which a plurality of semiconductor substrates are stacked (for example, refer to Patent Literature 1), a solid-state imaging device such as a complementary metal-oxide semiconductor (CMOS) image sensor is further reduced in size.

[0004] LIST OF CITATIONS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: JP 2014-72294 A SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] As the solid-state imaging device is reduced in size, it is difficult to reduce the device in size because the area of the terminal portion from which the output signal is extracted increases relative to the horizontal size of the device.

[0009] The present application has been made in view of such circumstances, and aims to further reduce the device size.

[0010] TECHNICAL SOLUTION TO THE PROBLEM

[0011] The solid-state imaging device according to the first aspect of the present application includes a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed, a glass substrate positioned above the first structure, and a second structure positioned below the first structure, in which an input circuit unit for allowing a predetermined signal to be input from the outside of the device, an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device, and a signal processing circuit are formed. An output unit and an input unit are provided below the pixel array unit of the first structure, the output unit includes the output circuit unit, a first via connected to the output circuit unit and penetrating a semiconductor substrate for constituting a part of the second structure, and an external terminal for signal output connecting the output circuit unit to the outside of the device through the first via, and the input unit includes the input circuit unit, a second via connected to the input circuit unit and penetrating the semiconductor substrate, and an external terminal for signal output connecting the input circuit unit to the outside of the device through the second via.

[0012] The solid-state imaging device according to the first aspect of the present application includes a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed, a glass substrate positioned above the first structure, and a second structure positioned below the first structure, in which an input circuit unit for allowing a predetermined signal to be input from the outside of the device, an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device, and a signal processing circuit are formed. An output unit and an input unit are provided below the pixel array unit of the first structure, the output unit includes the output circuit unit, a first via connected to the output circuit unit and penetrating a semiconductor substrate for constituting a part of the second structure, and an external terminal for signal output connecting the output circuit unit to the outside of the device through the first via, and the input unit includes the input circuit unit, a second via connected to the input circuit unit and penetrating the semiconductor substrate, and an external terminal for signal output connecting the input circuit unit to the outside of the device through the second via.

[0013] The solid-state imaging device according to the second aspect of the present application includes a laminate of a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed and a second structure in which an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device is formed. The output circuit unit, a first via hole that penetrates a semiconductor substrate for constituting a part of the second structure, and a signal output external terminal that is connected to the outside of the device are provided below the pixel array unit of the first structure. The output circuit unit is connected to the signal output external terminal through the first via hole.

[0014] The manufacturing method of the solid-state imaging device according to the third aspect of the present application includes: bonding a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed and a second structure in which an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device is formed below the pixel array unit so that wiring layers face each other; forming a via hole that penetrates a semiconductor substrate for constituting a part of the second structure; and forming a signal output external terminal at a position below the pixel array unit of the first structure, the signal output external terminal being electrically connected to the output circuit unit through the via hole and connected to the outside of the device.

[0015] According to the third aspect of the present application, a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed and a second structure in which an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device is formed below the pixel array unit are bonded so that wiring layers face each other. A via hole that penetrates a semiconductor substrate for constituting a part of the second structure is formed. A signal output external terminal is formed at a position below the pixel array unit of the first structure, the signal output external terminal being electrically connected to the output circuit unit through the via hole and connected to the outside of the device.

[0016] The electronic device according to the fourth aspect of the present application includes a solid-state imaging device including a laminate of a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed and a second structure in which an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device is formed. The output circuit unit, a via hole, and a signal output external terminal are provided below the pixel array unit of the first structure, the via hole penetrates a semiconductor substrate for constituting a part of the second structure, and the signal output external terminal is connected to the outside of the device. The output circuit unit is connected to the signal output external terminal through the via hole.

[0017] According to the second and fourth aspects of the present application, a laminate includes a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed and a second structure in which an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device is formed. The output circuit unit, a via hole, and a signal output external terminal are provided below the pixel array unit of the first structure, the via hole penetrates a semiconductor substrate for constituting a part of the second structure, and the signal output external terminal is connected to the outside of the device. The output circuit unit is connected to the signal output external terminal through the via hole.

[0018] The solid-state imaging device and the electronic device can be a stand-alone device or can be a module placed in another device.

[0019] Advantages of the Invention

[0020] According to the first to fourth aspects of the present application, the device size can be further reduced.

[0021] The effects described herein are not necessarily limiting and can also be any effect described herein. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a diagram illustrating a schematic configuration of a solid-state imaging device of the present application.

[0023] Figure 2 is a block diagram illustrating a system configuration example of a solid-state imaging device.

[0024] Figure 3 is a diagram illustrating a circuit arrangement configuration example of a pixel.

[0025] Figure 4 is a diagram illustrating a configuration example of an input circuit unit and an output circuit unit.

[0026] Figure 5is a view illustrating a first circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0027] Figure 6 is a view illustrating a cross-sectional structure along Figure 5 A-A' line in the solid-state imaging device.

[0028] Figure 7 is a view illustrating a second circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0029] Figure 8 is a view illustrating a cross-sectional structure along Figure 7 B-B' line in the solid-state imaging device.

[0030] Figure 9 is a view illustrating a cross section of the solid-state imaging device as a final shape of Comparative Example 1.

[0031] Figure 10 is a view illustrating a cross section of the solid-state imaging device as a final shape of Comparative Example 2.

[0032] Figure 11 is a view illustrating a cross section of the solid-state imaging device as a final shape of Comparative Example 3.

[0033] Figure 12 is a view illustrating a third circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0034] Figure 13 is a view illustrating a fourth circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0035] Figure 14 is a view illustrating a cross-sectional structure along Figure 13 C-C' line in the solid-state imaging device.

[0036] Figure 15 is a view illustrating a fifth circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0037] Figure 16 is a view illustrating a sixth circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0038] Figure 17 is a view illustrating a seventh circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0039] Figure 18 is a view illustrating an eighth circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0040] Figure 19FIG. 9 is a diagram illustrating a ninth circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0041] Figure 20 FIG. 10 is a diagram illustrating a tenth circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0042] Figure 21 FIG. 11 is a diagram illustrating a cross-sectional structure along a line D-D' in Figure 20 FIG. 12 is a diagram illustrating a cross-sectional structure along a line D-D' in

[0043] Figure 22 FIG. 13 is a diagram illustrating an eleventh circuit arrangement configuration example of a circuit arrangement in a solid-state imaging device.

[0044] Figure 23 FIG. 14 is an enlarged cross-sectional view illustrating a portion of the outer periphery of the solid-state imaging device 1.

[0045] Figure 24 FIG. 15 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0046] Figure 25 FIG. 16 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0047] Figure 26 FIG. 17 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0048] Figure 27 FIG. 18 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0049] Figure 28 FIG. 19 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0050] Figure 29 FIG. 20 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0051] Figure 30 FIG. 21 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0052] Figure 31 FIG. 22 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0053] Figure 32 FIG. 23 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0054] Figure 33 FIG. 24 is a diagram illustrating a manufacturing method of a solid-state imaging device having a twin contact structure.

[0055] Figure 34 This is a diagram illustrating the manufacturing method of a solid-state camera device with a dual-contact structure.

[0056] Figure 35 This is a diagram illustrating the manufacturing method of a solid-state camera device with a dual-contact structure.

[0057] Figure 36 This is a diagram illustrating the manufacturing method of a solid-state camera device with a dual-contact structure.

[0058] Figure 37 This is a diagram illustrating the manufacturing method of a solid-state camera device with a dual-contact structure.

[0059] Figure 38 This is a diagram illustrating the manufacturing method of a solid-state camera device with a dual-contact structure.

[0060] Figure 39 This is an explanation Figure 5 A diagram illustrating the manufacturing method of a solid-state camera device with a Cu-Cu direct bonding structure.

[0061] Figure 40 This is an explanation Figure 5 A diagram illustrating the manufacturing method of a solid-state camera device with a Cu-Cu direct bonding structure.

[0062] Figure 41 This is an explanation Figure 5 A diagram illustrating the manufacturing method of a solid-state camera device with a Cu-Cu direct bonding structure.

[0063] Figure 42 This is an explanation Figure 5 A diagram illustrating the manufacturing method of a solid-state camera device with a Cu-Cu direct bonding structure.

[0064] Figure 43 This is an explanation Figure 5 A diagram illustrating the manufacturing method of a solid-state camera device with a Cu-Cu direct bonding structure.

[0065] Figure 44 This is a diagram illustrating another modified embodiment 1 of the solid-state camera device.

[0066] Figure 45 This is a diagram illustrating another modified embodiment 2 of the solid-state camera device.

[0067] Figure 46 This is a diagram illustrating another modification example 3 of the solid-state camera device.

[0068] Figure 47 This is a diagram illustrating another modification example 4 of the solid-state camera device.

[0069] Figure 48 is a diagram illustrating an example in which the solid-state imaging device includes a three-layer stacked structure.

[0070] Figure 49 is a diagram illustrating an example in which the solid-state imaging device includes a three-layer stacked structure.

[0071] Figure 50 is a block diagram illustrating a configuration example of an imaging device as an electronic device of the present application.

[0072] Figure 51 is a diagram illustrating an example of use of the solid-state imaging device of Figure 1 DETAILED DESCRIPTION

[0073] Embodiments (hereinafter referred to as examples) for carrying out the present application will be explained below. Note that the explanation will be made in the following order.

[0074] 1. Schematic structure of solid-state imaging device

[0075] 2. System configuration of solid-state imaging device

[0076] 3. Circuit arrangement configuration example of pixel

[0077] 4. Configuration example of input circuit unit and output circuit unit

[0078] 5. Circuit arrangement configuration example of solid-state imaging device

[0079] 6. Cross-sectional structure of solid-state imaging device

[0080] 7. Circuit arrangement of solid-state imaging device in case of using other upper and lower wiring connection structure

[0081] 8. Example of comparison with other solid-state imaging device

[0082] 9. Other circuit arrangement configuration example of solid-state imaging device

[0083] 10. Detailed structure of solid-state imaging device

[0084] 11. Manufacturing method

[0085] 12. Other modification example

[0086] 13. Example of three-layer stacked structure

[0087] 14. Example applied to electronic device

[0088] 15. Example of use of image sensor

[0089] ​<1. Schematic structure of a solid-state imaging device>

[0090] Figure 1 A schematic configuration of a solid-state imaging device as a semiconductor device of the present application is illustrated.

[0091] Figure 1 The illustrated solid-state imaging device 1 converts light or electromagnetic waves incident on the device in the direction of the arrow in Figure 1

[0092] The solid-state imaging device 1 includes a laminated structure 13 in which a first structure 11 and a second structure 12 are laminated, an external terminal 14, and a protective substrate 18 formed on the upper side of the first structure 11. Note that, in the following description, for the sake of convenience, the side of the device on which the incident plane of light is incident is referred to as the upper side, the side of the device on the other plane facing the incident plane is referred to as the lower side, the first structure 11 is referred to as the upper structure 11, and the second structure 12 is referred to as the lower structure 12.

[0093] As described later, the solid-state imaging device 1 is formed by bonding a semiconductor substrate (wafer) constituting a part of the upper structure 11, a semiconductor substrate (wafer) constituting a part of the lower structure 12, and a wafer-level protective substrate 18, and then dividing the obtained structure into a plurality of single solid-state imaging devices 1.

[0094] In the structure of the upper structure 11 before being divided into a plurality of pieces, pixels for converting incident light into an electric signal are formed on the semiconductor substrate (wafer). For example, the pixels include a photodiode (PD) for photoelectric conversion and a plurality of pixel transistors for controlling a photoelectric conversion operation and a readout operation of an electric signal passing through the photoelectric conversion. There are cases where the upper structure 11 included in the solid-state imaging device 1 formed in a manner of being divided into a plurality of pieces is referred to as an upper chip, an image sensor substrate, or an image sensor chip.

[0095] Preferably, the pixel transistor provided in the solid-state imaging device 1 is, for example, a MOS transistor.

[0096] On the upper surface of the upper structure 11, for example, a color filter 15 of R (red), G (green), or B (blue) and an on-chip lens 16 are formed. The protective substrate 18 is provided on the upper side of the on-chip lens 16 for the purpose of protecting the structural objects of the solid-state imaging device 1, particularly the on-chip lens 16 and the color filter 15. The protective substrate 18 is, for example, a transparent glass substrate. If the hardness of the protective substrate 18 is higher than that of the on-chip lens 16, the protective substrate 18 more effectively protects the on-chip lens 16.​

[0097] In the structure of the lower structure 12 before being divided into multiple pieces, a semiconductor circuit including transistors and wiring is formed on a semiconductor substrate (wafer). There is a case where the lower structure 12 included in the solid-state imaging device 1 formed in a manner of being divided into multiple pieces is also referred to as a lower chip, a signal processing substrate, or a signal processing chip. A plurality of external terminals 14 (not illustrated) for electrically connecting with wiring outside the device are formed in the lower structure 12. The external terminals 14 are, for example, solder balls.

[0098] The solid-state imaging device 1 constitutes a cavity less structure in which the protection substrate 18 is fixed to the upper side of the upper structure 11 or the upper side of the on-chip lens 16 by the glass sealing resin 17 provided on the on-chip lens 16. Since the hardness of the glass sealing resin 17 is less than the hardness of the protection substrate 18, the glass sealing resin 17 can obtain an effect of relaxing transmission of pressure applied to the protection substrate 18 from the outside of the solid-state imaging device 1 to the inside of the device compared to a case where there is no sealing resin.

[0099] Note that, as a structure different from the cavity less structure, the solid-state imaging device 1 can be constituted so that a columnar or wall-shaped structure is formed on the upper surface of the upper structure 11 and a cavity structure fixed at the columnar or wall-shaped structure is formed, thereby supporting the protection substrate 18 on the on-chip lens 16 with a gap therebetween.

[0100] <2. System configuration of solid-state imaging device>

[0101] Figure 2 is a block diagram illustrating an example of a system configuration of the solid-state imaging device 1.

[0102] Figure 2 The solid-state imaging device 1 in the system configuration of the solid-state imaging device 1 includes a pixel array unit 24 in which a plurality of pixels 31 having a photoelectric conversion unit (PD) are arranged in a row direction and a column direction.

[0103] The pixel array unit 24 includes a row drive signal line 32 for driving the pixels 31 in units of rows and a vertical signal line (column read line) 33 for reading out a signal generated by photoelectric conversion from the plurality of pixels 31 driven in units of rows. As shown in Figure 2 The plurality of pixels 31 arranged in the row direction are connected to one row drive signal line 32. The plurality of pixels 31 arranged in the column direction are connected to one vertical signal line 33.

[0104] The solid-state imaging device 1 further includes a row drive unit 22 and a column signal processing unit 25.

[0105] The row drive unit 22 includes, for example, a row address control unit (in other words, a row decoder unit) that determines the position of the row in which the pixel to be driven is located, and a row drive circuit unit for generating a drive signal of the pixel 31.

[0106] The column signal processing unit 25 includes, for example, a load circuit unit connected to the vertical signal line 33 and forming a source follower circuit together with the pixel 31. In addition, the column signal processing unit 25 can include an amplifier circuit unit for amplifying a signal read out from the pixel 31 through the vertical signal line 33. In addition, the column signal processing unit 25 can further include a noise processing unit for removing a system noise level from a signal generated through photoelectric conversion that is read out from the pixel 31.

[0107] The column signal processing unit 25 includes an analog-digital converter (ADC) for converting a signal read out from the pixel 31 or an analog signal subjected to the above-described noise processing into a digital signal. The ADC includes a comparator unit for comparing an analog signal to be converted with a reference scan signal to be compared with the analog signal, and a counter unit that measures the number of times until the comparison result of the comparator unit is inverted. The column signal processing unit 25 can further include a horizontal scan circuit unit for controlling scanning of a read column.

[0108] The solid-state imaging device 1 further includes a timing control unit 23. The timing control unit 23 supplies a signal for controlling timing to the row drive unit 22 and the column signal processing unit 25 on the basis of a reference clock signal or a timing control signal input to the device. In the following description, in the present application, all or a part of the row drive unit 22, the column signal processing unit 25, and the timing control unit 23 are simply referred to as a pixel peripheral circuit unit, a peripheral circuit unit, or a control circuit unit.

[0109] The solid-state imaging device 1 further includes an image signal processing unit 26. The image signal processing unit 26 is a circuit that performs various signal processing on data obtained through photoelectric conversion (in other words, data obtained through an imaging operation of the solid-state imaging device 1). The image signal processing unit 26 is configured to include, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 26 can further include a processor unit.

[0110] An example of the signal processing performed in the image signal processing unit 26 can include a tone curve correction process for providing a certain amount of tone in the case where the AD-converted image data is data obtained by taking a dark object, and reducing tone in the case where the image data is data obtained by taking a bright object. In this case, it is preferable that tone curve characteristic data on which tone curve is used as a basis for correction of tone of the image data be stored in advance in the data holding unit of the image signal processing unit 26.

[0111] The solid-state imaging device 1 further includes an input unit 21A. The input unit 21A inputs, for example, the above-mentioned reference clock signal from outside the device to be stored in the data holding unit of the image signal processing unit 26, a timing control signal such as a vertical synchronization signal and a horizontal synchronization signal, characteristic data, and the like, to the solid-state imaging device 1. The input unit 21A includes an input terminal 41 which is an external terminal 14 for inputting data to the solid-state imaging device 1, and an input circuit unit 42 which extracts a signal input to the input terminal 41 to the inside of the solid-state imaging device 1.

[0112] The input unit 21A further includes an input amplitude varying unit 43 for varying an amplitude of a signal extracted by the input circuit unit 42 to an amplitude which can be easily utilized inside the solid-state imaging device 1.

[0113] The input unit 21A further includes an input data conversion circuit unit 44 for varying a sequence of a data string of input data. The input data conversion circuit unit 44 is, for example, a serial-parallel conversion circuit which receives a serial signal as input data, and converts the serial signal to a parallel signal.

[0114] Note that there is a case where the input amplitude varying unit 43 and the input data conversion circuit unit 44 are omitted.

[0115] In the case where the solid-state imaging device 1 is connected to an external memory device such as a flash memory, an SRAM, and a DRAM, the input unit 21A can further include a memory interface circuit for receiving data from these external memory devices.

[0116] The solid-state imaging device 1 further includes an output unit 21B. The output unit 21B outputs image data captured by the solid-state imaging device 1 and image data signal-processed by the image signal processing unit 26 from the solid-state imaging device 1 to the outside of the device. The output unit 21B includes an output terminal 48, which is an external terminal 14 for outputting data from the solid-state imaging device 1 to the outside of the device, and an output circuit unit 47, which is a circuit for outputting data from the inside of the solid-state imaging device 1 to the outside of the device, and is a circuit for driving an external wiring located outside the solid-state imaging device 1 which is connected to the output terminal 48.

[0117] The output circuit 21B further includes an output amplitude variation circuit 46 for varying the amplitude of a signal used inside the solid-state imaging device 1 to an amplitude which can be easily utilized in an external device connected to the outside of the solid-state imaging device 1.

[0118] The output circuit 21B further includes an output data conversion circuit unit 45 for varying the sequence of a data string of output data. For example, the output data conversion circuit unit 45 is a parallel-serial conversion circuit which converts a parallel signal used inside the solid-state imaging device 1 to a serial signal.

[0119] There are cases where the output data conversion circuit unit 45 and the output amplitude variation circuit 46 are omitted.

[0120] In a case where the solid-state imaging device 1 is connected to an external memory device such as a flash memory, an SRAM, and a DRAM, the output unit 21B can further include a memory interface circuit for outputting data to these external memory devices.

[0121] Note that, in the present application, there are cases where a circuit block including either or both of the input unit 21A and the output unit 21B is referred to as an input / output unit 21 for convenience. Further, there are cases where a circuit unit including either or both of the input circuit unit 42 and the output circuit unit 47 is referred to as an input / output circuit unit 49.

[0122] <3. Circuit arrangement configuration example of pixel>

[0123] Figure 3 A circuit arrangement configuration example of the pixel 1 of the solid-state imaging device 1 according to the present embodiment is illustrated.

[0124] The pixel 31 has a photodiode 51 as a photoelectric conversion element, a transfer transistor 52, a floating diffusion (FD) 53, a reset transistor 54, an amplification transistor 55, and a selection transistor 56.

[0125] The photodiode 51 generates and accumulates electric charges (signal charges) according to the amount of received light. The anode terminal of the photodiode 51 is grounded, and the cathode terminal is connected to the FD 53 via the transfer transistor 52.

[0126] When the transfer transistor 52 is turned on by the transfer signal TR, the transfer transistor 52 reads out the electric charges generated by the photodiode 51 and transfers the electric charges to the FD 53.

[0127] The FD 53 holds the electric charges read out from the photodiode 51. When the reset transistor 54 is turned on by the reset signal RST, the reset transistor 54 resets the potential of the FD 53 by discharging the electric charges accumulated in the FD 53 to the drain (constant voltage source Vdd).

[0128] The amplification transistor 55 outputs a pixel signal according to the potential of the FD 53. That is, the amplification transistor 55 constitutes a source follower circuit with a load MOS (not illustrated) connected through the vertical signal line 33 as a constant current source, and a pixel signal indicating a level in accordance with the electric charges accumulated in the FD 53 is output from the amplification transistor 55 to the column signal processing unit 25 through the selection transistor 56 and the vertical signal line 33.

[0129] When the pixel 31 is selected by the selection signal SEL, the selection transistor 56 is turned on and outputs the pixel signal of the pixel 31 to the column signal processing unit 25 through the vertical signal line 33. Each of the signal lines for transmitting the transfer signal TR, the selection signal SEL, and the reset signal RST corresponds to the row drive signal line 32 in Figure 2 .

[0130] Although the pixel 31 can be configured in the manner described above, the configuration thereof is not limited to this configuration, and other configurations can also be employed.

[0131] <4. Configuration example of input circuit unit and output circuit unit>

[0132] Figure 4 A circuit arrangement configuration example of the input circuit unit 42 provided in the input unit 21A and the output circuit unit 47 provided in the input unit 21B of the solid-state imaging device 1 according to the present embodiment is illustrated.

[0133] Note that, for one external terminal 14, the configuration of the input / output circuit unit 49 can include one of the input circuit unit 42 and the output circuit unit 47, or can be a bidirectional input / output circuit including both the input circuit unit 42 and the output circuit unit 47 in parallel.

[0134] The input circuit unit 42 is a circuit having the following features.

[0135] 1) The input circuit unit 42 is a circuit that maintains the same logic or inverts the logic only between data input from the input terminal 41 of the solid-state imaging device 1 to the input circuit unit 42 and data output from the input circuit unit 42 to the internal circuit of the solid-state imaging device 1. In other words, the input circuit unit 42 is a circuit that does not change the sequence of data in a signal sequence. Also, in other words, the input circuit unit 42 is a circuit that does not change a position at which logic "1" and "0" or "high" and "low" in a signal sequence are switched.

[0136] 2) The input circuit unit 42 is a circuit that converts the voltage amplitude of a signal input to the input terminal 41 of the solid-state imaging device 1 to a voltage amplitude that is advantageous for reception by a circuit (in other words, other circuit inside the solid-state imaging device 1) provided at a subsequent stage of the input circuit unit 42. There are cases in which the circuit converts data input to the circuit to have a smaller voltage amplitude.

[0137] 2) Alternatively, the input circuit unit 42 is a circuit that converts a signal (for example, amplitude differential signal of LVDS) input to the input circuit unit 42 to a format or voltage amplitude (for example, single end fully swings digital signal) that is advantageous for reception by a circuit (in other words, other circuit inside the solid-state imaging device 1) provided at a subsequent stage of the input circuit unit 42, and outputs the converted signal. There are cases in which the circuit converts data input to the circuit to have a larger voltage amplitude.

[0138] 3) Also, in a case in which excessive noise is input to the input circuit unit 42, there are cases in which a protection circuit is provided that cuts off the noise without propagating the noise to a circuit (in other words, other circuit inside the solid-state imaging device 1) provided at a subsequent stage of the input circuit unit 42.

[0139] The output circuit unit 47 is a circuit having the following characteristics.

[0140] 1) The output circuit unit 47 is a circuit that maintains the same logic or inverts the logic only between data input from the internal circuit of the solid-state imaging device 1 to the output circuit unit 47 and data output from the output circuit unit 47 to the outside of the solid-state imaging device 1 through the output terminal 48 of the solid-state imaging device 1. In other words, the output circuit unit 47 is a circuit that does not change the sequence of data in a signal sequence. Also, in other words, the output circuit unit 47 is a circuit that does not change a position at which logic "1" and "0" or "high" and "low" in a signal sequence are switched.

[0141] 2) The output circuit unit 47 is a circuit that increases the current capability of the signal line between the output terminal 48 of the solid-state camera device 1 and the external components connected to the solid-state camera device 1, or increases the voltage amplitude of the signal line. There are cases where this circuit converts the signal input to the circuit into one with a larger voltage amplitude.

[0142] 2) Alternatively, the output circuit unit 47 is a circuit that converts the signal (single-ended fully swing digital signal) input from the circuitry inside the solid-state imaging device 1 to the output circuit unit 47 into a format or voltage amplitude (e.g., a small-amplitude differential LVDS signal) that is convenient for external components connected to the output terminal 48 to receive, and outputs the converted signal. There are cases where the circuit converts data input to the circuitry into a signal with a reduced voltage amplitude.

[0143] like Figure 4 As shown, the input / output circuit unit 49, which includes at least one of the input circuit unit 42 and the output circuit unit 47, comprises one or more transistors. In this invention, for convenience, the transistors included in the input / output circuit unit 49 are referred to as input / output transistors. The input / output circuit unit 49 may include an inverter circuit, a buffer circuit, etc., or may also include an enable circuit for controlling input or output operations.

[0144] By appropriately setting the power supply voltage to be used in the circuit, the input circuit unit 42 or the output circuit unit 47 can also be used as an amplitude variation unit for the input signal or the output signal. For example, if the amplitude of the signal in a part of the pixel peripheral circuit unit or the image signal processing unit 26 of the solid-state imaging device 1 is V2, even if the amplitude of the signal input from outside the solid-state imaging device 1 to the input terminal 41 or the amplitude of the signal output from the output terminal 48 to the outside of the solid-state imaging device 1 is greater than V2, the circuit of the input circuit unit 42 or the output circuit unit 47 is, for example... Figure 4 In the circuit shown, by setting the power supply voltage of the inverter located on the internal circuit side of the solid-state camera device 1 to V2 and setting the power supply voltage of the inverter located on the outward side of the solid-state camera device 1 to V1, the input circuit unit 42 can receive a signal with amplitude V1 from the outside, and input the signal to the internal circuit of the solid-state camera device 1 after the amplitude drops to V2. The output circuit unit 47 can receive a signal with amplitude V2 from the internal circuit of the solid-state camera device 1, and output the signal to the outside after the amplitude increases to V1. Note that in... Figure 4In the case where the voltages V1 and V2 shown are the same voltage, the input circuit unit 42 and the output circuit unit 47 adopt a configuration that does not include a function of changing the signal amplitude.

[0145] Note that, in the present application including the above description, there is a case where the voltage difference between the reference voltage of the transistor circuit (in the case of the Figure 4 circuit, the ground voltage) and the power supply voltage that is to be supplied to the circuit and is different from the above-described reference voltage (in the case of the Figure 4 circuit, for example, V1) is simply referred to as the power supply voltage.

[0146] <5. Circuit arrangement configuration example of solid-state imaging device>

[0147] Next, the circuit arrangement of the solid-state imaging device 1 according to the present embodiment, that is, the manner in which the respective blocks of the solid-state imaging device 1 shown in FIG. 1 are mounted on the upper structure 11 and the lower structure 12 will be described. Figure 2

[0148] Figure 5 is a diagram illustrating a first circuit arrangement configuration example of the circuit arrangement in the solid-state imaging device 1.

[0149] In the first circuit arrangement configuration example, the pixel array unit 24 is provided in the upper structure 11.

[0150] Among the pixel peripheral circuit units of the solid-state imaging device 1, a part of the row drive unit 22 is provided in the upper structure 11, and a part of the row drive unit 22 is provided in the lower structure 12. For example, in the row drive unit 22, the row drive circuit unit is provided in the upper structure 11, and the row decoder unit is provided in the lower structure 12.

[0151] The row drive unit 22 provided in the upper structure 11 is provided outside the pixel array unit 24 in the row direction, and at least a part of the row drive unit 22 provided in the lower structure 12 is provided below the row drive unit 22 provided in the upper structure 11.

[0152] Among the pixel peripheral circuit units of the solid-state imaging device 1, a part of the column signal processing unit 25 is provided in the upper structure 11, and a part of the column signal processing unit 25 is provided in the lower structure 12. For example, in the column signal processing unit 25, the load circuit unit, the amplifier circuit unit, the noise processing unit, and the comparator unit of the ADC are provided in the upper structure 11, and the counter unit of the ADC is provided in the lower structure 12.

[0153] ​The column signal processing units 25 provided in the upper structure 11 are provided outside the pixel array unit 24 in the column direction, and at least a part of the column signal processing units 25 provided in the lower structure 12 is provided below the column signal processing units 25 provided in the upper structure 11.

[0154] The wiring connection units 29 for connecting the wirings of the row drive units 22 in the upper structure 11 and the row drive units 22 in the lower structure 12 are provided outside the row drive units 22 in the upper structure 11 and outside the row drive units 22 in the lower structure 12.

[0155] The wiring connection units 29 for connecting the wirings of the column signal processing units 25 in the upper structure 11 and the column signal processing units 25 in the lower structure 12 are also provided outside the column signal processing units 25 in the upper structure 11 and outside the column signal processing units 25 in the lower structure 12. In these wiring connection units 29, the wiring connection structure described later with reference to Figure 6 is used.

[0156] The image signal processing units 26 are provided inside the row drive units 22 and the column signal processing units 25 in the lower structure 12.

[0157] In the lower structure 12, the input / output circuit unit 49 is provided in a region below the pixel array unit 24 of the upper structure 11.

[0158] The input / output circuit unit 49 is a circuit unit including both or at least one of the input circuit unit 42 and the output circuit unit 47. In the case where the input / output circuit unit 49 includes both the input circuit unit 42 and the output circuit unit 47, a plurality of input / output circuit units 49 are provided in the lower structure 12 for each external terminal 14. In the case where the input / output circuit unit 49 is configured to have only the input circuit unit 42, a plurality of input circuit units 42 are provided in the lower structure 12 for each external terminal 14 (input terminal 41). In the case where the input / output circuit unit 49 is configured to have only the output circuit unit 47, a plurality of output circuit units 47 are provided in the lower structure 12 for each external terminal 14 (output terminal 48). The image signal processing unit 26 is provided around each of the plurality of separately provided input / output circuit units 49. In other words, the input / output circuit unit 49 is provided within a region in which the image signal processing unit 26 is provided.

[0159] Note that, in the lower structure 12, the input / output circuit unit 49 can be provided in a region below the row drive unit 22 or the column signal processing unit 25 in the upper structure 11.

[0160] In other words, the input / output circuit unit 49 can be provided in an arbitrary region on the lower structure 12 side where the external terminal 14 is formed, and positioned below the region of the pixel array unit 24 of the upper structure 11 or below the pixel peripheral circuit region 313 in the upper structure 11. Figure 6

[0161] Note that, in the solid-state imaging device 1 according to the present embodiment including other configuration examples to be described later, a power supply terminal or a ground terminal is provided in a region where the input terminal 41 and the input circuit unit 42, the output circuit unit 47, and the output terminal 48 are provided, instead of the input terminal 41 and the input circuit unit 42, the output circuit unit 47, and the output terminal 48.

[0162] Among the transistor circuits provided in the lower structure 12, the power supply voltage of the transistor circuits constituting the input circuit unit 42 and the output circuit unit 47 can be higher than the power supply voltage of the transistor circuits constituting the image signal processing unit 26.

[0163] For example, the power supply voltage of the transistor circuits constituting the input circuit unit 42 and the output circuit unit 47 can be 1.8 to 3.3 V, and the power supply voltage of the transistor circuits constituting the image signal processing unit 26 can be 1.2 to 1.5 V. Since the power supply voltage of the former (the transistor circuits constituting the input circuit unit 42 and the output circuit unit 47) is different from the power supply voltage of the latter (the transistor circuits constituting the image signal processing unit 26), the distance between the well region to which the power supply voltage is applied at the input circuit unit 42 and the output circuit unit 47 and the well region to which the power supply voltage is applied at the image signal processing unit 26 located around the input circuit unit 42 and the output circuit unit 47 (the two well regions are provided to be separated from each other), that is, the width of the well separation region, is preferably greater than the distance between the plurality of well regions to which the power supply voltage is applied within the image signal processing unit 26.

[0164] Further, the depth of the element separation region at the input circuit unit 42 and the output circuit unit 47 can be deeper than the depth of the element separation region within the image signal processing unit 26. In addition, the gate length of the transistor at the input circuit unit 42 and the output circuit unit 47 is preferably greater than the gate length of the transistor within the image signal processing unit 26.

[0165] ​In the pixel peripheral circuit unit of the solid-state imaging device 1, the power supply voltage of the transistor circuit constituting a part of the pixel peripheral circuit unit provided in the upper structure 11 (for example, one of the load circuit unit, the amplifier circuit unit, the noise processing unit, and the comparator unit of the ADC of the column signal processing unit 25) can be higher than the power supply voltage of the transistor circuit constituting a part of the pixel peripheral circuit unit provided in the lower structure 12 (for example, the counter unit of the ADC of the column signal processing unit 25). For example, the power supply voltage of the transistor circuit of the former (the pixel peripheral circuit unit provided in the upper structure 11, for example, one of the load circuit unit, the amplifier circuit unit, the noise processing unit, and the comparator unit of the ADC of the column signal processing unit 25) can be 1.8 to 3.3 V, and the power supply voltage of the transistor unit of the latter (the pixel peripheral circuit unit provided in the lower structure 12, for example, the counter unit of the ADC) can be 1.2 to 1.5 V. The power supply voltage of the transistor circuit of the latter can be the same as the power supply voltage of the transistor circuit constituting the image signal processing unit 26 provided in the lower structure 12. Since the power supply voltage of the transistor circuit of the former is higher than the power supply voltage of the transistor circuit of the latter, the distance between the plurality of well regions to which the power supply voltage is applied in the transistor circuit of the former is preferably greater than the distance between the plurality of well regions to which the power supply voltage is applied in the transistor circuit of the latter. Further, the depth of the element separation region at the transistor circuit of the former is preferably deeper than the depth of the element separation region at the transistor circuit of the latter. Further, the gate length of the transistor at the transistor circuit of the former is preferably longer than the gate length of the transistor at the transistor circuit of the latter.

[0166] Further, the power supply voltage of the pixel transistor constituting the pixel 31 provided in the upper structure 11 can be the same as the power supply voltage of the transistor circuit constituting the pixel peripheral circuit unit (for example, one of the load circuit unit, the amplifier circuit unit, the noise processing unit, and the comparator unit of the ADC of the column signal processing unit 25) provided in the upper structure 11.

[0167] The power supply voltage of the pixel transistor circuit constituting the pixel 31 provided in the upper structure 11 can be higher than the power supply voltage of the transistor circuit constituting the pixel peripheral circuit unit (for example, the counter unit of the ADC) provided in the lower structure 12 or the image signal processing unit 26. Therefore, in a case where the element isolation region having a structure formed by etching the semiconductor substrate into an element isolation region is used, the depth of a part of the element isolation region around the pixel transistor provided in the upper structure 11 can be deeper than the depth of the element isolation region around the transistor of the pixel peripheral circuit unit or the image signal processing unit 26 provided in the lower structure 12. Alternatively, as the element isolation region around the pixel transistor, as an alternative to the element isolation region formed by etching the semiconductor substrate, an element isolation region for forming an impurity region having a conductive type opposite to the conductive type of the diffusion layer of the pixel transistor can be partially used around the pixel transistor.

[0168] Further, the gate length of the pixel transistor provided in the upper structure 11 can be longer than the gate length of the transistor of the pixel peripheral circuit unit or the image signal processing unit 26 provided in the lower structure 12. Meanwhile, in consideration of the fact that the noise charge around the element isolation region increases as the element isolation region becomes deeper, in order to suppress the generation of noise charge around the element isolation region, the depth of the element isolation region around the pixel transistor provided in the upper structure 11 can be shallower than the depth of the element isolation region around the transistor constituting the pixel peripheral circuit unit in the upper structure 11.

[0169] <6. Cross-sectional structure of solid-state imaging device>

[0170] The cross-sectional structure and the circuit arrangement of the solid-state imaging device 1 according to the present embodiment will be further described with reference to Figure 6

[0171] Figure 6 is a view illustrating a cross-sectional structure along the line A-A' of the solid-state imaging device 1 according to Figure 5 Note that, for convenience, Figure 6 part of FIG. 1 is replaced with the cross-sectional structure of another configuration example of the present application described later.

[0172] ​The pixel array unit 24 is provided in a part of the upper structure 11 including the solid-state imaging device 1 and a part above the upper structure 11, and a plurality of pixels 31 are arranged in the pixel array unit 24 in an array form, each of the pixels 31 having an on-chip lens 16, a color filter 15, a pixel transistor, and a photodiode 51. A pixel transistor region 301 is also provided in a region (pixel array region) of the pixel array unit 24. The pixel transistor region 301 is a region in which at least one of a transfer transistor 52, an amplification transistor 55, and a reset transistor 54 is formed.

[0173] A plurality of external terminals 14 are provided on a surface of the lower side of the semiconductor substrate 81 of the lower structure 12 and in a region below the pixel array unit 24 provided in the upper structure 11.

[0174] Note that, in the description of Figure 6 the "region on the surface of the lower side of the semiconductor substrate 81 of the lower structure 12 and provided below the pixel array unit 24 of the upper structure 11" is referred to as a first specific region, and the "region on the surface of the upper side of the semiconductor substrate 81 of the lower structure 12 and provided below the pixel array unit 24 of the upper structure 11" is referred to as a second specific region.

[0175] At least a part of the plurality of external terminals 14 provided in the first specific region is a signal input terminal 14A for inputting a signal from the outside to the solid-state imaging device 1 or a signal output terminal 14B for outputting a signal from the solid-state imaging device 1 to the outside. In other words, the signal input terminal 14A and the signal output terminal 14B are external terminals 14 other than the power terminal and the ground terminal among the external terminals 14. In the present application, the signal input terminal 14A or the signal output terminal 14B is referred to as a signal input / output terminal 14C.

[0176] In the first specific region and in the vicinity of the signal input / output terminal 14C, a via hole 88 that penetrates the semiconductor substrate 81 is provided. Note that, in the present application, there is a case where a via hole that penetrates the semiconductor substrate 81 and a via hole wiring formed inside the via hole are collectively referred to as the via hole 88.

[0177] Preferably, the structure of the via hole is formed by being engraved from the lower surface of the semiconductor substrate 81 to a conductive pad 322 (hereinafter, there is a case where the conductive pad 322 is referred to as a via hole pad 322) that is a part of the multilayer wiring layer 82 provided above the upper surface of the semiconductor substrate 81, and the conductive pad 322 becomes an end portion (bottom portion) of the via hole.

[0178] The signal input / output terminal 14C provided in the first specific region is electrically connected to the via hole 88 (more specifically, a via hole wiring formed inside a via hole) provided in the same first specific region.

[0179] In the second specific region and in a region near the signal input / output terminal 14C and the above-mentioned via hole, an input / output circuit unit 49 including the input circuit unit 42 or the output circuit unit 47 is provided.

[0180] The signal input / output terminal 14C provided in the first specific region is electrically connected to the input / output circuit unit 49 through the via hole 88 and a portion of the via hole pad 322 or the multilayer wiring layer 82.

[0181] A region in which the input / output circuit unit 49 is provided is referred to as an input / output circuit region 311. On the upper surface of the semiconductor substrate 81 of the lower structure 12, a signal processing circuit region 312 is formed adjacent to the input / output circuit region 311. The signal processing circuit region 312 is a region in which a reference Figure 2 The region of the image signal processing unit 26 described above.

[0182] A region in which the reference Figure 2 A region in which the pixel peripheral circuit unit including all or a part of the row drive unit 22 and the column signal processing unit 25 described above is provided is referred to as a pixel peripheral circuit region 313. The pixel peripheral circuit region 313 is provided in a region outside the pixel array unit 24 on the lower surface of the semiconductor substrate 101 of the upper structure 11 and on the upper surface of the semiconductor substrate 81 of the lower structure 12.

[0183] The signal input / output terminal 14C can be provided in a region below the input / output circuit region 311 of the lower structure 12 or in a region below the signal processing circuit region 312. Alternatively, the signal input / output terminal 14C can be provided below the pixel peripheral circuit unit such as the row drive unit 22 and the column signal processing unit 24 of the lower structure 12.

[0184] In the present application, there is a case where a wiring connection structure connecting a wiring included in the multilayer wiring layer 102 of the upper structure 11 and a wiring included in the multilayer wiring layer 82 of the lower structure 12 is referred to as an up-down wiring connection structure, and a region in which this structure is provided is referred to as an up-down wiring connection region 314.

[0185] The upper and lower wiring connection structure is formed by a first through-hole electrode (through silicon via) 109, a second through-hole electrode (through chip via) 105, and a through-hole electrode connection wiring 106 connecting the two through silicon vias (TSVs). The first through-hole electrode 109 penetrates the semiconductor substrate 101 from the upper surface of the upper structure 11 and reaches the multilayer wiring layer 102. The second through-hole electrode 105 penetrates the semiconductor substrate 101 and the multilayer wiring layer 102 from the upper surface of the upper structure 11 and reaches the multilayer wiring layer 82 of the lower structure 12. In this invention, there is a case where the upper and lower wiring connection structure is referred to as a dual-contact structure.

[0186] The upper and lower wiring connection area 314 is located outside the pixel peripheral circuit area 313.

[0187] Although in this embodiment the pixel peripheral circuit region 313 is formed in both the upper structure 11 and the lower structure 12, the pixel peripheral circuit region 313 may be formed in only one of the upper structure 11 and the lower structure 12.

[0188] Furthermore, although in this embodiment the upper and lower wiring connection area 314 is disposed on the outside of the pixel array unit 24 and the outside of the pixel peripheral circuit area 313, the upper and lower wiring connection area 314 may be disposed on the outside of the pixel array unit 24 and the inside of the pixel peripheral circuit area 313.

[0189] Furthermore, in this embodiment, the structure that serves as the multilayer wiring layer 102 of the upper structure 11 and the multilayer wiring layer 82 of the lower structure 12 for electrical connection adopts a dual-contact structure that uses two through-hole electrodes, through silicon via 109 and through-chip via 105, for connection.

[0190] As a structure for electrically connecting the multilayer wiring layer 102 of the upper structure 11 and the multilayer wiring layer 82 of the lower structure 12, a common contact structure can be adopted, for example, where the wiring layer 103 of the upper structure 11 and the wiring layer 83 of the lower structure 12 are jointly connected to a through-hole electrode.

[0191] <7. Circuit layout of solid-state camera devices when using other top and bottom wiring connection structures>

[0192] Reference Figure 7 and 8 This describes the circuit layout and cross-sectional structure of the solid-state camera device 1 when using other top and bottom wiring connection structures.

[0193] Figure 8 The diagram shows the use of... Figure 6 The above and below wiring connection structures are different in the case of the structure. Figure 7 A cross-sectional view of the solid-state camera device 1 along line B-B'. Note that, for convenience, Figure 8part of the cross-sectional structure of another configuration example of the present application to be described later.

[0194] In Figure 8 In the pixel peripheral circuit region 313, a part of the wiring in the multilayer wiring layer 102 of the upper structure 11 is disposed on the lowermost surface of the multilayer wiring layer 102, in other words, on the joint surface of the upper structure 11 and the lower structure 12. Further, a part of the wiring in the multilayer wiring layer 82 of the lower structure 12 is also disposed on the uppermost surface of the multilayer wiring layer 82, in other words, on the joint surface of the upper structure 11 and the lower structure 12. The part of the wiring in the multilayer wiring layer 102 and the part of the wiring in the multilayer wiring layer 82 are substantially disposed at the same position on the joint surface, and these wirings are electrically connected to each other. As a manner in which the wirings are electrically connected to each other, a manner in which the two wirings are directly brought into contact with each other, or a manner in which a thin insulating film or a high-resistance film is formed between the two wirings and a part of the formed film is electrically conductive can be employed. Alternatively, a manner in which a thin insulating film or a high-resistance film is formed between the two wirings and the two wirings propagate electric charges by capacitive coupling can be employed.

[0195] In the present application, there is a case where the structure in which a part of the wiring of the multilayer wiring layer 102 of the upper structure 11 and a part of the wiring of the multilayer wiring layer 82 of the lower structure 12 are formed at the same position on the above-mentioned joint surface and the two wirings are electrically connected is collectively called an upper-and-lower-wiring-direct-connection structure or simply called a wiring-direct-connection structure.

[0196] As a specific example of the above-mentioned substantially same position, for example, a position at which the above-mentioned two wirings electrically connected when the solid-state imaging device 1 is viewed from the upper side to the lower side at least partially overlap can be used. In a case where, for example, copper (Cu) is used as a material of the two wirings to be connected, there is a case where the connection structure is called a Cu-Cu direct joint structure or simply called a Cu-Cu joint structure.

[0197] In the case of using the upper-and-lower-wiring direct connection structure, the connection structure can be provided outside the pixel array unit 24. Alternatively, the connection structure can be provided inside the pixel peripheral circuit region 313 of the upper structure 11 and inside the pixel peripheral circuit region 313 of the lower structure 12. More specifically, among wirings constituting the upper-and-lower-wiring direct connection structure, the wiring provided on the upper structure 11 side of the bonding surface can be provided below the circuit located at the pixel peripheral circuit region 313 of the upper structure 11. Further, among the wirings constituting the upper-and-lower-wiring direct connection structure, the wiring provided on the lower structure 12 side of the bonding surface can be provided above the circuit located at the pixel peripheral circuit region 313 of the lower structure 12. Alternatively, by using the wiring provided at the pixel array unit 24 (pixel transistor region 301) as the wiring of the upper structure 11, the upper-and-lower-wiring direct connection structure formed by the wiring of the upper structure 11 and the wiring of the lower structure 12 can be provided below the pixel array unit 24 (pixel transistor region 301).

[0198] <Second Circuit Arrangement Configuration Example>

[0199] Figure 7 is a diagram illustrating a second circuit arrangement configuration example of the solid-state imaging device 1.

[0200] In the second circuit arrangement configuration example, the above-described upper-and-lower-wiring direct connection structure is used as the upper-and-lower-wiring connection structure.

[0201] As shown in Figure 7 , the arrangement of the pixel array unit 24 in the second circuit arrangement configuration example is similar to that in the first circuit arrangement configuration example shown in Figure 5 . That is, the pixel array unit 24 is provided in the upper structure 11.

[0202] Further, as shown in Figure 7 , the arrangement of the row drive unit 22 and the column signal processing unit 25 of the solid-state imaging device 1 in the second circuit arrangement configuration example is similar to that in the first circuit arrangement configuration example shown in Figure 5

[0203] Meanwhile, the arrangement of the upper-and-lower-wiring connection unit in the second circuit arrangement configuration example is different from that in the first circuit arrangement configuration example shown in Figure 5

[0204] The connection between the wiring of the row drive unit 22 provided in the upper structure 11 and the wiring of the row drive unit 22 provided in the lower structure 12 is formed in a region in which the row drive unit 22 provided in the upper structure 11 overlaps the row drive unit 22 provided in the lower structure 12 by using the upper-and-lower-wiring direct connection structure. ​​

[0205] The connection between the wiring of the column signal processing unit 25 provided in the upper structure 11 and the wiring of the column signal processing unit 25 provided in the lower structure 12 is formed in a region in which the column signal processing unit 25 provided in the upper structure 11 overlaps the column signal processing unit 25 provided in the lower structure 12 by using the up-down wiring direct connection structure.

[0206] In Figure 5 In the first circuit arrangement configuration example illustrated in FIG. 1, the up-down wiring connection structure connecting the wiring of the row drive unit 22 and the up-down wiring connection structure connecting the wiring of the column signal processing unit 25 are provided at the wiring connection unit 29 located outside the row drive unit 22 and outside the column signal processing unit 25, respectively. Meanwhile, in the second circuit arrangement configuration example illustrated in FIG. 2, the up-down wiring connection structure connecting the wiring of the row drive unit 22 and the up-down wiring connection structure connecting the wiring of the column signal processing unit 25 are formed inside the region of the row drive unit 22 and inside the region of the column signal processing unit 25, respectively. Therefore, with the solid-state imaging device 1 illustrated in the second circuit arrangement configuration example in which the wiring connection unit 29 is omitted in the upper structure 11 and the lower structure 12, a device having an outer dimension smaller than that of the solid-state imaging device 1 illustrated in the first circuit arrangement configuration example can be realized. Figure 7

[0207] <8. Examples of comparison with other solid-state imaging devices>

[0208] <Comparison Example 1>

[0209] While comparing the structure of the solid-state imaging device 1 with the structures of other solid-state imaging devices, the features of the structure of the solid-state imaging device 1 are described.

[0210] Figure 9 is a diagram illustrating a cross section of a solid-state imaging device in a final shape disclosed in JP 2014-72294 A (hereinafter, referred to as a comparative structure disclosure 1) as a comparison example 1.

[0211] In Figure 9 The structure of the solid-state imaging device 600 of

[0212] ​In the solid-state imaging device 600, a structure connecting the first wiring 661 and the second wiring 663 via a conductive member 662 is formed outside the transistors Tr3 and Tr4 constituting the control unit, and outside the area where transistors Tr5 to Tr8 constituting the signal processing unit are disposed, and an external terminal 664 is disposed outside this connection structure. Note that the location of the input / output circuit is not described.

[0213] On the other hand, in this invention, the following structure enables the external dimensions to be smaller than [the specified dimensions]. Figure 9 The solid-state camera device 600 has the following external dimensions, in which 1) an external terminal 14, 2) a semiconductor region having an input circuit unit 42 or an output circuit unit 47 connected to the external terminal 14, 3) a semiconductor region having a photodiode 51 and a pixel transistor for performing imaging, 4) a color filter 15 and an on-chip lens 16, and 5) a protective substrate 18 are stacked in substantially the same region.

[0214] Figure 9 The solid-state imaging device 600 in the final shape does not include the protective substrate above the on-chip lens 652 for protecting the on-chip lens 652. This is for manufacturing purposes. Figure 9 The method for manufacturing a solid-state imaging device 600, as disclosed in comparative structural document 1, involves joining a first portion 623 and a second portion 643 to form a color filter 651 and an on-chip lens 652, and, after flipping the substrate, forming an opening for exposing electrode portions and an external terminal 664. When forming the external terminal 664, a stress equal to or greater than a specific value needs to be applied to bond the external terminal 664 to the metal wiring using pressure. In a solid-state imaging device 600 that does not include a protective substrate located on the on-chip lens 652, if the external terminal 664 is formed using the above manufacturing method, there is a possibility that the on-chip lens 652 may be damaged by being squeezed into the manufacturing apparatus when the external terminal 664 is bonded using pressure.

[0215] In addition, Figure 9 In the solid-state imaging device 600, the external terminal 664 is formed in the region outside the pixel array unit and is not formed directly below the on-chip lens 652. In this case, when the external terminal 664 is engaged by pressure, the force applied to the on-chip lens 652 is the force applied by engaging the external terminal 664 by pressure with an obliquely distributed force.

[0216] If the external terminal 664 is formed directly under the pixel region, i.e., directly under the on-chip lens 652 to realize a solid-state imaging device having a small form size, since the on-chip lens 652 is an extension in the direction of force applied to bond the external terminal 664 by pressure, the force applied to the on-chip lens 652 is greater, and there is a possibility that damage to the on-chip lens 652 becomes more serious.

[0217] Further, in the manufacturing method disclosed in Comparative Structure Disclosure Document 1, the color filter 651 and the on-chip lens 652 are formed after the external terminal 664 is formed.

[0218] However, in the case of this manufacturing method, in a state where the plurality of protrusions of the external terminal 664 are disposed on the surface of the solid-state imaging device, when the color filter 651 and the on-chip lens 652 are formed, there is a possibility that it is difficult to fix the solid-state imaging device in the manufacturing device using a general method (e.g., a vacuum suction method).

[0219] Meanwhile, Figure 1 The solid-state imaging device 1 in Comparative Structure Disclosure Document 2 includes a protective substrate 18 on the on-chip lens 16. Therefore, it is possible to form the external terminal 14 without pressing the on-chip lens 16 into the manufacturing device of the external terminal 14. The solid-state imaging device 1 can realize a smaller form size than Figure 9 The form size of the solid-state imaging device in Comparative Structure Disclosure Document 2, in which 1) the external terminal 14, 2) the semiconductor region in which the input circuit unit 42 or the output circuit unit 47 connected to the external terminal 14 is formed, 3) the semiconductor region in which the photodiode 51 and the pixel transistor that perform imaging are formed, 4) the color filter 15 and the on-chip lens 16, and 5) the protective substrate 18 are laminated in substantially the same region.

[0220] <Comparative Example 2>

[0221] Figure 10 is a sectional view illustrating a solid-state imaging device of a final shape disclosed in JP 2010-50149 A (Comparative Structure Disclosure Document 2) as Comparative Example 2.

[0222] Figure 10 The solid-state imaging device 700 in Comparative Structure Disclosure Document 2 is divided into an imaging region 722 and a peripheral region 723 formed around the imaging region 722, and a photodiode (not illustrated), a color filter 711, an on-chip lens 712, and the like are formed in the imaging region 722.

[0223] A first pad 724 for inputting / outputting a driving pulse or a signal is provided in the peripheral region 723. A bonding wire 725 is connected to the first pad 724. A second pad 726 for supplying a reference potential Vss is provided in the imaging region 722. An external terminal (solder ball) 727 is provided on the second pad 726.

[0224] As described above, the solid-state imaging device 700 includes the external terminal 727 on the lower side of the pixel array.

[0225] In the solid-state imaging device 1, it is possible to make the outer shape smaller than Figure 10 The outer shape of the solid-state imaging device 700 in which 1) the external terminal 14, 2) the semiconductor region in which the input circuit unit 42 or the output circuit unit 47 connected to the external terminal 14 is formed, 3) the semiconductor region in which the photodiode 51 and the pixel transistor that perform imaging are formed, 4) the color filter 15 and the on-chip lens 16, and 5) the protection substrate 18 are stacked in substantially the same region.

[0226] Figure 10 The solid-state imaging device 700 in which the upper structure 11 and the lower structure 12 such as the solid-state imaging device 1 are not included. In other words, the solid-state imaging device 700 includes only one layer of the semiconductor substrate in which the transistor circuit is formed.

[0227] In the solid-state imaging device 700 in which Figure 10 In the solid-state imaging device 700 in which

[0228] However, Figure 10 The external terminal 727 formed in the solid-state imaging device 700 is a terminal of the reference potential Vss (ground potential). The terminal of the reference potential Vss does not need to include an input circuit of the transistor circuit to supply the reference potential Vss to the inside of the solid-state imaging device. Therefore, in the solid-state imaging device 700 in which Figure 10 In the solid-state imaging device 700 in which

[0229] Meanwhile, the pixels including the photodiodes and the pixel transistors are arranged in the imaging region 722. Therefore, in the case where a structure in which only one layer of the semiconductor substrate 741 (in which the transistor circuit is formed) is formed is provided, it is difficult to form the input circuit in the pixel region in which the pixels are formed on the semiconductor substrate 741. Therefore, in the solid-state imaging device 700 in which Figure 10In the disclosed solid-state imaging device 700 including only one layer of the semiconductor substrate 741, although it is not required that the power terminal of the input / output circuit can be provided on the lower side of the pixel region, it is not possible to provide the external terminal (in other words, the external terminal for signal input or signal output) of the input circuit or the output circuit.

[0230] Further, as in the case of the solid-state imaging device 600 shown in Figure 9 Figure 10 the solid-state imaging device 700 in the

[0231] Meanwhile, the solid-state imaging device 1 includes a stacked structure of a plurality of semiconductor substrates in which a transistor circuit is formed. In this way, it is possible to provide the external terminal 14 (in other words, the signal input / output terminal 14C for signal input or for signal output) of the input circuit or the output circuit on the lower side of the pixel region. Further, the solid-state imaging device 1 includes a protective substrate 18 located on the on-chip lens 16. Therefore, it is possible to form the external terminal without pressing the on-chip lens 16 to the manufacturing device of the external terminal 14. In this way, the solid-state imaging device 1 can make the outer shape smaller than Figure 10 the outer shape of the solid-state imaging device 700 in the structure in which 1) the external terminal 14, 2) the semiconductor region in which the input circuit unit 42 or the output circuit unit 47 connected to the external terminal 14 is formed, 3) the semiconductor region in which the photodiode 51 and the pixel transistor performing imaging are formed, 4) the color filter 15 and the on-chip lens 16, and 5) the protective substrate 18 are stacked in substantially the same region.

[0232] <Comparative Example 3>

[0233] Figure 11 is a sectional view illustrating the final shape of the solid-state imaging device disclosed in JP 2011-9645 A (Comparative Structure Disclosure 3) as Comparative Example 3.

[0234] In the Figure 11 solid-state imaging device 800, the imaging element 812 including a photodiode and a transistor is formed on the first main surface (upper surface) of the semiconductor substrate 811. The multilayer wiring layer 813, the color filter 814, the cover layer 815, and the on-chip lens 816 are formed on the upper side of the imaging element 812. Further, the solid-state imaging device 800 includes a protective substrate 817 located on the upper side of the on-chip lens 816.

[0235] ​The peripheral circuit unit 823 is disposed outside the camera pixel unit 822. The camera element 812, color filter 814 and on-chip lens 816 are formed in the camera pixel unit 822. The through-silicon via 831 penetrating the semiconductor substrate 811 and the external terminal (solder ball) 832 connected to the outside are formed in the peripheral circuit unit 823.

[0236] Figure 11 The solid-state camera device 800 is a solid-state semiconductor device that does not include a stacked structure with an upper structure and a lower structure. In other words, as with the solid-state camera device 700 in Comparative Example 2, the solid-state camera device 800 only includes a single semiconductor substrate on which transistor circuitry is formed. Therefore, it is required that the external terminals of the input circuit or output circuit (in other words, external terminals for signal input or signal output) cannot be located on the lower side of the pixel area.

[0237] Meanwhile, the solid-state imaging device 1 includes a stacked structure of multiple semiconductor substrates on which transistor circuits are formed. In this way, external terminals 14 requiring input or output circuitry (in other words, signal input / output terminals 14C for signal input or signal output) can be located on the lower side of the pixel area. In this way, the solid-state imaging device 1 can achieve a smaller overall size by adopting the following structure. Figure 11 The external dimensions of the solid-state camera device 800 are such that, in this structure, 1) an external terminal 14, 2) a semiconductor region having an input circuit unit 42 or an output circuit unit 47 connected to the external terminal 14, 3) a semiconductor region having a photodiode 51 and a pixel transistor for performing imaging, 4) a color filter 15 and an on-chip lens 16, and 5) a protective substrate 18 are stacked in substantially the same region.

[0238] In addition, as with Figure 11 In the case of the solid-state camera device 800, where the through-silicon vias 831 are formed only in the outer peripheral portion (peripheral circuit unit 823) of the device, the power supply terminals or ground terminals are also similarly provided only in the outer peripheral portion of the device. In this case, it is necessary to provide multiple power supply terminals and ground terminals to address voltage drop (IR drop) and interconnection delay. Meanwhile, in the solid-state camera device 1, since through-holes 88 can be provided in any region of the lower structure 12 inside the upper and lower substrate connection region 314, a portion of these through-holes can be used as power supply terminals or ground terminals. That is, power supply terminals or ground terminals can also be provided in any region. In this way, the number of power supply terminals and ground terminals can be less than the number of power supply terminals and ground terminals when through-silicon vias are provided only in the outer peripheral portion. In this way, the overall circuit area of ​​the solid-state camera device 1 can be reduced.

[0239] < Figure 1Differences between the solid-state imaging device in the embodiment and comparative examples

[0240] In the solid-state imaging device 1, the outline size can be made small by using a structure in which 1) the external terminal 14, 2) the semiconductor region in which the input circuit unit 42 or the output circuit unit 47 connected to the external terminal 14 is formed, 3) the semiconductor region in which the photodiode 51 and the pixel transistor that perform imaging are formed, 4) the color filter 15 and the on-chip lens 16, and 5) the protection substrate 18 are stacked in substantially the same region.

[0241] In the case of the solid-state imaging devices described in Comparative Example 1 and Comparative Example 2 that have a semiconductor stacked structure that does not include a protection substrate, there is a possibility that the on-chip lens is damaged. That is, there is a blocking factor in obtaining a solid-state imaging device having an outline size equal to that of the present application that adopts a structure in which the above 1) to 4) are stacked in substantially the same region. That is, the solid-state imaging devices described in Comparative Example 1 and Comparative Example 2 that have a semiconductor stacked structure that does not include a protection substrate cannot obtain the function and operation of "a small solid-state imaging device achieved by stacking the above 1) to 4) in substantially the same region".

[0242] In the case of the solid-state imaging device described in Comparative Example 3 that includes only one layer of a semiconductor substrate in which a transistor circuit is formed, it is not possible to achieve a solid-state imaging device having an outline size equal to that of the present application that adopts a structure in which the above 1) to 5) are stacked in substantially the same region. In other words, there is a blocking factor. That is, the solid-state imaging device described in Comparative Example 3 that includes only one layer of a semiconductor substrate in which a transistor circuit is formed cannot obtain the function and operation of "a small solid-state imaging device achieved by stacking the above 1) to 5) in substantially the same region".

[0243] In this way, the function and operation of "a solid-state imaging device having a smaller outline size than that of a solid-state imaging device that does not include a structure in which the above 1) to 5) are stacked in substantially the same region" achieved by adopting a structure in which the above 1) to 5) are stacked in substantially the same region cannot be obtained from the configuration of "a solid-state imaging device having a semiconductor stacked structure that does not include a protection substrate" described in Comparative Example 1 and Comparative Example 2 alone, nor from the configuration of "a solid-state imaging device including only one layer of a semiconductor substrate in which a transistor circuit is formed" described in Comparative Example 3 alone.

[0244] <9. Other circuit arrangement configuration examples of the solid-state imaging device>

[0245] <Third circuit arrangement configuration example>

[0246] Figure 12This is a diagram illustrating another circuit arrangement example (i.e., a third circuit arrangement example) of the solid-state camera device 1, which is a variation of the first circuit arrangement example.

[0247] exist Figure 5 In the first circuit layout example shown, an input / output circuit unit 49 is provided for each external terminal 14. The image signal processing unit 26 surrounds each of the input / output circuit units 49.

[0248] At the same time, Figure 12 In the third circuit arrangement example shown, input / output circuit units 49 are shared for each group of external terminals 14. Within a region of the input / output circuit units 49, for example, the input / output circuit units 49 of one external terminal 14 and the input / output circuit units 49 of another external terminal 14 are arranged to be in contact with each other, and no image signal processing unit 26 is arranged between these input / output circuit units 49. Since the portion of the separation well regions with different power supply voltages is less in the third arrangement example (where multiple input / output circuit units 49 with the same power supply voltage are shared as one input / output circuit unit region) compared to the first circuit arrangement example (where input / output circuit units 49 with different power supply voltages and image signal processing units 26 are alternately arranged to be adjacent to each other), even if the external dimensions of the solid-state imaging device 1 are the same, there is still the possibility of mounting more circuitry on the image signal processing unit 26 in the lower structure 12.

[0249] In addition, Figure 12 In the third circuit arrangement example shown, a portion of the input / output circuit unit 49 may be located below the pixel peripheral circuit unit included in the upper structure 11, rather than below the pixel array unit 24 included in the upper structure 11. For example, a portion of the input / output circuit unit 49 may be located below the row driving unit 22 included in the upper structure 11 or outside the area where the image signal processing unit 26 included in the lower structure 12 is located. In this way, even if the external dimensions of the solid-state imaging device 1 are the same, there is still the possibility of mounting more circuitry on the image signal processing unit 26 in the lower structure 12.

[0250] <Example of Fourth Circuit Arrangement>

[0251] Figure 13 This is a diagram illustrating another circuit arrangement configuration (i.e., a fourth circuit arrangement configuration example) of the solid-state camera device 1, which is a variation of the first and third circuit arrangement configuration examples.

[0252] Figure 14 is a diagram illustrating a cross-sectional structure along the line C-C' of the solid-state imaging device 1 according to Figure 13 Note that, for convenience, a part of Figure 14 is replaced with a cross-sectional structure in another configuration example of the present application described later.

[0253] In the fourth circuit arrangement configuration example shown in Figure 13 and 14 , the input / output circuit unit 49 (in other words, both the input circuit unit 42 and the output circuit unit 47) is provided at an outer peripheral portion of a region in which the image signal processing unit 26 included in the lower structure 12 is provided. The region in which the input / output circuit unit 49 is provided can be located at a lower side of the row drive unit 22 and the column signal processing unit 25 (pixel peripheral circuit region 313) included in the upper structure 11, or can be located at a lower side of an outer peripheral portion of the pixel array unit 24 included in the upper structure 11.

[0254] Note that, for example, the region in which the input / output circuit unit 49 is provided is not necessarily provided seamlessly in the entire row direction of the column signal processing unit 25, and there can be a region in which the input / output circuit unit 49 is not provided between the column signal processing unit 25 and the image signal processing unit 26.

[0255] Further, the region in which the input / output circuit unit 49 is provided is not necessarily provided seamlessly in the entire column direction of the row drive unit 22, and there can be a region in which the input / output circuit unit 49 is not provided between the row drive unit 22 and the image signal processing unit 26.

[0256] Since the portion in which the unit is provided between the separate well regions having different power supply voltages is less in the fourth circuit arrangement configuration example than in the third circuit arrangement configuration example, there is a possibility that, for example, more circuits can be mounted on the image signal processing unit 26 in the lower structure 12 even if the outer shape size of the solid-state imaging device 1 is the same.

[0257] <5th Circuit Arrangement Configuration Example>

[0258] Figure 15 is a diagram illustrating another circuit arrangement configuration example (i.e., a fifth circuit arrangement configuration example) of the solid-state imaging device 1, which is a variation of the first, third, and fourth circuit arrangement configuration examples.

[0259] In the fifth circuit arrangement configuration example shown in Figure 13In the fourth circuit layout example shown, there are areas where no input / output circuit unit 49 is provided between the column signal processing unit 25 and the image signal processing unit 26 or between the row driving unit 22 and the image signal processing unit 26.

[0260] At the same time, Figure 15 In the fifth circuit layout example shown, the input / output circuit unit 49 is arranged along a line in the entire row direction of the column signal processing unit 25 or in the entire column direction of the row driving unit 22. In this way, it is possible to make the area of ​​the input / output circuit unit 49 larger.

[0261] Furthermore, in the fifth circuit layout example, even if the external dimensions are the same as those of the solid-state camera device 1 in the first and third circuit layout examples, there is still a possibility that more circuitry can be installed on the image signal processing unit 26 in the lower structure 12.

[0262] <Sixth Circuit Arrangement Construction Example>

[0263] Figure 16 This is a diagram illustrating another circuit arrangement example of the solid-state camera device 1 (i.e., the sixth circuit arrangement example), which is a variation of the first and third circuit arrangement examples.

[0264] In the first and third circuit arrangement examples, the input / output circuit unit 49 is disposed in the area of ​​the lower structure 12 below the pixel array unit 24 of the upper structure 11, and the image signal processing unit 26 is disposed around the input / output circuit unit 49.

[0265] exist Figure 16 In the sixth circuit layout example, the image signal processing unit 26 of the lower structure 12 is configured to employ multiple (divided by dashed lines) Figure 16 The circuit is constructed with 3 blocks. In the sixth circuit layout example, the input / output circuit unit 49 is located at the following location, which becomes the block boundary of the circuit block located at the image signal processing unit 26, or the boundary with the line driving unit 22.

[0266] In a case where the image signal processing unit 26 is provided while being divided into a plurality of circuit blocks, there is a case where a power supply line and a ground line of the circuit of each circuit block are provided at a block boundary portion. Therefore, there is a case where a distance between the circuits at the block boundary portion becomes larger than a distance between the circuits inside the circuit block. In this way, by providing the input / output circuit unit 49 at the boundary portion of the circuit block where the circuit density is relatively low, there is a possibility that the input / output circuit unit 49 can be provided in an easier layout design of the circuit and substantially without reducing the integration degree of the circuit, as compared with a case where the input / output circuit unit 49 is provided inside the circuit block. In this way, even if the outer size of the solid-state imaging device 1 is the same, by using the sixth circuit arrangement configuration example, there is a possibility that, for example, more circuits can be mounted on the image signal processing unit 26 in the lower structure 12.

[0267] <Seventh Circuit Arrangement Configuration Example>

[0268] Figure 17 is a diagram illustrating another circuit arrangement configuration example (i.e., a seventh circuit arrangement configuration example) of the solid-state imaging device 1, which is a variation of the fifth circuit arrangement configuration example.

[0269] In the seventh circuit arrangement configuration example of Figure 17 , the row drive unit 22 provided in the upper structure 11 is formed to have a larger area than that of the row drive unit 22 provided in the lower structure 12. Further, the row drive unit 22 provided in the lower structure 12 is provided to extend longer in the inward direction of the device, as compared with the row drive unit 22 provided in the upper structure 11.

[0270] In a similar manner, the column signal processing unit 25 provided in the lower structure 12 is formed to have a larger area than that of the column signal processing unit 25 provided in the upper structure 11. Further, the column signal processing unit 25 provided in the lower structure 12 is provided to extend longer in the inward direction of the device, as compared with the column signal processing unit 25 provided in the upper structure 11.

[0271] In this way, in the seventh circuit arrangement configuration example, even if the size of the pixel array unit 24 of the solid-state imaging device 1 is the same, there is a possibility that the outer size of the solid-state imaging device 1 can be made smaller than the outer size of the fifth circuit arrangement configuration example shown in Figure 15 .

[0272] Note that the arrangement example of the row drive unit 22 and the column signal processing unit 25 described in the seventh circuit arrangement configuration example can be applied to other configuration examples of the present application.

[0273] <Example of the eighth circuit arrangement configuration>

[0274] Figure 18 is a diagram illustrating another circuit arrangement configuration example (i.e., the eighth circuit arrangement configuration example) of the solid-state imaging device 1, which is a modification of the seventh circuit arrangement configuration example.

[0275] In the seventh circuit arrangement configuration example illustrated in Figure 17 , although the area of the row drive unit 22 provided in the upper structure 11 is smaller than the area of the row drive unit 22 provided in the lower structure 12, the row drive unit 22 is also provided in the upper structure 11. In a similar manner, although the area of the column signal processing unit 25 provided in the upper structure 11 is smaller than the area of the column signal processing unit 25 provided in the lower structure 12, the column signal processing unit 25 is also provided in the upper structure 11.

[0276] Meanwhile, in the eighth circuit arrangement configuration example in Figure 18 , the row drive unit 22 and the column signal processing unit 25 are provided only in the lower structure 12. The signal output from the row drive unit 22 to the pixel array unit 24 is transmitted from the row drive unit 22 provided in the lower structure 12 to the pixel array unit 24 provided in the upper structure 11 via the wiring connection unit 29 having an up-and-down wiring connection structure in the pixel peripheral circuit region 313 illustrated in Figure 8 . In the same manner, the signal input from the pixel array unit 24 to the column signal processing unit 25 is transmitted from the pixel array unit 24 provided in the upper structure 11 to the column signal processing unit 25 provided in the lower structure 12 via the wiring connection unit 29 having an up-and-down wiring connection structure in the pixel peripheral circuit region 313 illustrated in Figure 8 . In this way, compared with the seventh circuit arrangement configuration example illustrated in Figure 17 , even if the size of the pixel array unit 24 of the solid-state imaging device 1 is the same, there is a possibility that the outer shape size of the solid-state imaging device 1 can be made smaller in the eighth circuit arrangement configuration example.

[0277] Note that the arrangement example of the row drive unit 22 and the column signal processing unit 25 described in the eighth circuit arrangement configuration example can be applied to other configuration examples of the present application.

[0278] <Example of the ninth circuit arrangement configuration>

[0279] Figure 19 is a diagram illustrating another circuit arrangement configuration example (i.e., the ninth circuit arrangement configuration example) of the solid-state imaging device 1, which is a modification of the fifth circuit arrangement configuration example.

[0280] In Figure 19 the ninth circuit arrangement configuration example illustrated, the row drive unit 22 and the column signal processing unit 25 are both provided in the upper structure 11. In the lower structure 12, in a region located on the lower side of the row drive unit 22 and the column signal processing unit 25 provided in the upper structure 11, the image signal processing unit 26 is provided, and the input / output circuit unit 49 is provided. Figure 15 In the tenth circuit arrangement configuration example illustrated, the image signal processing unit 26 is provided to extend longer in the peripheral direction compared to the second circuit arrangement configuration example illustrated in Figure 15 In the tenth circuit arrangement configuration example illustrated, the image signal processing unit 26 is provided to extend longer in the peripheral direction compared to the second circuit arrangement configuration example illustrated in

[0281] Note that the arrangement example of the row drive unit 22 and the column signal processing unit 25 described in the ninth circuit arrangement configuration example can be applied to other configuration examples of the present application.

[0282] <The tenth circuit arrangement configuration example>

[0283] Figure 20 is a diagram illustrating another circuit arrangement configuration example (i.e., the tenth circuit arrangement configuration example) of the solid-state imaging device 1, which is a variation of the second circuit arrangement configuration example.

[0284] Figure 21 is a diagram illustrating the cross-sectional structure along the line D-D' of the solid-state imaging device 1 according to Figure 20 Note that, for convenience, Figure 21 part of the cross-sectional structure of

[0285] In Figure 20 and Figure 21 the tenth circuit arrangement configuration example illustrated, as in the case of the second circuit arrangement configuration example illustrated in Figure 7 and Figure 8 the tenth circuit arrangement configuration example illustrated, as in the case of the second circuit arrangement configuration example illustrated in

[0286] In addition, in Figure 20 and Figure 21In the tenth circuit arrangement example shown, the input / output circuit unit 49 (in other words, all of the input circuit unit 42 and output circuit unit 47) is located outside the area of ​​the lower structure 12 where the image signal processing unit 26 is located. The area where the input / output circuit unit 49 is located may be located below the row driving unit 22 and column signal processing unit 25 included in the upper structure 11, or it may be located below the pixel array unit 24 included in the upper structure 11.

[0287] Note that the area where the input / output circuit unit 49 is located does not necessarily have to be seamlessly located along the entire row direction of the column signal processing unit 25, and there may be areas between the column signal processing unit 25 and the image signal processing unit 26 where the input / output circuit unit 49 is not located.

[0288] Furthermore, the area where the input / output circuit unit 49 is located does not necessarily need to be seamlessly arranged along the entire column direction of the row driving unit 22, and there may be areas between the row driving unit 22 and the image signal processing unit 26 where the input / output circuit unit 49 is not located. In the tenth circuit layout example, even if the external dimensions are similar to... Figure 7 The solid-state camera device 1 in the second circuit arrangement example shown is the same size as the one in the lower structure 12, and there is a possibility that more circuits can be installed on the image signal processing unit 26 in the lower structure 12.

[0289] Note that the circuit layout example described in the tenth circuit layout construction example can also be applied to other construction examples of the present invention.

[0290] <Eleventh Circuit Layout Construction Example>

[0291] Figure 22 This is a diagram of another circuit arrangement example of the solid-state camera device 1 (i.e., the eleventh circuit arrangement example), which is a variation of the tenth circuit arrangement example.

[0292] exist Figure 20 In the tenth circuit arrangement example shown, a portion of the row driving unit 22 and a portion of the column signal processing unit 25 are disposed in both the upper structure 11 and the lower structure 12. In the lower structure 12, the input / output circuit unit 49 is disposed in a region below the row driving unit 22 disposed in the upper structure 11 and in a region located inside the device relative to the row driving unit 22 disposed in the lower structure 12. Similarly, in the lower structure 12, the input / output circuit unit 49 is disposed in a region below the column signal processing unit 25 disposed in the upper structure 11 and in a region located inside the device relative to the column signal processing unit 25 disposed in the lower structure 12.

[0293] In Figure 22 In the eleventh circuit arrangement configuration example shown in FIG. 11, a part of the row drive unit 22 and a part of the column signal processing unit 25 are provided in both the upper structure 11 and the lower structure 12. In the lower structure 12, the input / output circuit unit 49 is provided in a region located on the lower side of the row drive unit 22 provided in the upper structure 11 and in a region located on the outer side of the device with respect to the row drive unit 22 provided in the lower structure 12. In a similar manner, in the lower structure 12, the input / output circuit unit 49 is provided in a region located on the lower side of the column signal processing unit 25 provided in the upper structure 11 and in a region located on the outer side of the device with respect to the column signal processing unit 25 provided in the lower structure 12.

[0294] In this way, compared with the tenth circuit arrangement configuration example shown in FIG. 10, in the lower structure 12, for example, there is a possibility that signal lines between the image signal processing unit 26 and the row drive unit 22 and signal lines between the image signal processing unit 26 and the column signal processing unit 25 provided in the lower structure 12 can be easily provided or these signals can be densely provided. Figure 20

[0295] Note that the circuit arrangement example described in the eleventh circuit arrangement configuration example can also be applied to the other configuration examples of the present application.

[0296] <10. Detailed structure of solid-state imaging device>

[0297] Next, the detailed structure of the solid-state imaging device 1 will be described with reference to FIG. 12. Figure 23 is an enlarged cross-sectional view illustrating a part of the outer periphery of the solid-state imaging device 1 including a double contact structure. Figure 23

[0298] In the lower structure 12, a multilayer wiring layer 82 is formed on the upper side (the upper structure 11 side) of a semiconductor substrate 81 formed of, for example, silicon (Si). The input / output circuit region 311, the signal processing circuit region 312 (not shown in FIG. 12), the pixel peripheral circuit region 313, and the like are formed using the multilayer wiring layer 82. Figure 6 Figure 23

[0299] The multilayer wiring layer 82 includes a plurality of wiring layers 83 and an interlayer insulating film 84 formed between the wiring layers 83, and the plurality of wiring layers 83 are formed of a wiring layer 83a (the uppermost layer closest to the upper structure 11), an intermediate wiring layer 83b, a wiring layer 83c (the lowermost layer closest to the semiconductor substrate 81), and the like.

[0300] ​​​​The plurality of wiring layers 83 are formed using, for example, copper (Cu), aluminum (Al), tungsten (W), or the like, and the interlayer insulating layer 84 is formed of, for example, a silicon oxide film, a silicon nitride film, or the like. The plurality of wiring layers 83 and the interlayer insulating layer 84 can all be formed of the same material, or can be formed of two or more materials according to the layer.

[0301] A through-silicon via 85 that penetrates the semiconductor substrate 81 is formed at a predetermined position on the semiconductor substrate 81, and a via (through-silicon via, TSV) 88 is formed on the inner wall of the through-silicon via 85 by a connection conductor 87 that is embedded through an insulating film 86. The insulating film 86 can be formed of, for example, a SiO2 film, a SiN film, or the like. Although in the present embodiment the via 88 is formed in an inverted tapered shape in which the planar area on the wiring layer 83 side is smaller than the planar area on the external terminal 14 side, the via 88 can conversely be formed in a positive tapered shape having a smaller area on the external terminal 14 side, or can be formed in a non-tapered shape in which the area on the external terminal 14 side is substantially equal to the area on the wiring layer 83 side.

[0302] The connection conductor 87 of the via 88 is connected to a rewiring 90 formed on the lower side of the semiconductor substrate 81, and the rewiring 90 is connected to the external terminal 14. The connection conductor 87 and the rewiring 90 can be formed of, for example, copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium tungsten alloy (TiW), polysilicon, or the like.

[0303] Furthermore, a solder resist layer (solder resist) 91 is formed on the lower side of the semiconductor substrate 81, but is not formed in the region in which the external terminal 14 is formed, so as to cover the rewiring 90 and the insulating film 86.

[0304] Meanwhile, a multilayer wiring layer 102 is formed at the lower side of a semiconductor substrate 101 formed of, for example, silicon (Si) (the lower structure 12 side) in the upper structure 11. Figure 3 The circuit of the pixel 31 shown is formed by this multilayer wiring layer 102.

[0305] The multilayer wiring layer 102 includes a plurality of wiring layers 103 formed of a wiring layer 103a located at the uppermost layer closest to the semiconductor substrate 101, an intermediate wiring layer 103b, and a wiring layer 103c located at the lowermost layer closest to the lower structure 12, and an interlayer insulating film 104 formed between the wiring layers 103.

[0306] As the material for the plurality of wiring layers 103 and the interlayer insulating film 104, the same materials as the material types of the above-described wiring layer 83 and the interlayer insulating film 84 can be used. Furthermore, the plurality of wiring layers 103 and the interlayer insulating film 104 are the same as the above-described wiring layer 83 and the interlayer insulating film 84 in that they can be formed of one material or a plurality of different materials.

[0307] Note that, although in Figure 23 In the example, the multi-layer wiring layer 102 of the upper structure 11 includes five wiring layers 103, and the multi-layer wiring layer 82 of the lower structure 12 includes four wiring layers 83, but the total number of wiring layers is not limited to this, and the multi-layer wiring layer can be formed by any number of layers.

[0308] For each pixel 31, a photodiode 51 formed by a PN junction is formed within the semiconductor substrate 101.

[0309] In addition, although detailed descriptions are omitted, multiple pixel transistors such as transmission transistor 52 and amplification transistor 55, FD 53, etc. are also formed in the multilayer wiring layer 102 and the semiconductor substrate 101.

[0310] Silicon vias 109 connected to the predetermined wiring layer 103 of the upper structure 11 and chip vias 105 connected to the predetermined wiring layer 83 of the lower structure 12 are formed at predetermined positions on the semiconductor substrate 101 where color filters 15 and on-chip lenses 16 are not formed.

[0311] Through-chip via 105 and through-silicon via 109 are connected to interconnect wiring 106 formed on the upper surface of semiconductor substrate 101. In addition, an insulating film 107 is formed between each of the through-chip via 105 and through-silicon via 109 and semiconductor substrate 101.

[0312] A planarization film 108 is formed between the photodiode 51 and the color filter 15 on the semiconductor substrate 101, and a planarization film 110 is also formed between the on-chip lens 16 and the glass sealing resin 17.

[0313] As mentioned above, in Figure 1 In the stacked structure of the solid-state camera device 1 shown, the multilayer wiring layer 82 side of the lower structure 12 and the multilayer wiring layer 102 side of the upper structure 11 are bonded together. Figure 23 The surface where the multilayer wiring layer 82 of the lower structure 12 and the multilayer wiring layer 102 of the upper structure 11 are bonded together is illustrated by a dashed line.

[0314] Furthermore, in the stacked structure 13 of the solid-state imaging device 1, the wiring layer 103 of the upper structure 11 and the multilayer wiring layer 83 of the lower structure 12 are connected by two via electrodes: a through-silicon via 109 and a through-chip via 105. The wiring layer 83 of the lower structure 12 and the external terminal (back electrode) 14 are connected to the via 88 and the rewiring 90. In this way, the pixel signal generated at the pixel 31 of the upper structure 11 is transmitted to the lower structure 12, processed at the lower structure 12, and output to the outside of the device from the external terminal 14.

[0315] <11. Manufacturing Method>

[0316] <Manufacturing method in case of double contact structure>

[0317] A manufacturing method of the solid-state imaging device 1 including the double contact structure will be described below with reference to Figures 24 to 38

[0318] First, the lower structure 12 and the upper structure 11 in wafer state are manufactured separately.

[0319] As the lower structure 12, in the region of each chip portion of a silicon substrate (silicon wafer) 81, an input / output circuit unit 49 and a multilayer wiring layer 82 which becomes a part of the row drive unit 22 or the column signal processing unit 25 are formed. At this time, the semiconductor substrate 81 is in a state before being thinned, and has a thickness of about 600 μm, for example.

[0320] On the other hand, as the upper structure 11, in the region of each chip portion of a silicon substrate (silicon wafer) 101, a photodiode 51 and a source / drain region of a pixel transistor of each pixel 31 are formed. Further, on one face of the semiconductor substrate 101, a multilayer wiring layer 102 which constitutes the row drive signal line 32, the vertical signal line 33, and the like is formed. At this time, the semiconductor substrate 101 is also in a state before being thinned, and has a thickness of about 600 μm, for example.

[0321] Next, as shown in FIG. 6, the multilayer wiring layer 82 side of the manufactured lower structure 12 in wafer state and the multilayer wiring layer 102 side of the manufactured upper structure 11 in wafer state are adhered in a manner facing each other, and then, as shown in FIG. 7, the semiconductor substrate 101 of the upper structure 11 is thinned. Figure 24 Figure 25 Although the adhering can be implemented by, for example, plasma bonding or bonding using an adhesive, in the present embodiment, the adhering is implemented by plasma bonding. In the case of plasma bonding, the multilayer wiring layers are bonded by forming a film such as a plasma TEOS film, a plasma SiN film, a SiON film (barrier film), and a SiC film on each of the bonding surfaces of the upper structure 11 and the lower structure 12, performing plasma processing on the bonding surfaces and overlapping the bonding surfaces, and then performing an annealing process.

[0322] After the semiconductor substrate 101 of the upper structure 11 is thinned, as shown in FIG. 8, a silicon through hole 109 and a chip through hole 105, and a connection wiring 106 connecting these through holes are formed in a region which becomes an up-and-down wiring connection region 314 using a damascene method. Figure 26

[0323] Next, as shown in FIG. 9, the semiconductor substrate 101 of the upper structure 11 is thinned to a thickness of about 50 μm, for example, and then, as shown in FIG. 10, the semiconductor substrate 101 is thinned to a thickness of about 5 μm, for example, using a chemical mechanical polishing (CMP) method. Figure 27 ​​​As shown, a color filter 15 and an on-chip lens 16 are formed above the photodiode 51 of each pixel 31 through a planarization film 108.

[0324] Next, as Figure 28 As shown, glass sealing resin 17 is coated onto the entire surface of the on-plate lens 16, which has a laminated structure 13 (in which an upper structure 11 and a lower structure 12 are bonded), through a planarization film 110, and, as Figure 29 As shown, the glass protective substrate 18 is connected using a solid structure.

[0325] Next, as Figure 30 As shown, after flipping the entire stacked structure 13, the semiconductor substrate 81 of the lower structure 12 is thinned to a degree that does not affect the device characteristics, for example, between approximately 30 and 100 μm.

[0326] Next, as Figure 31 As shown, after the photoresist 221 is patterned to form an opening at the location where the via 88 (not shown) is provided on the thinned semiconductor substrate 81, a portion of the semiconductor substrate 81 and the interlayer insulating layer 84 located below the semiconductor substrate 81 are removed by dry etching, thereby forming the opening 222.

[0327] Next, as Figure 32 As shown, an insulating film (isolation film) 86 is formed on the entire upper surface of a semiconductor substrate 81, including the opening 222, using, for example, a plasma CVD method. As described above, the insulating film 86 may be, for example, a SiO2 film, a SiN film, etc.

[0328] Next, as Figure 33 As shown, the insulating film 86 on the bottom surface of the opening 222 is removed using an etch-back method, exposing the wiring layer 83c closest to the semiconductor substrate 81.

[0329] Next, as Figure 34 As shown, a barrier metal film (not shown) and a Cu seed layer 231 are formed using a sputtering method. The barrier metal film is used to prevent... Figure 35 The diffusion of the connecting conductor 87 (Cu) is shown, and when the connecting conductor 87 is embedded using an electroplating method, the Cu seed layer 231 becomes an electrode. As the material for the barrier metal film, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), their nitride films, carbide films, etc., can be used. In this embodiment, titanium is used as the barrier metal film.

[0330] Next, as Figure 35As shown, after the resist pattern 241 is formed in the required region of the Cu seed layer 231, copper (Cu) serving as the connection conductor 87 is plated using a plating method. In this way, the through-hole 88 is formed, and a re-wiring 90 is also formed on the upper side of the semiconductor substrate 81.

[0331] Next, as shown in FIG. 6B, after the resist pattern 241 is formed in the required region of the Cu seed layer 231, copper (Cu) serving as the connection conductor 87 is plated using a plating method. In this way, the through-hole 88 is formed, and a re-wiring 90 is also formed on the upper side of the semiconductor substrate 81. Figure 36 As shown, after the resist pattern 241 is removed, the barrier metal film (not shown) and the Cu seed layer 231 under the resist pattern 241 are removed by wet etching.

[0332] Next, as shown in FIG. 6B, after the resist pattern 241 is formed in the required region of the Cu seed layer 231, copper (Cu) serving as the connection conductor 87 is plated using a plating method. In this way, the through-hole 88 is formed, and a re-wiring 90 is also formed on the upper side of the semiconductor substrate 81. Figure 37 As shown, after the resist pattern 241 is removed, the barrier metal film (not shown) and the Cu seed layer 231 under the resist pattern 241 are removed by wet etching.

[0333] Next, as shown in FIG. 6B, after the resist pattern 241 is formed in the required region of the Cu seed layer 231, copper (Cu) serving as the connection conductor 87 is plated using a plating method. In this way, the through-hole 88 is formed, and a re-wiring 90 is also formed on the upper side of the semiconductor substrate 81. Figure 38 As shown, after the resist pattern 241 is removed, the barrier metal film (not shown) and the Cu seed layer 231 under the resist pattern 241 are removed by wet etching.

[0334] As described above, according to the manufacturing method of the present application, first, the upper structure (first semiconductor substrate in which a photodiode 51 for performing photoelectric conversion, a pixel transistor circuit, and the like are formed) 11 and the lower structure 12 (second semiconductor substrate in which an input / output circuit unit 49 for outputting a pixel signal output from a pixel 31 to the outside of the solid-state imaging device 1 is formed below the pixel array unit 24) are bonded so that the wiring layers face each other. Next, a through-hole 88 is formed through the lower structure 12, and an external terminal 14 that electrically connects the input / output circuit unit 49 and the outside of the solid-state imaging device 1 is formed. In this way, it is possible to manufacture Figure 5 the solid-state imaging device 1 shown in FIG. 1.

[0335] According to the manufacturing method of the present application, since the through-hole 88 is formed using the glass protection substrate 18 as a support substrate, the through-hole 88 has a shape formed by engraving the through-hole 88 from the external terminal 14 side to the wiring layer 83 (circuit) side.

[0336] [Manufacturing method in case of Cu-Cu direct bonding structure]

[0337] A manufacturing method of the solid-state imaging device 1 in the case where the lower structure 12 and the upper structure 11 are bonded using a Cu-Cu direct bonding structure will be described below with reference to Figures 39 to 43 First, as with the manufacturing method in the case where a dual contact structure is used as the upper and lower wiring connection structure, the lower structure 12 and the upper structure 11 are separately manufactured in wafer state.

[0338]

[0339] ​However, as shown in Figure 39 the manufacturing method differs from the manufacturing method in the case of the two-contact structure in that, in the upper-and-lower wiring connection structure 314 that further becomes the outside of the pixel array unit 24, in the upper structure 11, the wiring layer 103x for direct connection with the wiring layer 83x of the lower structure 12 is formed on the side closer to the lower structure 12, as compared with the wiring layer 103c that is the lowermost layer closest to the lower structure 12.

[0340] In a similar manner, in the upper-and-lower wiring connection structure 314, in the lower structure 12 as well, the wiring layer 83x for direct connection with the wiring layer 103x of the upper structure 11 is formed on the side closer to the upper structure 11, as compared with the wiring layer 83a that is the uppermost layer closest to the upper structure 11.

[0341] Next, as shown in Figure 40 after the multilayer wiring layer 82 side of the lower structure 12 and the multilayer wiring layer 102 side of the upper structure 11 are adhered in a manner facing each other, the semiconductor substrate 101 of the upper structure 11 is thinned. By this adhesion, the wiring layer 83x of the lower structure 12 and the wiring layer 103x of the upper structure 11 are connected by metal bonding (Cu-Cu bonding).

[0342] Next, as shown in Figure 41 the color filter 15 and the on-chip lens 16 are formed over the photodiode 51 of each pixel 31 with the planarization film 108 interposed.

[0343] Next, as shown in Figure 42 the glass sealing resin 17 is applied to the entire surface of the on-chip lens 16 on which the adhered lower structure 12 and upper structure 11 are formed, with the planarization film 110 interposed, thereby connecting the glass protection substrate 18 by a solid structure.

[0344] Note that, although in this embodiment, in the lower structure 12, the wiring layer 83x for direct connection with the wiring layer 103 of the upper structure 11 is formed separately from the wiring layers 83a to 83c (the wiring layers 83a to 83c become part of the input / output circuit unit 49 and the row drive unit 22 or the column signal processing unit 25), and in the upper structure 11, the wiring layer 103x for direct connection with the wiring layer 83 of the lower structure 12 is formed separately from the wiring layers 103a to 103c (the wiring layers 103a to 103c become a drive wiring of a pixel transistor or the like), it is also possible to connect the wiring layer 83a that is the uppermost layer of the lower structure 12 and the wiring layer 103c that is the lowermost layer of the upper structure 11 by metal bonding (Cu-Cu bonding).

[0345] Figure 42 the steps after the steps shown in Figures 30 to 38The steps described in the case of the double contact structure as the upper and lower wiring connection structure are similar. The final state is the state shown in Figure 43

[0346] <12. Other modification examples>

[0347] <Other modification example 1>

[0348] Other modification examples of the solid-state imaging device 1 will be described below with reference to Figure 44

[0349] Figure 44 A is a cross-sectional view of a portion near the outer periphery of the solid-state imaging device 1 according to Other modification example 1, and Figure 44 B is a plan view of the outer terminal 14 side of the solid-state imaging device 1 according to Other modification example 1.

[0350] In Other modification example 1, as shown in A, the outer terminal 14 is formed directly above the through-hole 88, so as to overlap the position of the through-hole 88 in the plan position. In this way, as shown in B, since it is not necessary to secure an area for forming the re-wiring 90 on the back surface side of the solid-state imaging device 1, the disadvantage of the area for forming the input / output unit 21 can be solved. Figure 44 Figure 44 <Other modification example 2>

[0351] Other modification examples of the solid-state imaging device 1 will be described below with reference to

[0352] Figure 45

[0353] Figure 45 is a cross-sectional view of the solid-state imaging device 1 according to Other modification example 2.

[0354] In Other modification example 2, the solid-state imaging device 1 includes a conductive pad 411 for setting a measurement needle, to measure the operation of the solid-state imaging device 1 in a state before the solid-state imaging device 1 is divided into a plurality of pieces (in other words, a state in which a plurality of solid-state imaging devices 1 are formed on a wafer) using, for example, a conventional semiconductor device measuring machine using a setting needle.

[0355] As shown in Figure 45 , the conductive pad 411 for measurement using a setting needle is formed in an area outside the pixel array unit 24, for example, on the upper side of the pixel peripheral circuit area 313 in which the row drive unit 22, the column signal processing unit 25, and the like are formed. The conductive pad 411 is connected to a predetermined wiring layer 103 of the upper structure 11 using a through-silicon via 412.

[0356] ​​​​​Preferably, the conductive pad 411 for measurement using a set probe is formed before the protective substrate 18 is placed on the surface of the solid-state imaging device 1. In this way, the operation of the solid-state imaging device 1 can be measured before the protective substrate 18 is fixed and while multiple solid-state imaging devices 1 are formed on the wafer.

[0357] The conductive pad 411 used for measurement with a set probe may be formed from a portion of a multilayer wiring layer 102 disposed in the upper structure 11.

[0358] Furthermore, a conductive pad 411 for measuring using a set probe may be formed on the upper side of the area for acquiring a reference level signal (in other words, a black level signal), which is generally referred to as the optical black pixel area provided on the solid-state imaging device 1 or simply as the optical black area (not shown).

[0359] By forming a conductive pad 411 on the solid-state camera 1 for measurement using a set probe before fixing the protective substrate 18 to the solid-state camera 1, it is possible to measure the operation of the solid-state camera 1 using a semiconductor device measurement device before forming the protective substrate 18, while multiple solid-state camera devices 1 are formed on a wafer.

[0360] <Other Modification Example 3>

[0361] The following will refer to Figure 46 To describe other modifications to the solid-state camera device 1.

[0362] Figure 46 This is a cross-sectional view of the solid-state camera device 1 based on other modified example 3.

[0363] According to other modified example 3, the solid-state camera device 1 also includes a conductive pad 421 for setting a measurement probe, so as to measure the operation of the solid-state camera device 1 in a state before the solid-state camera device 1 is divided into multiple pieces (in other words, in a state where multiple solid-state camera devices 1 are formed on a wafer) using a conventional semiconductor device measurement machine that uses the setting probe, for example.

[0364] like Figure 46 As shown, a conductive pad 421 for measurement using a set probe is formed on a scratch line (cut line) between solid-state imaging devices 1.

[0365] Preferably, the conductive pad 421 for measurement using a set probe is formed before the protective substrate 18 is placed on the surface of the solid-state imaging device 1. In this way, the operation of the solid-state imaging device 1 can be measured before the protective substrate 18 is fixed and while multiple solid-state imaging devices 1 are formed on the wafer.

[0366] The conductive pad 421 for measurement with a set probe is formed of a portion of the multilayer wiring layer 102 provided in the upper structure 11, or a portion of the multilayer wiring layer 82 provided in the lower structure 12, or can be formed of the same layer as a portion of the conductive layer used in the upper and lower wiring connection structure. The conductive pad 421 for measurement with a set probe can be connected to the inside of the solid-state imaging device 1 via a portion of the multilayer wiring layer 102 provided in the upper structure 11, or can be connected to the inside of the solid-state imaging device 1 via a portion of the multilayer wiring layer 82 provided in the lower structure 12.

[0367] By forming the conductive pad 421 for measurement with a set probe on the solid-state imaging device 1 before fixing the protective substrate 18 of the solid-state imaging device 1, it is possible to measure the operation of the solid-state imaging device 1 using a set probe with a measuring device of a semiconductor device before forming the protective substrate 18 in a state in which a plurality of solid-state imaging devices 1 are formed on a wafer.

[0368] <Other Modification Example 4>

[0369] Hereinafter, other modification examples of the solid-state imaging device 1 will be described with reference to Figure 47

[0370] Figure 47 is a cross-sectional view of the solid-state imaging device 1 according to other modification example 4.

[0371] The solid-state imaging device 1 according to other modification example 4 also includes a conductive pad 422 for setting a measurement probe for measuring the operation of the solid-state imaging device 1 in a state in which a plurality of solid-state imaging devices 1 are formed on a wafer.

[0372] As shown in Figure 47 , the conductive pad 422 for measurement with a set probe is formed on the lower side of the lower structure 12 in a state in which a plurality of solid-state imaging devices 1 are formed on a wafer. The conductive pad 422 for measurement with a set probe can be formed of, for example, the redistribution layer 90 provided in the lower structure 12.

[0373] It is possible to measure the operation of the solid-state imaging device 1 in a state in which a plurality of solid-state imaging devices 1 are formed on a wafer by turning upside down the wafer so that the protective substrate is provided on the lower side and the conductive pad 422 for measurement with a set probe is provided on the upper side after providing the protective substrate 18 on the surface of the solid-state imaging device 1. In this case, it is possible to measure the operation of the solid-state imaging device 1 using a device that causes light to be incident from the lower side of the solid-state imaging device 1.

[0374] <13. Example of Three-Layer Lamination Structure> ​

[0375] Although in the above-described embodiment, the stacked structure 13 of the solid-state imaging device 1 includes two layers of the lower structure 12 and the upper structure 11, the stacked structure 13 can include a three-layer or more structure.

[0376] An example in which the stacked structure 13 includes three layers by providing a third structure 511 between the lower structure 12 and the upper structure 11 will be described with reference to Figure 48 and 49

[0377] Figure 48 The illustrated pixel array unit 24 has a configuration in a case of a pixel sharing structure.

[0378] In this pixel sharing structure, although a photodiode (PD) 51 and a transfer transistor 52 are provided for each pixel, an FD 53, an amplification transistor 55, a reset transistor 55, and a selection transistor 56 are shared among a plurality of pixels.

[0379] Figure 48 The structure as a sharing unit 520 in which two in the row direction and two in the column direction (2 x 2) of four pixels share the FD 53, the amplification transistor 55, the reset transistor 55, and the selection transistor 56 is illustrated.

[0380] A transfer transistor drive signal line 521 extending in the row direction is connected to each of the gate electrodes of the four transfer transistors 52. Four transfer transistor drive signal lines 521 connected to the gate electrodes of the four transfer transistors 52, respectively, and extending in the row direction are provided in parallel with each other in the column direction.

[0381] The FD 53 is connected to the gate electrode of the amplification transistor 55 and the diffusion layer of the reset transistor 54 by a wiring not illustrated. One reset transistor drive signal line 522 extending in the row direction is connected to the gate electrode of the reset transistor 54.

[0382] One selection transistor drive signal line 523 extending in the row direction is connected to the gate electrode of the selection transistor 56. There is a case in which the selection transistor 56 is omitted.

[0383] In Figure 2 the illustrated system configuration example of the solid-state imaging device 1, a plurality of pixels 31 are connected to a vertical signal line 33 extending in the column direction for each pixel. Each of a plurality of vertical signal lines 33 is connected to a column signal processing unit 25 provided in front of them, and noise processing and AD conversion processing are performed in the column signal processing unit 25.

[0384] On the other hand, Figure 48 ​The illustrated solid-state imaging device 1 having a three-layer stacked structure 13 includes a region signal processing unit 531 in a third structure 511 between the lower structure 12 and the upper structure 11.

[0385] The region signal processing unit 531 includes a readout signal processing unit 532 having a noise processing unit and an ADC, and a data holding unit 533 that holds digital data that is AD-converted.

[0386] For example, in a case where each pixel 31 in the common unit 520 outputs data expressed in 16 bits after AD conversion, the data holding unit 533 includes data holding devices such as latches and shift registers corresponding to 64 bits, to hold the data.

[0387] The region signal processing unit 531 also includes an output signal wiring 537 for outputting a signal held in the data holding unit 533 to the outside of the region signal processing unit 531. The output signal wiring may, for example, be a 64-bit signal line for outputting 64-bit data held in the data holding unit 533 in parallel, or may be a 16-bit signal line for outputting data corresponding to four pixels held in the data holding unit 533 in a manner of one pixel at a time, or may be an 8-bit signal line corresponding to half the data of one pixel, or may be a 32-bit signal line corresponding to the data of two pixels. Alternatively, the output signal wiring can be a 1-bit signal line that reads out the data held in the data holding unit 533 in a form of one bit.

[0388] In Figure 48 In the illustrated solid-state imaging device 1, one common unit 520 of the upper structure 11 is connected to one region signal processing unit 531 of the third structure 511. In other words, the common unit 520 corresponds to the region signal processing unit 531 in a one-to-one manner. Therefore, as illustrated in FIG. 2, the region signal processing unit 531 is connected to the common unit 520 via the output signal wiring 537. Figure 48 As illustrated, the third structure 511 includes a region signal processing unit array 534 in which a plurality of region signal processing units 531 are arranged in a row direction and a column direction.

[0389] Further, the third structure 511 includes a row address control unit 535 that reads out data in the data holding unit 533 provided at each of the plurality of region signal processing units 531 arranged in the row direction and the column direction. The row address control unit 535 determines a readout position in the row direction in a similar manner to a conventional semiconductor memory device.

[0390] The area signal processing unit 531 arranged in the row direction of the area signal processing unit array 534 is connected to the control signal line extending from the row address control unit 535 in the row direction, and the operation of the area signal processing unit 531 is controlled by the row address control unit 535.

[0391] The regional signal processing unit 531 arranged in the column direction of the regional signal processing unit array 534 is connected to the column readout signal line 537 extending in the column direction, and the column readout signal line is connected to the column readout unit 536 disposed in front of the regional signal processing unit array 534.

[0392] Data held in the data holding unit 533 of each area signal processing unit 531 in the area signal processing unit array 534 can be read out in such a way that the data of all the data holding units 533 of the area signal processing units 531 arranged in the row direction are read out to the column readout unit 536 at the same time, or can be read out in such a way that only the data of a specific area signal processing unit 531 specified by the column readout unit 536 is read out.

[0393] Wiring for outputting data read from the area signal processing unit 531 to the outside of the third structure 511 is connected to the column readout unit 536.

[0394] The lower structure 12 includes a readout unit 541, which is connected to the wiring of the column readout unit 536 from the third structure 511 and receives data output from the column readout unit 536.

[0395] In addition, the lower structure 12 includes an image signal processing unit 26 for performing signal processing on data received from the third structure 511.

[0396] Furthermore, the lower structure 12 includes an input / output unit 21 for outputting data received from the third structure 511, via or without the image signal processing unit 26. The input / output unit 21 may include an input circuit unit 42 and an output circuit unit 47. The input circuit unit 42 is used to input, for example, timing signals used in the pixel array unit 24 and feature data used in the image signal processing unit 26, from the outside of the solid-state imaging device 1 to the inside of the device.

[0397] like Figure 49 As shown in B, each common unit 520 formed in the upper structure 11 is connected to the region signal processing unit 531 of the third structure 511, which is directly disposed below the common unit 520. The wiring of the upper structure 11 and the wiring of the third structure 511 can use, for example... Figure 8 The Cu-Cu direct bonding structure shown is used for connection.

[0398] In addition, such as Figure 49 As shown in B of FIG. 12, the column readout unit 536 formed outside the area signal processing unit array 534 in the third structure 511 is connected to the readout unit 541 of the lower structure 12 disposed directly below the column readout unit 536. The wiring of the third structure 511 and the wiring of the lower structure 12 can be connected using, for example, a Cu-Cu direct bonding structure as shown in A of FIG. 13 or a double contact structure as shown in B of FIG. 13. Figure 8 Figure 6

[0399] Therefore, as shown in A of FIG. 14, the pixel signals of each common unit 520 formed in the upper structure 11 are output to the corresponding area signal processing unit 531 of the third structure 511. The data held in the data holding unit 533 of the area signal processing unit 531 is output to the column readout unit 536 and supplied to the readout unit 541 of the lower structure 12. Then, in the image signal processing unit 26, the data is subjected to various signal processing (e.g., tone curve correction processing), and is output to the outside of the device via the input / output unit 21. Figure 49

[0400] Note that in the solid-state imaging device 1 formed by the three-layer stacked structure 13, the input / output unit 21 formed in the lower structure 12 can be disposed on the lower side of the row address control unit 535 of the third structure 511.

[0401] Further, in the solid-state imaging device 1 formed by the three-layer stacked structure 13, the input / output unit 21 formed in the lower structure 12 can be disposed on the lower side of the area signal processing unit 531 of the third structure 511.

[0402] Still further, in the solid-state imaging device 1 formed by the three-layer stacked structure 13, the input / output unit 21 formed in the lower structure 12 can be disposed on the lower side of the pixel array unit 24 of the upper structure 11.

[0403] <14. Application Example of Electronic Device>

[0404] The application of the present application is not limited to application to a solid-state imaging device. That is, the present application can be applied generally to electronic devices such as digital cameras and video cameras that use a solid-state imaging device in an imaging device (optical-electric conversion unit), mobile terminal devices having an imaging function, and copiers that use a solid-state imaging device in an image reading unit. The solid-state imaging device can be formed as one chip or can take the form of a module having an imaging function in which an imaging unit and a signal processing unit or an optical system are collectively packaged.

[0405] Figure 50 is a block diagram illustrating a configuration example of an imaging device as an electronic device to which the present application is applied. ​​​

[0406] Figure 50 The imaging device 900 in FIG. 1 includes an optical unit 901 formed of a lens group, an imaging element 902 that adopts the configuration of the solid-state imaging device 1 in FIG. 1, and a digital signal processor (DSP) circuit 903 (imaging signal processing unit). Further, the imaging device 900 includes a frame memory 904, a display unit 905, a recording unit 906, an operation unit 907, and a power supply unit 908. The DSP circuit 903, the frame memory 904, the display unit 905, the recording unit 906, the operation unit 907, and the power supply unit 908 are connected to each other through a bus 909. Figure 1

[0407] The optical unit 901 takes in incident light (image light) from an object and forms an image on an imaging surface of the solid-state imaging device 902. The solid-state imaging device 902 converts the light quantity of the incident light of the image formed on the imaging surface by the optical unit 901 into an electric signal in a pixel unit and outputs the electric signal as a pixel signal. As the solid-state imaging device 902, the solid-state imaging device 1 in FIG. 1, that is, a solid-state imaging device that does not have a conductive pad for setting a measurement probe at an outer peripheral portion for measurement of the layered structure 13 and that is made smaller by disposing the input / output circuit unit 49 in a region below the pixel array unit 24 of the upper structure 11 or in a region below the pixel peripheral circuit region 313 of the upper structure 11, can be used. Figure 1

[0408] The display unit 905 formed of, for example, a panel-type display device such as a liquid crystal panel and an organic electroluminescence (EL) panel displays a moving image or a still image imaged by the solid-state imaging device 902. The recording unit 906 records a moving image or a still image imaged by the solid-state imaging device 902 in a recording medium such as a hard disk and a semiconductor memory.

[0409] The operation unit 907 issues an operation instruction relating to various functions of the imaging device 900 under the operation of a user. As occasion demands, the power supply unit 908 supplies various power supplies that become operation power of the DSP circuit 903, the frame memory 904, the display unit 905, the recording unit 906, and the operation unit 907 to these supply targets.

[0410] As described above, by using the solid-state imaging device 1 according to the above-described embodiment as the solid-state imaging device 902, it is possible to make the package size of the semiconductor package smaller. Therefore, it is also possible to make the device such as a video camera, a digital camera, and a camera module designed for a mobile equipment such as a cellular phone in the imaging device 900 smaller.

[0411] ​​<15. Application examples of the image sensor>

[0412] Figure 51 is a diagram illustrating an application example of the above-described solid-state imaging device 1.

[0413] The CMOS image sensor as the solid-state imaging device 1 can be used, for example, in various situations described below for sensing light such as visible light, infrared light, ultraviolet light, and X-rays.

[0414] - An apparatus for taking an image for appreciation, for example, a digital video camera and a portable device having a video camera function.

[0415] - An apparatus for transportation, for example, a vehicle-mounted sensor for taking an image of the front, rear, surroundings, interior, or the like of a vehicle, a monitoring camera for monitoring a traveling vehicle or a road, a distance sensor for measuring a distance between vehicles or the like, and the like, which are used for automatic parking or recognition of a driver's state or the like.

[0416] - An apparatus for a home appliance such as a television, a refrigerator, and an air conditioner, which is used for taking an image of a user's gesture and performing an operation of the apparatus in accordance with the gesture.

[0417] - An apparatus for medical care or health care, for example, an endoscope and an apparatus for performing angiography by receiving infrared light.

[0418] - An apparatus for security, for example, a monitoring camera for criminal prevention and a camera for personal authentication.

[0419] - An apparatus for beauty care, for example, a skin measurement apparatus for taking an image of skin and a microscope for taking an image of a scalp.

[0420] - An apparatus for sports, for example, a sports video camera or a wearable camera for sports or the like.

[0421] - An apparatus for agriculture, for example, a camera for monitoring a condition of a field and a crop.

[0422] The solid-state imaging device 1 can be applied to an apparatus in which an electron is used as a signal charge and an apparatus in which a hole is used as a signal charge.

[0423] Further, the application of the present application is not limited to a solid-state imaging device for detecting a distribution of an incident light amount of visible light and taking the distribution as an image, and the present application can be applied generally to a solid-state imaging device for taking a distribution of an incident amount of infrared light, X-rays, particles, or the like as an image, or, in a broad sense, a solid-state imaging device (a physical quantity distribution detection device) for detecting a distribution of another physical quantity such as pressure and electrostatic capacitance and taking the distribution as an image, for example, a fingerprint detection sensor.

[0424] Furthermore, the present application can be applied not only to a solid-state imaging device but also to a semiconductor device having other semiconductor integrated circuits in general.

[0425] Embodiments of the present application are not limited to the above-described embodiments, and various changes can be made thereto without departing from the essence of the present application.

[0426] For example, embodiments in which all or a part of the above-described multiple embodiments are combined can be employed.

[0427] Note that the effects described in this specification are merely examples and the effects are not limited to those described in this specification. Effects other than those described in this specification can be present.

[0428] In addition, the present application can also be configured as follows:

[0429] (1) A solid-state imaging device including:

[0430] a laminate of a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed, a glass substrate positioned above the first structure, and a second structure in which an input circuit unit for allowing a predetermined signal to be input from the outside of the device, an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device, and a signal processing circuit are formed,

[0431] wherein an output unit including the output circuit unit, a first via connected to the output circuit unit and penetrating a semiconductor substrate for constituting a part of the second structure, and an external terminal for signal output connecting the output circuit unit to the outside of the device through the first via, and an input unit including the input circuit unit, a second via connected to the input circuit unit and penetrating the semiconductor substrate, and an external terminal for signal output connecting the input circuit unit to the outside of the device through the second via are provided below the pixel array unit of the first structure.

[0432] (2) A solid-state imaging device including:

[0433] A stack of a first structure in which a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed, and a second structure in which an output circuit unit for outputting a pixel signal output from the pixels to the outside of the device is formed,

[0434] wherein the output circuit unit, a first via, and a signal output external terminal are provided below the pixel array unit of the first structure, the first via penetrates a semiconductor substrate for constituting a part of the second structure, the signal output external terminal is connected to the outside of the device, and

[0435] the output circuit unit is connected to the signal output external terminal through the first via.

[0436] (3) The solid-state imaging device according to (2),

[0437] wherein in the first structure, at least a part of a drive unit for driving the pixels is formed as a pixel peripheral circuit region around the pixel array unit, and

[0438] a part of a plurality of the output circuit units is also provided below the pixel peripheral circuit region of the first structure, and is connected to the signal output external terminal through the first via.

[0439] (4) The solid-state imaging device according to (2) or (3),

[0440] wherein the signal output external terminal is a solder ball.

[0441] (5) The solid-state imaging device according to (4),

[0442] wherein the solder ball is formed at a planar position overlapping a position of the first via.

[0443] (6) The solid-state imaging device according to (4),

[0444] wherein the solder ball is electrically connected to the first via through a rewiring.

[0445] (7) The solid-state imaging device according to (2) or (3),

[0446] wherein the signal output external terminal is a rewiring.

[0447] (8) The solid-state imaging device according to any one of (2) to (7),

[0448] wherein the output circuit unit is provided in a one-to-one corresponding manner with respect to the signal output external terminal.

[0449] (9) The solid-state imaging device according to any one of (2) to (7),

[0450] wherein the output circuit units are arranged in a straight line.

[0451] (10) The solid-state imaging device according to any one of (2) to (7),

[0452] wherein the output circuit units are integrally provided in units of a plurality of the signal output external terminals.

[0453] (11) The solid-state imaging device according to any one of (2) to (7),

[0454] wherein an input circuit unit for allowing a predetermined signal to be input from the outside of the device is further formed in the second structure, and

[0455] the input circuit unit is provided below the pixel array unit of the first structure and is connected to a signal input external terminal connected to the outside of the device through a second via hole that penetrates through a semiconductor substrate for constituting a part of the second structure.

[0456] (12) The solid-state imaging device according to (11),

[0457] wherein in the first structure, at least a part of a drive unit for driving the pixels is formed as a pixel peripheral circuit region around the pixel array unit, and

[0458] a part of a plurality of the input circuit units is also provided below the pixel peripheral circuit region of the first structure and is connected to the signal output external terminal through the second via hole.

[0459] (13) The solid-state imaging device according to any one of (2) to (12),

[0460] wherein a signal processing circuit region is further formed in the second structure.

[0461] (14) The solid-state imaging device according to any one of (2) to (13),

[0462] wherein the first structure and the second structure are electrically connected by a double contact structure.

[0463] (15) The solid-state imaging device according to any one of (2) to (13),

[0464] wherein the first structure and the second structure are electrically connected by a common contact structure.

[0465] (16) The solid-state imaging device according to any one of (2) to (13),

[0466] wherein the first structure and the second structure are electrically connected by Cu-Cu bonding.

[0467] (17) The solid-state imaging device according to any one of (2) to (16),

[0468] wherein a protection substrate for protecting an on-chip lens is provided on the on-chip lens within the pixel array unit of the first structure.

[0469] (18) The solid-state imaging device according to any one of (2) to (17),

[0470] wherein the solid-state imaging device includes a three-layer stacked structure including a third structure in addition to the first structure and the second structure, and a data holding unit is formed in the third structure.

[0471] (19) A manufacturing method of a solid-state imaging device, the manufacturing method comprising:

[0472] bonding a first structure and a second structure so that wiring layers face each other, wherein a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed in the first structure, and an output circuit unit for outputting a pixel signal output from the pixels to an outside of the device is formed in the second structure which is located below the pixel array unit;

[0473] forming a through-hole which penetrates a semiconductor substrate for constituting a part of the second structure; and

[0474] forming an external terminal for signal output at a position below the pixel array unit of the first structure, the external terminal being electrically connected to the output circuit unit through the through-hole and connected to the outside of the device.

[0475] (20) An electronic device comprising:

[0476] a solid-state imaging device including a laminate of a first structure and a second structure, a pixel array unit in which pixels for performing photoelectric conversion are arranged two-dimensionally is formed in the first structure, and an output circuit unit for outputting a pixel signal output from the pixels to an outside of the device is formed in the second structure,

[0477] The output circuit unit, the via, and the signal output external terminal are provided below the pixel array unit of the first structure, the via penetrates a semiconductor substrate that constitutes a part of the second structure, the signal output external terminal is connected to the outside of the device, and

[0478] The output circuit unit is connected to the signal output external terminal through the via.

[0479] List of Reference Signs

[0480] 1 solid-state imaging device 11 first structure (upper structure)

[0481] 12 second structure (lower structure) 13 layered structure

[0482] 14 external terminal (signal input / output terminal) 15 color filter

[0483] 16 on-chip lens 17 glass sealing resin

[0484] 18 protective substrate 21 input / output unit

[0485] 22 row drive unit 24 pixel array unit

[0486] 25 column signal processing unit 26 image signal processing unit

[0487] 31 pixel 41 input terminal

[0488] 42 input circuit unit 47 output circuit unit

[0489] 48 output terminal 49 input / output circuit unit

[0490] 51 photodiode 81 semiconductor substrate

[0491] 88 via 90 rewiring

[0492] 101 semiconductor substrate 105 chip via

[0493] 106 connection wiring 109 through silicon via

[0494] 311 input / output circuit region 312 signal processing unit region

[0495] 313 pixel peripheral circuit region 314 upper and lower substrate connection region

[0496] 321 I / O circuit 511 third structure

[0497] 351 memory substrate 352 memory circuit

[0498] 400 image pickup device 402 solid-state image pickup device

[0499] 531 area signal processing unit 533 data holding unit

[0500] 900 image pickup device 902 solid-state image pickup device

Claims

1. A solid-state camera device, comprising: A first structure, the first structure comprising: A first semiconductor substrate, the first semiconductor substrate including a pixel array unit, the pixel array unit including pixels that perform photoelectric conversion, the pixels being arranged in two dimensions; A first multilayer wiring layer on the first semiconductor substrate; and A first bonding layer, wherein the first multilayer wiring layer is on the first bonding layer, and the first bonding layer comprises one or more of oxide, nitride material and carbon; A glass substrate, wherein the glass substrate is bonded to the first semiconductor substrate; The second structure includes: Second semiconductor substrate; A second multilayer wiring layer on the second semiconductor substrate; The second bonding layer, wherein the second multilayer wiring layer is on the second bonding layer, and the second bonding layer comprises one or more of oxide, nitride material and carbon; A first through-hole and a second through-hole, wherein the first through-hole and the second through-hole penetrate the second semiconductor substrate; and Signal input terminals and signal output terminals are formed on the lower surface of the second semiconductor substrate; The second structure includes an output circuit and an input circuit. The output circuit outputs a pixel signal from the pixel, and the input circuit extracts the input signal and stores it inside the solid-state camera device. Wherein, the first multilayer wiring layer is connected to the second multilayer wiring layer at at least one location, and The first structure is directly bonded to the second structure via the first bonding layer and the second bonding layer. The signal input terminal connects the input circuit to an external device via the first through-hole. The signal output terminal connects the output circuit to the external device via the second through-hole, and the input circuit and the output circuit are arranged in the region below the pixel array unit in the first structure.

2. The solid-state camera device according to claim 1, in, The connection between the first multilayer wiring layer and the second multilayer wiring layer is a Cu-Cu connection.

3. The solid-state camera device according to claim 1, in, In the cross-sectional view, the wiring of the first multilayer wiring layer at the at least one location is located at the bottom of the first multilayer wiring layer, and the wiring of the second multilayer wiring layer at the at least one location is located at the top of the second multilayer wiring layer.

4. The solid-state camera device according to claim 3, in, The wiring of the first multilayer wiring layer at the at least one location is copper, and the wiring of the second multilayer wiring layer at the at least one location is copper.

5. The solid-state camera device according to claim 1, in, The at least one position is a position located within the region of the row driving unit and a position located within the region of the column signal processing unit.

6. The solid-state camera device according to claim 5, in, The region of the row driving unit is the overlapping region of the row driving units arranged in the first structure and the row driving units arranged in the second structure, and the region of the column signal processing unit is the overlapping region of the column signal processing units arranged in the first structure and the column signal processing units arranged in the second structure.

Images