A method and device for motor speed regulation, a motor, and a storage medium

Abstract

The present invention discloses a motor speed regulation method, device, motor and storage medium. The method includes: detecting whether a set level signal is input to the VSP signal port of the drive chip of the motor; if it is detected that the set level signal is input to the VSP signal port of the drive chip of the motor, triggering the voltage change interruption function of the VSP signal pin of the drive chip of the motor; under the voltage change interruption function of the VSP signal pin of the drive chip of the motor, performing a bitwise exclusive OR operation on the state variable of the gear where the motor is located and the binary number 1 to realize two-gear switching speed regulation of the motor. With this solution, for the two-gear speed regulation mode, only by inputting a high-voltage signal to the chip I / O port can the gear switching be realized, and few external resources of the chip are required.

Description

Technical Field

[0001] The present invention belongs to the technical field of motors, and relates to a method and device for motor speed regulation, a motor and a storage medium. Specifically, it relates to a method and device for two-gear motor speed regulation, a two-gear motor and a storage medium. In particular, it relates to a method and device for two-gear motor speed regulation, a two-gear motor and a storage medium based on bitwise operation. Background Art

[0002] In related solutions, the speed regulation methods for motor control in the household appliance field are mainly digital speed regulation and analog speed regulation. Among them, for the digital speed regulation method, PWM (pulse width modulation) signals with different duty cycles of the required frequency are input into the digital port of the chip. After being processed by the internal Timer (timer) register to obtain the signal duty cycle, it is then input into the internal duty cycle - speed linear adjustment subroutine to achieve the speed regulation function. For analog speed regulation, different voltage signals are input into the analog port of the chip, processed by the internal A / D (analog-to-digital conversion) module, and then input into the internal voltage - speed linear adjustment subroutine to obtain the required speed regulation signal.

[0003] In application scenarios such as vacuum cleaners and hair dryers, a gear-shifting speed regulation mode is mostly adopted. For two-gear control, if digital speed regulation is used, two PWM signals with different duty cycles can be given to the chip to achieve it; if analog speed regulation is used, it is necessary to calculate the voltages corresponding to the required speeds for different gears, and there is at least a problem of insufficient resources at the VSP signal input end.

[0004] The above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The purpose of the present invention is to provide a method and device for motor speed regulation, a motor and a storage medium, so as to solve the problem that the speed regulation methods for motor control in household appliances mostly adopt a gear-shifting speed regulation mode. For two-gear control, there is at least a problem of insufficient resources at the VSP signal input end, and achieve the effect that for the two-gear speed regulation mode, only by inputting a high-voltage signal to the I / O port of the chip can the gear shift be realized, and the external resources required by the chip are few.

[0006] The present invention provides a method for motor speed regulation, including: detecting whether a set level signal is input to the VSP signal port of the driving chip of the motor; if it is detected that a set level signal is input to the VSP signal port of the driving chip of the motor, triggering the voltage change interruption function of the VSP signal pin of the driving chip of the motor; under the voltage change interruption function of the VSP signal pin of the driving chip of the motor, performing a bitwise exclusive OR operation on the state variable of the gear where the motor is located and the binary number 1 to realize two-gear switching speed regulation of the motor.

[0007] In some embodiments, when there is an input of the set level signal at the VSP signal port of the driving chip of the motor, it is a high-voltage signal sent to the VSP signal port of the driving chip of the motor at a set time interval.

[0008] In some embodiments, the two speed gears of the motor include: the first speed gear of the motor and the second speed gear of the motor; performing a bitwise exclusive OR operation on the state variable of the gear position where the motor is located and the binary number 1 to achieve the two-speed gear switching speed regulation of the motor, including: setting the state variable of the gear position where the motor is located as the first variable, performing a bitwise exclusive OR operation on the first variable and the binary number 1 to obtain an operation result; determining whether the operation result is equal to the binary number 1; if the operation result is equal to the binary number 1, then execute the set control command of the first speed gear of the motor; if the operation result is not equal to the binary number 1, then execute the set control command of the second speed gear of the motor.

[0009] In some embodiments, before triggering the voltage change interruption function of the VSP signal pin of the driving chip of the motor, it further includes: configuring the voltage change interruption function of the VSP signal pin of the driving chip of the motor.

[0010] In some embodiments, when the motor is equipped with a speed regulation device and the speed regulation device of the motor is equipped with a PWM speed regulation board or a rotary resistor, the VSP signal port of the driving chip of the motor has a first channel, a second channel, and a third channel; the first channel, the second channel, and the third channel can be switched to be used as the speed regulation channels of the motor; wherein, the first channel is used as the input channel of the set level signal; the second channel is used as the input channel of the given analog voltage signal; the third channel is used as the input channel of the given PWM signal; the motor speed regulation method further includes: configuring the signal input type of the VSP signal port of the driving chip of the motor according to the type of the given signal for motor speed regulation; receiving the given signal with the given signal type through the VSP signal port of the driving chip of the motor to achieve the switching speed regulation of the three speed regulation modes of the motor; wherein, the given signal with the given signal type includes any one of the set level signal, the given analog voltage signal, and the given PWM signal; when the given signal with the given signal type is the set level signal, the speed regulation mode of the motor is high and low level speed regulation; when the given signal with the given signal type is the given analog voltage signal, the speed regulation mode of the motor is analog speed regulation; when the given signal with the given signal type is the given PWM signal, the speed regulation mode of the motor is digital speed regulation.

[0011] Matched with the above method, on the other hand, the present invention provides a motor speed regulation device, including: a detection unit configured to detect whether a set level signal is input to the VSP signal port of the driving chip of the motor; a control unit configured to trigger the voltage change interruption function of the VSP signal pin of the driving chip of the motor if it is detected that a set level signal is input to the VSP signal port of the driving chip of the motor; the control unit is further configured to perform a bitwise exclusive OR operation on the state variable of the gear where the motor is located and the binary number 1 under the voltage change interruption function of the VSP signal pin of the driving chip of the motor to achieve two-gear switching speed regulation of the motor.

[0012] In some embodiments, the situation where a set level signal is input to the VSP signal port of the driving chip of the motor is a high voltage signal sent to the VSP signal port of the driving chip of the motor at a set time interval.

[0013] In some embodiments, the two gears of the motor include: the first gear of the motor and the second gear of the motor; the control unit performs a bitwise exclusive OR operation on the state variable of the gear where the motor is located and the binary number 1 to achieve two-gear switching speed regulation of the motor, including: setting the state variable of the gear where the motor is located as a first variable, performing a bitwise exclusive OR operation on the first variable and the binary number 1 to obtain an operation result; determining whether the operation result is equal to the binary number 1; if the operation result is equal to the binary number 1, then executing the set control command of the first gear of the motor; if the operation result is not equal to the binary number 1, then executing the set control command of the second gear of the motor.

[0014] In some embodiments, before triggering the voltage change interruption function of the VSP signal pin of the driving chip of the motor, the control unit further includes: configuring the voltage change interruption function of the VSP signal pin of the driving chip of the motor.

[0015] In some embodiments, when the motor is equipped with a speed regulating device and the speed regulating device of the motor is equipped with a PWM speed regulating board or a resolver resistor, the VSP signal port of the driving chip of the motor has a first channel, a second channel, and a third channel; the first channel, the second channel, and the third channel can be switched to be used as the speed regulating channels of the motor; wherein, the first channel is used as the input channel of the set level signal; the second channel is used as the input channel of the given analog voltage signal; the third channel is used as the input channel of the given PWM signal; the motor speed regulating device further includes: the control unit is further configured to configure the signal input type of the VSP signal port of the driving chip of the motor according to the type of the given signal for motor speed regulation; the control unit is further configured to receive the given signal with the given signal type through the VSP signal port of the driving chip of the motor to realize the switching speed regulation of the three speed regulation modes of the motor; wherein, the given signal with the given signal type includes any one of the set level signal, the given analog voltage signal, and the given PWM signal; when the given signal with the given signal type is the set level signal, the speed regulation mode of the motor is high and low level speed regulation; when the given signal with the given signal type is the given analog voltage signal, the speed regulation mode of the motor is analog speed regulation; when the given signal with the given signal type is the given PWM signal, the speed regulation mode of the motor is digital speed regulation.

[0016] Matched with the above device, on the other hand, the present invention provides a motor, including: the above-mentioned motor speed regulating device.

[0017] Matched with the above method, on the other hand, the present invention provides a storage medium, the storage medium includes a stored program, wherein, when the program runs, it controls the device where the storage medium is located to execute the above-mentioned motor speed regulating method.

[0018] Thus, in the solution of the present invention, for the two-gear speed regulation mode, the level of the VSP signal pin is changed by software to realize the interrupt function, that is, to enter the interrupt subroutine; in the interrupt subroutine, the gear state before the level change of the VSP signal pin is subjected to a bitwise exclusive OR operation with the binary number 1 to obtain an operation result; and the operation result is assigned to the gear state variable after the level change of the VSP signal pin, so as to realize that when a high-voltage signal is input to the VSP port of the motor externally, the level change interrupt is triggered to perform two-gear switching. Thus, for the two-gear speed regulation mode, it is realized that only by inputting a high-voltage signal to the chip I / O port, the gear switching can be realized, and the external resources of the chip required are few.

[0019] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present invention.

[0020] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic flowchart of an embodiment of the motor speed regulation method of the present invention;

[0022] Figure 2 is a schematic flowchart of an embodiment of realizing two-gear switching speed regulation of the motor in the method of the present invention;

[0023] Figure 3 is a schematic flowchart of an embodiment of realizing switching speed regulation of three speed regulation modes in the method of the present invention;

[0024] Figure 4 is a schematic structural diagram of an embodiment of the motor speed regulation device of the present invention;

[0025] Figure 5 is a schematic diagram of the given curve of the VSP input signal;

[0026] Figure 6 is a schematic flowchart of the execution process of the interrupt subroutine;

[0027] Figure 7 is a schematic structural diagram of the relevant circuit of the VSP signal.

[0028] In combination with the accompanying drawings, the reference numerals in the embodiments of the present invention are as follows:

[0029] 102 - Detection unit; 104 - Control unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] It is considered that the speed regulation methods for motor control in the household appliance field are mainly digital speed regulation and analog speed regulation. However, the hardware resources required for implementing these speed regulation methods are different, and the corresponding software configurations also vary, resulting in poor versatility. In some solutions, a two-channel interface circuit connecting the control input signal and the sampling signal is proposed. One path is a digital speed regulation circuit connected to a current-limiting branch, and the other path is an analog speed regulation circuit connected to a filtering branch. A selection switch is connected to the input end of the interface circuit. By software determining whether the input signal is a digital or analog signal, the corresponding software and hardware speed regulation methods are executed to achieve motor speed regulation.

[0032] Although this interface circuit enhances the versatility of the speed regulation solution, it does not essentially improve the software and hardware implementation frameworks for digital or analog speed regulation functions in related solutions. Therefore, there is an urgent need in the industry for a simple and general method for realizing gear-shifting speed regulation to facilitate motor research and production. So, the solution of the present invention proposes a speed regulation method based on bitwise operation.

[0033] According to an embodiment of the present invention, a motor speed regulation method is provided, as Figure 1 shown in the flowchart of an embodiment of the method of the present invention. The motor speed regulation method may include: step S110 to step S130.

[0034] At step S110, it is detected whether a set level signal is input to the VSP signal port of the driving chip of the motor. The set level signal is, for example, a high-level signal.

[0035] In some embodiments, the situation where a set level signal is input to the VSP signal port of the driving chip of the motor is a high-voltage signal sent to the VSP signal port of the driving chip of the motor at a set time interval.

[0036] Figure 5 It is a schematic diagram of the given curve of the VSP input signal. Figure 5 It can show the relationship between the given high-voltage signal of the VSP signal and time t. In Figure 5 the example shown, three rectangular bar signals represent inputting 3 short-time high-voltage signals to the VSP signal port of the motor, and a is the peak value of the high-voltage signal.

[0037] Among them, for different chips, the high-voltage signals input to the pins of different chips are different, and are specifically determined according to the V IH range specified by the relevant chips.

[0038] In the solution of the present invention, for the gear shifting and speed regulation mode used in the field of household appliances in the related solution, by changing the speed regulation function implementation framework in the related solution, it is possible to achieve gear shifting only by inputting a high-voltage signal to the chip I / O port, and the external resources required by the chip are few. In this way, the high-voltage input signal is used to replace the PWM signal generator / rheostat, solving the problem of insufficient resources at the VSP signal input end in the application of gear shifting and speed regulation.

[0039] At step S120, if a set level signal is detected to be input to the VSP signal port of the driving chip of the motor, the voltage change interruption function of the VSP signal pin of the driving chip of the motor is triggered.

[0040] At step S130, under the voltage change interruption function of the VSP signal pin of the driving chip of the motor, a bitwise exclusive OR operation is performed on the state variable of the gear where the motor is located and the binary number 1 to achieve two-gear switching speed regulation of the motor.

[0041] The solution of the present invention designs a speed regulation method based on bitwise operation for the application of two-gear motor speed regulation. By software, the level of the VSP signal (i.e., the motor speed regulation signal) pin changes to achieve an interruption function, that is, to enter the interruption subroutine. In the interruption subroutine, the gear state before the change of the VSP signal pin level is subjected to a bitwise exclusive OR operation with the binary number 1 to obtain an operation result. And this operation result is assigned to the gear state variable after the change of the VSP signal pin level. Among them, the two gear state values of 0 and 1 respectively correspond to the two-gear speed regulation subroutines, so as to achieve two-gear switching when a high-voltage signal is externally input to the VSP port of the motor to trigger a level change interruption. The range of the input high-voltage signal can be determined according to each chip. For example: in the solution of the present invention, the range of the high-voltage signal input by the main control chip used can be ≥2V.

[0042] In some embodiments, the two gears of the motor include: the first gear of the motor and the second gear of the motor.

[0043] For the specific situation of performing a bitwise exclusive OR operation on the state variable of the gear where the motor is located and the binary number 1 in step S130 to achieve two-gear switching speed regulation of the motor, refer to the following exemplary description.

[0044] The following combines Figure 2 The schematic flow diagram of an embodiment for realizing two-gear switching speed regulation of the motor in the method of the present invention shown, and further illustrates the specific process of realizing two-gear switching speed regulation of the motor in step S130, including: step S210 to step S240.

[0045] Step S210: Set the state variable of the motor's gear position to the first variable, and perform an exclusive OR operation on the first variable and the binary number 1 to obtain the operation result.

[0046] Step S220: Determine whether the operation result is equal to the binary number 1.

[0047] Step S230: If the operation result is equal to the binary number 1, execute the setting control command for the first gear position of the motor.

[0048] Step S240: If the operation result is not equal to the binary number 1, execute the setting control command for the second gear position of the motor.

[0049] Figure 6 It is a schematic diagram of the execution process of the interrupt subroutine. As Figure 6 shown, the execution process of the interrupt subroutine includes:

[0050] Step 1: Set the first variable as the state variable of the motor's gear position. When the rising edge interrupt is triggered, the program cuts into this interrupt subroutine.

[0051] Among them, each time a high level is input to the VSP signal port, the rising edge interrupt will be triggered.

[0052] Step 2: After the program cuts into this interrupt subroutine, first execute the command line first_variable ^= 1, that is, perform an exclusive OR operation on the first variable and 1.

[0053] Step 3: Then execute first_variable == 1, that is, judge whether the variable value (i.e., the first variable) is equal to 1: if so, execute Step 4. Otherwise, execute Step 5.

[0054] Step 4: If in the judgment result of first_variable == 1, the variable value (i.e., the first variable) is equal to 1, execute the relevant command line of the first gear position (such as gear position 1), and then execute Step 6. Among them, the rotation speeds of different gear positions are different, and different rotation speeds or different powers can be written in the subroutines of different gear positions to distinguish the gear positions.

[0055] Step 5: If in the judgment result of first_variable == 1, the variable value (i.e., the first variable) is not equal to 1, execute the subroutine related to the second gear position (such as gear position 2), and then execute Step 6.

[0056] Step 6: After executing the above statements, jump out of the interrupt until the next rising edge interrupt arrives again.

[0057] In the solution of the present invention, an exclusive OR operation is performed on the gear position state variable of the motor (such as the first variable) and the binary number 1, and combined with the chip level change interrupt function, so as to change the gear of the motor each time a high level is input to the VSP signal port, thereby realizing the two-gear speed regulation function.

[0058] In the solution of the present invention, for the two-gear speed regulation mode, through software configuration, it is possible to realize gear shifting only with a small number of command lines such as interrupt function resources and exclusive OR statements, requiring few internal resources of the chip. At the same time, this function responds quickly without delay. In this way, with the voltage change interrupt function and exclusive OR operation, instead of the chip digital / analog input signal processing and internal speed regulation subroutine, the problem of cumbersome software configuration of the speed regulation scheme in related solutions for two-gear speed regulation applications is solved.

[0059] In some embodiments, before triggering the voltage change interrupt function of the VSP signal pin of the driving chip of the motor in step S120, it further includes: configuring the voltage change interrupt function of the VSP signal pin of the driving chip of the motor.

[0060] Preferably, configure the voltage change interrupt function of the VSP signal pin of the driving chip of the motor, and detect whether there is a set level signal input to the VSP signal port of the driving chip of the motor, and the set level signal is such as a high level signal. If it is detected that there is the set level signal input to the VSP signal port of the driving chip of the motor, then trigger the voltage change interrupt function of the VSP signal pin of the driving chip of the motor.

[0061] The solution of the present invention relates to a two-gear speed regulation function. First, it is necessary to configure the registers related to the voltage change interrupt function of the VSP signal pin of the chip (such as the main control chip of the motor controller), and configure the corresponding I / O port to allow rising edge detection and generate an interrupt. When a high voltage signal a (greater than the threshold of the chip input high voltage signal) is given to this port instantaneously (such as Figure 5 shown), trigger this interrupt subroutine, and the specific interrupt subroutine flow is as Figure 6 shown. Among them, the pin to which the input signal of the main control chip of the motor controller is connected can be configured with a voltage change interrupt function. After enabling this function register, it can be configured to detect on the rising edge, falling edge, or transition edge. The corresponding I / O port is the pin of the main control chip to which the VSP input signal is connected. First, configure this pin as an input, and then enable the voltage change interrupt function of this pin.

[0062] After entering the interrupt subroutine, the first step is to execute the command line: the first variable ^= 1. The above statement means performing a bitwise exclusive OR operation between the first variable and 1. There are four cases for the bitwise exclusive OR operation: 0^0 = 0, 1^0 = 1, 0^1 = 1, 1^1 = 0 (0 when the two are the same, 1 when the two are different). Assume that the value of the first variable, which represents the gear state variable of the motor at this time, is 0, and its corresponding speed gear is the second gear (such as gear 2). When the above statement is executed, the value of the first variable changes from 0 to 1, and the program then enters the judgment command line: the first variable == 1. If the value of this variable is equal to 1, the commands related to the first gear (such as gear 1) are executed ( Figure 6 the "yes" corresponding branch in). After the execution is completed, the interrupt is exited. When a high voltage signal is given again at the VSP signal port and the interrupt subroutine is entered again, at this time the value of the first variable is 1. After executing the first variable ^= 1, the value of this variable changes from 1 to 0. After the program executes the judgment statement, the commands related to the second gear (such as gear 2) are executed ( Figure 6 the "no" corresponding branch in). By cycling in this way, two-gear switching can be achieved after a high level is given to the VSP signal.

[0063] In some embodiments, when the motor is equipped with a speed regulation device and the speed regulation device of the motor is equipped with a PWM speed regulation board or a resolver resistor, the VSP signal port of the drive chip of the motor has a first channel, a second channel, and a third channel. The first channel, the second channel, and the third channel can be switched to be used as the speed regulation channels of the motor. Among them, the first channel is used as the input channel for the set level signal. The second channel is used as the input channel for the given analog voltage signal. The third channel is used as the input channel for the given PWM signal.

[0064] Correspondingly, the motor speed regulation method further includes: a process of realizing the switching speed regulation of three speed regulation methods.

[0065] Next, in combination with Figure 3 the schematic flowchart of an embodiment of realizing the switching speed regulation of three speed regulation methods in the method of the present invention shown, the specific process of realizing the switching speed regulation of three speed regulation methods is further described, including: step S310 and step S320.

[0066] Step S310, according to the type of the given signal for motor speed regulation, configure the signal input type of the VSP signal port of the drive chip of the motor, so that the signal input type is consistent with the given signal type, and enable the VSP signal port of the drive chip of the motor to receive the given signal with the given signal type.

[0067] Step S320, through the VSP signal port of the drive chip of the motor, receive the given signal with the given signal type, and realize the switching speed regulation of the three speed regulation methods of the motor.

[0068] Among them, the given signal with the said given signal type includes any one of the said set-level signal, the said given analog voltage signal, and the said given PWM signal.

[0069] When the given signal with the said given signal type is the said set-level signal, the speed regulation mode of the motor is high-low level speed regulation.

[0070] When the given signal with the said given signal type is the said given analog voltage signal, the speed regulation mode of the motor is analog speed regulation.

[0071] When the given signal with the said given signal type is the said given PWM signal, the speed regulation mode of the motor is digital speed regulation.

[0072] Figure 7 Schematic diagram of the structure of the relevant circuit for the VSP signal. In Figure 7 In the shown example, box 1 is the VSP given input signal, where channel ① is the given high voltage signal, channel ② is the given analog voltage signal, and channel ③ is the given PWM signal. Box 2 is the clamping circuit, ensuring that the highest voltage at the center point of the two diodes is clamped at the sum of the conduction voltage drop of the diode and the +5V voltage, that is, (5 + the conduction voltage drop V T )V. The solution of the present invention uses a high voltage input signal to replace the PWM signal generator / resolver resistor, solving the problem of insufficient resources at the VSP signal input end (i.e., component 1) in the application of gear shift speed regulation.

[0073] The VSP signal-related circuit involved in the solution of the present invention is as Figure 7 shown. This VSP signal-related circuit consists of resistor R1, resistor R2, capacitor C, and a diode clamping circuit. The Speed signal is the speed regulation signal input to the chip. Assuming that the conduction voltage drop of the two diodes is V T (usually 0.5V or 0.7V), when the output voltage of the Speed signal (i.e., the voltage at point A) exceeds (5 + V T )V, the upper diode conducts, and at this time, the voltage at point B between the two diodes is clamped at (5 + V T )V.

[0074] When external resources are sufficient (i.e., there are speed control devices or components such as a PWM speed control board or a rotary resistor), the gear shifting and speed control function can be achieved in three cases. When a short-time high-voltage signal is given to channel ①, after configuring the I / O port of the relevant chip as a digital input, the gear shifting and speed control algorithm of the present invention described above can be executed. When an analog voltage signal is given to channel ②, the corresponding I / O port is configured as an analog input, and after the signal is converted by the internal A / D converter, an analog speed control program is applied. When a PWM signal is given to channel ③, if the Speed signal is input to the digital port of the chip, after the signal is processed by the internal Timer register, a digital speed control program is applied. If the I / O port can only be configured as an analog input at this time, the capacitance value of capacitor C needs to be greater than that in other speed control applications. At this time, the capacitance value of this capacitor determines the filtering depth of the RC filter circuit composed of resistor R1 and capacitor C, and a uF level is selected. When external resources are insufficient, a high-voltage signal can still be given to channel ① to achieve a two-gear speed control function.

[0075] In the two-gear speed control method provided by the solution of the present invention, by identifying the rising edge of the input signal, it jumps into the shift speed control interrupt subroutine. By performing a bitwise exclusive OR operation on the gear state variable of the motor with 1, each time it jumps into the interrupt subroutine, the gear state is changed to achieve shift speed control. In addition, for the three speed control methods of high and low level speed control, digital speed control, and analog speed control, the same VSP signal-related circuit is used to input to the I / O port of the chip. Thus, the problem of insufficient resources at the VSP signal input end in the application of gear shifting and speed control is solved, and the problem of cumbersome software configuration of the speed control scheme in the relevant schemes in the application of two-gear speed control is solved. At the same time, the speed control method requires fewer internal and external resources of the chip, and the response is rapid without delay.

[0076] Adopting the technical solution of this embodiment, for the two-gear speed control mode, the level of the VSP signal pin is changed by software to achieve the interrupt function, that is, to cut into the interrupt subroutine. In the interrupt subroutine, the gear state before the level change of the VSP signal pin is subjected to a bitwise exclusive OR operation with the binary number 1 to obtain the operation result. And this operation result is assigned to the gear state variable after the level change of the VSP signal pin, so as to realize that when a high-voltage signal is input to the VSP port of the motor externally, the level change interrupt is triggered to perform two-gear switching. Thus, for the two-gear speed control mode, it is realized that only by inputting a high-voltage signal to the I / O port of the chip can the gear be switched, and fewer external resources of the chip are required.

[0077] According to an embodiment of the present invention, there is also provided a motor speed control device corresponding to the motor speed control method. Refer to Figure 3 The structural schematic diagram of an embodiment of the device of the present invention shown. The motor speed control device may include: a detection unit 102 and a control unit 104.

[0078] Among them, the detection unit 102 is configured to detect whether a set level signal is input to the VSP signal port of the drive chip of the motor. The set level signal is, for example, a high level signal. For the specific functions and processing of the detection unit 102, refer to step S110.

[0079] In some embodiments, the situation where a set level signal is input to the VSP signal port of the drive chip of the motor is a high voltage signal sent to the VSP signal port of the drive chip of the motor at a set time interval.

[0080] Figure 5 It is a schematic diagram of the given curve of the VSP input signal. Figure 5 It can show the relationship between the given high voltage signal of the VSP signal and time t. In Figure 5 the example shown, the three rectangular bar signals represent inputting 3 short-time high voltage signals to the VSP signal port of the motor, and a is the peak value of the high voltage signal.

[0081] In the solution of the present invention, for the gear shifting and speed regulation mode used in the field of household appliances in the related solution, by changing the speed regulation function implementation framework in the related solution, it is realized that only by inputting a high voltage signal to the chip I / O port can the gear shift be achieved, and the external resources required by the chip are few. In this way, the high voltage input signal is used to replace the PWM signal generator / resolver resistor, and the problem of insufficient resources at the VSP signal input end in the gear shifting and speed regulation application is solved.

[0082] The control unit 104 is configured to trigger the voltage change interruption function of the VSP signal pin of the drive chip of the motor if it is detected that a set level signal is input to the VSP signal port of the drive chip of the motor. For the specific functions and processing of the control unit 104, also refer to step S120.

[0083] The control unit 104 is further configured to perform a bitwise exclusive OR operation on the state variable of the gear where the motor is located and the binary number 1 under the voltage change interruption function of the VSP signal pin of the drive chip of the motor, so as to realize the two-gear switching speed regulation of the motor. For the specific functions and processing of the control unit 104, also refer to step S130.

[0084] For the solution of the present invention, aiming at the two - speed motor speed regulation application, a speed regulation device based on bitwise operation is designed. By software, the pin level of the VSP signal (i.e., the motor speed regulation signal) changes to implement the interrupt function, that is, to cut into the interrupt subroutine. In the interrupt subroutine, the gear state before the change of the pin level of the VSP signal is subjected to an exclusive - OR operation with the binary number 1 to obtain the operation result. And this operation result is assigned to the gear state variable after the change of the pin level of the VSP signal. Among them, the two gear state values of 0 and 1 respectively correspond to the two - speed regulation subroutines, so as to realize the two - gear switching when a high - voltage signal is input to the VSP port of the motor externally, that is, triggering the level - change interrupt. The range of the input high - voltage signal can be determined according to each chip.

[0085] In some embodiments, the two gears of the motor include: the first gear of the motor and the second gear of the motor.

[0086] The control unit 104 performs an exclusive - OR operation on the state variable of the gear where the motor is located and the binary number 1 to realize the two - gear speed regulation of the motor, including:

[0087] The control unit 104 is specifically further configured to set the state variable of the gear where the motor is located as the first variable, perform an exclusive - OR operation on the first variable and the binary number 1 to obtain the operation result. For the specific functions and processing of this control unit 104, refer to step S210.

[0088] The control unit 104 is specifically further configured to determine whether the operation result is equal to the binary number 1. For the specific functions and processing of this control unit 104, refer to step S220.

[0089] The control unit 104 is specifically further configured to, if the operation result is equal to the binary number 1, execute the setting control command of the first gear of the motor. For the specific functions and processing of this control unit 104, refer to step S230.

[0090] The control unit 104 is specifically further configured to, if the operation result is not equal to the binary number 1, execute the setting control command of the second gear of the motor. For the specific functions and processing of this control unit 104, refer to step S240.

[0091] Figure 6 It is a schematic diagram of the execution process of the interrupt subroutine. As Figure 6 shown, the execution process of the interrupt subroutine includes:

[0092] Step 1: Set the first variable as the state variable of the gear where the motor is located. When the rising edge interrupt is triggered, the program cuts into this interrupt subroutine.

[0093] Among them, each time a high level is input to the VSP signal port, a rising edge interrupt is triggered.

[0094] Step 2: After the program cuts into this interrupt subroutine, first execute the command line: the first variable ^= 1, that is, perform a bitwise exclusive OR operation on the first variable and 1.

[0095] Step 3: Secondly, execute the first variable == 1, that is, determine whether the value of this variable (i.e., the first variable) is equal to 1: if it is, execute Step 4. Otherwise, execute Step 5.

[0096] Step 4: If in the judgment result of the first variable == 1, the value of this variable (i.e., the first variable) is equal to 1, then execute the relevant command lines of the first gear (such as gear 1), and then execute Step 6.

[0097] Step 5: If in the judgment result of the first variable == 1, the value of this variable (i.e., the first variable) is not equal to 1, then execute the relevant subroutine of the second gear (such as gear 2), and then execute Step 6.

[0098] Step 6: After executing the above statements, jump out of the interrupt until the next rising edge interrupt arrives again.

[0099] In the solution of the present invention, a bitwise exclusive OR operation is performed on the gear state variable of the motor (such as the first variable) and the binary number 1, and combined with the chip level change interrupt function, to change the motor gear each time a high level is input to the VSP signal port, thereby realizing the two-gear speed regulation function.

[0100] In the solution of the present invention, for the two-gear speed regulation mode, through software configuration, it is possible to realize gear switching only with a small number of command lines such as interrupt function resources and bitwise exclusive OR statements, requiring few internal resources of the chip, and at the same time, this function responds quickly without delay. In this way, using the voltage change interrupt function and bitwise exclusive OR operation to replace the chip digital / analog input signal processing and internal speed regulation subroutine solves the problem of cumbersome software configuration of the speed regulation scheme in related solutions for two-gear speed regulation applications.

[0101] In some embodiments, the control unit 104, before triggering the voltage change interrupt function of the VSP signal pin of the driving chip of the motor, further includes: the control unit 104 is specifically further configured to configure the voltage change interrupt function of the VSP signal pin of the driving chip of the motor.

[0102] Preferably, configure the voltage change interruption function of the VSP signal pin of the driving chip of the motor, and detect whether there is a set level signal input at the VSP signal port of the driving chip of the motor. The set level signal is, for example, a high level signal. If it is detected that there is the set level signal input at the VSP signal port of the driving chip of the motor, trigger the voltage change interruption function of the VSP signal pin of the driving chip of the motor.

[0103] The solution of the present invention relates to a two-gear speed regulation function. It is necessary to first configure the registers related to the voltage change interruption function of the VSP signal pin of the chip, and configure the corresponding I / O port to allow rising edge detection and generate an interruption. When a high voltage signal a (greater than the threshold of the chip input high voltage signal) is given to this port instantaneously (as Figure 5 shown), trigger this interruption subroutine. The specific interruption subroutine process is as Figure 6 shown. After entering the interruption subroutine, the first step is to execute the command line first variable ^=1. The above statement means to perform an exclusive OR operation between the first variable and 1. There are four cases for the exclusive OR operation: 0^0 = 0, 1^0 = 1, 0^1 = 1, 1^1 = 0 (0 when the two are the same, 1 when the two are different). Assume that the value of the first variable, which is the gear state variable of the motor at this time, is 0, and its corresponding speed gear is the second gear (such as gear 2). When the above statement is executed, the value of the first variable changes from 0 to 1, and the program then enters the judgment command line first variable == 1. When the value of this variable is equal to 1, execute the command line related to the first gear (such as gear 1) ( Figure 6 the "yes" corresponding branch in). After the execution is completed, jump out of this interruption. When a high voltage signal is given to the VSP signal port next time and enters the interruption subroutine again, at this time the value of the first variable is 1. After executing first variable ^=1, the value of this variable changes from 1 to 0. After the program executes the judgment statement, execute the command line related to the second gear (such as gear 2) ( Figure 6 the "no" corresponding branch in). In this way, by cycling, two-gear switching can be achieved after a high level is given to the VSP signal.

[0104] In some embodiments, when the motor is equipped with a speed regulation device, and the speed regulation device of the motor is equipped with a PWM speed regulation board or a resolver resistor, the VSP signal port of the driving chip of the motor has a first channel, a second channel, and a third channel. The first channel, the second channel, and the third channel can be switched to be used as the speed regulation channels of the motor. Among them, the first channel is used as the input channel for the set level signal. The second channel is used as the input channel for the given analog voltage signal. The third channel is used as the input channel for the given PWM signal.

[0105] Correspondingly, the motor speed regulation device further includes: a process of realizing the switching speed regulation of three speed regulation methods, which is specifically as follows:

[0106] The control unit 104 is further configured to configure the signal input type of the VSP signal port of the driving chip of the motor according to the type of the given signal for motor speed regulation, so that the signal input type is consistent with the type of the given signal, and the VSP signal port of the driving chip of the motor can receive the given signal with the type of the given signal. For the specific functions and processing of this control unit 104, refer to step S310.

[0107] The control unit 104 is further configured to receive, through the VSP signal port of the driving chip of the motor, the given signal with the type of the given signal, and implement the switching speed regulation of the three speed regulation modes of the motor. For the specific functions and processing of this control unit 104, refer to step S320.

[0108] Among them, the given signal with the type of the given signal includes any one of the set level signal, the given analog voltage signal, and the given PWM signal.

[0109] When the given signal with the type of the given signal is the set level signal, the speed regulation mode of the motor is high and low level speed regulation.

[0110] When the given signal with the type of the given signal is the given analog voltage signal, the speed regulation mode of the motor is analog speed regulation.

[0111] When the given signal with the type of the given signal is the given PWM signal, the speed regulation mode of the motor is digital speed regulation.

[0112] Figure 7 It is a schematic structural diagram of the circuit related to the VSP signal. In Figure 7 the example shown, box 1 is the VSP given input signal, where channel ① is the given high voltage signal, channel ② is the given analog voltage signal, and channel ③ is the given PWM signal. Box 2 is the clamping circuit, which ensures that the highest voltage at the center point of the two diodes is clamped at the sum of the conduction voltage drop of the diode and the +5V voltage. The solution of the present invention uses a high voltage input signal to replace the PWM signal generator / resolver resistor, and solves the problem of insufficient resources at the VSP signal input end (i.e., component 1) in the application of gear shifting speed regulation.

[0113] The circuit related to the VSP signal involved in the solution of the present invention is as Figure 7 shown. This VSP signal related circuit is composed of a resistor R1, a resistor R2, a capacitor C, and a diode clamping circuit. The Speed signal is the speed regulation signal input to the chip. Assuming that the conduction voltage drop of the two diodes is V T (usually 0.5V or 0.7V), when the output voltage of the Speed signal (i.e., the voltage at point A) exceeds (5 + VT )V, the upper diode conducts, and at this time the voltage at point B between the two diodes is clamped at (5 + V T )V.

[0114] When external resources are sufficient (i.e., there are speed control devices or components such as a PWM speed control board or a resolver resistor), the gear shifting and speed control function can be realized in three cases. When a short-term high-voltage signal is given to channel ①, after configuring the I / O port of the relevant chip as a digital input, the gear shifting and speed control algorithm of the present invention can be executed. When an analog voltage signal is given to channel ②, the corresponding I / O port is configured as an analog input, and the signal is applied to the analog speed control program after internal A / D conversion. When a PWM signal is given to channel ③, if the Speed signal is input to the digital port of the chip, the signal is applied to the digital speed control program after being processed by the internal Timer register. If the I / O port can only be configured as an analog input at this time, then the capacitance value of capacitor C needs to be greater than that in other speed control applications. At this time, the capacitance value of this capacitor determines the filtering depth of the RC filter circuit composed of resistor R1 and capacitor C, and the uF level is selected. When external resources are insufficient, a high-voltage signal can still be given to channel ① to realize the two-gear speed control function.

[0115] In the two-gear speed control device provided by the solution of the present invention, by identifying the rising edge of the input signal, it jumps into the shift speed control interrupt subroutine. By performing a bitwise exclusive OR operation on the gear state variable of the motor with 1, each time it jumps into the interrupt subroutine, the gear state is changed to realize shift speed control. In addition, for the three speed control methods of high and low level speed control, digital speed control, and analog speed control, the same VSP signal-related circuit is used to input to the I / O port of the chip. Thus, the problem of insufficient resources at the VSP signal input end in the application of gear shifting and speed control is solved, and the problem of cumbersome software configuration of the speed control scheme in the relevant schemes in the application of two-gear speed control is solved. At the same time, the speed control device requires fewer internal and external resources of the chip and has a fast response without delay.

[0116] Since the processing and functions realized by the device in this embodiment basically correspond to the embodiments, principles, and examples of the foregoing method, for the details not described in the description of this embodiment, reference can be made to the relevant descriptions in the foregoing embodiments and will not be elaborated here.

[0117] Adopting the technical solution of the present invention, for the two-gear speed control mode, by software, the level of the VSP signal pin is changed to realize the interrupt function, that is, to cut into the interrupt subroutine; in the interrupt subroutine, the gear state before the level change of the VSP signal pin is subjected to a bitwise exclusive OR operation with the binary number 1 to obtain the operation result; and the operation result is assigned to the gear state variable after the level change of the VSP signal pin, so as to realize the two-gear switching by triggering the level change interrupt when a high-voltage signal is input to the VSP port of the motor externally, and solve the problem of insufficient resources at the VSP signal input end in the application of gear shifting and speed control.

[0118] According to an embodiment of the present invention, there is also provided a motor corresponding to the motor speed regulation device. The motor may include: the motor speed regulation device described above.

[0119] Since the processing and functions implemented by the motor in this embodiment are basically corresponding to the embodiments, principles, and examples of the foregoing device, for the details not described in the description of this embodiment, reference may be made to the relevant descriptions in the foregoing embodiments, and details will not be repeated here.

[0120] By adopting the technical solution of the present invention, for the two-gear speed regulation mode, the level of the VSP signal pin is changed by software to implement the interrupt function, that is, to enter the interrupt subroutine; in the interrupt subroutine, the gear state before the level change of the VSP signal pin is exclusive-ORed with the binary number 1 to obtain the operation result; and the operation result is assigned to the gear state variable after the level change of the VSP signal pin, so as to realize the two-gear switching when a high-voltage signal is input to the VSP port of the motor externally, that is, triggering the level change interrupt, which solves the problem of insufficient resources at the VSP signal input end in the application of gear adjustment and speed regulation, solves the problem of cumbersome software configuration of the speed regulation scheme in the relevant schemes of two-gear speed regulation application, and at the same time, the speed regulation control method requires less internal and external resources of the chip and has a rapid response without delay.

[0121] According to an embodiment of the present invention, there is also provided a storage medium corresponding to the motor speed regulation method. The storage medium includes a stored program, wherein when the program runs, it controls the device where the storage medium is located to execute the above-mentioned motor speed regulation method.

[0122] Since the processing and functions implemented by the storage medium in this embodiment are basically corresponding to the embodiments, principles, and examples of the foregoing method, for the details not described in the description of this embodiment, reference may be made to the relevant descriptions in the foregoing embodiments, and details will not be repeated here.

[0123] By adopting the technical solution of the present invention, for the two-gear speed regulation mode, the level of the VSP signal pin is changed by software to implement the interrupt function, that is, to enter the interrupt subroutine; in the interrupt subroutine, the gear state before the level change of the VSP signal pin is exclusive-ORed with the binary number 1 to obtain the operation result; and the operation result is assigned to the gear state variable after the level change of the VSP signal pin, so as to realize the two-gear switching when a high-voltage signal is input to the VSP port of the motor externally, that is, triggering the level change interrupt, which solves the problem of cumbersome software configuration of the speed regulation scheme in the relevant schemes of two-gear speed regulation application.

[0124] In summary, it is easy for those skilled in the art to understand that, without conflict, the above-mentioned advantageous ways can be freely combined and superimposed.

[0125] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A motor speed regulation method, characterized in that, Including: Detecting whether a set-level signal is input to the VSP signal port of the drive chip of the motor; If it is detected that a set-level signal is input to the VSP signal port of the drive chip of the motor, triggering the voltage change interruption function of the VSP signal pin of the drive chip of the motor; Under the voltage change interruption function of the VSP signal pin of the drive chip of the motor, performing an exclusive OR operation on the state variable of the gear position where the motor is located and the binary number 1 to achieve two-gear switching speed regulation of the motor; for the two-gear speed regulation mode, by software, changing the level of the VSP signal pin to achieve the interruption function, that is, entering the interruption subroutine; in the interruption subroutine, performing an exclusive OR operation on the gear position state before the level change of the VSP signal pin and the binary number 1 to obtain the operation result; and assigning the operation result to the gear position state variable after the level change of the VSP signal pin, so as to achieve two-gear switching when a high-voltage signal is input to the VSP signal port of the motor externally, triggering a level change interruption.

2. The motor speed regulation method according to claim 1, wherein The situation where a set-level signal is input to the VSP signal port of the drive chip of the motor is a high-voltage signal sent to the VSP signal port of the drive chip of the motor at a set time interval.

3. The motor speed regulation method according to claim 1, characterized in that, The two gears of the motor include: the first gear of the motor and the second gear of the motor; Performing an exclusive OR operation on the state variable of the gear position where the motor is located and the binary number 1 to achieve two-gear switching speed regulation of the motor, including: Setting the state variable of the gear position where the motor is located as the first variable, and performing an exclusive OR operation on the first variable and the binary number 1 to obtain the operation result; Determining whether the operation result is equal to the binary number 1; If the operation result is equal to the binary number 1, executing the set control command of the first gear of the motor; If the operation result is not equal to the binary number 1, executing the set control command of the second gear of the motor.

4. The motor speed regulation method according to any one of claims 1 to 3, characterized in that, Before triggering the voltage change interruption function of the VSP signal pin of the drive chip of the motor, it further includes: Configuring the voltage change interruption function of the VSP signal pin of the drive chip of the motor.

5. The motor speed regulation method according to any one of claims 1 to 3, characterized in that, When the motor is equipped with a speed regulation device, and the speed regulation device of the motor is equipped with a PWM speed regulation board or a rotary resistor, the VSP signal port of the drive chip of the motor has a first channel, a second channel, and a third channel; the first channel, the second channel, and the third channel can be switched as the speed regulation channels of the motor; among them, the first channel is used as the input channel of the set-level signal; the second channel is used as the input channel of the given analog voltage signal; the third channel is used as the input channel of the given PWM signal; The motor speed regulation method further includes: Configuring the signal input type of the VSP signal port of the drive chip of the motor according to the type of the given signal for motor speed regulation; Receiving a given signal with the given signal type through the VSP signal port of the drive chip of the motor to achieve switching speed regulation of three speed regulation modes of the motor; Among them, the given signal with the said given signal type includes any one of the said set level signal, the said given analog voltage signal, and the said given PWM signal; When the given signal with the said given signal type is the said set level signal, the speed regulation method of the motor is high-low level speed regulation; When the given signal with the said given signal type is the said given analog voltage signal, the speed regulation method of the motor is analog speed regulation; When the given signal with the said given signal type is the said given PWM signal, the speed regulation method of the motor is digital speed regulation.

6. A motor speed control device, characterized in that, It includes: A detection unit configured to detect whether there is a set level signal input at the VSP signal port of the drive chip of the motor; A control unit configured to trigger the voltage change interruption function of the VSP signal pin of the drive chip of the motor if it is detected that there is the said set level signal input at the VSP signal port of the drive chip of the motor; The said control unit is further configured to perform a bitwise exclusive OR operation on the state variable of the gear position where the motor is located and the binary number 1 under the voltage change interruption function of the VSP signal pin of the drive chip of the motor to realize two-gear switching speed regulation of the motor; for the two-gear speed regulation mode, the level of the VSP signal pin is changed through software to realize the interruption function, that is, to cut into the interruption subroutine; in the interruption subroutine, the gear position state before the level change of the VSP signal pin is subjected to a bitwise exclusive OR operation with the binary number 1 to obtain an operation result; and the operation result is assigned to the state variable of the gear position after the level change of the VSP signal pin, so as to realize two-gear switching by triggering the level change interruption when a high voltage signal is input to the VSP signal port of the motor externally.

7. The motor speed regulation device according to claim 6, characterized in that, The situation where there is the said set level signal input at the VSP signal port of the drive chip of the motor is a high voltage signal sent to the VSP signal port of the drive chip of the motor at a set time interval.

8. The motor speed regulation device according to claim 6, characterized in that, The two gears of the motor include: the first gear of the motor and the second gear of the motor; The control unit performs a bitwise exclusive OR operation on the state variable of the gear position where the motor is located and the binary number 1 to realize two-gear switching speed regulation of the motor, including: Setting the state variable of the gear position where the motor is located as the first variable, and performing a bitwise exclusive OR operation on the first variable and the binary number 1 to obtain an operation result; Determining whether the operation result is equal to the binary number 1; If the operation result is equal to the binary number 1, then execute the set control command of the first gear of the motor; If the operation result is not equal to the binary number 1, then execute the set control command of the second gear of the motor.

9. The motor speed regulation device according to any one of claims 6 to 8, characterized in that, Before triggering the voltage change interruption function of the VSP signal pin of the drive chip of the motor, the control unit further includes: Configuring the voltage change interruption function of the VSP signal pin of the drive chip of the motor.

10. The motor speed regulation device according to any one of claims 6 to 8, characterized in that When the motor is equipped with a speed regulation device, and the speed regulation device of the motor is equipped with a PWM speed regulation board or a resolver resistor, the VSP signal port of the driving chip of the motor has a first channel, a second channel, and a third channel; the first channel, the second channel, and the third channel can be switched to be the speed regulation channels of the motor; wherein, the first channel serves as the input channel of the set level signal; the second channel serves as the input channel of the given analog voltage signal; the third channel serves as the input channel of the given PWM signal; The motor speed regulation device further includes: The control unit is further configured to configure the signal input type of the VSP signal port of the driving chip of the motor according to the type of the given signal for motor speed regulation; The control unit is further configured to receive the given signal with the given signal type through the VSP signal port of the driving chip of the motor to achieve the switching speed regulation of the three speed regulation modes of the motor; Wherein, the given signal with the given signal type includes any one of the set level signal, the given analog voltage signal, and the given PWM signal; When the given signal with the given signal type is the set level signal, the speed regulation mode of the motor is high and low level speed regulation; When the given signal with the given signal type is the given analog voltage signal, the speed regulation mode of the motor is analog speed regulation; When the given signal with the given signal type is the given PWM signal, the speed regulation mode of the motor is digital speed regulation.

11. A motor, characterized in that, Including: The motor speed regulation device according to any one of claims 6 to 10.

12. A storage medium, characterized in that, The storage medium includes a stored program, wherein when the program runs, it controls the device where the storage medium is located to execute the motor speed regulation method according to any one of claims 1 to 5.

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