Integrated transistors having gate material through semiconductor material pillars, and methods of forming integrated transistors

Abstract

Some embodiments include an integrated assembly having a semiconductor material pillar. The pillar has a base region and diverges into two sections that extend upward from the base region. The two sections are horizontally spaced apart from each other by an intermediate region. A conductive gate is located within the intermediate region. A first source / drain region is located within the base region, a second source / drain region is located within the sections, and a channel region is located within the sections. The channel region is located adjacent to the conductive gate and is vertically disposed between the first source / drain region and the second source / drain region. Some embodiments include methods of forming an integrated assembly.

Description

[0001] Relevant patent data

[0002] This application relates to U.S. Patent Application No. 16 / 526,074, filed July 30, 2019, entitled "Integrated Transistors Having Gate Material Passing Through a Pillar of Semiconductor Material, and Methods of Forming Integrated Transistors," the entire contents of which are incorporated herein by reference. Technical Field

[0003] Integrated assemblies (e.g., memory arrays). Integrated assemblies having transistors having gate material passing through semiconductor material pillars. Methods for forming integrated assemblies. Background Technology

[0004] Memory is a type of integrated circuit system used in computer systems to store data. An example of memory is DRAM (Dynamic Random Access Memory). DRAM cells may each include transistors combined with capacitors. DRAM cells may be arranged in an array; word lines extend along the rows of the array, and digital lines extend along the columns of the array. Word lines may be coupled to the transistors of the memory cells. Each memory cell can be uniquely addressed by a combination of one word line and one digital line.

[0005] The ongoing goal is to increase the integration density of integrated circuit systems, with a related objective being to increase the packaging density of integrated circuit components. The aim is to develop new DRAM architectures that can be scaled to high integration levels, and methods for manufacturing such DRAM architectures. Attached Figure Description

[0006] Figure 1 It is a graphical 3D view of the region of the instance memory array.

[0007] Figure 2A and 2B This is a top-down diagram of the region of the instance memory array.

[0008] Figure 3A and 3B This is a schematic cross-sectional side view of the region of the instance integration assembly at the process stage of the instance method. Figure 3A The view along Figure 3B Line AA, and Figure 3BThe view along Figure 3A BB line.

[0009] Figure 4A and 4B Is Figure 3A and 3B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 4A The view along Figure 4B Line AA, and Figure 4B The view along Figure 4A BB line.

[0010] Figure 5A and 5B Is Figure 4A and 4B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 5A The view along Figure 5B Line AA, and Figure 5B The view along Figure 5A BB line.

[0011] Figure 6A and 6B Is Figure 5A and 5B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 6A The view along Figure 6B Line AA, and Figure 6B The view along Figure 6A BB line.

[0012] Figure 7A and 7B Is Figure 6A and 6B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 7A The view along Figure 7B Line AA, and Figure 7B The view along Figure 7A BB line.

[0013] Figure 8A and 8B Is Figure 7A and 7B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 8A The view along Figure 8B Line AA, and Figure 8B The view along Figure 8A BB line.

[0014] Figure 8C and 8D Is Figure 7A After the process stage and for Figure 8A Examples of alternatives to the process stage Figure 3A A schematic cross-sectional side view of the area of ​​the example integrated assembly.

[0015] Figure 9A and 9B Is Figure 8A and 8B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 9A The view along Figure 9B Line AA, and Figure 9B The view along Figure 9A BB line.

[0016] Figure 10A and 10B Is Figure 9A and 9B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 10A The view along Figure 10B Line AA, and Figure 10B The view along Figure 10A BB line.

[0017] Figure 11A and 11B Is Figure 10A and 10B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 11A The view along Figure 11B Line AA, and Figure 11B The view along Figure 11A BB line.

[0018] Figure 12A and 12B Is Figure 11A and11B Example process stages after the process stage Figure 3A and 3B A schematic cross-sectional side view of the area of ​​the example integrated assembly. Figure 12A The view along Figure 12B Line AA, and Figure 12B The view along Figure 12A BB line.

[0019] Figure 13 It is a graphical 3D view of the region of the instance memory array.

[0020] Figure 14 yes Figure 13 A 3D diagram of an enlarged area of ​​the memory array.

[0021] Figure 14A yes Figure 14 A diagrammatic 3D view of the regions of an alternative memory array.

[0022] Figure 15 This is a schematic diagram of the regions of the instance memory array.

[0023] Figure 16 It is a schematic cross-sectional side view of the region including the stacked layer of the instance assembly. Detailed Implementation

[0024] Some embodiments include an assembly with an integrated transistor having a conductive gate material extending through a semiconductor material pillar. The integrated transistor may be incorporated into a memory array (e.g., a DRAM array). Some embodiments include a method of forming the integrated transistor. Reference Figures 1 to 16 Describe an example implementation.

[0025] refer to Figure 1 The integrated assembly 10 includes a memory array 14 supported above the base 12.

[0026] The base 12 may include semiconductor materials; and may include, for example, single-crystal silicon, substantially composed of, or composed of. The base 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductor materials, including but not limited to bulk semiconductor materials, such as semiconductor wafers (alone or in combinations comprising other materials), and semiconductor material layers (alone or in combinations comprising other materials). The term "substrate" means any support structure, including but not limited to the semiconductor substrates described above. In some applications, the base 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include one or more of, for example, refractory metals, barrier materials, diffusion materials, insulating materials, etc.

[0027] A gap is provided between the base and the memory array 14 to indicate that other materials and components may be formed between the base 12 and the memory array 14. For example, the memory array may be supported by an insulating material (not shown).

[0028] The memory array 14 includes digital lines (bit lines, sense lines) 16 extending along a first direction represented by the y-axis and word lines (access lines) 18 extending along a second direction represented by the x-axis. In some embodiments, word lines 18 may be considered to extend along the row direction of the memory array 14, and digital lines 16 may be considered to extend along the column direction of the memory array. One of the x-axis and y-axis directions may be referred to as the first horizontal direction, and the other may be referred to as the second horizontal direction; wherein the first horizontal direction intersects the second horizontal direction. In the illustrated embodiment, the first horizontal direction (the direction of the x-axis or y-axis) is substantially orthogonal to the second horizontal direction (the direction of the other of the x-axis and y-axis); wherein the term "substantially orthogonal" means orthogonal within reasonable tolerances of fabrication and measurement.

[0029] The digital line 16 and word line 18 may comprise any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). The digital line 16 and word line 18 may comprise compositions identical to each other, or may comprise compositions different from each other.

[0030] Post 20 extends upward from number line 16. Post 20 includes semiconductor material 22. Semiconductor material 22 may include any suitable composition; and in some embodiments, it may include one or more of silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., substantially composed of, or composed of; wherein the term group III / V semiconductor material refers to semiconductor materials comprising elements selected from groups III and V of the periodic table (where group III and V are older nomenclature and are now referred to as groups 13 and 15). In some embodiments, semiconductor material 22 may include silicon, substantially composed of, or composed of.

[0031] The column 20 extends vertically along the z-axis; the z-axis is shown to be substantially orthogonal to both the x-axis and y-axis.

[0032] The column 20 may have any suitable size; and in some embodiments, it may have a height H ranging from about 100 nanometers (nm) to about 300 nm; a width W ranging from about 5 nm to about 30 nm (and in some embodiments less than or equal to about 25 nm); and a length L ranging from about 5 nm to about 30 nm (and in some embodiments less than or equal to about 25 nm). The width W may be equal to the length L, or may be different from the length.

[0033] Word lines 18 are illustrated as passing through the central region of pillars 20 (wherein the term "central region of pillar" means a region inside the pillar, which may or may not be centered relative to the pillar). In some embodiments, each of the pillars 20 is incorporated into an integrated transistor. The word lines include a gate region located within the pillar and are used to operate the integrated transistor. The transistor may be a ferroelectric transistor or a non-ferroelectric transistor, as will be discussed in more detail below.

[0034] If the transistor is a ferroelectric transistor, then it can be used as a memory cell within a memory array.

[0035] If the transistor is a nonferroelectric transistor, then it can be used as an access transistor within a memory array. A memory element (e.g., a capacitor) can be coupled to the access transistor and used within a memory cell of a memory array (e.g., a DRAM array). Example memory elements are described in more detail below.

[0036] Figure 1 The diagram illustrates word lines electrically coupled to driver circuitry (e.g., CMOS) 24 via connections 26 at the ends of the word lines. The advantage of having word lines pass through the central region of the semiconductor pillar 20 is that this provides more space between adjacent word lines than is available in a conventional configuration (where word lines pass along the edges of the semiconductor pillars rather than through them), which simplifies the fabrication of connections 26; and this further improves the scalability of the memory array 14 compared to conventional configurations of similar memory arrays.

[0037] Figure 2A and 2B This shows memory array 14 in a pair of instance configurations.

[0038] Figure 2A The configuration shows adjacent word lines 18a and 18b coupled to connections 26a and 26b, respectively, wherein such connections are coupled to driver circuitry 24. Connections 26a and 26b are located at the ends of word lines 18a and 18b and are offset relative to each other along the row axis direction (x-axis direction, word line (WL) direction). Offset connections 26a and 26b may be located at the same ends of adjacent word lines 18a and 18b, or may be located at opposite ends of the adjacent word lines (as shown).

[0039] Figure 2B The configuration shows that connections 26a and 26b are directly adjacent to each other relative to the row axis and offset only along the column axis (y-axis direction, DL line direction). Figure 2B In the illustrated embodiment, connections 26a and 26b are located at both ends of word lines 18a and 18b. In other embodiments, connections 26a and 26b may be located only at one end of the word line. In any case, Figure 2B This demonstrates the advantages that the memory configuration described herein can achieve compared to conventional configurations. Specifically, the word line 18 passing through the semiconductor pillar 20 allows for a wider spacing between word lines than would be achieved in a conventional configuration where word lines pass along the edge of the semiconductor pillar. This allows connections 26a and 26b to be directly adjacent to each other in the highly integrated memory configuration described herein, which would be impossible in a conventional memory configuration with similar integration.

[0040] Memory array 14 can be formed using any suitable processing. (Reference) Figure 3A to 1 2. Description of instance processing.

[0041] refer to Figure 3A and 3B The process stage after the semiconductor material 22 is formed above the digital line 16 describes the assembly 10. Figure 3A and 3B The views are orthogonal to each other; where Figure 3A The view along Figure 3B Line AA, and Figure 3B The view along Figure 3A BB line. Figure 3A The view can be considered as along the corresponding Figure 1 The direction of the y-axis, and Figure 3B The view can be considered as along the corresponding Figure 1 The direction of the x-axis.

[0042] Digital line 16 is shown to include conductive digital line material 17. Such digital line material may include any suitable conductive composition; for example, various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., one or more of conductively doped silicon, conductively doped germanium, etc.). In some embodiments, digital line material 17 may include metals (e.g., tungsten, titanium, etc.) and / or one or more metal-containing compositions (e.g., titanium nitride, tungsten nitride, titanium silicide, tungsten silicide, etc.).

[0043] Semiconductor material 22 is patterned into pillars 20, wherein such pillars extend upward from digital lines 16.

[0044] The protective material 28 is located on top of the column 20. The protective material 28 may include any suitable composition; and in some embodiments, it may include, be substantially composed of, or be composed of silicon dioxide.

[0045] Insulating material 30 laterally surrounds post 20. Insulating material 30 may include any suitable composition; and in some embodiments, it may include, be substantially composed of, or be composed of silicon dioxide. Insulating material 30 may correspond to spin-on dielectric (SOD).

[0046] In some embodiments, Figure 3A and 3B The configuration can be considered to include a block 32 extending across the digital line 16; wherein such a block includes semiconductor pillars 20, and materials 28 and 30 surrounding the pillars.

[0047] To simplify the diagram, base 12 ( Figure 1 )exist Figure 3A and 3B It is not shown in the image, but it usually appears below the number 16.

[0048] refer to Figure 4A and 4B The insulating material 30 is recessed relative to the protective material 28. In the illustrated embodiment, the upper surface 31 of the insulating material 30 extends together with the bottom surface 29 of the protective material 28 after the material 30 is recessed.

[0049] refer to Figure 5A and 5B A second protective material 34 is formed above the upper surface 31 of the recessed material 30 and adjacent to the first protective material 28. The second protective material 34 may comprise any suitable composition; and in some embodiments, it may comprise, substantially comprise, or comprise a material including silicon and carbon (e.g., silicon carbide). In the illustrated embodiment, a planarized surface 35 is formed to extend across the first protective material 28 and the second protective material 34. The planarized surface 35 may be formed by any suitable treatment; including, for example, chemical mechanical polishing (CMP).

[0050] Materials 22, 30, 28, and 34 can be considered together as incorporated into block 32, which extends across the number line 16.

[0051] refer to Figure 6A and 6B Remove the first protective material 28 ( Figure 5A and 5B This forms an opening 36 extending into the block 32. The opening 36 is located directly above the semiconductor pillar 22 and exposes the upper surface 23 of the semiconductor pillar.

[0052] Material 38 is formed over block 32. Material 38 may include any suitable composition; and in some embodiments, it may include, substantially consist of, or consist of silicon nitride.

[0053] Material 38 conforms to the top surface of block 32 and extends into opening 36. The upper morphology of material 38 has valleys 40 above semiconductor pillar 20 and peaks 42 between the valleys. In some embodiments, material 38 may be referred to as patterned material to indicate that the material has a patterned morphology including the described peaks 42 and valleys 40.

[0054] refer to Figure 7A and 7B , Tanibe 40( Figure 6A and 6B This extends into the semiconductor pillar 20, forming an opening 44 within the semiconductor pillar. In the illustrated embodiment, such an opening is incorporated into a slit 46 relative to... Figure 7A The cross-section extends into the page and along... Figure 7B The cross-sectional extension. The opening 44 can help align the slit 46 with the central region of the post 20. However, the slit 46 can be patterned with any suitable treatment. For example, in addition to forming the opening 46 with conformal material 38, or as an alternative to forming the opening 46 with conformal material 38, the slit 46 can correspond to a trench patterned using an optically lithographically patterned photoresist mask (not shown).

[0055] Each of the patterned pillars 20 includes a base region 48 and a pair of segments (protrusions) 50 and 52 extending upward from the base region. In some embodiments, the pillar 20 may be considered to extend vertically from the upper surface of the digital line 16; include a base region 48 directly above the digital line; and branch into a first segment 50 and a second segment 52 extending upward from the base region.

[0056] The first segment 50 and the second segment 52 are horizontally spaced apart from each other by an intermediate region (gap) 54. In some embodiments, each of the patterned columns 20 may be considered to have an associated slit 46 and an intermediate gap 54 corresponding to the associated slit.

[0057] In the illustrated embodiment, the lower region of the pillar 20 is conductively doped to form a first source / drain region 56 within the lower region. The approximate upper boundary of the first source / drain region is illustrated using dashed line 57. The upper boundary of the source / drain region 56 can be located at any suitable location within the pillar 20, and in some embodiments may be above or below the illustrated location 57.

[0058] The source / drain region 56 can be formed at any suitable process stage, and is included in Figure 7A and 7B Previous process stages (e.g., in) Figure 3A and 3B (Pad doping before the process stage). However, in Figure 7A and 7B Forming the source / drain region 56 during the process stage can be advantageous because it allows the source / drain region to be aligned with the semiconductor pillar 20.

[0059] refer to Figure 8A and 8B An insulating material 58 is formed along the sidewall 47 of the slit 46; and in the illustrated embodiment, it is also formed along the bottom 49 of the slit. The insulating material 58 may be referred to as a first insulating material to distinguish it from other insulating materials that may also be formed within the slit 46. In some embodiments, the insulating material 58 may be referred to as a gate dielectric material.

[0060] The insulating material 58 may include any suitable composition; and in some embodiments may include silicon dioxide and / or one or more high-k dielectric materials (wherein the term high-k means a dielectric constant greater than that of silicon dioxide). Examples of high-k dielectric materials include alumina, hafnium oxide, zirconium oxide, etc.

[0061] In some embodiments, insulating material 58 may include a ferroelectric material suitable for ferroelectric transistors. The ferroelectric material may include any suitable composition; and may, for example, include one or more materials selected from the group consisting of, substantially consisting of, or consisting of: transition metal oxides, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconate titanate, tantalum oxide, and barium strontium titanate; and may contain dopants including one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and rare earth elements. The ferroelectric material may be provided in any suitable configuration, for example, a single homogeneous material, or a stack of two or more discrete individual materials.

[0062] In some embodiments, the insulating material 58 may be composed of a nonferroelectric material (e.g., silicon dioxide).

[0063] The insulating material 58 may be oxidized and grown from the semiconductor material 22 of the semiconductor pillar 20. For example, if the semiconductor material 22 comprises silicon, then the insulating material 58 may comprise, be substantially composed of, or be composed of silicon dioxide, which is oxidized and grown from such semiconductor material.

[0064] In addition to, or as an alternative to, oxidative growth, insulating material 58 may be deposited along the sidewalls 47 and bottom 49 of the slit 46. Such deposition may be performed using any suitable process, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

[0065] Figure 8A This illustrates an embodiment in which material 58 is selectively formed along surfaces 47 and 49 of semiconductor material 22 relative to the surfaces of materials 34 and 38. This can be achieved by selective deposition of material 58 and / or by oxidative growth of material 58 from the exposed surface of semiconductor material 22. In other embodiments (discussed below), material 58 may also be formed along the surfaces of materials 34 and 38 in addition to being formed along the surface of semiconductor material 22.

[0066] Conductive material 19 is formed within slit 46 and adjacent to (above) insulating material 58. Conductive material 19 is ultimately used to form word lines 18 and may be referred to as word line material. Conductive material 19 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 19 may include one or more metals (e.g., tungsten, titanium, etc.); and / or one or more metal-containing compositions (e.g., metal nitrides, metal carbides, metal silicides, etc.). Word line material 19 may be the same composition as digital line material 17, or it may be a different composition relative to digital line material.

[0067] The upper surface of the line material 19 can be planarized to remove some of the excess material 19.

[0068] Figure 8C and 8D Display can be used as an alternative Figure 8A The processing stage of the process.

[0069] Figure 8C This illustrates an embodiment in which insulating material 58 is deposited along the surfaces of all materials 22, 34, and 38, and then conductive material 19 is formed within slit 46 and above insulating material 58.

[0070] Figure 8DAn embodiment is described in which another insulating material 60 is formed within the slit 46 prior to the formation of the insulating material 58 and the conductive material 46. The insulating material 60 may be referred to as the second insulating material to distinguish it from the first insulating material 58. The insulating material 60 may comprise any suitable composition; and in some embodiments, it may comprise, substantially comprise, or consist of silicon dioxide, a low-k dielectric material, and / or a high-k dielectric material. The term "low-k" means a dielectric constant less than that of silicon dioxide. An example low-k dielectric material is porous silicon dioxide. In some embodiments, the insulating material 60 may be the same composition as the insulating material 58, and in other embodiments, the insulating material 60 may be a different composition from the insulating material 58.

[0071] The insulating material 60 can form a step that lifts the word line material 19 to a desired position within the slit 46. Ultimately, the word line material 19 is patterned into word lines 18, and the insulating material 60 can be used to align such word lines relative to the bottom portions of the protrusions 50 and 52 of the semiconductor pillars 20 at a desired position.

[0072] Despite Figure 8D In the embodiments, the insulating material 58 is shown to not extend across the upper surface of the insulating material 60, but it should be understood that it can be formed with... Figure 8D Other embodiments similar to the one described above, wherein material 58 is deposited (similar to...) Figure 8C The deposition shown in the figure extends across the upper surface of material 60 and across the surfaces of materials 34 and 38.

[0073] refer to Figure 9A and 9B Assembly 10 is shown in Figure 8A and 8B This is a processing stage following the previous processing stage. Materials 19 and 58 are recessed within the slit 46 to form an opening 62 in the upper region of the slit 46. The patterned material 19 becomes similar to the above reference. Figure 1 The character line described is character line 18.

[0074] The second source / drain region 64 is formed within segments 50 and 52 of the semiconductor pillar 20. The approximate lower boundary of the second source / drain region is illustrated by dashed line 65. The lower boundary of the source / drain region 64 may be located at any suitable location within the pillar 20, and in some embodiments may be located above or below the illustrated location 65.

[0075] The source / drain region 64 can be formed at any suitable process stage, and is included in Figure 9A and 9B Previous process stages (e.g., in) Figure 3A and 3B (Pad doping before the process stage). However, in Figure 9A and 9B Forming the source / drain region 64 during the process stage is advantageous because it allows the source / drain region to be aligned with the upper surface of the semiconductor pillar 20 and word line 18.

[0076] Channel region 66 is located within vertically extending sections 50 and 52, and is vertically positioned between the lower source / drain region 56 and the upper source / drain region 64 (in some embodiments, source / drain regions 56 and 64 may be considered to be perpendicularly spaced apart from each other by channel region 66). Channel region 66 can be doped to any suitable level with any suitable dopant (and in some embodiments may be intrinsically doped). Doping of the channel region may occur... Figure 9A and 9B The processing stage, and / or another processing stage (e.g., in Figure 3A and 3B The processing stage preceding the main processing stage utilizes blanket doping.

[0077] In some embodiments, regions 56, 64, and 66 are incorporated into an n-channel device; and therefore, source / drain regions 56 and 64 are n-type doped. In other embodiments, regions 56, 64, and 66 are incorporated into a p-channel device; and therefore, source / drain regions 56 and 64 are p-type doped.

[0078] Each word line 18 has a pair of opposing sidewall surfaces 67, a top surface 69, and a bottom surface 71; wherein the sidewall surfaces extend between the top and bottom surfaces. The region of the word line 18 within the pillar 20 can be used as the gate of a transistor device; and can be referred to as a gate region, transistor gate, or transistor gate area.

[0079] refer to Figure 10A and 10B Insulating material 68 is formed within the opening 62 of slit 46. Insulating material 68 is located above the upper surface 69 of word line 18. Insulating material 62 may include any suitable composition; and in some embodiments, may include, substantially consist of, or consist of silicon dioxide. Insulating material 68 may include the same composition as insulating material 58 (as shown), or may include a different composition relative to insulating material 58. In some embodiments, insulating material 68 may be referred to as a second insulating material to distinguish it from the first insulating material 58. In some embodiments, assembly 10 may include insulating material 60 in addition to insulating materials 58 and 68. Figure 8D In such embodiments, insulating materials 58, 68, and 60 may be referred to as first insulating material, second insulating material, and third insulating material to distinguish them from each other.

[0080] refer to Figure 11A and11B The insulating material 68 is removed from above materials 38 and 34 using a planarization process (e.g., CMP); and a patterned material 70 is formed over the areas of the insulating material 68 and materials 38 and 34. The patterned material 70 may include any suitable composition; and in some embodiments, it may include a combination of silicon and carbon (e.g., silicon carbide), and may be the same composition as material 34. Material 70 can be patterned using any suitable process, including a so-called "pitch doubling" process.

[0081] The patterned material 70 has an opening 72 extending therefrom, wherein such opening is aligned with the digital line 16.

[0082] The opening 72 extends into the insulating material 68.

[0083] refer to Figure 12A and 12B Conductive material 74 is formed within opening 72. Conductive material 74 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 74 may include one or more metals (e.g., titanium, tungsten, etc.) and / or one or more metal-containing compositions (titanium nitride, tungsten nitride, titanium silicide, tungsten silicide, etc.).

[0084] In some embodiments, conductive material 74 may be provided to overfill opening 72, and excess material 74 (together with material 70) may be removed by a planarization process. Planarized surface 73 extends across materials 34, 38, and 74.

[0085] Figure 12A and 12B The conductive material 74 is patterned into conductive interconnects 76.

[0086] In some embodiments, the slit 46 may be considered to have along... Figure 12A The first dimension D of the cross-section, and the conductive interconnect 76 can be considered to have a second dimension along the cross-section; wherein the second dimension is the same as the first dimension.

[0087] The pillar 20 can be considered to be incorporated into the transistor 78. Each of the transistors has a lower source / drain region 56 electrically coupled to the digital line 16 and an upper source / drain region 64 electrically coupled to the conductive interconnect 76. The transistor has a conductive gate 80 between vertically extending sections 50 and 52 of the pillar 20. The gate 80 is operatively adjacent to the channel region 66 such that the gate can be used to apply an electric field over the adjacent (associated) channel region to couple the source / drain regions 56 and 64 to each other through the channel region. The gate 80 is along the word line 18, and the electric field applied by the gate 80 can be controlled by the operation of the word line 18.

[0088] In some embodiments, the insulating material 58 between the gate 80 and the channel region 66 may include a ferroelectric material, and therefore the transistor 78 may be a ferroelectric transistor that can be used as a memory cell within a memory array. In other embodiments, the insulating material 58 between the gate 80 and the channel region 66 may include a non-ferroelectric material, and the transistor may be a field-effect transistor (FET) used as an access device within a memory array. In such embodiments, the memory element may be electrically coupled to the source / drain region 64 via the interconnect 76.

[0089] Figure 13 A three-dimensional view of a region of the example memory array 14 is shown, along with interconnects 76 electrically coupled to memory element 82. Memory element 82 can be any suitable device having at least two detectable states; and in some embodiments, it can be, for example, a capacitor, a resistive memory device, a conductive bridging device, a phase-change memory (PCM) device, a programmable metallization cell (PMC), etc.

[0090] Figure 14 illustrate Figure 13 The memory array 14 contains a region and individual transistors 78. These transistors are incorporated as access transistors into memory cells 84. Each memory cell 84 has a storage element 82 configured as a capacitor. The capacitor 82 has an electrode 83 electrically coupled to an interconnect 76 and another electrode 85 electrically coupled to a reference voltage 87. The reference voltage 87 can be any suitable voltage, including, for example, ground, VCC / 2, etc.

[0091] The capacitor 82 also includes an insulating material 89 between electrodes 83 and 85. The insulating material 89 may be a ferroelectric material (e.g., may include a ferroelectric composition described above as suitable for use in material 58) and may be used in a ferroelectric capacitor. Alternatively, the insulating material 89 may consist of only one or more non-ferroelectric compositions (e.g., silicon dioxide).

[0092] Figure 14The view shows the interconnect 76 located directly above the digital line 16. In the illustrated embodiment, the interconnect 76 is configured as a plate, and specifically as a rectangular plate. A portion 86 of the rectangular plate is located between the protrusions 50 and 52 of the semiconductor pillar 20, while another portion 88 is located above the protrusions 50 and 52 of the semiconductor pillar 20.

[0093] Figure 14A The display is similar to Figure 14 The transistor 78, but the above reference Figure 8D The described insulating material 60 is disposed below the letter line 18.

[0094] With regard to the transistor 78 described above being used as an access transistor for a memory array, such a memory array can have any suitable configuration. Figure 15 The area shown is an example memory array 14 configured as a DRAM array utilizing single-transistor single-capacitor (1T-1C) memory cells 84. Memory array 14 includes word lines (WL1-WL4) extending along a first direction (row direction) of the memory array and digital lines (DL1-DL4) extending along a second direction (column direction) of the memory array. Each memory cell 84 is uniquely addressed by a combination of one word line and one digital line.

[0095] In some embodiments, the memory array (e.g., 14) may be located within a memory layer (i.e., a memory stack), which is situated within a vertical stacking arrangement of layers (or stacks). The vertical stacking arrangement may be referred to as a multilayer assembly. Figure 16 This illustration shows a portion of an example multilayer assembly 200, which includes a vertically stacked arrangement of layers 202, 204, and 206. The vertical stacking arrangement may extend upwards to include additional layers. Layers 202, 204, and 206 can be considered as instances of layers stacked one on top of another. The layers may be located within different semiconductor dies, or at least two of the layers may be located within the same semiconductor die.

[0096] The bottom layer 202 may include a control circuit system and / or a sensing circuit system 208 (e.g., may include a driver, a sensing amplifier, etc.); and in some applications may include a CMOS circuit system. The upper layers 204 and 206 may include memory arrays, such as the memory array 14 described above; wherein an example memory array is shown as “memory” 210 within layer 204.

[0097] Circuitry from an upper layer can be electrically connected to circuitry from a lower layer via electrical interconnects. Example electrical interconnect 212 is shown to electrically couple memory circuitry 210 from layer 204 to circuitry 208 from layer 202. In some embodiments, interconnect 212 can connect digital lines from memory circuitry 210 to sense amplifiers of circuitry 208; can connect word lines, multiplexed lines, and / or board lines of memory circuitry 210 to drivers of circuitry 208; etc.

[0098] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate) and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layer, multi-chip modules. Electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0099] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including (e.g.) atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0100] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonyms in this disclosure. The use of the term “dielectric” in some instances and the term “insulating” (or “electrically insulating”) in others is a linguistic variation provided within this disclosure to simplify the premises within the appended claims and is not intended to indicate any significant chemical or electrical differences.

[0101] The terms "electrical connection" and "electrical coupling" may be used in this disclosure. These terms are considered synonyms. Using one term in some cases and another in others provides linguistic variation within this disclosure to simplify the presuppositions of the appended claims.

[0102] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between various features, whether the structure is in or rotated relative to the specific orientation of the drawings.

[0103] To simplify the illustrations, unless otherwise indicated, the accompanying cross-sectional views show only features within the plane of the cross-section and do not show the material behind the plane of the cross-section.

[0104] When a structure is referred to above as being "on," "adjacent to," or "against" another structure, it may be directly on the other structure or there may be an intermediate structure. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there is no intermediate structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate upright alignment.

[0105] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure typically extends upward from the underlying base (e.g., a substrate). A vertically extending structure may extend substantially orthogonally relative to the upper surface of the base, or it may not extend at all.

[0106] Some embodiments include an integrated assembly having a semiconductor material pillar. The pillar has a base region and is branched into two segments extending upward from the base region. The two segments are a first segment and a second segment, horizontally spaced apart from each other by an intermediate region. A conductive gate is located within the intermediate region. A first source / drain region is located within the base region, a second source / drain region is located within the first and second segments, and a channel region is located within the first and second segments. The channel region is adjacent to the conductive gate and vertically positioned between the first and second source / drain regions.

[0107] Some embodiments include a memory array having digital lines extending horizontally along a first direction. Semiconductor pillars extend upward from the digital lines. Word lines pass through a central region of the pillars. The word lines extend horizontally along a second direction intersecting the first direction. Each of the word lines has a pair of opposing sidewall surfaces extending between a top surface and a bottom surface. The semiconductor material of the pillar extends along two of the opposing sidewall surfaces. A first source / drain region is located within the pillar and electrically coupled to the digital lines. A second source / drain region is located within the pillar and vertically offset from the first source / drain region. A channel region is located within the pillar, adjacent to the word lines, and vertically disposed between the first and second source / drain regions. A memory element is electrically coupled to the second source / drain region.

[0108] Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include semiconductor pillars extending upward from digital lines. The digital lines extend along a first direction. Slits are patterned to partially extend into the pillars. Each pillar has associated segments patterned in the slits and is configured to have a base region and a pair of segments extending upward from the base region. The pair of segments are spaced apart from each other by intermediate gaps corresponding to the associated segments in the slits. A first insulating material is formed along the sidewalls of the slits. Conductive word lines are formed within the slits and adjacent to the first insulating material. The conductive word lines extend along a second direction intersecting the first direction. A first source / drain region is formed within the base region of the pillar. A second source / drain region is formed within a segment of the pillar and is perpendicularly spaced from the first source / drain region by a channel region. A second insulating material is formed within the slits and above the word lines. Conductive interconnects are formed within the slits and above the second insulating material.

[0109] As per the regulations, the subject matter disclosed herein has been described in a more specific or less specific manner regarding structural and methodological features. However, it should be understood that since the methods disclosed herein include exemplary embodiments, the claims are not limited to the specific features shown and described. Therefore, the claims are provided with full scope by literal wording and are to be properly interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: Semiconductor material pillars; The column has a base region extending through the insulating material and forked into two sections, the two sections extending upward from the base region; the two sections are a first section and a second section, and are horizontally separated from each other by a middle region, the first section and the second section each including an inner sidewall and an opposite outer sidewall along the middle region, the insulating material extending continuously along the base region and the respective outer sidewalls of the first section and the second section; A conductive gate located within the intermediate region; and A first source / drain region is located within the base region; a second source / drain region is located within the first segment and the second segment; and a channel region is located within the first segment and the second segment; the channel region is adjacent to the conductive gate and is vertically disposed between the first source / drain region and the second source / drain region.

2. The integrated assembly of claim 1, wherein the semiconductor material comprises silicon.

3. The integrated assembly according to claim 1, wherein the integrated assembly includes a digital line located below the base region and electrically coupled to the first source / drain region, and the integrated assembly includes a memory element electrically coupled to the second source / drain region.

4. The integrated assembly of claim 1, wherein the insulating material is a first insulating material, wherein the conductive gate includes a top surface, a bottom surface, and a sidewall surface extending between the top surface and the bottom surface; and the integrated assembly includes a second insulating material along the sidewall surface of the conductive gate.

5. The integrated assembly according to claim 4, wherein the second insulating material comprises a ferroelectric material.

6. The integrated assembly according to claim 4, wherein the second insulating material does not include ferroelectric materials.

7. The integrated assembly of claim 4, wherein the insulating material further extends along the top surface of the conductive gate.

8. The integrated assembly of claim 4, wherein a third insulating material having a composition different from the second insulating material runs along the top surface of the conductive gate.

9. The integrated assembly of claim 4, wherein the second insulating material further extends along the bottom surface of the conductive gate.

10. The integrated assembly of claim 4, wherein the insulating material is a first insulating material, and wherein a second insulating material having a composition different from the first insulating material is present along the bottom surface of the conductive gate.

11. The integrated assembly of claim 1, wherein the conductive gate includes a top surface; and wherein a conductive interconnect is located above the top surface and spaced apart from the top surface by an intermediate dielectric material; and wherein at least a portion of the conductive interconnect is located between the first segment and the second segment.

12. The integrated assembly of claim 11, comprising a storage element electrically coupled to the second source / drain region via the conductive interconnect.

13. The integrated assembly of claim 12, wherein the storage element is a capacitor.

14. The integrated assembly of claim 13, wherein the capacitor comprises a ferroelectric insulating material.

15. The integrated assembly of claim 13, wherein the capacitor does not include ferroelectric insulating material.

16. A memory array comprising: The digital line extends horizontally along the first direction; Semiconductor material pillars extending upward from the digital lines; The letter line passes through the central area of ​​the column; The letter lines extend horizontally along a second direction intersecting the first direction; each of the letter lines has a pair of opposing sidewall surfaces extending between a top surface and a bottom surface; The semiconductor material of the column extends along two of the opposing sidewall surfaces. The first source / drain region is located within the pillar and electrically coupled to the digital line; The second source / drain region is located within the pillar and is offset perpendicularly from the first source / drain region; The channel region is located inside the column, adjacent to the word line, and is vertically positioned between the first source / drain region and the second source / drain region; and A storage element that is electrically coupled to the second source / drain region.

17. The memory array of claim 16, wherein the memory element is a capacitor.

18. The memory array of claim 16, wherein it is located within a layer of a multilayer assembly.

19. The memory array of claim 16, wherein each of the pillars includes a base region and a pair of protrusions extending upward from the base region; the word line passes between the protrusions.

20. The memory array of claim 19, wherein the second source / drain region and the channel region are located within the protrusion.

21. The memory array of claim 19, wherein conductive interconnects are located above the word lines and between the protrusions; and wherein the memory elements are electrically coupled to the second source / drain region via the conductive interconnects.

22. The memory array of claim 21, wherein the conductive interconnect comprises a metal.

23. The memory array of claim 21, wherein the conductive interconnect is located directly above the digital line.

24. The memory array of claim 21, wherein the conductive interconnects are spaced apart from the word lines by one or more insulating materials.

25. The memory array of claim 16, further comprising a gate dielectric material located between the word line and the channel region.

26. The memory array of claim 25, wherein the gate dielectric material is located below the word line.

27. The memory array of claim 25, wherein the gate dielectric material is not located below the word line.

28. The memory array of claim 25, wherein the gate dielectric material is located above the word line.

29. The memory array of claim 25, wherein the gate dielectric material is not located above the word line.

30. The memory array of claim 16, wherein the ends of the word lines are coupled to a driver circuitry via connections at the ends of the word lines; and wherein adjacent word lines space the connections only along the column axis.

31. The memory array of claim 16, wherein the ends of the word lines are coupled to a driver circuitry via connections at the ends of the word lines; and wherein adjacent word lines offset the connections relative to each other along the row axis.

32. The memory array of claim 16, wherein the ends of the word lines are coupled to a driver circuitry via connections at the ends of the word lines; and wherein adjacent word lines position the connections at opposite ends relative to each other.

33. A method for forming an integrated assembly, comprising: The arrangement includes semiconductor pillars extending upward from digital lines; the digital lines extend along a first direction; Patterned slits extend partially into the columns; each of the columns is patterned with an associated element of the slit and is configured to have a base region and a pair of segments extending upward from the base region, wherein the segments in the pair are spaced apart from each other by an intermediate gap corresponding to the associated element of the slit; A first insulating material is formed along the sidewall of the slit; Conductive character lines are formed adjacent to the first insulating material within the slit, and the conductive character lines extend along a second direction intersecting the first direction; A first source / drain region is formed in the base region of the column; A second source / drain region is formed within the section of the column, and the second source / drain region is perpendicularly spaced from the first source / drain region through a channel region; A second insulating material is formed within the slit and above the letter line; and Conductive interconnects are formed within the slit and above the second insulating material.

34. The method of claim 33, wherein the first insulating material and the second insulating material are the same composition as each other.

35. The method of claim 33, wherein the first insulating material and the second insulating material are compositions that are different from each other.

36. The method of claim 33, wherein the first insulating material is formed along the bottom of the slit.

37. The method of claim 33, wherein the first insulating material is deposited.

38. The method of claim 33, wherein the first insulating material is oxidatively grown from the semiconductor material of the semiconductor pillar.

39. The method of claim 33, further comprising forming a spacer of a third insulating material along the bottom of the slit prior to forming the conductive letter line.

40. The method of claim 39, wherein the third insulating material is a composition different from the first insulating material.

41. The method of claim 39, wherein the third insulating material is the same composition as the first insulating material.

42. The method of claim 33, further comprising forming a storage element electrically coupled to the conductive interconnect.

43. The method of claim 33, wherein forming the slit comprises: A block is formed to include the semiconductor pillar and to include one or more materials surrounding the semiconductor pillar; An opening is formed to extend into the block, wherein the opening is located above the semiconductor pillar and exposes the top surface of the semiconductor pillar; A patterned material is formed to conformally extend over the block and into the opening, the upper morphology of the patterned material having a valley above the semiconductor pillar; The valley is extended into the semiconductor pillar to form an opening in the semiconductor pillar; and The slit is formed to contain the opening.

44. The method of claim 33, wherein each of the slits has a first dimension along the cross-section; and wherein each of the conductive interconnects has a second dimension along the cross-section, wherein the second dimension is the same as the first dimension.

Images