Task scheduling method, device and computer system

Abstract

The application relates to a task scheduling method, device and computer system, and relates to the technical field of computers.The method is applied to a computer system with multiple processor cores, and the method comprises the following steps: obtaining a target task, wherein the target task is a task that needs to be processed by a processor core in a turbo state; determining a target core from the multiple processor cores according to failure information of the multiple processor cores, wherein the failure information of any processor core is used for indicating the service life of the processor core in the turbo state; and distributing the target task to the target core, so that the target core processes the target task in the turbo state.Thus, by scheduling tasks among the multiple processor cores, the service life of the device can be guaranteed while the running frequency of a high-load task is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and particularly relates to a task scheduling method and device and a computer system. BACKGROUND

[0002] A central processing unit (CPU) is the operation and control core of a computer, and the operation of all software layers in a computer system will ultimately be mapped to the operation of the CPU through an instruction set. In order to meet the upper-layer work requirements of an operating system (OS), modern processors further introduce functions such as parallelization and multi-core (i.e., two or more cores integrated in one CPU), which constantly promote the development of upper-layer information systems. With the continuous emergence and increasing complexity of various application programs (applications), the industry has proposed turbo technology to improve CPU performance to meet the application requirements of high workloads.

[0003] Turbo Mode, as the name implies, is an acceleration mode that intelligently completely closes some unused cores by analyzing the current CPU load, leaves energy to the cores that are being used, and makes them run at a higher frequency to further improve performance; conversely, when multiple cores are needed, the corresponding cores are dynamically started, and the frequency is intelligently adjusted. In this way, without affecting the thermal design power (TDP) of the CPU, the core operating frequency can be adjusted to be higher. When a running program is started, the processor will automatically accelerate to the appropriate frequency, and the original running speed will be increased by 10% to 20% to ensure smooth program running; when the processor processes complex application programs, it can automatically increase the running frequency to speed up and easily handle multi-task processing with higher performance requirements; when the work task is switched, if only the memory and the hard disk are performing the main work, the processor will immediately enter the power saving state. In this way, not only is the effective use of energy guaranteed, but the program speed is also greatly improved. By intelligently accelerating the processor speed, the performance is maximized according to the application requirements, the running frequency of high-load tasks is increased by up to 20% to obtain the best performance, that is, the performance is maximized to meet the application requirements of high workloads: by allocating multiple threads to process the requirements of artificial intelligence, physical simulation, and rendering, a more smooth and realistic gaming experience can be provided to users.

[0004] Currently, in a computer system with a multi-core processor, an OS kernel adopts a random scheduling mechanism to randomly schedule a turbo task to run on a certain core, and there is a case that multiple turbo tasks are assigned to the same core, which greatly increases the usage frequency of the core, and accordingly, the service life of the core is shortened, thereby causing uneven wear of multiple cores of the processor, which directly affects the service life of the processor. In order to guarantee the service life of the processor, the actual use of the processor needs to lower the highest running frequency, which will cause the performance of the processor to decline.

[0005] Therefore, how to guarantee the service life of the device while improving the running frequency for high-load tasks is still a problem to be solved. SUMMARY

[0006] Embodiments of the present application provide a task scheduling method, device and computer system, which helps to guarantee the service life of the device while improving the running frequency for high-load tasks.

[0007] In a first aspect, embodiments of the present application provide a task scheduling method, which can be applied to a computer system with multiple processor cores. The method can include: obtaining a target task, wherein the target task is a task that needs to be processed by a processor core in a turbo state; determining a target core from the multiple processor cores according to failure information of the multiple processor cores; wherein the failure information of any processor core indicates the service life of the processor core in the turbo state; and assigning the target task to the target core, so that the target core processes the target task in the turbo state.

[0008] Through the above design, in a computer system with multiple processor cores, the target task that needs to be processed by a processor core in a turbo state can be scheduled according to the failure information of the processor core, so as to balance the usage frequency of multiple processor cores as much as possible, to achieve wear balancing between multiple processor cores, and to guarantee the service life of the device (including a processor to which the processor core belongs and / or a chip corresponding to the processor) while improving the running frequency for high-load tasks.

[0009] In a possible design, the target core is determined from the failure information of the plurality of processor cores, including: obtaining the failure information of the plurality of processor cores; and selecting, from the plurality of processor cores, the target core whose failure information satisfies a first scheduling condition according to the failure information of the plurality of processor cores. The failure information of any processor core includes a failure rate of the processor core; and the first scheduling condition includes: the smallest failure rate; and / or, the failure rate is not greater than a first value, where the first value is an average of the failure rates of the plurality of processor cores.

[0010] With the above design, when scheduling a target task, a target processor core (referred to as a target core for short) is selected according to a first scheduling condition, so as to balance the usage frequencies of the plurality of processor cores as much as possible, and to balance the wear and tear among the plurality of processor cores.

[0011] In a possible design, the computer system includes one processor, and the plurality of processor cores are located in the processor. The obtaining the target task includes: obtaining a to-be-processed task; and determining the to-be-processed task as the target task when it is determined that at least one processor core in the plurality of processor cores has a load exceeding a first load threshold.

[0012] With the above design, the computer system to which the scheme is applicable can be a system including only one multi-core processor. By scheduling tasks among the plurality of processor cores of the multi-core processor, the usage frequencies of the plurality of processor cores are balanced as much as possible, the wear and tear among the plurality of processor cores is balanced, the running frequency of a high-load task is improved, and the service life of a device is guaranteed.

[0013] In a possible design, the computer system includes a plurality of processors, and at least one processor core in the plurality of processor cores is located in a first processor in the plurality of processors. The obtaining the target task includes: obtaining a to-be-processed task; and determining the to-be-processed task as the target task when it is determined that the to-be-processed task is to be allocated to the first processor, and a load of the first processor exceeds a second load threshold.

[0014] Through the above design, the computer system to which the scheme is applicable can be a system comprising multiple processors, any processor can comprise at least one processor core, and the computer system can implement task scheduling across processors. In this way, by scheduling tasks among multiple processors, wear leveling among multiple processors is achieved as much as possible by balancing the usage frequency of multiple processors, while the service life of the device is guaranteed while the running frequency of the high-load task is improved. It can be understood that in a computer system having multiple processors, multiple processors can have different specification parameters and capabilities, and accordingly, the reference for the computer system to implement task scheduling across processors can be different, that is, scheduling can be performed according to the capabilities of different processors, which is not limited in the present application.

[0015] In a possible design, the target core is determined from the multiple processor cores according to the failure information of the multiple processor cores, including: obtaining the failure information of the multiple processors, wherein the failure information of any processor is used to indicate the service life of the processor in a turbo state; selecting, according to the failure information of the multiple processors, the first processor whose failure information satisfies a second scheduling condition from the multiple processors, wherein the failure information of any processor comprises a failure rate of the processor, and the second scheduling condition comprises: the smallest failure rate, and / or the failure rate is not greater than a second value, wherein the second value is an average value of the failure rates of the multiple processors; determining, from the multiple processor cores, at least one alternative processor core located at the first processor; and determining the target core from the at least one alternative processor core according to the failure information of the at least one alternative processor core.

[0016] Through the above design, in a computer system comprising multiple processors, when scheduling a target task, a processor can be selected according to a set second scheduling condition, and then each processor core of the processor is used as an alternative processor core, and then a target core is selected from the alternative processor core. In this way, by balancing the usage frequency of multiple processors, wear leveling among multiple processors is achieved as much as possible, while the service life of the device is guaranteed while the running frequency of the high-load task is improved.

[0017] In a possible design, the failure information of the multiple processor cores is obtained, including: determining the failure information of a first processor core from the multiple processor cores according to saved state information of the first processor core, wherein the first processor core is any one of the multiple processor cores, and the state information of the first processor core comprises at least one of the following information of the first processor core running in a turbo state: running frequency information, running voltage information, running temperature information, and running time length information.

[0018] Through the above design, since the processor core runs in the turbo state to execute the target task, the heat, power consumption and the like of the processor core will affect the service life of the processor core. By determining the failure information of the processor core according to the state information of the processor core in the running process, the failure information that can more accurately represent the service life of the processor core is obtained, and then the wear balancing between multiple processor cores is realized as much as possible when scheduling tasks.

[0019] In a possible design, in the case that the first processor core has multiple working gears, the running frequency information includes running frequencies corresponding to the multiple working gears; the running voltage information includes running voltages corresponding to the multiple working gears; the running temperature information includes running temperatures corresponding to the multiple working gears; and the running time length includes running time lengths corresponding to the multiple working gears. The determining, according to the saved state information of the first processor core, of the failure information of the first processor core includes: performing normalization processing on the running frequency, the running voltage, the running temperature and the running time length corresponding to each working gear to obtain normalized data corresponding to each working gear; and determining the failure information of the first processor core according to the normalized data corresponding to each working gear.

[0020] Through the above design, the failure information of the first processor core is obtained by performing normalization processing on the state information corresponding to multiple working gears of the first processor core.

[0021] In a possible design, the method further includes: saving the state information of the target core when the target core processes the target task.

[0022] Through the above design, the state information of the target core is saved during the process of the target core processing the target task, so that the failure information of the target core can be obtained accordingly, and the task scheduling is facilitated. It can be understood that, in the embodiments of the present application, any processor core of the computer system with multiple processor cores can be the target core, and accordingly, the state information of the processor core can be saved during the process of any processor core running in the turbo state to execute the target task.

[0023] In a second aspect, the embodiments of the present application provide a task scheduling apparatus, which can be applied to a computer system with multiple processor cores. The task scheduling apparatus can specifically realize the functions of the behaviors of the task scheduling method in the first aspect. The task scheduling apparatus can be a hardware or software unit in the computer system, and can include at least one module for implementing the task scheduling method provided in the first aspect.

[0024] In a third aspect, an embodiment of the present application provides a task scheduling apparatus, comprising at least one processor coupled with at least one memory, wherein the at least one processor is configured to execute computer programs or instructions stored in the at least one memory, so that the apparatus performs the method in any possible design of the first aspect. Optionally, the apparatus further comprises a communication interface, and the processor is coupled with the communication interface. The communication interface can be a transceiver or an input / output interface; when the apparatus is a chip included in a network device, the communication interface can be an input / output interface of the chip. Optionally, the transceiver can be a transceiver circuit, and the input / output interface can be an input / output circuit.

[0025] In a fourth aspect, an embodiment of the present application provides a computing device, comprising a processor and a memory, wherein the processor comprises a plurality of processor cores, the memory is configured to store failure information of the plurality of processor cores, and the processor is configured to perform the task scheduling method in any one of the first aspect.

[0026] In a fifth aspect, an embodiment of the present application provides a computer system, which can comprise a scheduler, a power consumption controller and a plurality of processor cores, wherein the scheduler is configured to perform the method in the first aspect according to the failure information of the plurality of processor cores obtained from the power consumption controller.

[0027] In a sixth aspect, an embodiment of the present application provides a readable storage medium for storing instructions, which, when executed, cause the method in the first aspect to be performed.

[0028] In a seventh aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, cause the computer to perform the method in the first aspect.

[0029] In an eighth aspect, an embodiment of the present application provides a chip system, comprising a processor coupled with a memory, wherein the memory is configured to store programs or instructions, and the chip system can further comprise an interface circuit configured to receive code instructions and transmit the code instructions to the processor; when the programs or instructions are executed by the processor, the chip system performs the method in any possible design of the first aspect.

[0030] Optionally, the processor in the chip system can be one or more. The processor can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented by software, the processor can be a general-purpose processor, which is configured to read software code stored in the memory.

[0031] Optionally, the memory in the chip system can also be one or more. The memory can be integrated with the processor, or can be arranged separately from the processor, and the application does not limit. For example, the memory can be a non-transient processor, such as a read-only memory (ROM), which can be integrated on the same chip as the processor, or can be arranged separately on different chips, and the application does not limit the type of memory and the arrangement of the memory and the processor.

[0032] On the basis of the implementation provided by the above aspects, the application can be further combined to provide more implementations. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 Schematic diagram of a computer system applicable to the embodiments of the application;

[0034] Figure 2a Schematic diagram of a computer system provided for an example of the application;

[0035] Figure 2b Schematic diagram of a computer system provided for another example of the application;

[0036] Figure 3 Flowchart of a task scheduling method provided by the embodiments of the application;

[0037] Figure 4 Structural schematic diagram of a task scheduling device provided by the embodiments of the application;

[0038] Figure 5 Schematic diagram of a computing device provided by the embodiments of the application. DETAILED DESCRIPTION

[0039] At present, the turbo state of a computer system is realized by a basic input output system (BIOS) / load utilization rate. If the turbo mode is enabled in the BIOS, when the load utilization rate of a single processor core is high, the turbo state is entered, so that the processor core runs at a higher frequency, to improve the performance of the single processor core. Since the processor core runs at a higher frequency in the turbo state, the power consumption is increased, and the wear and tear degree of the processor core is further aggravated. If the usage frequency of a certain processor core in the computer system is higher than that of other processor cores, the wear and tear of the multiple processor cores of the computer system is unbalanced, which will directly affect the service life of a device (such as a processor or a chip) configured with the multiple processor cores.

[0040] To solve the problems mentioned in the background, the embodiments of the present application provide a task scheduling method and device and a computer system, which help to improve the running frequency of high-load tasks while guaranteeing the service life of the device. The method and device are based on the same technical concept, and since the principles of the method and device for solving problems are similar, the implementation of the device and the method can be mutually referred to, and the repeated parts will not be described again.

[0041] In the embodiments of the present application, in a computer system having a plurality of processor cores, for a target task that needs to be processed by a processor core in a turbo state, a target core is determined from the plurality of processor cores according to failure information of the plurality of processor cores, and the target task that needs to be processed by a processor core in a turbo state is assigned to the target core, so that the target core processes the target task in a turbo state. Through this scheme, the computer system can schedule the target task according to the failure information of the processor cores, to balance the usage frequency of the plurality of processor cores, and as much as possible to achieve wear leveling between the plurality of processor cores, so as to balance the service life of all processor cores while improving the running frequency of high-load tasks, thereby guaranteeing the service life of the entire computer system.

[0042] In the following, some terms in the present application are explained and described to facilitate understanding by those skilled in the art.

[0043] (1) A computer system consists of hardware (sub) system and software (sub) system. Among them, the hardware (sub) system includes various physical components composed of electricity, magnetism, light, and mechanical principles, which is an organic combination of the entity on which the system works; the software (sub) system includes various programs and files, which are used to command the whole system to work according to the specified requirements. With the development of computer technology, modern computer systems range from microcomputers and personal computers to large computers and their networks, with various forms and characteristics, and have been widely used in scientific computing, transaction processing and process control, and are increasingly penetrating into various fields of society, having a profound impact on social progress.

[0044] In an implementation manner, the computer system in the embodiments of the present application can be a computer system in a terminal device, which is a device that provides service to users and has voice or data communication function. The terminal device can also be called terminal equipment, user equipment (UE), mobile station (MS), mobile terminal (MT), etc., and the terminal device can also be a chip. In subsequent embodiments and descriptions of the present application, the terminal equipment is taken as an example for specific description.

[0045] For example, the terminal device can be a handheld device, a vehicle-mounted device, etc. with wireless connection function. Currently, some examples of terminal devices are: mobile phone, tablet computer, notebook computer, palm computer, mobile internet device (MID), point of sale (POS), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, various types of smart meters (smart water meter, smart electricity meter, smart gas meter), etc.

[0046] In another implementation, the computer system in the embodiments of the present application can be a server, which is a device providing data connection service. Since the server can respond to the service request of the terminal device and process, in general, the server should have the ability to undertake services and guarantee services. In the present application, the server can be a server located in a data network (DN), such as a general server, a server in a cloud platform; or a multi-access edge computing (MEC) server located in a core network, etc.

[0047] (2) Operating system (OS): is the most basic system software running on the computer system, such as windows system, Android system, IOS system, windows server system, Netware system, Unix system, Linux system. Those skilled in the art can understand that similar algorithms can also be used in other operating systems, and the present application does not limit this.

[0048] (3) Kernel: is the core of an operating system, is the first layer of software expansion based on hardware, provides the most basic functions of the operating system, is the basis of the operating system, it is responsible for managing the processes, memory, drivers, files and network systems of the system, determines the performance and stability of the system.

[0049] (4) Failure rate, refers to the probability of failure of a product that has not failed at a certain time, after the time, the probability of failure per unit time, can be used to represent the life of the product. Failure rate is generally denoted as λ, which is also a function of time t, so it is also denoted as λ(t), which is called failure rate function, sometimes also called failure rate function or risk function.

[0050] In the embodiments of the present application, the meaning of failure rate is different in the case of different forms of products. For example, if the product refers to a processor core, the failure rate of the processor core refers to the probability of failure of the processor core per unit time after a certain time; if the product refers to a processor, the failure rate of the processor refers to the probability of failure of the processor per unit time after a certain time; if the product refers to a chip with one or more processors, the failure rate of the chip refers to the probability of failure of the chip per unit time after a certain time. The failure rates of the processor core, the processor, the chip, etc. can be obtained by recording the corresponding running state information during use and calculating according to the running state information and related algorithms. The present application does not limit the running state information and related algorithms.

[0051] It should be understood that the failure rate is only an example of the parameter used to represent the life of the product in the embodiments of the present application, but not any limitation. In other embodiments, other parameters and corresponding parameter values can also be used to represent the life of the product, and the present application does not make any limitation.

[0052] (5) Multiple, refers to two or more.

[0053] (6) At least one, refers to one or more.

[0054] (7) "And / or", describes the association between the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases: A alone, A and B together, and B alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0055] In addition, it should be understood that in the description of the present application, the words "first", "second", etc. are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

[0056] The task scheduling scheme of the present application will be described in detail below in combination with the drawings and embodiments.

[0057] Figure 1 A schematic diagram of a computer system suitable for use according to the embodiments of the present application. Referring to Figure 1 As shown, the computer system can include a scheduler, a power consumption controller and a plurality of processor cores.

[0058] The scheduler is a unit or module with a task scheduling function in the computer system. The scheduler can run on a processor of the computer system, and can allocate a target task to be processed in the computer system to a processor core in the processor for processing according to the task scheduling method of the embodiments of the present application.

[0059] The processor core, which can also be referred to as a processor kernel, can be used to implement computing, accept / storage commands, process data, and the like in the computer system. The scheduler can select a target core for a target task from among multiple processor cores and allocate the target task to the target core. After obtaining the target task allocated by the scheduler, the target core can start running and process the target task.

[0060] The power consumption controller can be a unit or module in the computer system for power consumption control, energy saving feature control, and the like. The power consumption controller can monitor the running state of multiple processor cores. During the running of a processor core, the power consumption controller can record and save relevant state information of the processor core, such as running frequency information, running temperature information, running voltage information, and running time length information, and the like. The state information of any processor core can be processed by a relevant algorithm to obtain the failure information of the processor core, which can be used to represent the service life of the processor core. The power consumption controller can interact with the scheduler and provide the obtained failure information of multiple processor cores to the scheduler.

[0061] The failure information of multiple processor cores can be one of the bases for the scheduler to perform task scheduling. When performing task scheduling, the scheduler can determine a target core for a target task in combination with the failure information of any processor core in multiple processor cores, so as to balance the use frequency of multiple processor cores through task scheduling, thereby as much as possible to achieve wear leveling among multiple processor cores, so as to improve the running frequency for high-load tasks while guaranteeing the service life of devices (including a processor to which multiple processor cores belong and / or a chip corresponding to the processor, and the like).

[0062] It can be understood that in the embodiments of the present application, the scheduler can use the failure information of multiple processor cores as one of the bases for task scheduling, but not as the only basis. In actual applications, if multiple scheduling strategies are configured in the computer system, for example, different scheduling strategies can be configured with corresponding priority or weight factor based on the application scenario, business demand, and the like of the computer system, the target core for a target task can be determined by comprehensively considering multiple scheduling strategies and their respective priority or weight factor. Under the same conditions, the target core can also be determined based on the task scheduling strategy of the present application according to the failure information of multiple processor cores, and the present application does not limit this.

[0063] In this embodiment, the target task can be any task to be processed in the computer system, or a specific task, such as a task that requires the processor core to process in turbo mode. Since the lifespan of the processor core is significantly reduced when running in turbo mode compared to non-turbo mode, this embodiment uses a task requiring the processor core to process in turbo mode as an example to illustrate the task scheduling scheme. The scheduler can analyze the tasks to be processed in the computer system and the failure information of multiple processor cores to determine and schedule the target task requiring the processor core to process in turbo mode.

[0064] It is understandable that for computer systems with multiple processor cores, while ensuring the performance of the processor cores, the task scheduling method of this application can also be used to schedule tasks that do not require the processor cores to process in turbo mode, thereby reducing the lifespan of related devices. This application does not limit this.

[0065] In the embodiments of this application, the computer system may also include other functional modules, and the computer system and its various functional modules may also have different product forms, which are not limited in this application.

[0066] In one specific implementation, see [reference] Figure 2a As shown, a computer system can contain a processor, multiple processor cores, and a power controller (recorder) located in the processor. The scheduler can be a scheduler in the operating system kernel (OS kernel) running on the processor.

[0067] An application running in the computer system can trigger one or more pending tasks. When the scheduler in the OS kernel obtains any pending task and determines that the pending task is a target task that needs to be processed by a processor core in a turbo state, the scheduler can determine a target core (e.g., corel) for the target task according to the failure information of the plurality of processor cores by using the task scheduling method described in the embodiments of the present application, and assign the target task to corel, so that corel processes the target task in the turbo state. When corel processes the target task in the turbo state, the power consumption controller can record and save the state information of the target core in real time, such as the running frequency information, the running voltage information, the running temperature information, the running time length information, and the like. The power consumption controller can obtain the failure information of corel according to the state information of corel and a related algorithm, and the failure information can be used to represent the service life of the processor core. The power consumption controller can provide the failure information of corel to the scheduler. The scheduler can update the saved failure information of the plurality of processor cores according to the failure information of corel obtained from the power consumption controller, and use the failure information of the plurality of processor cores as one of the bases to schedule the subsequently triggered target task.

[0068] In another specific implementation, as shown in Figure 2b The computer system can include a plurality of processors, each of which can include a power consumption controller and at least one processor core, and the plurality of processor cores of the computer system can include at least one processor core in any of the plurality of processors. The scheduler can be a scheduler in an operating system kernel (OS kernel) running on the plurality of processors. An application running in the computer system can trigger one or more pending tasks, and the scheduler in the OS kernel can first determine a target processor to which the pending task is to be assigned after obtaining the pending task.

[0069] If the scheduler determines to assign the pending task to a first processor (any of the plurality of processors) in the plurality of processors by using a related assignment strategy, the first processor can be used as Figure 2a The processor shown in FIG. 4, refer to Figure 2aThe description states that when it is determined that the task to be processed is a target task that requires a processor core to process in turbo mode, a target core is determined for the target task among at least one processor core of the first processor. If the scheduler determines that the task to be processed should be assigned to the first processor, and determines that the load utilization of the first processor is high, triggering relevant scheduling conditions, then the task to be processed can be determined to be a target task that requires cross-processor scheduling and requires a processor core to process in turbo mode. In this case, based on the task scheduling method of this application, a target processor can be determined among multiple processors, and a target core can be determined for the target task among at least one processor core of the target processor.

[0070] It should be noted that, Figure 2b In this application, the scheduler can use any suitable allocation strategy to determine the first processor to which the task to be processed should be assigned, and this application does not limit the allocation strategy.

[0071] Understandable Figure 1 , Figure 2a , Figure 2b This application provides illustrative examples of the structure of a computer system to which the embodiments of this application apply, and is not intended to limit the scope of the application. In other embodiments, the computer system and its related modules may have different product forms, and this application does not limit these forms. For example, the power controller may be located in the scheduler, interact with multiple processor cores, monitor the operation of multiple processor cores in real time and record their status information, and use relevant algorithms to obtain failure information of multiple processor cores. Alternatively, the power controller may be a module in the computer system independent of the scheduler and processors, which may interact with multiple processor cores, monitor the operation of multiple processor cores in real time and record their status information, use relevant algorithms to obtain failure information of multiple processor cores, and provide the failure information of multiple processor cores to the scheduler.

[0072] The task scheduling method in this application embodiment can be derived from the above. Figure 1 , Figure 2a , Figure 2b The implementation of the computer system and its various functional modules.

[0073] To better understand the technical solution of this application, the following is combined with... Figure 3 The method flowchart shown is for Figure 1 , Figure 2a , Figure 2b The computer system and the specific processes by which its various functional modules are implemented are described in detail. For example... Figure 3 As shown, the task scheduling method may include the following steps:

[0074] S310: The power consumption controller reports the failure information of the plurality of processor cores to the scheduler. The failure information of any processor core indicates the life of the processor core in the turbo state.

[0075] In the embodiments of the present application, when any processor core as a target core is started and runs in the turbo state and processes the target task, the power consumption controller responsible for monitoring the processor core can record and save the state information of the processor core in real time, such as running frequency information, running voltage information, running temperature information, and running time length. The power consumption controller can normalize the state information of the processor core and convert it into the failure information of the processor core. The failure information can be used to indicate the life of the processor core. The power consumption controller can report the failure information of any processor core to the scheduler, so that the scheduler schedules the target task based on the failure information.

[0076] In a specific implementation, any processor core of the computer system can have a plurality of working gears. Accordingly, in the running process of each processor core, the state information recorded and saved by the power consumption controller can include state information corresponding to the plurality of working gears. For example, the running frequency information can include running frequencies corresponding to the plurality of working gears, the running voltage information can include running voltages corresponding to the plurality of working gears, the running temperature information can include running temperatures corresponding to the plurality of working gears, and the running time length information can include running time lengths corresponding to the plurality of working gears. When the power consumption controller normalizes the state information of the processor core, it can normalize the running frequency, running voltage, running temperature, and running time length corresponding to each working gear to obtain normalized data corresponding to each working gear, and then determine the failure information of the processor core according to the normalized data corresponding to each working gear.

[0077] As an example, assume that multiple working gears of a processor core can be: running frequency divided into L gears, running voltage divided into M gears, and running temperature divided into N gears, where L, M, and N are positive numbers. Assume that a processor core core i (i is an integer, used to represent the serial number of the processor core in multiple processor cores of a computer system) is determined as a target core by a scheduler. The core i starts running upon accepting a turbo request initiated by the scheduler, and a power consumption controller can increase the running frequency and the running voltage corresponding to the core i. During the running of the core i in the turbo state, the power consumption controller can record the running frequency, the running voltage, the running temperature corresponding to each working gear, and the running time length of each working gear, and aggregate the records into a state information table corresponding to the core i. The power consumption controller can perform normalization processing based on the state information table corresponding to the core i to obtain normalized data corresponding to each working gear of the core i. The normalized data may, for example, include relevant information capable of reflecting the life consumption of the processor core, such as the running temperature, the running voltage, and the running time length, and is denoted as core i-[Vm, Tn, t], where V represents the running voltage, T represents the running temperature, t represents the running time length, and m and n represent the working gears corresponding to the running voltage and the running temperature, respectively. The power consumption controller can determine the failure information of the core i according to the normalized data corresponding to each working gear of the core i, and report the failure information of the core i to the scheduler.

[0078] It should be noted that in the embodiments of the present application, the power consumption controller can use any suitable normalization processing manner when performing normalization processing on the state information of each working gear, which is not limited in the present application. As an example, the highest running voltage, the highest running temperature, and the corresponding running time length corresponding to each working gear can be used as the normalized data; or any specified running voltage, any specified running temperature, and the corresponding running time length corresponding to each working gear can be used as the normalized data; or the average value of the running voltage, the average value of the running temperature, and the average value of the running time length obtained for each working gear can be used as the normalized data. Moreover, when determining the failure information of the core i according to the normalized data corresponding to each working gear, the normalized data can be converted into reliability data of the core i, i.e., the failure information, based on a set algorithm (such as a formula or a calculation model), and is denoted as core i-Ri, where R is used to represent the failure information.

[0079] It can be understood that only the function of the power consumption controller of reporting the failure information of the processor core to the scheduler is schematically represented in S310, and any limitation on the implementation of the function is not intended. For details, refer to Figure 2a and Figure 2bIn the computer system shown, if the computer system comprises a plurality of processors and each power consumption controller monitors at least one processor core, S310 can be that each power consumption controller reports the failure information of the at least one processor core loaded to the scheduler, which is not described herein again. In addition, the power consumption controller can report the failure information of the plurality of processor cores to the scheduler based on a predetermined time period, or can report the failure information of the plurality of processor cores to the scheduler when a related condition is met (for example, the state of any processor core changes), or can report the failure information of the plurality of processor cores to the scheduler after receiving related indication information from the scheduler, which is not limited in the present application. In addition, the power consumption controller and the scheduler can interact based on any suitable manner, for example, the power consumption controller can report the failure information of each processor core to the scheduler through shared memory, which is not limited in the present application.

[0080] S320: The scheduler acquires a target task, wherein the target task is a task that needs to be processed by a processor core in a turbo state.

[0081] In the embodiments of the present application, the turbo state can be determined by the load utilization rate of at least one processor core or at least one processor.

[0082] In a specific implementation manner, referring to Figure 2a In the computer system shown, after the scheduler acquires the to-be-processed task, when it is determined that there is at least one processor core whose load exceeds the first load threshold in the plurality of processor cores, the scheduler determines that the to-be-processed task is the target task that needs to be processed by a processor core in a turbo state.

[0083] In a specific implementation manner, referring to Figure 2b In the computer system shown, after the scheduler acquires the to-be-processed task, the scheduler can assign the to-be-processed task to a first processor in the plurality of processors according to a related assignment strategy. When the scheduler determines to assign the to-be-processed task to the first processor and the load of the first processor exceeds the second load threshold, the scheduler determines that the to-be-processed task is the target task that needs to be processed by a processor core in a turbo state.

[0084] It can be understood that in the embodiments of the present application, the scheduler can adopt any suitable assignment strategy to assign the to-be-processed task to the first processor in the plurality of processors, which is not limited in the present application. The load threshold that needs to be met to trigger the turbo state for each processor or each processor core can be set according to the application scenario and business requirement of the computer system, and the load threshold corresponding to different processors or different processor cores can be the same or different, which is not limited in the present application.

[0085] S330: The scheduler determines a target core from the multiple processor cores according to the failure information of the multiple processor cores.

[0086] In the embodiments of the present application, the related task scheduling program of the task scheduling strategy can be configured in the scheduler in advance, including the scheduling algorithm and the related scheduling conditions. When the scheduler performs task scheduling, the target core can be selected from the multiple processor cores according to the failure information of the multiple processor cores, which satisfies the corresponding scheduling conditions.

[0087] For example, referring to the computer system shown in Figure 2a In S330, the scheduler can select the target core from the multiple processor cores according to the failure information of the multiple processor cores, which satisfies the first scheduling condition. The failure information of the processor core can be any information used to represent the life of the processor core in the turbo state, for example, the failure rate of the processor core. Correspondingly, the first scheduling condition can be that the failure rate is the smallest, or the failure rate is not greater than a first value, which can be the average value of the failure rates of the multiple processor cores.

[0088] For example, referring to the computer system shown in Figure 2b In S330, the scheduler can obtain the failure information of the multiple processors, wherein the failure information of any processor is used to represent the life of the processor in the turbo state, and the failure information of the processor can be obtained according to the failure information of at least one processor core located in the processor. Then, the first processor is selected from the multiple processors according to the failure information of the multiple processors, which satisfies the second scheduling condition, and at least one alternative processor core located in the first processor is determined from the multiple processor cores, and the target core is determined from the at least one alternative processor core according to the failure information of the at least one alternative processor core. The failure information of the processor can also be any information used to represent the life of the processor in the turbo state, for example, the failure information of the processor. Correspondingly, the second scheduling condition can be that the failure rate is the smallest, or the failure rate is not greater than a second value, which can be the average value of the failure rates of the multiple processors.

[0089] It can be understood that, if the computer system has set the task scheduler to schedule tasks among at least two processor cores, the scheduler can select at least two processor cores meeting the relevant scheduling conditions as target cores when scheduling tasks, and assign threads of the target task to the at least two processor cores respectively, which will not be described herein again. In addition, the failure rate of the processor or the processor core is only one of the bases for the scheduler to schedule tasks, but not any limitation. In other embodiments, the failure information can also include other information in addition to the failure rate. Correspondingly, the scheduler can also include a task scheduling strategy configured in combination with other information, which will not be described herein again.

[0090] S340: The scheduler assigns the target task to the target core, so that the target core processes the target task in the turbo state.

[0091] In the embodiments of the present application, the scheduler can assign the target task to the target core in the form of initiating a turbo request to the target core, and the target core can accept the turbo request initiated by the scheduler and start running. In the process of running of the target core in the turbo state, the power consumption controller raises the running frequency and the running voltage of the target core, and records and saves the state information of the target core, including the running frequency information, the running voltage information, the running temperature information and the running time length information, etc. And based on the recorded and saved state information of the target core, the failure information of the target core is updated, and the updated failure information is reported to the scheduler, so that the scheduler performs task scheduling based on the updated failure information as one of the bases. The recording of the state information and the algorithm can be referred to the related description of S310 above, which will not be described herein again.

[0092] So far, by combining Figure 1 , Figure 2a , Figure 2b , Figure 3 The computer system of the embodiments of the present application and the task scheduling method based on the computer system are introduced. The state information of the processor core in the turbo state is recorded and saved by the power consumption controller, and the failure information of the processor core is obtained by combining the related algorithm and provided to the scheduler. The failure information can be used to represent the life of the processor core in the turbo state. The scheduler can consider the life wear of different processor cores in the turbo state when scheduling tasks, so as to balance the use frequency of multiple processor cores, and as far as possible to realize the wear balance among multiple processor cores, so as to improve the running frequency for high load tasks while guaranteeing the service life of the device.

[0093] As shown in Table 1, based on actual simulation data, for a processor with 40 cores, if the wear leveling of the processor cores is not considered at all, and the scheduling of the turbo task is performed among 10 processor cores, the service life of the processor under the 1.1v-3.6G scenario is about 3.3 years. Correspondingly, if the scheduling strategy of the scheduler does not consider the use of the processor cores in the turbo state, the service life of the chip that can be provided to the user is 3.3 years. If the task scheduling method of the embodiment of the present application is used, and the turbo task is scheduled in combination with the failure information of the processor cores, the service life of the chip can be extended to 13.2 years. Therefore, if the user's requirement for the service life of the chip is 5 years, based on the task scheduling method of the present application, the running voltage and the running frequency of the processor cores can be improved to provide better CPU performance in the case of guaranteeing the basic service life of the chip.

[0094] Table 1

[0095]

[0096] Based on the same technical concept, the embodiment of the present application provides a task scheduling device. The task scheduling device can be applied to a scheduler (or a scheduling program) in a computer system with multiple processor cores, such as the computer system shown in Figure 1 、 Figure 2a 、 Figure 2b The task scheduling method shown in Figure 3 . As shown in Figure 4 , the task scheduling device 400 can include an acquisition unit 410, a determination unit 420, and a scheduling unit 430.

[0097] In one specific implementation, the acquisition unit 410 can be used to acquire a target task, wherein the target task is a task that needs to be processed by a processor core in a turbo state. For details, please refer to the detailed description of S320 in the embodiment shown in Figure 3 .

[0098] The determination unit 420 is configured to determine a target core from the multiple processor cores according to the failure information of the multiple processor cores, wherein the failure information of any processor core is used to indicate the service life of the processor core in the turbo state. For details, please refer to the detailed description of S330 in the embodiment shown in Figure 3 .

[0099] The scheduling unit 430 is configured to assign the target task to the target core, so that the target core processes the target task in the turbo state. For details, please refer to the detailed description of S340 in the embodiment shown in Figure 3The detailed description of S340 in the illustrated embodiment will not be repeated here.

[0100] In one specific implementation, the determining unit 420 is configured to: acquire failure information of the plurality of processor cores; and select, from the plurality of processor cores, the target core whose failure information satisfies a first scheduling condition according to the failure information of the plurality of processor cores. The failure information of any processor core includes a failure rate of the processor core. The first scheduling condition includes: the failure rate is the smallest; and / or the failure rate is not greater than a first value, where the first value is an average of the failure rates of the plurality of processor cores. For more details, please refer to Figure 3 The detailed description of S330 in the illustrated embodiment will not be repeated here.

[0101] In one specific implementation, the computer system includes one processor, and the plurality of processor cores are located in the processor. The acquiring unit is configured to: acquire a to-be-processed task; and determine the to-be-processed task as the target task when it is determined that there is at least one processor core whose load exceeds a first load threshold in the plurality of processor cores. For more details, please refer to Figure 2a and Figure 3 The detailed description of S330 in the illustrated embodiment will not be repeated here.

[0102] In one specific implementation, the computer system includes a plurality of processors, and there is at least one processor core of a first processor in the plurality of processors in the plurality of processor cores. The acquiring unit is configured to: acquire a to-be-processed task; and determine the to-be-processed task as the target task when it is determined that the to-be-processed task is to be assigned to the first processor and a load of the first processor exceeds a second load threshold. For more details, please refer to Figure 2b and Figure 3 The detailed description of S330 in the illustrated embodiment will not be repeated here.

[0103] In an embodiment, the determining unit 420 is configured to: acquire failure information of the plurality of processors, wherein the failure information of any processor indicates the life of the processor in the turbo state; select, according to the failure information of the plurality of processors, the first processor from the plurality of processors, wherein the failure information of any processor includes the failure rate of the processor, and the second scheduling condition includes that the failure rate is minimum and / or the failure rate is not greater than a second value, wherein the second value is the average of the failure rates of the plurality of processors; determine, from the plurality of processor cores, at least one alternative processor core located at the first processor; and determine, according to the failure information of the at least one alternative processor core, the target core from the at least one alternative processor core. For details, refer to the detailed description of S330 in the embodiments shown in Figure 2b and Figure 3 The detailed description of S330 in the embodiments shown in Figs. 3 and 4 will not be repeated here.

[0104] In an embodiment, the acquiring unit 410 is configured to: determine, according to the saved state information of the first processor core from the plurality of processor cores, the failure information of the first processor core, wherein the first processor core is any one of the plurality of processor cores, and the state information of the first processor core includes at least one of the following information of the first processor core running in the turbo state: running frequency information, running voltage information, running temperature information, and running time length information. For details, refer to the detailed description of S310 in the embodiments shown in Figure 3 The detailed description of S310 in the embodiments shown in Figs. 3 and 4 will not be repeated here.

[0105] In an embodiment, when the first processor core has a plurality of working gears, the running frequency information includes running frequencies corresponding to the plurality of working gears; the running voltage information includes running voltages corresponding to the plurality of working gears; the running temperature information includes running temperatures corresponding to the plurality of working gears; and the running time length includes running time lengths corresponding to the plurality of working gears. The acquiring unit is configured to: normalize the running frequency, running voltage, running temperature, and running time length corresponding to each working gear to obtain normalized data corresponding to each working gear; and determine the failure information of the first processor core according to the normalized data corresponding to each working gear. For details, refer to the detailed description of S310 in the embodiments shown in Figure 3 The detailed description of S310 in the embodiments shown in Figs. 3 and 4 will not be repeated here.

[0106] In an embodiment, the apparatus further includes a storage unit configured to save the state information of the target core when the target core processes the target task. For details, refer to the detailed description of the apparatus in the embodiments shown in Figure 3Detailed description of S310 in the illustrated embodiment will not be repeated here.

[0107] It can be understood that the specific implementation process of the device when used in the information receiving method described above and the corresponding beneficial effects can refer to the related description in the foregoing method embodiments, which will not be repeated here.

[0108] Based on the same technical concept, the embodiments of the present application also provide a computing device. The device internally contains a computer system as shown in Figure 1 、 Figure 2a and Figure 2b , can implement the task scheduling method as shown in Figure 3 , and contains a device with the function of the task scheduling device as shown in Figure 4 .

[0109] Referring to Figure 5 , the computing device 500 can include at least one processor 520 and a memory 510, the at least one processor including a plurality of processor cores. The memory 510 is configured to store failure information of the plurality of processor cores; and the processor 520 is configured to execute the task scheduling method described in the above embodiments.

[0110] Optionally, the processor 520 and the memory 510 are connected to each other through a bus 530. The bus 530 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0111] The at least one processor 520 can include at least one of a CPU, a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits for controlling program execution of the solutions of the present application. Among them, the CPU can include a power consumption controller and at least one processor core, and the power consumption controller can obtain the failure information of the at least one processor core and store the failure information of the at least one processor core into the memory 510.

[0112] The memory 510 can be a ROM, or other type of static storage device that can store static information and instructions; a RAM, or other type of dynamic storage device that can store information and instructions; and / or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magnetic disk storage or other magnetic storage devices, or any other medium capable of storing instructions or data that can be accessed by a computer, but not limited to. The memory can exist independently, and be connected to the processor via the bus 530. The memory can also be integrated with the processor.

[0113] The memory 510 is configured to store computer-executable instructions for implementing the solutions of the present application, and the processor 520 is configured to execute the computer-executable instructions stored in the memory 510, so as to implement the task scheduling method provided by the above-described embodiments of the present application.

[0114] Optionally, the computer-executable instructions in the embodiments of the present application can also be referred to as application program codes, which are not specifically limited in the embodiments of the present application.

[0115] Those skilled in the art can understand that the first, second, and other various numbers involved in the present application are only used for differentiation for convenience of description, and do not limit the scope of the embodiments of the present application, nor represent the sequence. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. "At least one" means one or more. At least two means two or more. "At least one", "any one", or similar expressions mean any combination of these items, including any combination of single item or multiple items. For example, at least one (one, kind) of a, b, or c can mean a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple. "Multiple" means two or more, and other quantifiers are similar. In addition, for the elements (element) appearing in the singular form "a", "an" and "the", unless the context clearly indicates otherwise, it does not mean "one or only one", but means "one or more than one". For example, "a device" means one or more such devices.

[0116] In the embodiments described above, all or some of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or some of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded into and executed by a computer, all or some of the processes or functions according to the embodiments described in the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, solid state disk (SSD)) and the like.

[0117] The various illustrative logical blocks and circuits described in the embodiments of the present application can be implemented or operated by a general purpose processor, a digital signal processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of the above. The general purpose processor can be a microprocessor, and optionally, the general purpose processor can also be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a digital signal processor core, or any other similar configuration.

[0118] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is tangible. In addition, the storage medium can be connected to the processor, so that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC.

[0119] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The flowchart blocks or blocks in the flowcharts represent steps in a process or algorithms and / or functions. The steps of the process or algorithms and / or functions can be embodied in computer program instructions, which can be executed on a computer or other programmable apparatus. Figure 1 The flowchart blocks or blocks in the flowcharts represent steps in a process or algorithms and / or functions. The steps of the process or algorithms and / or functions can be embodied in computer program instructions, which can be executed on a computer or other programmable apparatus.

[0120] Although the present application has been described in connection with specific features thereof, it will be evident to an artisan of ordinary skill that many modifications and changes can be made to the application without departing from the spirit and scope of the application. Accordingly, all statements herein are intended to be illustrative only, and not limiting. It is therefore intended that the scope of the application be determined by the following claims, which include all adaptations and modifications equivalent to those recited in the claims. It is further intended that the scope of the application include all equivalents of the subject matter recited in the claims.

Claims

1. A task scheduling method, characterized by, The method is applied to a computer system having a plurality of processor cores, and comprises: obtaining a target task, wherein the target task is a task that needs to be processed by a processor core in a turbo state; determining a target core from the plurality of processor cores according to failure information of the plurality of processor cores, wherein the failure information of any processor core indicates the life of the processor core in the turbo state, and the failure information is determined based on state information of the processor core running in the turbo state; allocating the target task to the target core, so that the target core processes the target task in the turbo state.

2. The method of claim 1, wherein, The method further comprises: obtaining the failure information of the plurality of processor cores; selecting the target core from the plurality of processor cores according to the failure information of the plurality of processor cores, wherein the failure information of any processor core satisfies a first scheduling condition.

3. The method of claim 2, wherein, The failure information of any processor core comprises a failure rate of the processor core, and the first scheduling condition comprises: the failure rate is the smallest, and / or the failure rate is not greater than a first value, wherein the first value is an average value of the failure rates of the plurality of processor cores.

4. The method according to any one of claims 1-3, characterized in that, The computer system comprises one processor, and the plurality of processor cores are located in the processor, and the obtaining of the target task comprises: obtaining a to-be-processed task; determining that the to-be-processed task is the target task when it is determined that at least one processor core from the plurality of processor cores has a load exceeding a first load threshold.

5. The method according to any one of claims 1-3, characterized in that, The computer system comprises a plurality of processors, and at least one processor core from the plurality of processor cores is located in a first processor from the plurality of processors, and the obtaining of the target task comprises: obtaining a to-be-processed task; determining that the to-be-processed task is the target task when it is determined that the to-be-processed task is to be allocated to the first processor and the load of the first processor exceeds a second load threshold.

6. The method of claim 5, wherein, The method further comprises: obtaining the failure information of the plurality of processors, wherein the failure information of any processor indicates the life of the processor in the turbo state; selecting the first processor from the plurality of processors according to the failure information of the plurality of processors, wherein the failure information of any processor comprises a failure rate of the processor, and the second scheduling condition comprises: the failure rate is the smallest, and / or the failure rate is not greater than a second value, wherein the second value is an average value of the failure rates of the plurality of processors; determining at least one alternative processor core from the plurality of processor cores, wherein the at least one alternative processor core is located in the first processor; determining the target core from the at least one alternative processor core according to the failure information of the at least one alternative processor core.

7. The method of claim 2, wherein, The obtaining of the failure information of the plurality of processor cores comprises: According to the saved state information of the first processor core of the plurality of processor cores, determine the failure information of the first processor core, wherein the first processor core is any one of the plurality of processor cores, and the state information of the first processor core includes at least one of the following information of the first processor core running in a turbo state: running frequency information, running voltage information, running temperature information, and running time length information.

8. The method of claim 7, wherein, In the case that the first processor core has a plurality of working gears, the running frequency information includes the running frequency corresponding to the plurality of working gears; the running voltage information includes the running voltage information corresponding to the plurality of working gears; the running temperature information includes the running temperature corresponding to the plurality of working gears; and the running time length information includes the running time length corresponding to the plurality of working gears. According to the saved state information of the first processor core, determine the failure information of the first processor core, comprising: Normalizing the running frequency, running voltage, running temperature, and running time length corresponding to each working gear to obtain normalized data corresponding to each working gear; According to the normalized data corresponding to each working gear, determine the failure information of the first processor core.

9. The method according to claim 7 or 8, characterized in that, The method further comprises: Saving the state information of the target core when the target core processes the target task.

10. A task scheduling apparatus characterized by comprising: Applied to a computer system having a plurality of processor cores, comprising: An acquisition unit configured to acquire a target task, wherein the target task is a task that needs to be processed by a processor core in a turbo state; A determination unit configured to determine a target core from the plurality of processor cores according to the failure information of the plurality of processor cores, wherein the failure information of any processor core indicates the service life of the processor core in a turbo state, and the failure information is determined based on the state information of the processor core running in a turbo state; A scheduling unit configured to assign the target task to the target core so that the target core processes the target task in a turbo state.

11. The apparatus of claim 10, wherein, The determination unit is configured to: Acquire the failure information of the plurality of processor cores; and select the target core whose failure information satisfies a first scheduling condition from the plurality of processor cores according to the failure information of the plurality of processor cores.

12. The apparatus of claim 11, wherein, The failure information of any processor core includes the failure rate of the processor core; and the first scheduling condition includes: The minimum failure rate; and / or, the failure rate is not greater than a first value, wherein the first value is the average of the failure rates of the plurality of processor cores.

13. The apparatus of any one of claims 10-12, wherein, The computer system includes a processor, and the plurality of processor cores are located in the processor, and the acquisition unit is configured to: Acquire a to-be-processed task; Determine that the to-be-processed task is the target task when at least one processor core of the plurality of processor cores has a load exceeding a first load threshold.

14. The apparatus of any one of claims 10-12, wherein, The computer system comprises a plurality of processors, at least one processor core of the plurality of processor cores is located in a first processor of the plurality of processors; the obtaining unit is configured to: obtain a to-be-processed task; when it is determined that the to-be-processed task is to be allocated to the first processor and the load of the first processor exceeds a second load threshold, determine that the to-be-processed task is the target task.

15. The apparatus of claim 14, wherein, The determining unit is configured to: obtain failure information of the plurality of processors, wherein the failure information of any processor is used to indicate the life of the processor in a turbo state; select, according to the failure information of the plurality of processors, the first processor whose failure information satisfies a second scheduling condition from the plurality of processors, wherein the failure information of any processor comprises a failure rate of the processor, and the second scheduling condition comprises that the failure rate is the smallest and / or the failure rate is not greater than a second value, wherein the second value is an average value of the failure rates of the plurality of processors; determine, in the plurality of processor cores, at least one alternative processor core located in the first processor; determine, according to the failure information of the at least one alternative processor core, the target core from the at least one alternative processor core.

16. The apparatus of claim 11, wherein, The obtaining unit is configured to: determine, according to saved state information of a first processor core in the plurality of processor cores, the failure information of the first processor core, wherein the first processor core is any one of the plurality of processor cores, and the state information of the first processor core comprises at least one of the following information of the first processor core running in a turbo state: running frequency information, running voltage information, running temperature information, and running time length information.

17. The apparatus of claim 16, wherein, In a case where the first processor core has a plurality of working gears, the running frequency information comprises running frequencies corresponding to the plurality of working gears; the running voltage information comprises running voltages corresponding to the plurality of working gears; the running temperature information comprises running temperatures corresponding to the plurality of working gears; and the running time length comprises running time lengths corresponding to the plurality of working gears. The obtaining unit is configured to: normalize the running frequency, the running voltage, the running temperature, and the running time length corresponding to each working gear to obtain normalized data corresponding to each working gear; and determine the failure information of the first processor core according to the normalized data corresponding to each working gear.

18. The apparatus of claim 16 or 17, wherein, The apparatus further comprises: a storage unit configured to save the state information of the target core when the target core processes the target task.

19. A computing device, comprising: The apparatus comprises a processor and a memory, the processor comprises a plurality of processor cores; the memory is configured to store failure information of the plurality of processor cores; the processor is configured to perform the task scheduling method in any one of claims 1-9.

20. A computer system, characterized by The apparatus comprises a scheduler, a power consumption controller, and a plurality of processor cores, the scheduler is configured to implement the method in any one of claims 1-9 according to the failure information of the plurality of processor cores obtained from the power consumption controller.

21. A computer readable medium characterized by A computer program product for storing a computer program comprising instructions for performing the method according to any one of claims 1-9. A computer program product for storing a computer program comprising instructions for performing the method according to any one of claims 1-9.

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