A method, system, device, and medium for updating an L2P table

Abstract

The application discloses a method for updating an L2P table, comprising the following steps: in response to a data write request received by a first core, generating a message body with preset bits according to the continuity of a logical address carried in the data write request; sending the logical address and the message body to a second core; and updating the L2P table according to the message body and the logical address by the second core. The application also discloses a system, a computer device and a readable storage medium. The scheme provided by the application can save core resources, prevent the processing speed of the core from becoming a speed bottleneck, and reduce the operation required by the core in a single write process and write delay.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, in particular to a method, system and device for updating L2P table and storage medium. BACKGROUND

[0002] In order to efficiently read and write and fully exert the performance of multi-core CPU, different cores or different states of the same core are usually required to be divided to process HOST commands and update L2P table functions.

[0003] The core resources of SSD are very valuable, and it is too wasteful to use cores for large-scale operations such as modifying L2P table after completing write operation. Therefore, hardware batch of CPU is used for the modification. In order to more efficiently use hardware batch to process DDR, the mapping relationship is usually polled before modification to check whether the logical address is continuous, which still consumes a certain amount of core resources. SUMMARY

[0004] Therefore, in order to overcome at least one aspect of the above problems, the embodiments of the present application provide a method for updating L2P table, comprising the following steps:

[0005] In response to the first core receiving a data write request, generating a message body of a preset bit according to the continuity of the logical address carried in the data write request;

[0006] Sending the logical address and the message body to the second core;

[0007] The second core updates the L2P table according to the message body and the logical address.

[0008] In some embodiments, generating a message body of a preset bit according to the continuity of the logical address carried in the data write request further comprises:

[0009] In response to the continuity between the previous logical address and the next logical address, setting the flag of the corresponding bit in the message body to a first preset value;

[0010] In response to the discontinuity between the previous logical address and the next logical address, setting the flag of the corresponding bit in the message body to a second preset value.

[0011] In some embodiments, the second core updates the L2P table according to the message body and the logical address further comprises:

[0012] Determining the position of the second preset value in the message body;

[0013] determine a plurality of continuous logical addresses in the logical addresses according to a position of the second preset value;

[0014] update the physical addresses in the L2P table according to each of the continuous logical addresses.

[0015] In some embodiments, the generating module is further configured to:

[0016] generate the message body of the preset bit positions according to a length of the logical addresses carried in the data write request.

[0017] Based on the same inventive concept, according to another aspect of the present application, embodiments of the present application further provide a system for updating an L2P table, comprising:

[0018] a generating module configured to, in response to the first core receiving a data write request, generate a message body of preset bit positions according to continuity of logical addresses carried in the data write request;

[0019] a sending module configured to send the logical addresses and the message body to the second core;

[0020] an updating module configured to cause the second core to update an L2P table according to the message body and the logical addresses.

[0021] In some embodiments, the generating module is further configured to:

[0022] in response to continuity between a previous logical address and a next logical address, set a flag of a corresponding bit position in the message body to a first preset value;

[0023] in response to discontinuity between the previous logical address and the next logical address, set the flag of the corresponding bit position in the message body to a second preset value.

[0024] In some embodiments, the updating module is further configured to:

[0025] determine a position of the second preset value in the message body;

[0026] determine a plurality of continuous logical addresses in the logical addresses according to the position of the second preset value;

[0027] update the physical addresses in the L2P table according to each of the continuous logical addresses.

[0028] In some embodiments, the generating module is further configured to:

[0029] generate the message body of the preset bit positions according to a length of the logical addresses carried in the data write request.

[0030] Based on the same inventive concept, according to another aspect of the present application, embodiments of the present application further provide a computer device, comprising:

[0031] at least one processor; and

[0032] a memory storing a computer program run on the processor, characterized in that the processor executes the following steps when executing the program:

[0033] generating a preset-bit message body according to continuity of logical addresses carried in the data write request in response to the first core receiving the data write request;

[0034] sending the logical addresses and the message body to the second core;

[0035] updating an L2P table according to the message body and the logical addresses by the second core.

[0036] In some embodiments, generating a preset-bit message body according to continuity of logical addresses carried in the data write request further comprises:

[0037] setting a flag of a corresponding bit in the message body to a first preset value in response to continuity between a previous logical address and a next logical address;

[0038] setting the flag of the corresponding bit in the message body to a second preset value in response to discontinuity between the previous logical address and the next logical address.

[0039] In some embodiments, updating an L2P table according to the message body and the logical addresses by the second core further comprises:

[0040] determining a position of the second preset value in the message body;

[0041] determining a plurality of continuous logical addresses in the logical addresses according to the position of the second preset value;

[0042] updating physical addresses in the L2P table according to each of the plurality of continuous logical addresses.

[0043] In some embodiments, generating a preset-bit message body according to continuity of logical addresses carried in the data write request further comprises:

[0044] generating a preset-bit message body according to a length of logical addresses carried in the data write request.

[0045] Based on the same inventive concept, according to another aspect of the present application, embodiments of the present application also provide a computer readable storage medium storing a computer program, the computer program being executed by a processor to perform the following steps:

[0046] In response to the first core receiving the data write request, generating a message body of preset bit positions according to continuity of logical addresses carried in the data write request;

[0047] Sending the logical addresses and the message body to the second core;

[0048] The second core updates an L2P table according to the message body and the logical addresses.

[0049] In some embodiments, generating the message body of preset bit positions according to continuity of logical addresses carried in the data write request further comprises:

[0050] In response to continuity between the previous logical address and the next logical address, setting a flag position of a corresponding bit position in the message body to a first preset value;

[0051] In response to discontinuity between the previous logical address and the next logical address, setting the flag position of the corresponding bit position in the message body to a second preset value.

[0052] In some embodiments, the second core updates the L2P table according to the message body and the logical addresses further comprises:

[0053] Determining a position of the second preset value in the message body;

[0054] Determining a plurality of continuous logical addresses in the logical addresses according to the position of the second preset value;

[0055] Updating physical addresses in the L2P table according to each of the continuous logical addresses.

[0056] In some embodiments, generating the message body of preset bit positions according to continuity of logical addresses carried in the data write request further comprises:

[0057] Generating the message body of preset bit positions according to lengths of the logical addresses carried in the data write request.

[0058] The present application has one of the following beneficial technical effects: the scheme provided by the present application can save core resources, prevent the processing speed of the core from becoming a speed bottleneck, and reduce the operations required by the core in a single write process and write delay. BRIEF DESCRIPTION OF DRAWINGS

[0059] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and other embodiments can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0060] Figure 1 The flowchart of the method for updating the L2P table provided by the embodiments of the present application is shown in the figure.

[0061] Figure 2 The structural diagram of the system for updating the L2P table provided by the embodiments of the present application is shown in the figure.

[0062] Figure 3 The structural diagram of the computer device provided by the embodiments of the present application is shown in the figure.

[0063] Figure 4 The structural diagram of the computer readable storage medium provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0064] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and other embodiments can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0065] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same name but different entities or different parameters. It can be seen that "first" and "second" are only used for the convenience of description, and should not be understood as a limitation of the embodiments of the present application. The subsequent embodiments will not be described one by one.

[0066] According to one aspect of the present application, the embodiments of the present application provide a method for updating an L2P table, as shown in the figure, which can include the following steps: Figure 1

[0067] S1, in response to the first core receiving a data write request, generating a preset bit message body according to the continuity of the logical address carried in the data write request;

[0068] S2, sending the logical address and the message body to the second core;

[0069] S3, the second core updating the L2P table according to the message body and the logical address.

[0070] In some embodiments, generating a preset bit message body according to the continuity of the logical address carried in the data write request further includes:

[0071] ​in response to continuity between the previous logical address and the next logical address, setting a flag of a corresponding bit in the message body to a first preset value;

[0072] in response to discontinuity between the previous logical address and the next logical address, setting the flag of the corresponding bit in the message body to a second preset value.

[0073] In some embodiments, the second core updates the L2P table according to the message body and the logical address, further comprising:

[0074] determining a position of the second preset value in the message body;

[0075] determining a plurality of continuous logical addresses in the logical address according to the position of the second preset value;

[0076] updating the physical address in the L2P table according to each continuous logical address.

[0077] In some embodiments, the message body of the preset bit is generated according to continuity of the logical address carried in the data write request, further comprising:

[0078] generating the message body of the preset bit according to the length of the logical address carried in the data write request.

[0079] Specifically, the core processing the HOST is referred to as core A (first core), and the core processing the L2P table information is referred to as core B (second core). When the core A receives the data write request, when the core A sends the logical address of the data write request to the core B, a message body recording whether the logical address is continuous can be added in the communication between the core A and the core B, the number of bits of the message body is greater than the range of the logical address, and the recording is performed by each bit indicating whether the current logical address is continuous with the next logical address. If continuous, the corresponding bit is 0, and if discontinuous, the corresponding bit is 1. The core A can fill in a write information after obtaining the HOST message, and set the record bit corresponding to the last segment of the continuous information to 1. For example, the logical address corresponding to the received data write request is 01235678, wherein the first four logical addresses are continuous, and the last four logical addresses are continuous. Thus, the message body can be 00010001. When the core B writes and completes the table, it is not necessary to poll and find whether each table is continuous with the next table, and the position of the bit being 1 in the record can be directly read to operate the hardware to batch update the table.

[0080] In this way, since the continuity of some logical addresses is directly determined by the core processing the HOST message, while the core processing the mapping table needs to access and compare each node one by one to determine whether each node is continuous, the core processing the HOST message can directly obtain the continuity relationship by confirming whether the logical addresses in the L2P table are continuous, recording it, and sending it to the core processing the mapping table. Compared to comparing each node one by one, the processing algorithm complexity is reduced from n to 1, saving core resources.

[0081] The solution proposed in this invention can save core resources, prevent core processing speed from becoming a bottleneck, and reduce the operations required by the core in a single write process, thereby reducing write latency.

[0082] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a system 400 for updating L2P tables, such as... Figure 2 As shown, it includes:

[0083] The generation module 401 is configured to generate a message body of preset bits in response to the first core receiving a data write request, based on the continuity of the logical address carried in the data write request.

[0084] Sending module 402 is configured to send the logical address and the message body to the second core;

[0085] The update module 403 is configured to enable the second core to update the L2P table based on the message body and the logical address.

[0086] In some embodiments, the generation module 401 is further configured to:

[0087] In response to the continuity between the previous logical address and the next logical address, the flag position of the corresponding bit in the message body is set to the first preset value;

[0088] In response to a discontinuity between the previous and next logical addresses, the flag position of the corresponding bit in the message body is set to a second preset value.

[0089] In some embodiments, the update module 403 is further configured to:

[0090] Determine the position of the second preset value in the message body;

[0091] Based on the position of the second preset value, determine several consecutive logical address segments in the logical address;

[0092] The physical addresses in the L2P table are updated based on each consecutive logical address segment.

[0093] In some embodiments, the generation module 401 is further configured to:

[0094] generate a message body of preset bits according to continuity of logical addresses carried in the data write request.

[0095] The scheme provided by the application can save core resources, prevent the processing speed of the core from becoming a speed bottleneck, and reduce the operations required by the core in a single write process and write delay.

[0096] Based on the same inventive concept, according to another aspect of the application, as Figure 3 The embodiment of the application also provides a computer device 501, which comprises:

[0097] at least one processor 520; and

[0098] a memory 510, wherein the memory 510 stores a computer program 511 capable of running on the processor, and the processor 520 executes the following steps when executing the program:

[0099] S1, in response to the first core receiving a data write request, generating a message body of preset bits according to continuity of logical addresses carried in the data write request;

[0100] S2, sending the logical addresses and the message body to the second core;

[0101] S3, the second core updating an L2P table according to the message body and the logical addresses.

[0102] In some embodiments, generating a message body of preset bits according to continuity of logical addresses carried in the data write request further comprises:

[0103] in response to continuity between a previous logical address and a next logical address, setting a flag of a corresponding bit in the message body to a first preset value;

[0104] in response to discontinuity between the previous logical address and the next logical address, setting the flag of the corresponding bit in the message body to a second preset value.

[0105] In some embodiments, the second core updating an L2P table according to the message body and the logical addresses further comprises:

[0106] determining a position of the second preset value in the message body;

[0107] determining a plurality of continuous logical addresses in the logical addresses according to the position of the second preset value;

[0108] updating a physical address in the L2P table according to each of the plurality of continuous logical addresses.

[0109] In some embodiments, the message body with preset bits is generated according to continuity of logical addresses carried in the data write request, and further includes:

[0110] The message body with preset bits is generated according to length of logical addresses carried in the data write request.

[0111] The scheme provided by the application can save core resources, prevent the processing speed of the core from becoming a speed bottleneck, and reduce the operations required by the core in a single write process and write delay.

[0112] Based on the same inventive concept, according to another aspect of the application, as Figure 4 As shown in the figure, the embodiments of the application also provide a computer readable storage medium 601, which stores computer program instructions 610, and the computer program instructions 610 are executed by a processor to perform the following steps:

[0113] S1, in response to the first core receiving a data write request, generating a message body with preset bits according to continuity of logical addresses carried in the data write request;

[0114] S2, sending the logical addresses and the message body to the second core;

[0115] S3, the second core updating an L2P table according to the message body and the logical addresses.

[0116] In some embodiments, the message body with preset bits is generated according to continuity of logical addresses carried in the data write request, and further includes:

[0117] In response to continuity between the previous logical address and the next logical address, setting a flag of a corresponding bit in the message body to a first preset value;

[0118] In response to discontinuity between the previous logical address and the next logical address, setting a flag of a corresponding bit in the message body to a second preset value.

[0119] In some embodiments, the second core updates the L2P table according to the message body and the logical addresses, and further includes:

[0120] Determining a position of the second preset value in the message body;

[0121] Determining a plurality of continuous logical addresses in the logical addresses according to the position of the second preset value;

[0122] Updating a physical address in the L2P table according to each continuous logical address.

[0123] In some embodiments, the message body of preset bits is generated according to continuity of logical addresses carried in the data write request, and further comprising:

[0124] The message body of preset bits is generated according to length of logical addresses carried in the data write request.

[0125] The scheme provided by the application can save core resources, prevent the processing speed of the core from becoming a speed bottleneck, and reduce the operation required by the core in a single write process and write delay.

[0126] Finally, it should be noted that all or part of the processes in the above-mentioned embodiments can be understood by those of ordinary skill in the art, and can be completed by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the above-mentioned embodiments.

[0127] In addition, it should be understood that the computer-readable storage medium (for example, the memory) herein can be a volatile memory or a non-volatile memory, or can include both volatile memory and non-volatile memory.

[0128] Those skilled in the art will also appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends on the particular application and design constraints imposed on the overall system. Those skilled in the art can implement the functionality in various ways for each particular application, but such implementation decisions do not affect the scope of the disclosure embodiments.

[0129] The above is an exemplary embodiment disclosed by the application, but it should be noted that various changes and modifications can be made without departing from the scope of the disclosure embodiments defined by the claims. The functions, steps and / or acts of the method claims described herein need not be performed in any particular order. Furthermore, although the elements of the disclosure embodiments disclosed can be described or claimed in individual forms, unless expressly limited to the singular, they can also be understood to include plural forms.

[0130] It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0131] The above-mentioned example number of embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0132] A person of ordinary skill in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or can be instructed by a program to complete the related hardware, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0133] Those of ordinary skill in the art will understand that the above discussion of any of the embodiments is only exemplary and is not intended to imply that the scope (including claims) of the embodiments disclosed by the present application is limited to these examples; under the idea of the embodiments of the present application, the above embodiments or technical features in different embodiments can also be combined, and there are many other changes of different aspects of the embodiments of the present application as above. In order to be brief, they are not provided in details. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principles of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A method of updating an L2P table, the method comprising: The method comprises the following steps: In response to the first core receiving a data write request, generating a preset bit message body according to the continuity of a logical address carried in the data write request; Sending the logical address and the message body to the second core; The second core updates an L2P table according to the message body and the logical address; Generating a preset bit message body according to the length of the logical address carried in the data write request, further comprising: Generating a preset bit message body according to the length of the logical address carried in the data write request; In response to the continuity between the previous logical address and the next logical address, setting the flag position of the corresponding bit in the message body to a first preset value; In response to the discontinuity between the previous logical address and the next logical address, setting the flag position of the corresponding bit in the message body to a second preset value; The second core updates an L2P table according to the message body and the logical address, further comprising: Determining the position of the second preset value in the message body; Determining a plurality of continuous logical addresses in the logical address according to the position of the second preset value; Updating the physical address in the L2P table according to each continuous logical address.

2. A system for updating an L2P table, the system comprising: Comprise: The generating module is configured to generate a preset bit message body according to the continuity of a logical address carried in the data write request in response to the first core receiving a data write request; The sending module is configured to send the logical address and the message body to the second core; The updating module is configured to enable the second core to update an L2P table according to the message body and the logical address; The generating module is further configured to: Generate a preset bit message body according to the length of the logical address carried in the data write request; In response to the continuity between the previous logical address and the next logical address, set the flag position of the corresponding bit in the message body to a first preset value; In response to the discontinuity between the previous logical address and the next logical address, set the flag position of the corresponding bit in the message body to a second preset value; The updating module is further configured to: Determine the position of the second preset value in the message body; Determine a plurality of continuous logical addresses in the logical address according to the position of the second preset value; Update the physical address in the L2P table according to each continuous logical address.

3. A computer device, comprising: At least one processor; And A memory, the memory stores a computer program executable on the processor, characterized in that when the processor executes the program, the steps of the method of claim 1 are executed.

4. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 3. The computer program is executed by the processor to execute the steps of the method of claim 1.

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