Semiconductor memory device and method of operating the same

Abstract

Embodiments of the present disclosure relate to a semiconductor memory device and an operating method thereof, the semiconductor memory device comprising a memory cell array and a peripheral circuit. The memory cell array comprises memory cells, each memory cell storing N bits of data. The peripheral circuit performs a programming operation on a physical page including a selected memory cell. The peripheral circuit is configured to receive data segments of N logical pages and program the data segments of the N logical pages to the physical page based on a logical code. The logical code is determined to balance the number of sensing operations required to read the data segments of the N logical pages. A weak read level is assigned using the logical code to read the data of the logical page with the least number of sensing operations.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0124984 filed on September 25, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly to semiconductor memory devices and methods of operating the semiconductor memory devices. Background Art

[0004] The memory device may have a two-dimensional (2D) structure in which the strings are arranged horizontally on a semiconductor substrate. Alternatively, the memory device may have a three-dimensional (3D) structure in which the strings are stacked vertically on a semiconductor substrate. As memory devices having a 2D structure reach their physical scaling limits (i.e., limits of integration), 3D memory devices comprising a plurality of memory cells stacked vertically on a semiconductor substrate are increasingly being produced. Summary of the invention

[0005] Various embodiments of the present disclosure are directed to a semiconductor memory device and a method of operating the semiconductor memory device, which can improve read performance of programmed data after programming the data.

[0006] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory cells, each of the plurality of memory cells storing N bits of data, where N is a natural number of 2 or greater. The peripheral circuit may be configured to perform a programming operation on a physical page including a memory cell selected from the plurality of memory cells. The peripheral circuit is configured to receive data corresponding to N logical pages, and to program the data corresponding to the N logical pages to the physical page based on a logical code. The logical code may be determined to balance the number of sensing operations required to read the data corresponding to the N logical pages, respectively. A weak read level may be assigned according to the logical code to read the data of the logical page with the smallest number of sensing operations among the N logical pages.

[0007] In one embodiment, N may be 3, and each of the selected memory cells may be determined to belong to any one of eight threshold voltage states.

[0008] In one embodiment, the first to seventh read levels may be used to distinguish eight threshold voltage states, and among the first to seventh read levels, the weak read levels may be the first and seventh read levels.

[0009] In one embodiment, the logic code can be configured so that the second read level, the fourth read level, and the sixth read level are used to read data corresponding to the first logical page of the three logical pages, the third read level and the seventh read level are used to read data corresponding to the second logical page of the three logical pages, and the first read level and the fifth read level are used to read data corresponding to the third logical page of the three logical pages.

[0010] In one embodiment, N may be 5, and each of the selected memory cells may be determined to belong to any one of 32 threshold voltage states.

[0011] In one embodiment, the first to thirty-first read levels may be used to distinguish 32 threshold voltage states from one another, and the weak read levels may be the first, second, thirtieth, and thirty-first read levels.

[0012] In one embodiment, the logic code can be configured so that the ninth read level, the eleventh read level, the fourteenth read level, the twenty-fifth read level, the twenty-seventh read level and the thirtieth read level are used to read data corresponding to a first logical page among five logical pages, the second read level, the sixth read level, the eighth read level, the eighteenth read level, the twenty-second read level and the twenty-fourth read level are used to read data corresponding to a second logical page among the five logical pages, the first read level, the seventh read level, the sixteenth read level, the nineteenth read level, the twenty-first read level and the twenty-eighth read level are used to read data corresponding to a third logical page among the five logical pages, the fourth read level, the twelfth read level, the twentieth read level, the twenty-sixth read level, the twenty-ninth read level and the thirty-first read level are used to read data corresponding to a fourth logical page among the five logical pages, and the third read level, the fifth read level, the tenth read level, the thirteenth read level, the fifteenth read level, the seventeenth read level and the twenty-third read level are used to read data corresponding to a fifth logical page among the five logical pages.

[0013] In one embodiment, the logic code may be a Gray code.

[0014] Embodiments of the present disclosure may provide a method for operating a semiconductor memory device including a plurality of memory cells, wherein each of the memory cells stores N bits of data, and the memory cells included in one physical page store data corresponding to N logical pages. The method may include: receiving data corresponding to N logical pages from a memory controller; determining a threshold voltage state of a memory cell selected from a plurality of memory cells based on data corresponding to the N logical pages and a logic code; and programming the selected memory cell based on the determined threshold voltage state. The logic code may be determined to balance the number of sensing operations required to read the data corresponding to the N logical pages, respectively. A weak read level may be assigned according to the logic code to read the data of the logical page with the smallest number of sensing operations among the N logical pages.

[0015] In one embodiment, N may be 3, and each of the selected memory cells may be determined to belong to any one of eight threshold voltage states.

[0016] In one embodiment, among three logical pages, two sense operations may be allocated to read the first logical page, two sense operations are allocated to read the second logical page, and three sense operations are allocated to read the third logical page.

[0017] In one embodiment, a weak read level may be assigned to read the first logical page and the second logical page.

[0018] In one embodiment, N may be 5, and each of the selected memory cells may be determined to belong to any one of 32 threshold voltage states.

[0019] In one embodiment, among five logical pages, six sensing operations are allocated to read the first logical page, six sensing operations are allocated to read the second logical page, six sensing operations are allocated to read the second logical page, six sensing operations are allocated to read the third logical page, six sensing operations are allocated to read the fourth logical page, and seven sensing operations are allocated to read the fifth logical page.

[0020] In one embodiment, a weak level may be assigned to read the first logical page and the second logical page.

[0021] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory cells, each of the plurality of memory cells storing N bits of data, where N is a natural number of 2 or greater. The peripheral circuit may be configured to perform a programming operation on a physical page including a memory cell selected from the plurality of memory cells. The peripheral circuit may be configured to receive data corresponding to N logical pages, and program the data corresponding to the N logical pages to the physical page based on a logical code. The logical code may be determined to balance the number of sensing operations required to read the data corresponding to the N logical pages, respectively. In a method having a sequential size to store 2 N The threshold voltage states are distinguished from each other by a first reading level to a second reading level (2 N Among the read levels, the first read level as the lowest read level and the second read level as the highest read level N -1) The read level may be allocated to read data corresponding to different logical pages among data corresponding to N logical pages.

[0022] In one embodiment, N can be 3, and each of the selected memory cells can be determined to belong to any one of eight threshold voltage states, and among the first read level to the seventh read level having sequential values, the first read level and the seventh read level can be assigned to read data corresponding to different logical pages.

[0023] In one embodiment, N can be 5, and each of the selected memory cells can be determined to belong to any one of 32 threshold voltage states, and among the first read level to the thirty-first read level having sequential values, the first read level and the thirty-first read level can be assigned to read data corresponding to different logical pages.

[0024] In one embodiment, among the first to thirty-first read levels, the first read level, the second read level, the thirtieth read level, and the thirty-first read level may be allocated to respectively read different logical pages. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0026] Figure 2 It is shown Figure 1 1 is a block diagram of an embodiment of a memory cell array 110.

[0027] Figure 3 It is shown Figure 2A circuit diagram of an example of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0028] Figure 4 It is shown Figure 2 A circuit diagram of an example of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0029] Figure 5 It shows that the Figure 1 1 is a circuit diagram of an example of any one memory block BLKc among the memory blocks BLK1 to BLKz in the memory cell array 110 of FIG.

[0030] FIG. 6A to FIG. 6E is a diagram showing distribution of programming states or voltage levels of memory cells included in a semiconductor memory device.

[0031] Figure 7 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0032] Fig. 8A is a diagram for describing a method of programming memory cells each storing 3-bit data using a logic code according to an embodiment of the present disclosure.

[0033] Figure 8B is with Fig. 8A Compare the figures used to describe features of the present disclosure.

[0034] Fig. 9 is a diagram for describing a method of programming memory cells each storing 5-bit data using a logic code according to an embodiment of the present disclosure.

[0035] Fig.10 It shows that Figure 1 1 is a block diagram of a memory system 1000 of a semiconductor memory device 100.

[0036] Fig.11 It is shown Fig.10 A block diagram of an application of a memory system.

[0037] Fig.12 is shown including reference Fig.11 A block diagram of a computing system that describes a memory system. DETAILED DESCRIPTION

[0038] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are exemplified to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0039] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0040] refer to Figure 1 , the semiconductor memory device 100 includes a memory cell array 110 , an address decoder 120 , a read and write circuit 130 , a control logic 140 , and a voltage generator 150 .

[0041] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz are coupled to the address decoder 120 through word lines WL. The memory blocks BLK1 to BLKz are coupled to the read and write circuit 130 through bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells may be nonvolatile memory cells and may be implemented as nonvolatile memory cells having a vertical channel structure. The memory cell array 110 may be implemented as a memory cell array having a two-dimensional (2D) structure. In one embodiment, the memory cell array 110 may be implemented as a memory cell array having a three-dimensional (3D) structure. At the same time, each of the memory cells included in the memory cell array may store at least one bit of data. In one embodiment, each of the memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing 1 bit of data. In one embodiment, each of the memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing 2 bits of data. In one embodiment, each of the memory cells included in the memory cell array 110 may be a triple level cell (TLC) storing 3-bit data. In one embodiment, each of the memory cells included in the memory cell array 110 may be a quad level cell (QLC) storing 4-bit data. According to an embodiment, the memory cell array 110 may include a plurality of memory cells, each of which stores 5-bit data or more.

[0042] The address decoder 120, the read and write circuit 130, the control logic 140, and the voltage generator 150 are operated as a peripheral circuit for driving the memory cell array 110. The address decoder 120 is coupled to the memory cell array 110 through the word line WL. The address decoder 120 may be operated under the control of the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) provided in the semiconductor memory device 100.

[0043] The address decoder 120 may decode the block address in the received address. The address decoder 120 selects at least one memory block based on the decoded block address. In addition, when performing a read voltage application operation during a read operation, the address decoder 120 may apply a read voltage Vread generated by the voltage generator 150 to a selected word line of a selected memory block, and may apply a pass voltage Vpass to the remaining word lines, i.e., unselected word lines. In addition, during a program verification operation, the address decoder 120 may apply a verification voltage generated by the voltage generator 150 to a selected word line of a selected memory block, and may apply a pass voltage Vpass to the remaining word lines, i.e., unselected word lines.

[0044] The address decoder 120 may decode the column address in the received address and may send the decoded column address to the read and write circuit 130 .

[0045] The read and program operations of the semiconductor memory device 100 are each performed in units of pages. The addresses received in response to the requests for the read and program operations may include block addresses, row addresses, and column addresses. The address decoder 120 may select a memory block and a word line according to the block address and the row address. The column address may be decoded by the address decoder 120 and then provided to the read and write circuit 130.

[0046] The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

[0047] The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The read and write circuit 130 may be operated as a “read circuit” during a read operation of the memory cell array 110, and may be operated as a “write circuit” during a write operation of the memory cell array 110. The plurality of page buffers PB1 to PBm are coupled to the memory cell array 110 through bit lines BL1 to BLm. In order to sense the threshold voltage of the memory cell during a read operation and a program verification operation, each of the page buffers PB1 to PBm may sense a change in the amount of flowing current according to a programming state of the corresponding memory cell through a sensing node, and latch as sensing data while continuously providing a sensing current to a bit line coupled to the memory cell. The read and write circuit 130 may respond to a page buffer control signal CTR output from the control logic 140. PB And being operated.

[0048] During a read operation, the read and write circuit 130 may sense data stored in a memory cell and temporarily store the read data, and may then output the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, the read and write circuit 130 may include a column selection circuit, etc., and a page buffer (or page register).

[0049] The control logic 140 is coupled to the address decoder 120, the read and write circuit 130, and the voltage generator 150. The control logic 140 can be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 can be a control logic circuit that operates according to an algorithm and / or a processor that executes the control logic code. The control logic 140 can receive the command CMD and the control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 can control the overall operation of the semiconductor memory device 100 in response to the control signal CTRL. In addition, the control logic 140 can output the control signal CTR PB , for controlling a plurality of page buffers PB1 to PBm included in the read and write circuit 130. The control logic 140 may control the read and write circuit 130 to perform a read operation of the memory cell array 110.

[0050] The voltage generator 150 may generate a read voltage Vread and a pass voltage Vpass for a read operation in response to a control signal output from the control logic 140. In addition, the voltage generator 150 may generate voltages for generating various control signals required to control the operation of the semiconductor memory device.

[0051] Figure 2 It is shown Figure 1 1 is a block diagram of an embodiment of a memory cell array 110.

[0052] refer to Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block has a three-dimensional (3D) structure. Each of the memory blocks may include a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged in the +X direction, the +Y direction, and the +Z direction. Figure 3 and Figure 4 The structure of each memory block is described in more detail.

[0053] Figure 3 It is shown Figure 2 A circuit diagram of any memory block BLKa of the memory blocks BLK1 to BLKz.

[0054] refer to Figure 3, the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in a row direction (ie, a positive (+) X direction). Figure 3 , two cell strings are shown to be arranged in the column direction (ie, the positive (+) Y direction). However, this illustration is for convenience of description, and it will be understood that three or more cell strings may be arranged in the column direction.

[0055] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0056] The selection transistors SST and DST and the memory cells MC1 to MCn may have similar structures. In one embodiment, each element in the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a pillar for providing a channel layer may be provided in each cell string. In one embodiment, a pillar for providing at least one of a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0057] The source selection transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 to MCp.

[0058] In one embodiment, source selection transistors of cell strings arranged in the same row are coupled to a source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows are coupled to different source selection lines. Figure 3 , source selection transistors of cell strings CS11 to CS1m in a first row are coupled to a first source selection line SSL1. Source selection transistors of cell strings CS21 to CS2m in a second row are coupled to a second source selection line SSL2.

[0059] In one embodiment, source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m may be commonly coupled to one source selection line.

[0060] The first to nth memory cells MC1 to MCn in each cell string are coupled between a source select transistor SST and a drain select transistor DST.

[0061] The first to nth memory cells MC1 to MCn may be divided into the first to pth memory cells MC1 and the p+1th memory cells MCp+1 to the nth memory cells MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in a direction opposite to the positive (+) Z direction and are coupled in series between the source selection transistor SST and the pipe transistor PT. The p+1th memory cells MCp+1 to the nth memory cells MCn are sequentially arranged in the +Z direction and are coupled in series between the pipe transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 and the p+1th memory cells MCp+1 to the nth memory cells MCn are coupled to each other through the pipe transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are respectively coupled to the first to nth word lines WL1 to WLn.

[0062] The gate of the pipe transistor PT of each cell string is coupled to the pipeline PL.

[0063] The drain selection transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are coupled to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11 to CS1m in the first row are coupled to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m in the second row are coupled to the second drain selection line DSL2.

[0064] The cell strings arranged in the column direction may be coupled to the bit lines extending in the column direction. Figure 3 , the cell strings CS11 and CS21 in the first column are coupled to the first bit line BL1. The cell strings CS1m and CS2m in the mth column are coupled to the mth bit line BLm.

[0065] Memory cells coupled to the same word line in the cell strings arranged in the row direction form a single page. For example, in the cell strings CS11 to CS1m in the first row, memory cells coupled to the first word line WL1 form a single page. In the cell strings CS21 to CS2m in the second row, memory cells coupled to the first word line WL1 form another single page. By selecting any one of the drain selection lines DSL1 and DSL2, a cell string arranged in a single row direction can be selected. By selecting any one of the word lines WL1 to WLn, a page can be selected from the selected cell string.

[0066] In one embodiment, instead of the first to m-th bit lines BL1 to BLm, even bit lines and odd bit lines may be provided. In the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction, the even cell strings may be coupled to the corresponding even bit lines. In the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction, the odd cell strings may be coupled to the corresponding odd bit lines.

[0067] In one embodiment, one or more memory cells of the first memory cell MC1 to the nth memory cell MCn may be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells are provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As the number of dummy memory cells provided increases, the reliability of the operation of the memory block BLKa may be improved, and the size of the memory block BLKa may be increased. As the number of dummy memory cells provided decreases, the size of the memory block BLKa may be reduced, and the reliability of the operation of the memory block BLKa may deteriorate.

[0068] In order to effectively control one or more dummy memory cells, the corresponding dummy memory cells may have a desired threshold voltage. Before or after performing an erase operation on the memory block BLKa, a programming operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after a programming operation has been performed, the corresponding dummy memory cells may have a desired threshold voltage by controlling the voltage applied to the dummy word line coupled to the corresponding dummy memory cell.

[0069] Figure 4 It is shown Figure 2 1 is a circuit diagram of an example of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0070] refer to Figure 4 , the memory block BLKb may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends in a positive Z (+Z) direction. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0071] The source select transistor SST of each cell string is connected between a common source line CSL and memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are coupled to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row are coupled to the first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row are coupled to the second source select line SSL2. In one embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be commonly coupled to a single source select line.

[0072] The first to nth memory cells MC1 to MCn in each cell string are connected in series between source select transistors SST and drain select transistors DST. Gates of the first to nth memory cells MC1 to MCn are coupled to first to nth word lines WL1 to WLn, respectively.

[0073] The drain selection transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain selection transistors of the cell strings arranged in the row direction are coupled to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11' to CS1m' in the first row are coupled to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21' to CS2m' in the second row are coupled to the second drain selection line DSL2.

[0074] As a result, in addition to excluding the pipe transistor PT from each cell string, Figure 4 The memory block BLKb has Figure 3 The equivalent circuit of the memory block BLKa is similar.

[0075] In one embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction, the even cell strings may be respectively coupled to the even bit lines, and in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction, the odd cell strings may be respectively coupled to the odd bit lines.

[0076] In one embodiment, one or more memory cells of the first memory cell MC1 to the nth memory cell MCn may be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells are provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKb is improved, but the size of the memory block BLKb increases. As fewer memory cells are provided, the size of the memory block BLKb is reduced, but the reliability of the operation of the memory block BLKb may deteriorate.

[0077] In order to effectively control one or more dummy memory cells, each of the dummy memory cells may have a desired threshold voltage. Before or after performing an erase operation of the memory block BLKb, a programming operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after a programming operation has been performed, the dummy memory cell may have a desired threshold voltage by controlling the voltage to be applied to the dummy word line coupled to the corresponding dummy memory cell.

[0078] Figure 5 is shown to be included in Figure 1 1 is a circuit diagram of an example of any one memory block BLKc of the memory blocks BLK1 to BLKz in the memory cell array 110 of FIG.

[0079] refer to Figure 5 , the memory block BLKc may include a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm may be coupled to a plurality of bit lines BL1 to BLm, respectively. Each of the cell strings CS1 to CSm includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST.

[0080] The selection transistors SST and DST and the memory cells MC1 to MCn may have similar structures. In one embodiment, each element in the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a pillar for providing a channel layer may be provided in each cell string. In one embodiment, a pillar for providing at least one of a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0081] The source selection transistor SST of each cell string is coupled between the common element line CSL and the memory cells MC1 to MCn.

[0082] The first to nth memory cells MC1 to MCn in each cell string are coupled between a source select transistor SST and a drain select transistor DST.

[0083] The drain selection transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MC1 to MCn.

[0084] Memory cells coupled to the same word line may constitute a single page. Cell strings CS1 to CSm may be selected by selecting a drain selection line DSL. One page may be selected from a selected cell string by selecting any one of word lines WL1 to WLn.

[0085] In other embodiments, even and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Among the cell strings CS1 to CSm, even cell strings may be respectively coupled to even bit lines, and odd cell strings may be respectively coupled to odd bit lines.

[0086] like Figures 2 to 4 As shown, the memory cell array 110 of the semiconductor memory device 100 may be implemented as a memory cell array having a 3D structure. Figure 5 As shown, the memory cell array 110 of the semiconductor memory device 100 may be implemented as a memory cell array having a 2D structure.

[0087] FIG. 6A to FIG. 6E is a diagram showing the distribution of programming states or voltage levels of memory cells included in a semiconductor memory device. FIG. 6A to FIG. 6E The distribution shown in can be the distribution of programming states or voltage levels of memory cells. FIG. 6A to FIG. 6E In the graph of , the x-axis represents the threshold voltage Vth of the memory cell, and the y-axis represents the number of memory cells.

[0088] refer to Fig. 6A , when the memory cells included in the memory cell array 110 are single-level cells (SLC), each of the memory cells may belong to any one of an erase state E and a program state P. Since the SLC cell may be in any one of two different states, each memory cell may store one bit. In this case, a plurality of memory cells coupled to one word line may form one physical page, and one physical page may store one page of data (one page data segment). One page data segment may be data including bits corresponding to corresponding memory cells included in one physical page.

[0089] refer to Figure 6B , when the memory cells included in the memory cell array 110 are multi-level cells (MLC), each of the memory cells may belong to an erase state E or any one of the first programming state P1 to the third programming state P3. Because the MLC cell can be in a state corresponding to one of four different states, each cell can be programmed or store two different bits according to a predefined code scheme. The first bit, as the higher bit of the two bits, may be referred to as the most significant bit (MSB), and the second bit, as the lower bit of the two bits, may be referred to as the least significant bit (LSB). In this case, a plurality of memory cells coupled to one word line may form one physical page, and one physical page may store data of two logical pages, namely, MSB page data and LSB page data. The MSB page data may include the MSB stored in the corresponding memory cells included in the physical page. The LSB page data may include the LSB stored in the corresponding memory cells included in the physical page.

[0090] refer to Figure 6C , when the memory cells included in the memory cell array 110 are three-level cells (TLC), each of the memory cells may belong to an erase state E or any one of the first programming state P1 to the seventh programming state P7. Because the TLC cell may be in a state corresponding to one of eight different states, each cell may be programmed or stored in three different bits according to a predefined programming scheme. The first bit, as the upper bit of the three bits, may be referred to as the MSB, the second bit, as the central bit of the three bits, may be referred to as the central significant bit (CSB), and the third bit, as the lower bit of the three bits, may be referred to as the LSB. In this case, a plurality of memory cells coupled to one word line may form one physical page, and one physical page may store storage data of three logical pages, namely, MSB page data, CSB page data, and LSB page data. The MSB page data may include the MSB stored in the corresponding memory cells included in the physical page. The CSB page data may include the CSB stored in the corresponding memory cells included in the physical page. The LSB page data may include the LSB stored in the corresponding memory cells included in the physical page.

[0091] refer to Fig.6D, when the memory cells included in the memory cell array 110 are quad-level cells (QLC), each of the memory cells may belong to an erase state E or any one of the first programming state P1 to the fifteenth programming state P15. Because the QLC cell can be in a state corresponding to one of 16 different states, each cell can be programmed or stored in four different bits according to a predefined programming scheme. The first bit, as the high bit among the four bits, may be referred to as the MSB, the second bit, as the high center bit among the four bits, may be referred to as the high center valid bit (HCSB), the third bit, as the low center bit among the four bits, may be referred to as the low center valid bit (LCSB), and the fourth bit, as the low bit among the four bits, may be referred to as the LSB. In this case, a plurality of memory cells coupled to one word line may form one physical page, and one physical page may store data of four logical pages, namely, MSB page data, HCSB page data, LCSB page data, and LSB page data. The MSB page data may include the MSB stored in the corresponding memory cells included in the physical page. The HCSB page data may include the HCSB stored in the corresponding memory cells included in the physical page. The LCSB page data may include LCSBs stored in corresponding memory cells included in the physical page. The LSB page data may include LSBs stored in corresponding memory cells included in the physical page.

[0092] refer to Fig. 6E , when the memory cells included in the memory cell array 110 are cells for storing 5-bit data, each of the memory cells may belong to the erase state E or any one of the first to thirty-first program states P1 to P31. In this case, a plurality of memory cells coupled to one word line may form one physical page, and one physical page may store data of five logical pages, i.e., first to fifth page data.

[0093] like FIG. 6A to FIG. 6E As shown, according to the number of bits stored in each of the memory cells included in the memory cell array 110, the number of program states of the threshold voltages of the memory cells distinguished from each other may vary.

[0094] Figure 7 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0095] refer to Figure 7According to an embodiment of the present disclosure, a method for operating a semiconductor memory device may include: a step S100 of receiving data of N logical pages from a memory controller; a step S200 of determining a threshold voltage state of a selected memory cell based on the received data of the N logical pages and a logic code; and a step of programming the selected memory cell based on the determined threshold voltage state.

[0096] At step S100, the semiconductor memory device 100 may receive a programming command, a programming address, and programming data from a memory controller. The programming command may be a command for controlling the semiconductor memory device 100 to perform a programming operation. The programming address may be an address indicating the location of a physical page on which a programming operation is to be performed. At the same time, the semiconductor memory device 100 may sequentially receive data of N logical pages from the memory controller. In an embodiment of the present disclosure, N may be a natural number of 3 or greater. When the memory cells included in the memory cell array 110 of the semiconductor memory device 100 are TLC, the semiconductor memory device may receive MSB page data, CSB page data, and LSB page data, which are to be stored in a physical page corresponding to the programming address at step S100. When the memory cells included in the memory cell array 110 of the semiconductor memory device 100 are QLC, the semiconductor memory device may receive MSB page data, HCSB page data, LCSB page data, and LSB page data, which are to be stored in a physical page corresponding to the programming address at step S100. When the memory cells included in the memory cell array 110 of the semiconductor memory device 100 are memory cells each of which stores 5-bit data, the semiconductor memory device can receive first to fifth page data to be stored in a physical page corresponding to the program address at step S100.

[0097] At step S200, the threshold voltage state of the selected memory cell may be determined based on the received data of the N logical pages and a preset logic code. The logic code may be a code for mapping a data segment to be stored in a corresponding memory cell and a threshold voltage of the corresponding memory cell to each other.

[0098] At step S200 , the semiconductor memory device 100 according to an embodiment of the present disclosure may determine a threshold voltage state of a selected memory cell according to received data of N logical pages based on a logic code having at least one of the following features (i) to (iv).

[0099] Feature (i) “Gray code”

[0100] According to an embodiment of the present disclosure, the logic code used in the programming operation of the semiconductor memory device may be a Gray code. For the bit data of each programming state in a plurality of programming states, when the bit data segment corresponding to the adjacent programming state has only a 1-bit difference, such a code may be designated as a Gray code. When the data segments of N logical pages (i.e., N logical page data segments) are programmed using the Gray code, even if a sensing error occurs in a subsequent reading process, only a 1-bit error is included in the logical page data, so that an advantage can be obtained in error correction.

[0101] Feature (ii) “Balanced number of sensing operations for reading logical page data”

[0102] Depending on the scheme for configuring the logic code, the number of sensing operations for reading each of the N logical pages may vary. In an example, the logic code may be configured so that the deviation between the number of sensing operations for respectively reading the N logical pages is a large value, or so that the deviation between the number of sensing operations for respectively reading the N logical pages is minimized. According to the semiconductor memory device and the method for operating the semiconductor memory device according to an embodiment of the present disclosure, the threshold voltage state of the selected memory cell may be determined using a logic code that is configured to minimize the deviation between the number of sensing operations for respectively reading the N logical pages. In this case, because the deviation between the read times indicating the time required to respectively read the N logical pages is also minimized, the read performance of the semiconductor memory device 100 may be improved.

[0103] When the semiconductor memory device 100 and the method of operating the semiconductor memory device according to an embodiment of the present disclosure use a logic code configured to minimize the deviation between the number of sensing operations for reading N logical pages separately, the relationship shown in the following equation (1) can be established for the corresponding logic code.

[0104] NRMAxNRmin≤NTH(1)

[0105] In the above equation (1), N RMAX represents the number of sensing operations for the logical page data that requires the maximum number of sensing operations among the N logical page data segments, and N Rmin represents the number of sensing operations for logical page data that requires the minimum number of sensing operations among N logical page data segments. Therefore, “N RMAX -N Rmin ” respectively represent the deviations between the numbers of sensing operations required to read N logical page data segments.

[0106] In addition, N THrepresents a value appropriately determined according to the number of bits stored in each memory cell. For example, when the memory device included in the memory cell array 110 of the semiconductor memory device 100 is a TLC, N TH can be set to 1. This means that the logic code is configured so that the deviation between the numbers of sensing operations for respectively reading three logical page data segments included in a logical page is less than or equal to 1. In an example, when each of the memory cells in the memory cell array 110 included in the semiconductor memory device 100 stores 5 bits, N TH can be set to 2. This means that the logic code is configured so that the deviation between the numbers of sensing operations for respectively reading five logical page data segments included in a physical page is less than or equal to 2.

[0107] Feature (iii) Assign weak read levels to logical pages with the smallest number of sense operations ”

[0108] In the case of a physical page storing N logical page data segments, 2 N -1 read level to sense the corresponding programming state. Depending on the aforementioned feature (ii), the number of sensing operations for reading the corresponding logical page data segments can be balanced. However, even in this case, there may be a need to respectively RMAX The corresponding multiple sensing operations are logical pages and need to be compared with N Rmin According to the semiconductor memory device and the method of operating the semiconductor memory device according to the embodiment of the present disclosure, N logical page data segments are programmed using a logic code, which assigns weak read levels to the N logical page data segments. Rmin logical page for sensing operations.

[0109] A weak read level may mean a read level where it is difficult to find the boundary between programmed states because a relatively large shift in the threshold voltage distribution occurs due to disturbance or retention. Figure 6C , the memory cell corresponding to the erased state E may be susceptible to program disturbance, so it may be difficult to find a boundary between the erased state E and the first programming state P1, and a sensing error may occur relatively frequently in the corresponding area. Therefore, the first read level R1 for distinguishing the erased state E from the first programming state P1 may be included in the weak read level. At the same time, the memory cell corresponding to the seventh programming state P7 having a high threshold voltage is easy to retain, so it may be difficult to find a boundary between the sixth programming state P6 and the seventh programming state P7, and a sensing error may occur relatively frequently in the corresponding area. Therefore, the seventh read level R7 for distinguishing the sixth programming state P6 from the seventh programming state P7 may be included in the weak read level.

[0110] According to an embodiment of the present disclosure, N logical page data segments are programmed using a logic code that assigns weak read levels to the N logical page data segments that require Rmin Therefore, since weak read levels are assigned to logical pages requiring relatively fewer number of sensing operations, sensing errors can be minimized.

[0111] Feature (iv) “Assigning multiple weak read levels to different logical pages”

[0112] As mentioned above in feature (iii) Figure 6C As described above, there may be multiple weak read levels. In this case, when multiple weak read levels are centrally assigned to one logical page, the possibility of a read error may increase. Therefore, according to the semiconductor memory device and the method for operating the semiconductor memory device according to an embodiment of the present disclosure, the logic code is configured to assign multiple weak read levels to different logical pages. Therefore, the error rate occurring in the read operation can be reduced.

[0113] According to the semiconductor memory device 100 and the method of operating the semiconductor memory device according to the embodiment of the present disclosure, the threshold voltage state of the selected memory cell can be determined according to the received N logical page data segments based on the logic code having at least one of the aforementioned features (i) to (iv). Therefore, during the read operation after the programming operation, the possibility of the occurrence of a read error can be minimized. Fig. 8A and Figure 8B Features (i) to (iv) of the logic code used in the semiconductor memory device 100 and a method of operating the semiconductor memory device according to an embodiment of the present disclosure are described in detail.

[0114] When the threshold voltage state of the selected memory cell is determined at step S200, the selected memory cell is programmed based on the threshold voltage state determined at step S300. That is, the peripheral circuit of the semiconductor memory device 100 can program the selected memory cell based on the logic code having at least one of the aforementioned features (i) to (iv).

[0115] Fig. 8A is a diagram for describing a method of programming memory cells each storing 3-bit data using a logic code according to an embodiment of the present disclosure. Figure 8B is used with Fig. 8A The following is a diagram that illustrates the features of the present disclosure. Fig. 8A and Figure 8B Features (i) to (iv) of the logic code according to an embodiment of the present disclosure are described together in detail.

[0116] refer to Fig. 8A , shows the threshold voltage state of the memory cell determined based on the logic code according to the embodiment of the present disclosure. Fig. 8A , the memory cells storing bits “1 1 1” in the order of MSB-CSB-LSB are maintained in the erased state E. The memory cells storing bits “1 1 0” are programmed to the first programmed state P1. In this way, the memory cells storing bits “0 10”, “0 0 0”, “1 0 0”, “1 0 1”, “0 0 1”, and “0 1 1” are programmed to the second programmed state P2 to the seventh programmed state P7, respectively. In order to distinguish the threshold voltage states of the corresponding memory cells from each other, the first read level R1 to the seventh read level R7 may be used.

[0117] refer to Fig. 8A , as shown in the dotted box, the erased state E and the first programmed state P1 differ from each other only in the LSB. That is, the erased state E and the first programmed state P1 have the same MSB (i.e., 1) and have the same CSB (i.e., 1). In addition, the erased state E and the first programmed state P1 have different LSB values, in such a way that the LSB of the erased state E is 1, while the LSB of the first programmed state P1 is 0. At the same time, the first programmed state P1 and the second programmed state P2 differ from each other only in the CSB. In addition, the second programmed state P2 and the third programmed state P3 differ from each other only in the CSB. As described above, according to Fig. 8A The threshold voltage states shown in FIG. 1 and FIG. 2 have only a 1-bit difference between the bit data segments corresponding to the adjacent programming states. That is, Fig. 8A Corresponds to the threshold voltage state of the memory cell programmed based on feature (i) "Gray code".

[0118] refer to Fig. 8A , in order to read the data of the MSB page, the second read level R2, the fourth read level R4 and the sixth read level R6 should be used to sense the threshold voltage of the memory cell. In addition, in order to read the data of the CSB page, the third read level R3 and the seventh read level R7 should be used to sense the threshold voltage of the memory cell. At the same time, in order to read the data of the LSB page, the first read level R1 and the fifth read level R5 should be used to sense the threshold voltage of the memory cell. At the same time, Fig. 8A In FIG. 1 , the first read level R1 susceptible to disturbance and the seventh read level R7 susceptible to retention are indicated by dotted lines as weak read levels. The following Table 1 summarizes these contents.

[0119] Table 1

[0120] Logical Page Reading level Number of sensing operations Weak read level MSB R2, R4, R6 3 X CSB R3,R7 2 R7 LSB R1,R5 2 R1

[0121] Referring to Table 1, the number of sensing operations required to read the MSB page is 3, and the number of sensing operations required to read each of the CSB page and the LSB page is 2. As can be seen from the aforementioned equation (1), the logic code has been configured so that N RMAX The value of N is 3, Rmin The value of is 2, and N TH The value of is 1. Therefore, referring to Table 1, the logic code has been configured so that (ii) "the number of sensing operations for reading logical page data is balanced."

[0122] Meanwhile, the weak read levels are the first read level R1 and the seventh read level R7. The first read level R1 is assigned to the LSB page whose number of sensing operations is 2, and the seventh read level R7 is assigned to the CSB page whose number of sensing operations is 2. Therefore, it can be seen that (iii) "the weak read levels R1 and R7 are assigned to the logical page data (LSB and CSB) whose number of sensing operations is the least."

[0123] Finally, it can be seen that (iv) “a plurality of weak read levels R1 and R7 are dispersed and allocated to different logical page data segments (LSB and CSB)” rather than being allocated to any one logical page.

[0124] refer to Figure 8B , it can be seen that Fig. 8A Similarly, (i) the threshold voltage states of the memory cells programmed based on the Gray code are shown. Figure 8B , in order to read the data of the MSB page, the fourth read level R4 should be used to sense the threshold voltage of the memory cell. In addition, in order to read the data of the CSB page, the second read level R2 and the sixth read level R6 should be used to sense the threshold voltage of the memory cell. In addition, in order to read the data of the LSB page, the first read level R1, the third read level R3 and the seventh read level R7 should be used to sense the threshold voltage of the memory cell. At the same time, Figure 8B In FIG. 1 , the first read level R1 susceptible to disturbance and the seventh read level R7 susceptible to retention are indicated by dotted lines as weak read levels. The following Table 2 summarizes these contents.

[0125] Table 2

[0126]

[0127] Referring to Table 2, the number of sensing operations required to read the MSB page is 1, the number of sensing operations required to read the CSB page is 2, and the number of sensing operations required to read the LSB page is 4. As can be seen from the aforementioned equation (1), the logic code has been configured so that N RMAX The value of N is 4 and Rmin The value of is 1. As mentioned above Fig. 8A As mentioned above, when N TH When the value of is 1, N in Table 2 RMAX and N Rmin The relationship of equation (1) is not satisfied. That is, referring to Table 2, it can be seen that, unlike Table 1, (ii) the logic code is not configured so that the number of sensing operations for reading logical page data is balanced.

[0128] Meanwhile, the weak read levels are the first read level R1 and the seventh read level R7. Both the first read level R1 and the seventh read level R7 are allocated to the LSB page, and the number of sensing operations for the LSB page is 4. That is, referring to Table 2, it can be seen that, unlike Table 1, (iii) the weak read levels R1 and R7 are not allocated to the logical page data (MSB and CSB) having the least number of sensing operations.

[0129] Finally, (iv) a plurality of weak read levels R1 and R7 are assigned to the LSB page, i.e., a logical page. That is, it can be seen that Figure 8B The corresponding logic code is provided with feature (i), but not with the other features (ii) to (iv).

[0130] Can be summarized with Fig. 8A The corresponding logic codes are shown in Table 3 below.

[0131] Table 3

[0132]

[0133] Figure 3 A logic code including all of the features (i) to (iv) is shown. As shown in Table 3, according to the semiconductor memory device 100 and the method of operating the semiconductor memory device according to an embodiment of the present disclosure, a programming operation is performed based on the logic code including features (i) to (iv). Therefore, when a read operation is performed after the programming operation has been performed, the read error rate can be minimized and the speed of the read operation can be increased. Therefore, the performance of the semiconductor memory device 100 can be enhanced.

[0134] According to an embodiment of the present disclosure, a logic code for programming a TLC used in the semiconductor memory device 100 and a method of operating the semiconductor memory device are not limited to Table 3. For example, a TLC may be programmed using a logic code such as shown in Table 4 below.

[0135] Table 4

[0136]

[0137] When comparing Table 3 with Table 4, the bit programming state mapping relationship corresponding to the MSB of Table 3 can match the bit programming state mapping relationship corresponding to the CSB of Table 4. Moreover, the bit programming state mapping relationship corresponding to the CSB of Table 3 can match the bit programming state mapping relationship corresponding to the MSB of Table 4. At the same time, the bit programming state mapping relationship corresponding to the LSB of Table 3 is the same as the bit programming state mapping relationship corresponding to the LSB of Table 4. That is, when the first row and the second row of Table 3 are interchanged, the logic code of Table 4 can be obtained. Even in this case, a logic code that satisfies all of the above features (i) to (iv) is configured. That is, a logic code including all of the features (i) to (iv) can be obtained by changing the order of the three rows included in the logic code of Table 3.

[0138] Already referenced Fig. 8A and Figure 8B A logic code satisfying all of the characteristics (i) to (iv) in the programming of TLC is described. However, this is only an example, and a logic code satisfying all of the characteristics (i) to (iv) may be configured for a QLC storing 4-bit data. In addition, even for a memory cell storing 5-bit data, a logic code satisfying all of the characteristics (i) to (iv) may be configured. Fig. 9 An example of a logic code satisfying all of features (i) to (iv) is described in detail.

[0139] Fig. 9 is a diagram for describing a method of programming memory cells each storing 5-bit data using a logic code according to an embodiment of the present disclosure.

[0140] refer to Fig. 9 , shows the threshold voltage state of the memory cell determined based on the logic code according to an embodiment of the present disclosure. Fig. 9 In the embodiment, the memory cells storing the bits "1 1 1 1 1" in the order of the first bit to the fifth bit are maintained in the erased state E. The memory cells storing the bits "1 1 0 11" are programmed to the first programmed state P1. In this way, in Fig. 9 The second to thirty-first program states P2 to P31 are shown in . The first to thirty-first read levels R1 to R31 may be used to distinguish threshold voltage states of corresponding memory cells from one another.

[0141] refer to Fig. 9 As shown in each dotted box, the erase state E and the first programming state P1 differ from each other only in the third bit. At the same time, the first programming state P1 and the second programming state P2 differ from each other only in the second bit. As described above, according to Fig. 9The threshold voltage states shown in FIG. 1 and FIG. 2 have only a 1-bit difference between the bit data segments corresponding to the adjacent programming states. That is, Fig. 9 Threshold voltage states of memory cells based on (i) "Gray code" programming are shown.

[0142] exist Fig. 9 In FIG. 5 , the first read level R1 and the second read level R2 susceptible to disturbance and the 30th read level R30 and the 31st read level R31 susceptible to retention are indicated as weak read levels by dotted lines. Fig. 9 The read levels of the corresponding logical page data segments, the number of sensing operations thereof, and the weak read levels are shown in .

[0143] Table 5

[0144]

[0145]

[0146] Referring to Table 5, the number of sensing operations required to read the first to fifth bit pages may be 6, 6, 6, 6, and 7, respectively. As can be seen from the aforementioned equation (1), the logic code has been configured so that N RMAX The value of N is 7, Rmin The value of is 5, and N TH The value of is 1. Therefore, referring to Table 5, the logic code has been configured so that (ii) the number of sensing operations for reading logical page data is balanced.

[0147] Meanwhile, the weak read levels may be a first read level R1, a second read level R2, a thirtieth read level R30, and a thirty-first read level R31. The first read level R1 is assigned to the third bit page whose number of sensing operations is 6, and the second read level R2 is assigned to the second bit page whose number of sensing operations is 6. The thirtieth read level R30 is assigned to the first bit page whose number of sensing operations is 6, and the thirty-first read level R31 is assigned to the fourth bit page whose number of sensing operations is 6. Therefore, it can be seen that (iii) the weak read levels R1, R2, R30, and R31 are respectively assigned to the third bit page, the second bit page, the first bit page, and the fourth bit page whose number of sensing operations is the smallest.

[0148] Finally, it can be seen that the plurality of weak read levels R1 , R2 , R30 , and R31 are dispersed and assigned to the first to fourth bit pages, which are different logical pages (LSB and CSB), rather than to any one logical page.

[0149] Can be summarized with Fig. 9 The corresponding logic codes are shown in Table 6 below.

[0150] Table 6

[0151]

[0152]

[0153] Meanwhile, according to an embodiment of the present disclosure, the logic code for programming a memory cell storing 5-bit data used in the semiconductor memory device 100 and the method of operating the semiconductor memory device are not limited to Table 6. For example, a memory cell storing 5-bit data may be programmed using a logic code such as shown in Table 7 below.

[0154] Table 7

[0155] E P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 First place 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Second Place 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 Third Place 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 Fourth Place 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Fifth 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 First place 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 Second Place 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 Third Place 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Fourth Place 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 Fifth 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1

[0156] Referring to Table 6 and Table 7 together, the first row of Table 6 matches the second row of Table 7, and the second row of Table 6 matches the first row of Table 7. At the same time, the third row of Table 6 matches the fourth row of Table 7, and the fourth row of Table 6 matches the fifth row of Table 7. Finally, the fifth row of Table 6 matches the third row of Table 7. Even in this case, a logic code that satisfies all of the above-mentioned features (i) to (iv) is configured. In this way, a logic code including all of the features (i) to (iv) can be obtained by changing the order of the three rows included in the logic code of Table 6.

[0157] Fig.10 It is shown that Figure 1 1 is a block diagram of a memory system 1000 of a semiconductor memory device 100.

[0158] refer to Fig.10 , the semiconductor system 1000 may include a semiconductor memory device 100 and a semiconductor controller 1100. The semiconductor memory device 100 may be a reference Figure 1 Hereinafter, repeated descriptions will be omitted.

[0159] The memory controller 1100 is coupled to the host Host and the semiconductor memory device 100. The memory controller 1100 may access the semiconductor memory device 100 in response to a request from the host Host. For example, the memory controller 1100 may control read, write, erase, and background operations of the semiconductor memory device 100. The memory controller 1100 may provide an interface between the semiconductor memory device 100 and the host Host. The memory controller 1100 may run firmware for controlling the semiconductor memory device 100.

[0160] The memory controller 1100 includes a random access memory (RAM) 1110, a processor 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 is used as at least one working memory for the processor 1120, a cache memory between the semiconductor memory device 100 and the host Host, and a cache memory between the semiconductor memory device 100 and the host. The processor 1120 may control the overall operation of the memory controller 1100. In addition, the memory controller 1100 may temporarily store programming data provided from the host Host during a write operation.

[0161] The host interface 1130 includes a protocol for performing data exchange between the host Host and the memory controller 1100. In an embodiment, the memory controller 1100 may communicate with the host Host through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a dedicated protocol.

[0162] The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface 1140 may include a NAND interface or a NOR interface.

[0163] The error correction block 1150 may detect and correct errors in data received from the semiconductor memory device 100 using an error correction code (ECC). In example embodiments, the error correction block 1150 may be provided as an element of the memory controller 1100.

[0164] The memory controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device. In an embodiment, the memory controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card, such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or MMCmicro), an SD card (SD, miniSD, microSD or SDHC), or a Universal Flash Storage (UFS) device.

[0165] The memory controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a solid state drive (SSD). The SSD includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as an SSD, the operating speed of the host Host coupled to the memory system 1000 may be significantly improved.

[0166] In an embodiment, the memory system 1000 may be provided as one of various elements of an electronic device (such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a device capable of sending / receiving information in a wireless environment), one of various electronic devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, a radio frequency identification (RFID) device, or one of various elements for forming a computing system.

[0167] In an embodiment, the semiconductor memory device 100 or the memory system 1000 may be installed in various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 may be packaged and installed in a type such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic lead chip carrier (PLCC), plastic dual in-line package (PDIP), waffle die, wafer die, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SOIC), thermally reduced size package (SSOP), thin small outline (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level manufacturing package (WFP) or wafer-level processing stacked package (WSP).

[0168] Fig.11 It is shown Fig.10 1000 is a block diagram of an example application of a memory system 1000.

[0169] refer to Fig.11, the memory system 2000 may include a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 may include a plurality of semiconductor memory chips. The semiconductor memory chips are divided into a plurality of groups.

[0170] exist Fig.11 , it is shown that a plurality of groups communicate with the memory controller 2200 through the first channel CH1 to the kth channel CHk. Figure 1 The semiconductor memory device 100 described above configures and operates each semiconductor memory chip in the same manner.

[0171] Each group can communicate with the memory controller 2200 through a common channel. The memory controller 2200 may have a common channel with the reference Fig.10 The memory controller 1100 described above has the same configuration and may control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

[0172] Fig.12 is shown including reference Fig.11 A block diagram of a computing system is depicted in FIG. 2000 .

[0173] The computing system 3000 includes a central processing unit (CPU) 3100 , a RAM 3200 , a user interface 3300 , a power supply 3400 , a system bus 3500 , and a memory system 2000 .

[0174] The memory system 2000 is electrically coupled to the CPU 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 may be stored in the memory system 2000.

[0175] exist Fig.12 , the semiconductor memory device 2100 is shown as being coupled to the system bus 3500 through the semiconductor controller 2200. However, the semiconductor memory device 2100 may be directly coupled to the system bus 3500. Here, the function of the memory controller 2200 may be performed by the CPU 3100 and the RAM 3200.

[0176] exist Fig.12 References are provided in Fig.11 However, the memory system 2000 described herein may be used with reference Fig.10 The memory system 1000 described above is used to replace the memory system 2000. In an embodiment, the computing system 3000 may include the reference Fig.10 and Fig.11Both memory system 1000 and memory system 2000 are described.

[0177] The present disclosure may provide a semiconductor memory device and a method of operating the semiconductor memory device, which may improve read performance of programmed data after programming the data.

Claims

1. A semiconductor memory device, comprising: A memory cell array including a plurality of memory cells, each of the plurality of memory cells storing N-bit data, wherein N is a natural number of 2 or greater; as well as a peripheral circuit that performs a program operation on a physical page, the physical page including a memory cell selected from the plurality of memory cells, wherein the peripheral circuit receives data corresponding to N logical pages, and programs the data corresponding to the N logical pages into the physical page based on a logical code, wherein the logic code is determined to balance the number of sensing operations required to respectively read the data corresponding to the N logic pages, and According to the logic code, a weak read level is assigned to read data of the smallest number of logical pages of the sensing operation among the N logical pages. 2 . The semiconductor memory device according to claim 1 , wherein N is 3, and each of the selected memory cells is determined to belong to any one of eight threshold voltage states.

3. The semiconductor memory device according to claim 2, wherein: The first to seventh read levels are used to distinguish the eight threshold voltage states, and Among the first to seventh read levels, the weak read levels are the first and seventh read levels.

4. The semiconductor memory device according to claim 3, wherein the logic code causes: The second read level, the fourth read level, and the sixth read level are used to read data corresponding to a first logical page of the three logical pages. The third read level and the seventh read level are used to read data corresponding to a second logical page of the three logical pages, and The first read level and the fifth read level are used to read data corresponding to a third logical page of the three logical pages. 5 . The semiconductor memory device according to claim 1 , wherein N is 5, and each of the selected memory cells is determined to belong to any one of 32 threshold voltage states.

6. The semiconductor memory device according to claim 5, wherein: The first to thirty-first read levels are used to distinguish the 32 threshold voltage states from each other, and The weak read levels are a first read level, a second read level, a thirtieth read level, and a thirty-first read level.

7. The semiconductor memory device according to claim 6, wherein the logic code causes: a ninth read level, an eleventh read level, a fourteenth read level, a twenty-fifth read level, a twenty-seventh read level, and a thirtieth read level are used to read data corresponding to a first logical page of the five logical pages, The second read level, the sixth read level, the eighth read level, the eighteenth read level, the twenty-second read level and the twenty-fourth read level are used to read data corresponding to the second logical page of the five logical pages, The first read level, the seventh read level, the sixteenth read level, the nineteenth read level, the twenty-first read level and the twenty-eighth read level are used to read data corresponding to a third logical page of the five logical pages, a fourth read level, a twelfth read level, a twentieth read level, a twenty-sixth read level, a twenty-ninth read level, and a thirty-first read level are used to read data corresponding to a fourth logical page of the five logical pages, and The third read level, the fifth read level, the tenth read level, the thirteenth read level, the fifteenth read level, the seventeenth read level, and the twenty-third read level are used to read data corresponding to the fifth logical page of the five logical pages.

8. The semiconductor memory device according to claim 1, wherein the logic code is a Gray code.

9. A method of operating a semiconductor memory device including a plurality of memory cells, wherein each of the memory cells stores N-bit data, and memory cells included in one physical page store data corresponding to N logical pages, the method comprising: receiving data corresponding to the N logical pages from a memory controller; determining a threshold voltage state of a memory cell selected from the plurality of memory cells based on the data and logic codes corresponding to the N logical pages; as well as programming the selected memory cell based on the determined threshold voltage state, wherein the logic code is determined to balance the number of sensing operations required to respectively read the data corresponding to the N logic pages; as well as According to the logic code, a weak read level is assigned to read data of the smallest number of logical pages of the sensing operation among the N logical pages.

10. The method of claim 9, wherein N is 3, and each of the selected memory cells is determined to belong to any one of eight threshold voltage states.

11. The method according to claim 10, wherein in the three logical pages: Two sensing operations are allocated to read the first logical page; Two sensing operations are allocated to read the second logical page; and Three sense operations are allocated to read the third logical page. 12 . The method of claim 11 , wherein the weak read level is assigned to read the first logical page and the second logical page.

13. The method of claim 9, wherein N is 5, and each of the selected memory cells is determined to belong to any one of 32 threshold voltage states.

14. The method according to claim 13, wherein in the five logical pages: Six sense operations are allocated to read the first logical page; Six sense operations are allocated to read the second logical page; Six sense operations are allocated to read the third logical page; six sense operations are allocated to read a fourth logical page; and Seven sense operations are allocated to read the fifth logical page. 15 . The method of claim 14 , wherein the weak read level is assigned to read the first logical page and the second logical page.

16. A semiconductor memory device comprising: A memory cell array including a plurality of memory cells, each of the plurality of memory cells storing N-bit data, wherein N is a natural number of 2 or greater; as well as a peripheral circuit that performs a program operation on a physical page, the physical page including a memory cell selected from the plurality of memory cells, wherein the peripheral circuit receives data corresponding to N logical pages, and programs the data corresponding to the N logical pages into the physical page based on a logical code, wherein the logic code is determined to balance the number of sensing operations required to respectively read the data corresponding to the N logic pages, wherein according to the logic code, a weak read level is assigned to read data of the smallest number of logical pages of the sensing operation among the N logical pages, and Among them, in order to have a size of 2 N The threshold voltage states are distinguished from each other by a first reading level to a second reading level (2 N -1) read level, the first read level and the (2 N -1) read level is assigned to read data corresponding to different logical pages among the data corresponding to the N logical pages, the first read level being the lowest read level, and the (2 N -1) The read level is the highest read level.

17. The semiconductor memory device according to claim 16, wherein: N is 3, and each of the selected memory cells is determined to belong to any one of eight threshold voltage states, and Among the first to seventh read levels having sequential values, the first read level and the seventh read level are allocated to read data corresponding to different logical pages.

18. The semiconductor memory device according to claim 16, wherein: N is 5, and each of the selected memory cells is determined to belong to any one of 32 threshold voltage states, and Among the first to thirty-first read levels having sequential values, the first and thirty-first read levels are assigned to read data corresponding to different logical pages. 19 . The semiconductor memory device according to claim 18 , wherein among the first to thirty-first read levels, the first, second, thirtieth, and thirty-first read levels are respectively assigned to read different logical pages.

Images