Semiconductor structure preparation method and semiconductor structure

Abstract

The present application relates to a method for fabricating a semiconductor structure and a semiconductor structure, comprising: providing a substrate, forming a first patterned mask layer on the upper surface of the substrate, etching the substrate based on the first patterned mask layer to form a shallow trench in the substrate; forming a liner layer on the sidewalls and bottom of the shallow trench; forming a first drift region surrounding the shallow trench and a second drift region directly below the shallow trench in the substrate, wherein the doping concentration of the first drift region is different from the doping concentration of the second drift region by controlling the thickness of the first patterned mask layer and the energy of ion implantation; annealing the resulting structure; and forming a dielectric layer in the shallow trench, wherein the dielectric layer fills the shallow trench. The present application can reduce the on-resistance of the device while maintaining a high withstand voltage, and reduces the number of process steps.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the rapid development of integrated circuit manufacturing processes, the requirements for semiconductor product integration are becoming increasingly higher. Furthermore, as semiconductor products become increasingly integrated, the size of semiconductor devices and their isolation structures is also decreasing. To achieve higher device integration while improving device breakdown voltage, existing medium- and high-voltage BCD processes often add a long, high-temperature annealing step after ion implantation in the drift region to achieve a uniform drift region doping concentration.

[0003] Furthermore, traditional semiconductor manufacturing processes typically use shallow trench isolation (STI) structures as field plates to compensate for the insufficient gate oxide withstand voltage at the edge of the polysilicon within shallow trenches. However, BCD devices made with this process typically have high on-resistance because the current in the on-state must "detour" around the bottom of the field plate. This also increases the process flow, increasing semiconductor device manufacturing costs and reducing device yield. Summary of the Invention

[0004] Based on this, it is necessary to address the problems in the above-mentioned background technology and provide a semiconductor structure preparation method and semiconductor structure that can reduce the on-resistance of the device while ensuring the high withstand voltage value of the manufactured semiconductor device, and reduce the process steps, thereby reducing the manufacturing cost of the semiconductor device while improving the yield of the manufactured device.

[0005] To achieve the above-mentioned and other related objectives, one aspect of the present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0006] Providing a substrate, forming a first patterned mask layer on an upper surface of the substrate, and etching the substrate based on the first patterned mask layer to form a shallow trench in the substrate;

[0007] forming a liner layer on the sidewall and bottom of the shallow trench;

[0008] forming a first drift region surrounding the shallow trench and a second drift region directly below the shallow trench in the substrate, wherein the doping concentration of the first drift region is different from the doping concentration of the second drift region by controlling the thickness of the first patterned mask layer and the energy of ion implantation;

[0009] annealing the obtained structure;

[0010] A dielectric layer is formed in the shallow trench, and the dielectric layer fills the shallow trench.

[0011] In the method for fabricating a semiconductor structure in the above-described embodiment, a shallow trench is first formed in a substrate. A liner layer is then formed on the sidewalls and bottom of the shallow trench to eliminate damage caused by etching the shallow trench and provide a protective layer for subsequent filling of the shallow trench. A first drift region surrounding the shallow trench and a second drift region directly below the shallow trench are then formed in the substrate. By controlling the thickness of the first patterned mask layer and the energy of ion implantation, the doping concentration of the first drift region is different from that of the second drift region, thereby improving the impurity concentration in the current path and effectively improving the on-resistance of the device. By utilizing the significant step difference on the substrate surface after forming the shallow trench isolation structure, the depth of the second drift region formed directly below the shallow trench is deeper than that of the drift region formed in this area in traditional semiconductor fabrication processes, thereby increasing the cross-sectional area for current flow and further improving the on-resistance of the device. Since the drift region high-temperature well-pushing process is simultaneously achieved during the annealing of the liner layer, compared to the traditional process flow in which high-temperature annealing of the liner layer and high-temperature well-pushing of the ion implantation region are performed in two separate process steps, the process steps are effectively reduced. Therefore, the present application reduces the on-resistance of the device while ensuring a high withstand voltage value of the manufactured semiconductor device, and reduces the process steps, thereby reducing the manufacturing cost of the semiconductor device while improving the yield rate of the manufactured device.

[0012] In one embodiment, forming a first patterned mask layer on the upper surface of the substrate includes:

[0013] forming a first mask layer on the upper surface of the substrate;

[0014] Coating a first photoresist layer on the upper surface of the first mask layer and performing patterning to form a first patterned photoresist layer;

[0015] The first mask layer is etched based on the first patterned photoresist layer to form the first patterned mask layer. A first opening pattern is formed in the first patterned mask layer. The first opening pattern defines the position and shape of the shallow trench.

[0016] In one embodiment, a thermal oxidation process is used to form an oxide layer on the sidewall and bottom of the shallow trench as the liner layer, which can effectively eliminate damage formed during the shallow trench etching process.

[0017] In one embodiment, a first drift region surrounding the shallow trench and a second drift region directly below the shallow trench are formed in the substrate:

[0018] forming a second patterned mask layer on the upper surface of the substrate, wherein a second opening pattern is formed in the second patterned mask layer, and the second opening pattern defines the position and shape of the first drift region and the second drift region;

[0019] Performing ion implantation on the substrate based on the second patterned mask layer to form the first drift region and the second drift region;

[0020] The second patterned mask layer is removed.

[0021] In one embodiment, forming the dielectric layer in the shallow trench includes:

[0022] forming a dielectric material layer on the surface of the liner layer;

[0023] The first patterned mask layer on the upper surface of the substrate and the dielectric material layer on the upper surface of the first patterned mask layer are removed, so that the dielectric material layer remaining in the shallow trench is the dielectric layer.

[0024] In one embodiment, the step of annealing the obtained structure comprises:

[0025] The obtained structure is annealed by a wet annealing process or a dry annealing process, and high-temperature well driving is performed on the first drift region and the second drift region.

[0026] In one embodiment, the doping concentration of the first drift region formed in the substrate is less than the doping concentration of the second drift region, and reducing the doping concentration of the first drift region can reduce the risk of breakdown at the corners of the shallow trench isolation structure of the device under high voltage, improve the voltage resistance of the device, and reduce the generation of hot carriers near the channel and gate oxide of the device, thereby improving the HCI reliability of the device.

[0027] In one embodiment, the step of controlling the thickness of the first patterned mask layer and the energy of ion implantation so that the doping concentration of the first drift region is different from the doping concentration of the second drift region comprises:

[0028] A low-energy ion implantation process is used to form a third drift region in the second drift region, and the third drift region includes a third upper drift region and a third lower drift region located directly below the shallow trench, and the third upper drift region is located between the shallow trench and the third lower drift region.

[0029] In one embodiment, the doping concentration of the formed third upper drift region is greater than the doping concentration of the third lower drift region.

[0030] In one embodiment, after forming the dielectric layer in the shallow trench, the method further includes:

[0031] forming a well region in the substrate, wherein the well region is located on one side of the first drift region;

[0032] forming a gate on the upper surface of the substrate;

[0033] A source region, a drain region and a body region are formed in the substrate; the source region is located in the well region and on a side of the gate away from the first drift region; the drain region is located in the first drift region and on a side of the shallow trench away from the well region; the body region is located in the well region and on a side of the source region away from the shallow trench.

[0034] Another aspect of the present application provides a semiconductor structure, including a substrate and a drift region, wherein a shallow trench isolation structure is provided in the substrate, the shallow trench isolation structure including a shallow trench, a liner layer and a dielectric layer, the liner layer being located on the sidewalls and bottom of the shallow trench, the dielectric layer being located in the shallow trench and filling the shallow trench; the drift region being located in the substrate, the drift region including a first drift region surrounding the shallow trench, a second drift region located directly below the shallow trench, and a third drift region formed in the second drift region, wherein the doping concentration of the third drift region adjacent to the bottom area of the shallow trench is greater than the doping concentration of the first drift region.

[0035] In the semiconductor structure of the above embodiment, the damage formed during the process of etching the shallow trench is eliminated during the formation of the liner layer, and a protective layer is provided for the subsequent filling of the shallow trench; the doping concentration of the first drift region is different from the doping concentration of the second drift region, which improves the impurity concentration on the current path and can effectively improve the on-resistance of the device. The depth of the second drift region formed directly below the shallow trench is deeper than the depth of the drift region formed in this part in the traditional semiconductor manufacturing process, which can increase the cross-sectional area of the current flow. The doping concentration of the third drift region formed in the second drift region near the bottom area of the shallow trench is greater than the doping concentration of the first drift region, so that the semiconductor device prepared based on the semiconductor device structure provided by the present application has a higher withstand voltage value and a lower on-resistance; and the semiconductor device structure provided by the present application has fewer process steps, and thus has a lower manufacturing cost and a higher device yield.

[0036] In one embodiment, the semiconductor structure further comprises:

[0037] a gate, located on the upper surface of the substrate;

[0038] a well region, located in the substrate and on one side of the first drift region;

[0039] a source region, located in the well region and on a side of the gate away from the first drift region;

[0040] a drain electrode located in the first drift region and on a side of the shallow trench away from the well region;

[0041] The body region is located in the well region and on a side of the source region away from the shallow trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to better describe and illustrate the embodiments and / or examples of the applications disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed applications, the presently described embodiments and / or examples, and any of the best modes currently understood for these applications.

[0043] Figure 1 Shown is a flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0044] Figures 2 to 4 Shown is a schematic cross-sectional structural diagram of a structure obtained in step S1 of a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0045] Figure 5 Shown is a schematic cross-sectional structural diagram of a structure obtained in step S2 of a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0046] Figures 6 and 7 Shown is a schematic cross-sectional structural diagram of a structure obtained in step S3 of a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0047] Figures 8 and 9 Shown is a schematic cross-sectional structural diagram of a structure obtained in step S5 of a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0048] Figures 10 and 11 Shown is a schematic cross-sectional view of a structure obtained by a method for preparing a semiconductor structure provided in another embodiment of the present application.

[0049] Figure 12 Display as Figure 11 The embodiment shown in FIG is a schematic cross-sectional view of a structure obtained by a conventional process of forming a drift region after forming an STI in a substrate.

[0050] Figure 13 Display as Figure 11The embodiment shown in FIG is a schematic cross-sectional view of a structure obtained in a conventional process of forming a drift region before forming an STI in a substrate.

[0051] Description of reference numerals:

[0052] 10, substrate; 11, first patterned mask layer; 20, shallow trench;

[0053] 30, liner layer; 41, first drift region; 42, second drift region; 43, third drift region;

[0054] 431, the third upper drift region; 432, the third lower drift region;

[0055] 44, well region; 50, dielectric layer; 51, dielectric material layer;

[0056] 60, drain region; 70, gate region; 80, source region; 90, body region. DETAILED DESCRIPTION

[0057] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0059] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0060] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0061] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] Embodiments of the present invention are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present invention should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing. The regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the present invention.

[0063] See also Figures 1-13 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present application. Although the diagrams only show components related to the present application and are not drawn according to the number, shape, and size of components in actual implementation, the type, quantity, and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complex.

[0064] See also Figure 1 In one embodiment of the present application, a method for preparing a semiconductor structure includes the following steps:

[0065] Step S1: providing a substrate, forming a first patterned mask layer on the upper surface of the substrate, and etching the substrate based on the first patterned mask layer to form a shallow trench in the substrate;

[0066] Step S2: forming a liner layer on the sidewall and bottom of the shallow trench;

[0067] Step S3: forming a first drift region surrounding the shallow trench and a second drift region directly below the shallow trench in the substrate, wherein the doping concentration of the first drift region is different from the doping concentration of the second drift region by controlling the thickness of the first patterned mask layer and the energy of ion implantation;

[0068] Step S4: annealing the obtained structure;

[0069] Step S5: forming a dielectric layer in the shallow trench, wherein the dielectric layer fills the shallow trench.

[0070] Specifically, in the method for fabricating a semiconductor structure in the above-described embodiment, a shallow trench is first formed in a substrate, and then a liner layer is formed on the sidewalls and bottom of the shallow trench to eliminate damage caused by etching the shallow trench and provide a protective layer for subsequent filling of the shallow trench. A first drift region surrounding the shallow trench and a second drift region directly below the shallow trench are then formed in the substrate. By controlling the thickness of the first patterned mask layer and the energy of ion implantation, the doping concentration of the first drift region is different from that of the second drift region, thereby improving the impurity concentration in the current path and effectively improving the on-resistance of the device. By utilizing the significant step difference on the substrate surface after forming the shallow trench isolation structure, the depth of the second drift region formed directly below the shallow trench is deeper than the depth of the drift region formed in this area in traditional semiconductor fabrication processes, thereby increasing the cross-sectional area for current flow and further improving the on-resistance of the device. Since the drift region high-temperature well-pushing process is simultaneously achieved during the annealing of the liner layer, compared to the traditional process flow in which high-temperature annealing of the liner layer and high-temperature well-pushing of the ion implantation region are performed in two separate process steps, the process steps are effectively reduced. Therefore, the present application reduces the on-resistance of the device while ensuring a high withstand voltage value of the manufactured semiconductor device, and reduces the process steps, thereby reducing the manufacturing cost of the semiconductor device while improving the yield rate of the manufactured device.

[0071] In step S1, see Figure 1 Step S1 in Figure 2 and Figure 3 , providing a substrate 10, forming a first patterned mask layer 11 on the upper surface of the substrate 10, and etching the substrate 10 based on the first patterned mask layer 11 to form a shallow trench 20 in the substrate 10.

[0072] As an example, the substrate 10 may include, but is not limited to, a silicon substrate, a silicon-germanium substrate, and a silicon-on-insulator substrate. The material of the semiconductor layer is silicon, germanium, or silicon-germanium. Those skilled in the art can select the substrate type based on the type of transistor to be formed on the substrate 10. Therefore, the type of substrate 10 should not limit the scope of protection of this application.

[0073] As an example, step S1 may include the following steps:

[0074] Step S10 : forming a first patterned mask layer 11 on the upper surface of the substrate 10 . An opening (not shown) is formed in the patterned mask layer 11 . The opening defines the position and shape of the shallow trench 20 .

[0075] Step S12 : etching the upper surface of the substrate 10 using a dry etching process or a wet etching process based on the first patterned mask layer 11 to obtain a shallow trench 20 .

[0076] In this embodiment, the dry etching process parameters include: a gas comprising one or more of a fluorocarbon gas, HBr, and Cl2, and a carrier gas. The fluorocarbon gas comprises CF4, CHF3, CH2F2, or CH3F. The carrier gas is an inert gas, such as He. The gas flow rate is 50 sccm-400 sccm, and the pressure is 3 mTorr-8 mTorr. The etchant used in the wet etching process may be a mixed solution of hydrofluoric acid and hydrogen peroxide.

[0077] As an example, the number of shallow trenches 20 in step S12 can be multiple, the depth of each shallow trench can be the same or different; the width of each shallow trench 20 can be the same or different; the depth of the shallow trench 20 is less than the thickness of the substrate 10.

[0078] As an example, forming a first patterned mask layer on the upper surface of the substrate 10 in step S10 may include the following steps:

[0079] Step S101: forming a first mask layer (not shown) on the upper surface of the substrate 10;

[0080] Step S102: coating a first photoresist layer (not shown) on the upper surface of the first mask layer (not shown), and performing a patterning process to form a first patterned photoresist layer (not shown);

[0081] Step S103: etching the first mask layer based on the first patterned photoresist layer to form the first patterned mask layer 11, wherein a first opening pattern is formed in the first patterned mask layer 11, and the first opening pattern defines the position and shape of the shallow trench;

[0082] Step S104: removing the first patterned photoresist layer.

[0083] As an example, the first patterned mask layer formed may include a hard mask layer, which may be a single-layer structure or a multi-layer stacked structure, and its material may be silicon oxide; then, a photoresist is coated on the hard mask layer, and a series of steps such as exposure and development are performed to form a patterned photoresist layer, the patterned photoresist layer defining the position and shape of the shallow trench, and then the hard mask layer is etched based on the patterned photoresist layer to form a patterned mask layer, and then the patterned photoresist layer is removed. Of course, in other embodiments of the present application, the patterned photoresist layer may also be retained during the process of forming the first patterned mask layer, and the patterned photoresist layer may be removed after etching the substrate.

[0084] In step S2, see Figure 1 The S2 step in Figure 4 A liner layer 30 is formed on the sidewalls and bottom of the shallow trench 20 , and the liner layer 30 covers the surface of the shallow trench 20 and the upper surface of the substrate 10 .

[0085] As an example, an oxidation process can be used to form a liner layer 30 on the sidewalls and bottom of the shallow trench 20. The oxidation process includes a thermal oxidation process, a wet oxidation process, or a chemical oxidation process. In the present application, a thermal oxidation process is preferably used to form the liner layer 30 on the surface of the shallow trench 20 and the upper surface of the substrate 10. The liner layer 30 may include, but is not limited to, a silicon oxide layer.

[0086] As an example, a thermal oxidation process can be used to form a liner layer 30 on the sidewalls and bottom of the shallow trench 20. The thermal oxidation process of forming the liner layer 30 can repair damage to the surface of the substrate 10 caused by the previous etching process. Furthermore, the liner layer 30 can protect the surface of the substrate 10 during subsequent processes.

[0087] As an example, see Figure 5 , step S3 may include the following steps:

[0088] Step S32 : forming a second patterned mask layer (not shown) on the upper surface of the substrate, wherein a second opening pattern (not shown) is formed in the second patterned mask layer, and the second opening pattern defines the position and shape of the first drift region 41 and the second drift region 42 .

[0089] Step S34 : performing ion implantation on the substrate 10 based on the second patterned mask layer to form the first drift region 41 and the second drift region 42 .

[0090] As an example, see Figure 6-Figure 7 , step S3 may include the following steps:

[0091] right Figure 5 The obtained structure is processed by ion implantation process to form a first drift region 41 surrounding the shallow trench 20 and a second drift region 42 located directly below the shallow trench in the substrate 10, wherein the doping concentration of the first drift region 41 is different from the doping concentration of the second drift region 42 by controlling the thickness of the first patterned mask layer 11 and the energy of the ion implantation.

[0092] As an example, see Figure 6 , in the right Figure 5During the ion implantation process of the structure obtained, the doping concentration of the first drift region 41 is lower than that of the second drift region 42 due to the blocking effect of the first patterned mask layer 11. Due to the presence of the shallow trench isolation structure, during the ion implantation process to form the second drift region 42, compared to the ion implantation process before the shallow trench isolation structure is formed, a lower ion implantation energy can be used, resulting in a greater depth of the formed second drift region 42, which is beneficial for widening the current path in the drift region.

[0093] As an example, see Figure 7 , you can Figure 5 In the process of ion implantation for treating the obtained structure, the energy values of the ions implanted to form the first drift region 41 and the second drift region 42 are controlled to be different. For example, a low-energy ion implantation process can be added to form the third drift region 43 in the second drift region 42, and the formed third drift region 43 includes a third upper drift region 431 and a third lower drift region 432 located directly below the shallow trench 20, wherein the third upper drift region 431 is located between the shallow trench 20 and the third lower drift region 432, and the bottom of the third drift region 43 is lower than the bottom of the third lower drift region 432; and in the low-energy ion implantation process, the first drift region 41 is shielded by the first patterned mask layer on the top surface, so that after the low-energy ion implantation process, the doping concentration of the first drift region 41 is less than the doping concentration of the third upper drift region 431, and the doping concentration of the third upper drift region 431 is greater than the doping concentration of the third lower drift region 432, which is beneficial to reducing the on-resistance while increasing the cross-sectional area of the current flow path. Figure 7 , it is indicated that the bottom of the first drift region 41 is lower than the bottom of the shallow trench 20 . In other embodiments of the present application, the bottom of the first drift region 41 may be higher than or equal to the bottom of the shallow trench 20 .

[0094] As an example, in step S4, Figure 7 The resulting structure is subjected to a high-temperature annealing treatment, and a high-temperature well-pushing process is simultaneously performed on the first drift region 41 and the second drift region 42, thereby densifying the surface of the liner layer 30 and repairing the voids in the liner layer 30. The annealing process can be a wet annealing process or a dry annealing process; the parameters of the annealing process may include: a temperature of 800°C to 1500°C, for example, the annealing temperature may be 800°C, 900°C, 1000°C, 1100°C, 1200°C, 1300°C, 1400°C, or 1500°C; the annealing gas includes one or more combinations of H2, O2, N2, Ar, and He; and the annealing time is 1.5 hours to 2.5 hours, for example, the annealing time may be 1.5 hours, 2.0 hours, or 2.5 hours. When the annealing gas includes H2 and O2, the annealing process is a wet annealing process.

[0095] As an example, see Figure 8 and Figure 9 , step S5 may include the following steps:

[0096] Step S52: forming a dielectric material layer 51 on the surface of the liner layer 30;

[0097] Step S54 : removing the first patterned mask layer 11 on the upper surface of the substrate 10 and the dielectric material layer 51 on the upper surface of the first patterned mask layer 11 , so that the dielectric material layer remaining in the shallow trench is the dielectric layer 50 .

[0098] For example, see Figure 8 The dielectric material layer 51 in step S52 may be formed by one or more of a flowable chemical vapor deposition (FCVD) process, a high-density plasma (HDP) process, and a plasma-enhanced deposition process. In this application, the HDP process is preferably used to form the dielectric material layer 51 on the surface of the liner layer 30. The dielectric material layer 51 includes, but is not limited to, silicon oxide.

[0099] As an example, see Figure 10 In step S54, a chemical mechanical polishing process can be used to remove the first patterned mask layer 11 located on the upper surface of the substrate 10 and the dielectric material layer 51 located on the upper surface of the first patterned mask layer 11; preferably, before chemical mechanical polishing, the dielectric material layer 51 is subjected to water vapor annealing to release stress, densify the dielectric material layer 51, and repair the gaps in the dielectric material layer 51.

[0100] As an example, see Figure 10 , after forming the dielectric layer in the shallow trench, the method further includes:

[0101] Step S62: forming a well region in the substrate, wherein the well region is located on one side of the first drift region.

[0102] As an example, see Figure 10 , an ion implantation process may be used to form a well region 44 in the substrate 10 , and the well region 44 is located on one side of the first drift region.

[0103] Step S64: forming a gate 70 on the upper surface of the substrate 10;

[0104] Step S66: forming a source region 80, a drain region 60 and a body region 90 in the substrate 10; the source region 80 is located in the well region 44 and is located on the side of the gate 70 away from the first drift region; the drain region 60 is located in the first drift region and is located on the side of the shallow trench away from the well region 44; the body region 90 is located in the well region 44 and is located on the side of the source region 80 away from the shallow trench.

[0105] As an example, see Figure 11 In one embodiment of the present application, a semiconductor structure is provided, including a substrate 10 and a drift region, wherein a shallow trench isolation structure is provided in the substrate 10, wherein the shallow trench isolation structure includes: a shallow trench, a liner layer 30 and a dielectric layer 50, wherein the liner layer 30 is located on the sidewall and bottom of the shallow trench, and the dielectric layer 50 is located in the shallow trench and fills the shallow trench; the drift region is located in the substrate 10; the drift region includes a first drift region 41 surrounding the shallow trench, a second drift region 42 located directly below the shallow trench, and a third drift region 43 formed in the second drift region 42, wherein the doping concentration of the third drift region 43 adjacent to the bottom area of the shallow trench is greater than the doping concentration of the first drift region.

[0106] For details, please refer to Figure 11 In the process of forming the liner layer 30, the damage caused by etching the shallow trench is eliminated, and a protective layer is provided for the subsequent filling of the shallow trench; the doping concentration of the first drift region 41 is different from the doping concentration of the second drift region 42, which improves the impurity concentration on the current path and can effectively improve the on-resistance of the device. Figure 11 and Figure 12 、 13 It can be found that in the semiconductor structure provided by the present application, not only is the doping concentration of the drift region near the bottom of the shallow trench significantly higher than the doping concentration of the corresponding portion of the semiconductor structure prepared using a conventional process, but the depth of the second drift region is also deeper than the depth of the drift region formed in this portion in a conventional semiconductor fabrication process, which is beneficial for widening the current path and can effectively reduce the on-resistance of the device. Therefore, the semiconductor device fabricated based on the semiconductor device structure provided by the present application has a higher withstand voltage and a lower on-resistance; and the semiconductor device structure provided by the present application has fewer process steps, thus having a lower manufacturing cost and a higher device yield.

[0107] As an example, see Figure 11The third drift region 43 formed includes a third upper drift region 431 and a third lower drift region 432 located directly below the shallow trench. The third upper drift region 431 is located between the shallow trench and the third lower drift region 432. The doping concentration of the third upper drift region 431 can be set to be greater than the doping concentration of the first doping region 41, thereby reducing the on-resistance of the device while ensuring the high withstand voltage value of the semiconductor device, and at the same time increasing the cross-sectional area of the current flow path.

[0108] In one embodiment of this application, please continue to refer to Figure 11 The semiconductor structure further includes a drain 60, a gate 70, a source region 80, a body region 90 and a well region 44, wherein the gate 70 is located on the upper surface of the substrate 10; the well region 44 is located in the substrate 10 and on one side of the first drift region; the source region 80 is located in the well region 44 and on a side of the gate 70 away from the first drift region; the drain 60 is located in the first drift region and on a side of the shallow trench away from the well region 44; the body region 90 is located in the well region 44 and on a side of the source region 80 away from the shallow trench.

[0109] As an example, the number of shallow trenches 20 formed in the substrate 10 can be set according to actual needs. The number of shallow trenches 20 can be one or more.

[0110] In summary, the present application provides a method for fabricating a semiconductor structure and a semiconductor structure. During the formation of a liner layer, damage caused by etching a shallow trench is eliminated, while providing a protective layer for subsequent filling of the shallow trench. A first drift region surrounding the shallow trench and a second drift region located directly below the shallow trench are then formed within the substrate. By controlling the thickness of the first patterned mask layer and the energy of ion implantation, the doping concentration of the first drift region is different from that of the second drift region, thereby improving the impurity concentration in the current path. The doping concentration of a third drift region formed within the second drift region adjacent to the bottom of the shallow trench can be set to be greater than that of the first drift region, effectively improving the on-resistance of the device. By utilizing the significant step difference on the substrate surface after the shallow trench isolation structure is formed, the depth of the second drift region formed directly below the shallow trench is deeper than that of the drift region formed in this location in conventional semiconductor fabrication processes, thereby increasing the cross-sectional area for current flow and further improving the on-resistance of the device. Since the drift region high-temperature well-pushing process is simultaneously achieved during the annealing of the liner layer, compared to the traditional process flow in which high-temperature annealing of the liner layer and high-temperature well-pushing of the ion implantation region are performed in two separate process steps, the process steps are effectively reduced. Therefore, the present application reduces the on-resistance of the device while ensuring a high withstand voltage value of the manufactured semiconductor device, and reduces the process steps, thereby reducing the manufacturing cost of the semiconductor device while improving the yield rate of the manufactured device.

[0111] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, forming a first patterned mask layer on an upper surface of the substrate, and etching the substrate based on the first patterned mask layer to form a shallow trench in the substrate; forming a liner layer on the sidewall and bottom of the shallow trench; forming a second patterned mask layer on the upper surface of the substrate, wherein a second opening pattern is formed in the second patterned mask layer, and the second opening pattern defines the position and shape of the first drift region and the second drift region; Ion implantation is performed on the substrate based on the second patterned mask layer to form the first drift region surrounding the shallow trench and the second drift region directly below the shallow trench in the substrate; wherein the doping concentration of the first drift region is lower than the doping concentration of the second drift region by controlling the thickness of the first patterned mask layer and the energy of the ion implantation to utilize the blocking effect of the first patterned mask layer; performing an annealing treatment on the obtained structure and performing high temperature well driving on the first drift region and the second drift region; A dielectric layer is formed in the shallow trench, and the dielectric layer fills the shallow trench.

2. The method for preparing a semiconductor structure according to claim 1, wherein: Forming a first patterned mask layer on the upper surface of the substrate includes: forming a first mask layer on the upper surface of the substrate; Coating a first photoresist layer on the upper surface of the first mask layer and performing patterning to form a first patterned photoresist layer; The first mask layer is etched based on the first patterned photoresist layer to form the first patterned mask layer. A first opening pattern is formed in the first patterned mask layer. The first opening pattern defines the position and shape of the shallow trench.

3. The method for preparing a semiconductor structure according to claim 1, wherein: A thermal oxidation process is adopted to form an oxide layer on the sidewall and bottom of the shallow trench as the liner layer.

4. The method for preparing a semiconductor structure according to claim 1, wherein: After performing ion implantation on the substrate based on the second patterned mask layer to form the first drift region and the second drift region, the method further includes: The second patterned mask layer is removed.

5. The method for preparing a semiconductor structure according to claim 1, wherein: Forming the dielectric layer in the shallow trench includes: forming a dielectric material layer on the surface of the liner layer; The first patterned mask layer on the upper surface of the substrate and the dielectric material layer on the upper surface of the first patterned mask layer are removed, so that the dielectric material layer remaining in the shallow trench is the dielectric layer.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The process used for annealing the obtained structure includes a wet annealing process or a dry annealing process.

7. The method for preparing a semiconductor structure according to claim 1, wherein: The doping concentration of the first drift region formed in the substrate is lower than the doping concentration of the second drift region.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that: The step of controlling the thickness of the first patterned mask layer and the energy of ion implantation so that the doping concentration of the first drift region is different from the doping concentration of the second drift region comprises: A low-energy ion implantation process is used to form a third drift region in the second drift region, and the third drift region includes a third upper drift region and a third lower drift region located directly below the shallow trench, and the third upper drift region is located between the shallow trench and the third lower drift region.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The doping concentration of the formed third upper drift region is greater than the doping concentration of the third lower drift region.

10. The method for preparing a semiconductor structure according to claim 9, wherein: After forming the dielectric layer in the shallow trench, the method further includes: forming a well region in the substrate, wherein the well region is located on one side of the first drift region; forming a gate on the upper surface of the substrate; A source region, a drain region and a body region are formed in the substrate; the source region is located in the well region and on a side of the gate away from the first drift region; the drain region is located in the first drift region and on a side of the shallow trench away from the well region; the body region is located in the well region and on a side of the source region away from the shallow trench.

11. A semiconductor structure, characterized in that The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 10; The semiconductor structure comprises: A substrate having a shallow trench isolation structure provided therein, the shallow trench isolation structure comprising: a shallow trench, a liner layer, and a dielectric layer, the liner layer being located on the sidewalls and bottom of the shallow trench, the dielectric layer being located in the shallow trench and filling the shallow trench; A drift region is located in the substrate, and the drift region includes a first drift region surrounding the shallow trench, a second drift region located directly below the shallow trench, and a third drift region formed in the second drift region, wherein the doping concentration of the first drift region is less than the doping concentration of the second drift region; the doping concentration of the third drift region near the bottom of the shallow trench is greater than the doping concentration of the first drift region.

12. The semiconductor structure according to claim 11, wherein: Also includes: a gate, located on the upper surface of the substrate; a well region, located in the substrate and on one side of the first drift region; a source region, located in the well region and on a side of the gate away from the first drift region; a drain electrode located in the first drift region and on a side of the shallow trench away from the well region; The body region is located in the well region and on a side of the source region away from the shallow trench.

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