A large-size chip design layout structure

Abstract

The application discloses a large-size chip design layout structure, which comprises a plurality of splicing modules, each of which is less than or equal to the maximum exposure field of view of a photoetcher; a light-shielding belt arranged at a splicing position of any two adjacent splicing modules; and a cutting path located at an edge position of the splicing module except the splicing position. In addition, the structure further comprises a bonding alignment mark arranged in the cutting path; and an auxiliary mark arranged in the cutting path and located at a position adjacent to the bonding alignment mark. The auxiliary mark is a directional mark. When a plurality of bonding alignment marks appear in the photoetching exposure field of view, the directional auxiliary mark can be used to accurately identify which alignment mark should be used for alignment, thereby improving the alignment precision of wafer bonding.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing process, and particularly relates to a large-size chip design layout structure. BACKGROUND

[0002] At present, the larger the size of a complementary metal oxide semiconductor (CMOS) image sensor is, the larger the photosensitive area is, the larger the area of a photosensitive device is, the more photons are captured, the better the photosensitive performance is, the higher the signal-to-noise ratio is, and the better the imaging effect is. For example, some full-frame digital cameras, medical imaging and other professional imaging application fields need to use large-size image sensors. However, the maximum size of a single exposure field is limited, and the size of these large-size image sensors exceeds the maximum size of a single exposure field of a photolithography machine, so a splicing technology needs to be used in the manufacturing process. The splicing technology, as the name implies, is to divide the involved patterns into sub-regions, expose them one by one, and finally splice them into a large-size image sensor.

[0003] The pixel structure of a CMOS image sensor also experiences a trend from a previous front-illuminated pixel structure to a back-illuminated pixel structure, and now the back-illuminated pixel structure has basically become mainstream. Because of the front-illuminated structure, the incident light needs to pass through the metal interconnection layer and the dielectric layer before reaching the photosensitive region, and the incident light is lost to a certain extent in this process. The back-illuminated pixel structure allows the incident light to directly enter the photosensitive region, with almost no loss in between, and the fill factor can basically reach 100%, greatly improving the sensitivity performance.

[0004] The back-illuminated pixel structure needs to be realized through a back-illumination process, which is completed on the basis of a front-illumination process. Now the device and metal interconnection process in the front-illumination process is completed. Then the back-illumination process is entered, mainly including wafer bonding, thinning, etching of pads and other processes. The quality of wafer bonding is a key factor for whether the subsequent back-illumination process can continue. If the bonding fails, the wafer may be directly scrapped at the bonding stage, or the bonding precision is not high, which may lead to the failure of the subsequent process and finally face the risk of scrapping.

[0005] At present, in order to improve the bonding precision, specific positions are selected to place bonding alignment marks at the time of publication, so that the bonding machine can identify the bonding alignment marks, so that the two silicon wafers can find the bonding alignment marks for alignment when bonding. Generally, multiple sets of bonding alignment marks are placed, and the positions are placed as far apart as possible on the mask plate. However, for splicing products, the alignment marks originally placed far apart on the mask plate may be very close after the actual splicing process, for example, fromFigure 1 As shown in the partial enlarged view of the elliptical region, the three alignment marks are close to each other, so that several groups of alignment marks can be seen in the lithography field of view, but it is impossible to automatically identify which alignment mark should be used for alignment, and alignment error can occur, resulting in abnormal wafer bonding or poor precision.

[0006] Therefore, how to monitor and compensate the splicing precision of the splicing lithography process is a problem to be solved by those skilled in the art. SUMMARY

[0007] The embodiment of the present application provides a large-size chip design layout structure, which is used to improve the alignment precision of back-illumination large-size chip wafer bonding.

[0008] In a first aspect, the present application provides a large-size chip design layout structure, which comprises: a plurality of splicing modules, each of the splicing modules being less than or equal to the maximum exposure field of view of a lithography machine; a light-shielding belt arranged at a splicing position of any two adjacent splicing modules; a cutting path located at an edge position of the splicing module except the splicing position; a bonding alignment mark arranged in the cutting path; and an auxiliary mark arranged in the cutting path and located at a position adjacent to the bonding alignment mark, the auxiliary mark being a directional mark.

[0009] The large-size chip design layout structure provided by the present application has the beneficial effect that the auxiliary mark in the structure is directional, so that the shapes of auxiliary marks in different directions are different, and the auxiliary mark helps to identify which bonding alignment mark should be used for alignment during wafer bonding, thereby avoiding alignment error.

[0010] Optionally, the auxiliary mark and the bonding alignment mark form a group of directional alignment marks.

[0011] Optionally, the auxiliary mark and the bonding alignment mark need to be in the same exposure field of view of a lithography machine, but the distance between the auxiliary mark and the bonding alignment mark is not fixed, and there is no need to specify a minimum distance, the auxiliary mark helps to identify which bonding alignment mark should be used for alignment, thereby avoiding alignment error.

[0012] Optionally, the width of the light-shielding belt is greater than or equal to 60 um.

[0013] Optionally, the width of the cutting path is greater than or equal to 60 um.

[0014] Optionally, the bonding alignment mark is one or more.

[0015] Optionally, the auxiliary mark is an auxiliary mark which is asymmetric in up-down direction and / or asymmetric in left-right direction.

[0016] Optionally, the bonding alignment mark is a photolithography bonding alignment mark.

[0017] Optionally, the splicing module is a small-size pattern.

[0018] Compared with the prior art, the large-size chip design layout structure provided by the application can identify which bonding alignment mark should be used for alignment by means of the auxiliary mark even if several groups of bonding alignment marks appear in the field of view of photolithography exposure, thereby improving the back-illumination large-size chip wafer bonding alignment precision. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0020] Figure 1 A design layout structure schematic diagram provided by the prior art;

[0021] Figure 2 A large-size chip design layout structure schematic diagram provided by the embodiment of the application;

[0022] Figure 3 Another large-size chip design layout structure schematic diagram provided by the embodiment of the application;

[0023] Figures 4 to 7 A shape schematic diagram of an auxiliary mark provided by the embodiment of the application.

[0024] Element number explanation

[0025] 100 splicing module

[0026] 11 light shielding belt

[0027] 22 cutting path

[0028] 33 bonding alignment mark

[0029] 44 auxiliary mark DETAILED DESCRIPTION

[0030] In order to make the content of the application more clear and easy to understand, the content of the application will be further described in combination with the drawings of the specification. Of course, the application is not limited to this specific embodiment, and general substitutions well known by those skilled in the art are also covered by the protection scope of the application.

[0031] It should be noted that in the following detailed description, in order to clearly show the structure of the present application in order to facilitate the description, the structure in the drawings is not drawn according to the general proportion, and is partially enlarged, deformed and simplified, therefore, it should be avoided to be understood as the limitation of the present application.

[0032] According to the application purpose of the present application, the present application provides a large-size chip design layout structure, as shown in the accompanying drawings, comprising: a plurality of splicing modules 100, a light shielding belt 11, a cutting path 22, a bonding alignment mark 33 and an auxiliary mark 44. Figure 2

[0033] Specifically, a plurality of splicing modules 100, each of which is less than or equal to the maximum exposure field of view of the photolithography machine. That is, a chip design layout larger than the maximum exposure field of view of the photolithography machine is divided into a plurality of splicing design layouts smaller than or equal to the maximum exposure field of view of the photolithography machine, which is suitable for large-size chips, and the large-size chips can include image sensor type chips. Exemplarily, the maximum exposure field of view of the photolithography machine is 26mm x 33mm. Figure 2 Splicing module A, splicing module B, splicing module C, splicing module D, splicing module E, splicing module F and splicing module G are shown. As shown in Figure 2 The splicing module is a small-size pattern such as a square, and it should be noted that Figure 2 The number of splicing modules and the pattern shape in the above are only an example, and the actual chip can be a chip design layout structure composed of more or fewer splicing modules.

[0034] In this embodiment, the light shielding belt 11 is arranged at the splicing position of any two adjacent splicing modules 100. In a possible implementation, the width of the light shielding belt 11 can be 60um or more. Alternatively, the light shielding belt 11 can be composed of a light-proof material such as metal chromium covered on the mask, which is mainly used to shield the edge of the adjacent non-exposed area when the target area is exposed. Exemplarily, in combination with Figure 2 The light shielding belt 11 is located at the splicing position between the splicing module A and the splicing module B, the light shielding belt 11 is located at the splicing position between the splicing module B and the splicing module D, the light shielding belt 11 is located at the splicing position between the splicing module D and the splicing module F, and the like, which can be referred to in detail in Figure 2 which will not be described here.

[0035] In this embodiment, the cutting path 22 is located at the edge position of the splicing module 100 except the splicing position. Alternatively, the width of the cutting path is 60um or more.

[0036] ​In this embodiment, the bonding alignment mark 33 is located in the cutting path 22. There can be one or more bonding alignment marks; exemplarily, the bonding alignment mark 33 is... Figure 3 The cross-shaped mark shown.

[0037] In this embodiment, an auxiliary mark 44 with directional markings is also placed in the dicing path 22, and positioned adjacent to the bonding alignment mark 33. This embodiment does not limit the distance between the bonding alignment mark 33 and the auxiliary mark 44; the auxiliary mark and the bonding alignment mark only need to be in the same lithography exposure field. The auxiliary mark 44 and the bonding alignment mark 33 can form a set of directional alignment marks.

[0038] like Figure 3 As shown, because auxiliary marks 44 are provided adjacent to the bonding alignment marks 33 in the large-size chip design layout, even if alignment marks belonging to different chips are very close together after the actual splicing process, such as... Figure 3 As can be seen from the magnified view of the elliptical region, the three alignment marks are relatively close together. However, because the auxiliary mark 44 is a directional mark, the shape of the auxiliary marks in different directions is different. During wafer bonding, the auxiliary marks help to identify which bonding alignment mark should be used for alignment, thus avoiding alignment errors.

[0039] It should be noted that the auxiliary markers in this embodiment can be various directional markers, and these directional markers have asymmetrical shapes, either vertically or horizontally. One possible scenario is that the auxiliary markers can be as follows: Figure 4 The L-shaped auxiliary mark shown, Figure 4 The auxiliary marker shown in (a) is Figure 4 The auxiliary marker shown in (b) is Figure 4 The auxiliary markers shown in (c) and Figure 4 The auxiliary markers shown in (d) have different orientations, so they can be distinguished from the bonding alignment markers.

[0040] In another possible scenario, auxiliary markers could be such as Figure 5 The T-shaped auxiliary mark shown Figure 5 The auxiliary marker shown in (a) is Figure 5 The auxiliary marker shown in (b) is Figure 5 The auxiliary markers shown in (c) and Figure 5 The auxiliary markers shown in (d) have different orientations, so they can be distinguished from the bonding alignment markers.

[0041] In another possible scenario, auxiliary markers could be as follows: Figure 6 The T-shaped auxiliary mark shownFigure 6 The auxiliary marker shown in (a) is Figure 6 The auxiliary marker shown in (b) is Figure 6 The auxiliary markers shown in (c) and Figure 6 The auxiliary markers shown in (d) have different orientations, so they can be distinguished from the bonding alignment markers.

[0042] In other possible cases, auxiliary markers can be such as Figure 7 The F-shaped auxiliary mark shown, Figure 7 The auxiliary marker shown in (a) is Figure 7 The auxiliary marker shown in (b) is Figure 7 The auxiliary markers shown in (c) and Figure 7 The auxiliary markers shown in (d) have different orientations, so they can be distinguished from the bonding alignment markers.

[0043] It should be noted that the above graphic examples are only for illustrating auxiliary markers and do not constitute a limitation on auxiliary markers.

[0044] The above description is merely a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made based on the description and drawings of the present invention should also be included within the scope of protection of the present invention. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.

[0045] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A large chip design layout structure, characterized in that, The structure comprises: a plurality of stitching modules, each of the stitching modules being less than or equal to the maximum exposure field of view of a photolithography machine; a light-shielding belt arranged at a stitching position of any two adjacent stitching modules; a cutting track located at an edge position of the stitching module other than the stitching position; a bonding alignment mark disposed in the cutting track; an auxiliary mark disposed in the cutting track and located adjacent to the bonding alignment mark, the auxiliary mark being a directional mark; the auxiliary mark and the bonding alignment mark are in the same exposure field of view of a photolithography machine.

2. The chip design layout structure of claim 1, wherein, The auxiliary mark and the bonding alignment mark form a set of directional alignment marks.

3. The chip design layout structure according to any one of claims 1 to 2, wherein, The width of the light-shielding belt is greater than or equal to 60 um.

4. The chip design layout structure according to any one of claims 1 to 2, wherein, The width of the cutting track is greater than or equal to 60 um.

5. The chip design layout structure according to any one of claims 1 to 2, wherein, The bonding alignment mark is one or more.

6. The chip design layout structure according to any one of claims 1 to 2, wherein, The auxiliary mark is an up-down asymmetric and / or left-right asymmetric auxiliary mark.

7. The chip design layout structure according to any one of claims 1 to 2, wherein, The bonding alignment mark is a photolithography bonding alignment mark.

8. The chip design layout structure according to any one of claims 1 to 2, wherein, The stitching module is a small-size pattern.

9. The chip design layout structure according to any one of claims 1 to 2, wherein, The large-size chip includes a chip of an image sensor type.

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