Semiconductor device and method of manufacturing the same

Abstract

The present application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a gate stack structure located on the substrate; a plurality of openings penetrating the gate stack structure; a slot penetrating the gate stack structure; a sacrificial layer, a barrier layer, and a contact structure located in the slot; an insulating layer for forming a first air gap in the plurality of openings and achieving electrical isolation between the barrier layer, the contact structure, and the gate stack structure, wherein the contact structure penetrates the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and a part of the barrier layer extends above the sacrificial layer. The semiconductor device increases the distance between the first end and the second end of the barrier layer and the contact structure, thereby greatly reducing the possibility of the second air gap contacting the contact structure, and improving the yield and reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and more particularly, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The development direction of semiconductor technology is the reduction of feature size and the improvement of integration degree. For storage devices, the improvement of the storage density of storage devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller and smaller, the storage density of storage devices becomes higher and higher.

[0003] In the manufacturing process of semiconductor devices, an air gap is increasingly used as a dielectric layer. Using an air gap as a dielectric layer has many advantages. For example, the use of an air gap is conducive to the reduction of feature size. In addition, in the manufacturing process of NAND flash memory chips, the use of an air gap is also conducive to reducing the mutual interference between word lines, thereby facilitating the reduction of signal interference in flash memory chips to a relatively low level.

[0004] However, during the formation of the air gap, parasitic voids are often formed simultaneously. Since the feature size of semiconductor manufacturing processes is getting smaller and smaller, once these parasitic voids are close to the key structures of semiconductor devices, the yield and reliability of semiconductor devices will be greatly reduced, and they may even become unusable. Please refer to Figure 1 , Figure 1 is a cross-sectional image of a NAND semiconductor device observed by a scanning electron microscope. In the process step of forming the air gap 1, parasitic voids 2 and 2' are formed between the select tubes. The voids 2 and 2' are respectively close to the contact structures 3 and 3' (contact holes) between the select tubes. Among them, the void 2' is close to the contact structure 3' to the extent of mutual contact. Therefore, the void 2' has caused great adverse effects on this semiconductor device. The above situation is extremely common in the manufacturing process of semiconductor devices.

[0005] Therefore, it is desirable to further improve semiconductor devices and their manufacturing methods to improve the yield and reliability of semiconductor devices. Summary of the Invention

[0006] In view of the above problems, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are conducive to increasing the distances between the first end and the second end of the barrier layer and the contact structure, thereby reducing the possibility of the second air gap coming into contact with the contact structure, and improving the yield and reliability of the semiconductor device.

[0007] A semiconductor device provided according to the present disclosure includes: a substrate; a gate stack structure located on the substrate; a plurality of openings penetrating the gate stack structure to form a plurality of word lines separated from each other in the gate stack structure; a slot penetrating the gate stack structure to form a first selection control gate line and a second selection control gate line for controlling adjacent selection transistors in the gate stack structure, the slot isolating the first selection control gate line from the second selection control gate line; a sacrificial layer, a barrier layer, and a contact structure located in the slot; a bit line located above the substrate, the bit line being electrically connected to a common source-drain region of the adjacent selection transistors via the contact structure; an insulating layer for forming a first air gap in the plurality of openings and achieving electrical isolation between the barrier layer, the contact structure, and the gate stack structure, wherein the contact structure penetrates the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and a part of the barrier layer extends above the sacrificial layer.

[0008] Optionally, a second air gap is provided at the first end and / or the second end of the barrier layer.

[0009] Optionally, the insulating layer includes a first oxide layer, a third oxide layer, a fourth oxide layer, and a fifth oxide layer. The first oxide layer, the sacrificial layer, the third oxide layer, the barrier layer, and the fourth oxide layer are sequentially stacked on the substrate. The fifth oxide layer at least fills a cavity formed by removing the sacrificial layer and the barrier layer on the sidewall of the slot, thereby forming the second air gap.

[0010] Optionally, the sacrificial layer and the barrier layer are made of the same material.

[0011] Optionally, the thickness of the barrier layer is less than the thickness of the sacrificial layer.

[0012] Optionally, the semiconductor device further includes a third air gap located above the sacrificial layer.

[0013] A manufacturing method of a semiconductor device according to the present disclosure is characterized by comprising: forming a gate stack structure on a substrate; forming a plurality of openings penetrating the gate stack structure to form a plurality of word lines separated from each other in the gate stack structure; forming a slot penetrating the gate stack structure to form a first selection control gate line and a second selection control gate line for controlling adjacent selection transistors in the gate stack structure, the slot isolating the first selection control gate line from the second selection control gate line; forming a first oxide layer covering sidewalls of the plurality of word lines and sidewalls of the first selection control gate line and the second selection control gate line; forming a sacrificial layer filling and covering a gap between sidewalls of the plurality of word lines and the first oxide layer; forming a second oxide layer covering the sacrificial layer; partially removing the sacrificial layer, the first oxide layer, and the second oxide layer in the slot to form an implantation window; removing the remaining second oxide layer; sequentially forming a third oxide layer, a barrier layer, and a fourth oxide layer; partially removing the sacrificial layer and the barrier layer to form a first air gap between the plurality of word lines; forming a fifth oxide layer covering the gate stack structure, the openings, and the slot; forming a contact structure in the slot.

[0014] Optionally, the sacrificial layer and the barrier layer are made of the same material.

[0015] Optionally, after forming the sacrificial layer, it further comprises: performing ion implantation on the substrate through the implantation window to form a common source-drain region of the adjacent selection transistors.

[0016] Optionally, after forming the implantation window, the sacrificial layer in the slot is in an "L" shape.

[0017] Optionally, the contact structure penetrates the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and a part of the barrier layer extends above the sacrificial layer.

[0018] A semiconductor device according to the present disclosure is characterized by comprising: a substrate; a gate stack structure on the substrate, the gate stack structure including a gate stack of a storage unit and a gate stack of a selection transistor; wherein, between gate stacks of two adjacent selection transistors, there are a sacrificial layer, a barrier layer, an insulating layer, and a contact structure penetrating the barrier layer and the insulating layer, the contact structure connecting common source-drain regions of the two adjacent selection transistors, the sacrificial layer and the barrier layer are separated by the insulating layer, and a part of the barrier layer extends above the sacrificial layer.

[0019] Optionally, the semiconductor device further comprises a first air gap between gate stacks of adjacent storage units.

[0020] Optionally, the sacrificial layer and the barrier layer are made of the same material.

[0021] Optionally, the thickness of the blocking layer is less than the thickness of the sacrificial layer.

[0022] Optionally, the semiconductor structure further includes second air gaps located on both sides of the blocking layer.

[0023] Optionally, the semiconductor device is a NAND flash memory.

[0024] The semiconductor device and the manufacturing method thereof provided by the present invention reduce the sidewall thickness of the sacrificial layer, so that the third oxide layer and the blocking layer are also offset in a direction away from the contact structure accordingly. Therefore, in the finally formed semiconductor device, the blocking layer is stepped, increasing the distances between the first end portion and the second end portion of the blocking layer and the contact structure. Also, since the second air gap is connected to the contact structure via the blocking layer, the possibility of the second air gap coming into contact with the contact structure is greatly reduced, improving the yield and reliability of the semiconductor device. Description of the Drawings

[0025] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0026] Figure 1 A cross-sectional image of a semiconductor device according to the prior art is shown;

[0027] Figure 2 An example layout diagram of a semiconductor device according to an embodiment of the present invention is shown;

[0028] Figure 3 A partial perspective view of a memory cell string is shown;

[0029] Figure 4a A cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention taken along Figure 2 line A - A' is shown;

[0030] Figure 4b Shown is Figure 4a A partial enlarged view of the BB region in

[0031] Figures 5a to 5h Cross-sectional schematic diagrams of various stages of a manufacturing method of a semiconductor device according to an embodiment of the present invention are shown. Detailed Description of the Embodiments

[0032] The present invention will be described in more detail below with reference to the drawings. In the respective drawings, like elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps may be described in one drawing.

[0033] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or the other region, or there may be other layers or regions between it and the other layer or the other region. And if the device is flipped, this layer or region will be "below" or "beneath" the other layer or the other region.

[0034] If it is for describing the case of being directly above another layer or another region, in this text, the expressions "directly on..." or "on... and adjacent thereto" will be adopted.

[0035] Many specific details of the present invention are described hereinafter, such as the structure, materials, dimensions, processing techniques and technologies of the device, so as to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0036] The present invention can be presented in various forms, and some examples will be described hereinafter.

[0037] Figure 2 An example layout diagram of a semiconductor device according to an embodiment of the present invention is shown; Figure 3 A partial perspective view of a memory cell string is shown; Figure 4a An embodiment of a semiconductor device according to the present invention is shown along Figure 2 A schematic cross-sectional view taken along line A-A' is shown; Figure 4b Shown is Figure 4a A partial enlarged view of the BB region in

[0038] The semiconductor device of the present application can be a non-volatile memory, such as NAND flash memory, NOR flash memory, EEPROM, etc. In NOR flash memory, each memory cell is independently connected to a bit line and a word line, so NOR flash memory has excellent random access time. In NAND flash memory, since the memory cells are connected in series and a memory cell string has only one contact hole with the bit line, NAND flash memory has excellent integration characteristics and is usually used in high-density flash memories. Hereinafter, the semiconductor device being NAND flash memory will be taken as an example for illustration.

[0039] As Figure 2 and 3As shown, the active regions 11 of the semiconductor device 100 can extend parallel to each other in a first direction. A plurality of word lines WL and gate lines SL of the selection transistors extend in a second direction and are arranged in the first direction. The word lines WL and the gate lines SL of the selection transistors can be arranged perpendicular to the bit lines BL. A plurality of memory cells are formed in each active region 11. The plurality of memory cells are connected in series to form a memory cell string, and each memory cell is connected to a corresponding word line WL. The memory cell can be implemented by a field-effect transistor having a charge trapping layer sandwiched between two dielectric layers, and the charge trapping layer can be a floating gate or a charge trapping dielectric layer. Adjacent active regions 11 are isolated, for example, by shallow trench isolation (STI). A first selection transistor and a second selection transistor are also formed at both ends of the memory cell string. The word lines WL are distributed between the gate line of the first selection transistor and the gate line of the second selection transistor. The common source line CSL can be arranged between the gate lines GSL of the second selection transistors of adjacent memory cell strings to extend in the second direction. The bit lines BL can be arranged to extend in the first direction and are electrically connected to the drain regions between the first selection transistors of adjacent memory cell strings through bit line contact structures DC. That is, adjacent memory cell strings can share the contact holes of the bit lines or the contact holes of the common source line CSL. According to an exemplary embodiment of the present disclosure, as Figure 3 , Figure 4a and Figure 4b shown, the semiconductor device 100 includes a substrate 101 and a gate stack structure 110 on the substrate. The gate stack structure 110 includes gate stacks of a plurality of memory cells, a gate stack of the first selection transistor (the first selection control gate line), and a gate stack of the second selection transistor (the second selection control gate line). Figure 4a The first selection transistor and the second selection transistor shown belong to two adjacent memory cell strings. Refer to Figure 4b , Figure 4a In the BB region in, that is, the gate stack of a memory cell includes a floating gate 111, an isolation layer 112, and a control gate 113 stacked in sequence. In the gate stacks of the first selection transistor and the second selection transistor, the isolation layer 112 is partially removed or completely removed, and the material forming the floating gate 111 and the control gate 113 are connected together as a single gate.

[0040] The floating gate 111 is, for example, silicon, polysilicon, germanium, or other semiconductor materials. The isolation layer 112 is, for example, silicon oxide or silicon nitride. The control gate 113 is, for example, silicon, polysilicon, germanium, or other semiconductor materials. Optionally, the floating gate 111 and the control gate 113 are made of the same material. The isolation layer 112 may be a dielectric layer with a high dielectric constant (k). For example, the isolation layer 112 may include at least one of an oxide / nitride / oxide (ONO) layer, an alumina layer, a hafnium dioxide layer, a hafnium aluminum oxide layer, and a zirconia layer. The control gate 113 may include a doped polysilicon layer and / or a metal silicide layer. A pattern may be formed in the control gate 113. For example, the control gate 113 may include Figure 2 the word line WL and the gate line SL of the selection transistor shown.

[0041] According to an exemplary embodiment, an opening and a slot are formed through the gate stack structure 110, and an insulating layer 148 is covered on the surface of the gate stack structure 110. The insulating layer 148 located above the opening is used to form a first air gap 122, and the insulating layer 148 filled in the slot separates the gate stacks of the selection transistors of adjacent memory cell strings. The insulating layer 148 may be a silicon oxide layer. The opening is used to form the first air gap 122, so as to provide good isolation between the word lines WL; the slot is used to form a contact structure 150, and after the contact structure 150 is connected to a metal conductor, a bit line contact structure DC can be formed.

[0042] In this embodiment, during the process of forming the first air gap 122 and the contact structure 150, the insulating layer 148 is formed in steps, and these steps may form a parasitic second air gap 134 between the selection transistor and the contact structure 150. Specifically, a sacrificial layer 142 and a barrier layer 145 are further included in the slot. The sacrificial layer 142 and the barrier layer 145 are separated by the insulating layer, and at least a part of the barrier layer 145 is located above the sacrificial layer 142, so that the barrier layer 145 is stepped; the first end and the second end of the barrier layer 145 are adjacent to the first selection control gate line and the second selection control gate line respectively, and extend in a stepped manner away from the contact structure 150. The contact structure 150 penetrates through the part of the barrier layer 145 located between the first end and the second end and the insulating layer 148; the bit line BL is electrically connected to the active region 103 in the substrate 101 through the contact structure 150, and the active region 103 is the common source-drain region of the selection transistors of two adjacent memory cell strings. Optionally, the sacrificial layer 142 and the barrier layer 145 are made of the same material. Optionally, the thickness of the sacrificial layer 142 is twice the thickness of the barrier layer 145. For example, the thickness of the sacrificial layer 142 is The thickness of the barrier layer 145 is Optionally, the semiconductor device further includes a third air gap located above the sacrificial layer 142 in the slot, and the third air gap is also a parasitic air gap.

[0043] In this embodiment, since the first air gap 122 is filled with air, the dielectric constant of the first air gap 122 can be lower than that of the silicon oxide layer. Therefore, the first air gap 122 can significantly reduce the parasitic capacitance between adjacent memory cells. That is, the first air gap 122 can minimize the interference effect between adjacent memory cells.

[0044] Figures 5a to 5h A cross-sectional schematic diagram showing various stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0045] The method for manufacturing a semiconductor device according to an embodiment of the present invention begins with a semiconductor structure in which a tunneling oxide layer 102 and a gate stack structure 110 have been formed on the surface of a semiconductor substrate 101. The gate stack structure 110 includes gate stacks of a plurality of memory cells, a gate stack of a first select transistor, and a gate stack of a second select transistor. The gate stack of the memory cell includes a floating gate 111, an isolation layer 112, and a control gate 113 stacked in sequence. As Figure 5a shown, in this step, a plurality of openings 120 and slots 130 penetrating through the tunneling oxide layer 102 and the gate stack structure 110 are also formed. The openings 120 separate the gate stacks of the plurality of memory cells and separate the gate stack of the select transistor and the gate stack of the memory cell. The slots 130 separate adjacent memory cell strings, and with reference to Figure 5h , a contact structure 150 is formed in the slots 130. The contact structure 150 is used to connect a bit line or a common gate line.

[0046] As an example, the semiconductor substrate 101 is selected from any one or more of silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). The tunneling oxide layer 153 is, for example, silicon oxide. The floating gate 111 is, for example, silicon, polysilicon, germanium, or other semiconductor materials. The isolation layer 112 is, for example, silicon oxide or silicon nitride. The control gate 113 is, for example, silicon, polysilicon, germanium, or other semiconductor materials. Optionally, the materials of the floating gate 111 and the control gate 113 are the same. In this embodiment, the isolation layer 112 is an ONO structure (oxide-nitride-oxide). For example, the floating gate 111 and the isolation layer 112 are sequentially formed on the active region; the isolation layer 112 in the select transistor region is partially removed, and then the control gate 113 is formed.

[0047] In this step, methods for forming the bottom tunneling oxide layer 102 and the gate stack structure 110 are, for example, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD). Preferably, Plasma Enhanced Chemical Vapor Deposition (PECVD) is used to form the bottom tunneling oxide layer 102 and the gate stack structure 110.

[0048] Further, a first oxide layer 141 (the first oxide layer 141 covers the sidewalls of multiple word lines WL and the sidewalls of the first select control gate line and the second select control gate line) and a sacrificial layer 142 (the sacrificial layer 142 fills and covers the voids between the sidewalls of multiple word lines WL and the first oxide layer 141) are formed within multiple opening holes 120, a first oxide layer 141, a sacrificial layer 142, and a second oxide layer 143 (the second oxide layer 143 covers the sacrificial layer 142) are formed within the grooved slots 130, and an active region 103 is formed on the substrate 101, as Figure 5b shown.

[0049] As an example, the materials of the first oxide layer 141 and the second oxide layer 143 are the same. For example, both the first oxide layer 141 and the second oxide layer 143 are silicon oxide, and the material of the sacrificial layer 142 is, for example, silicon nitride. In this embodiment, an "L"-shaped sacrificial layer 142 is formed, reducing the thickness of the sacrificial layer 142 on the sidewalls of the select tube. In an alternative embodiment, the shape of the sacrificial layer 142 is not necessarily "L"-shaped.

[0050] In this step, a first oxide layer 141 is first formed to cover the sidewalls and bottom of the plurality of openings 120 and grooves 130. The first oxide layer 141 forms a hollow cylinder with an opening in the plurality of openings 120 and grooves 130. Further, a sacrificial layer 142 is filled in the hollow cylinder formed by the first oxide layer 141 in the plurality of openings 120, and the sacrificial layer 142 is formed on the sidewalls and bottom of the hollow cylinder formed by the first oxide layer 141 in the grooves 130. In this step, since the sizes of the openings 120 and grooves 130 are quite different, and the size of the openings 120 is much smaller than that of the grooves 130, the sacrificial layer 142 can completely fill the openings 120, and at the same time, the sacrificial layer 142 covers the bottom and sidewalls of the grooves 130. Further, a second oxide layer 143 is deposited. Optionally, by controlling the time and deposition rate of the deposition processes for forming the sacrificial layer 142 and the second oxide layer 143, the total thickness of the sacrificial layer 142 and the second oxide layer 143 on the sidewall of the selection tube is a predetermined value. Optionally, after forming the second oxide layer 143, the surface of the semiconductor structure is planarized. Further, a groove 140 is formed in the groove 130 to penetrate the first oxide layer 141, the sacrificial layer 142, and the second oxide layer 143. The groove 140 serves as an implantation window, and the substrate 101 is ion-implanted through the groove 140 to form the active region 103, and the active region 103 can serve as a common source-drain region for adjacent selection tubes. In this step, the groove 140 can be formed by anisotropic etching, such as dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, the etching stops near the surface of the substrate 101.

[0051] Further, the second oxide layer 143 located in the groove 140 is removed, as Figure 5c shown.

[0052] In this step, the second oxide layer 143 can be removed by anisotropic etching or isotropic etching. When removing the second oxide layer 143, a part of the first oxide layer 141 located in the opening 120 is also removed. Isotropic etching can use selective wet etching or gas-phase etching. In wet etching, an etching solution is used as the etchant, in which the semiconductor structure is immersed in the etching solution. In gas-phase etching, an etching gas is used as the etchant, in which the semiconductor structure is exposed to the etching gas.

[0053] Further, a third oxide layer 144 is formed to cover the surface of the semiconductor structure. A barrier layer 145 is formed on the surface of the third oxide layer 144, and a fourth oxide layer 146 is formed in the cavity formed by the barrier layer 145, as Figure 5dAs shown. Optionally, the thickness of the barrier layer 145 is approximately one - half of the thickness of the sacrificial layer 142. For example, the thickness of the sacrificial layer 142 is the thickness of the barrier layer 145 is

[0054] In this embodiment, the thickness of the barrier layer 145 should be less than that of the sacrificial layer 142, and the barrier layer 145 and the sacrificial layer 142 are made of the same material. In this step, for example, atomic layer deposition, physical vapor deposition or chemical vapor deposition is used to sequentially form the third oxide layer 144, the barrier layer 145 and the fourth oxide layer 146. After that, chemical mechanical polishing is performed on the surface of the semiconductor structure.

[0055] Furthermore, etch - back processing is performed on the first oxide layer 141, the sacrificial layer 142, the third oxide layer 144, the barrier layer 145 and the fourth oxide layer 146, as Figure 5e shown.

[0056] In this step, anisotropic etching or isotropic etching can be used to perform etch - back processing on the first oxide layer 141, the sacrificial layer 142, the third oxide layer 144, the barrier layer 145 and the fourth oxide layer 146, so that the etching stops at a certain depth inside the semiconductor structure. As observed from the cross - section shown in Figure 5e the side walls of the etched first oxide layer 141, sacrificial layer 142, third oxide layer 144, barrier layer 145 and fourth oxide layer 146 are perpendicular or approximately perpendicular to the substrate 101.

[0057] Furthermore, part of the sacrificial layer 142 and part of the barrier layer 145 are removed to form a first cavity 121, a second cavity 131 and a third cavity 132, as Figure 5f shown.

[0058] In this embodiment, the sacrificial layer 142 located within the opening 120 is completely removed, thereby forming the first cavity 121. Part of the sacrificial layer 142 and part of the barrier layer 145 located within the slot 130 are removed, thereby forming the second cavity 131 and the third cavity 132 respectively. Among them, the size of the second cavity 131 should be smaller than that of the third cavity 132. As observed from the cross - section shown in Figure 5f the width of the second cavity 131 is smaller than the width of the third cavity 132.

[0059] Furthermore, a fifth oxide layer 147 covering the semiconductor structure is formed to form a first air gap 122 and a second air gap 134, as Figure 5gAs shown. In this step, since the size of the second cavity 131 is smaller than that of the third cavity 132, the fifth oxide layer 147 completely fills the third cavity 132, thereby forming a second air gap 134 at the bottom of the second cavity 131; the size of the first cavity 121 is much smaller than that of the second cavity 131, so the fifth oxide layer 147 cannot completely fill the first cavity 121, and the fifth oxide layer 147 closes the top of the first cavity 121, thereby forming a first air gap 122.

[0060] Further, a contact structure 150 penetrating the insulating layer 148 and the barrier layer 145 is formed, and the position of the contact structure 150 is connected to the active region 103, as Figure 5h shown. It should be understood that, for the sake of clarity of the drawings, in Figure 5h the Figure 5g shown first oxide layer 141, third oxide layer 144, fourth oxide layer 146, and fifth oxide layer 147 are shown as a whole, and the first oxide layer 141, third oxide layer 144, fourth oxide layer 146, and fifth oxide layer 147 are collectively referred to as the insulating layer 148.

[0061] In this step, preferably, the etching process for forming the contact structure 150 is carried out step by step. For example, the barrier layer 145 is used as an etching stop layer to form the upper half of the contact hole. Then, the barrier layer 145 is etched and the insulating layer 148 between the barrier layer 145 and the substrate 101 is further etched. Then, a metal conductor is filled inside the contact hole to form the contact structure 150. The metal conductor is, for example, tungsten metal, to provide an electrical connection path from the substrate 101 to the bit line (please refer to Figure 2 the bit line contact structure DC shown). The above step-by-step etching steps are beneficial to defining the position of the etching stop in the etching process of the contact structure 150, thereby reducing the probability of problems such as under-etching or over-etching in each region.

[0062] In this embodiment, since an "L"-shaped sacrificial layer 142 is formed in the Figure 5b shown step, reducing the sidewall thickness of the sacrificial layer 142, the third oxide layer 144 and the barrier layer 145 are also offset in a direction away from the contact structure 150 accordingly. Therefore, in the finally formed semiconductor device, the barrier layer 145 is stepped, increasing the distance between the first end and the second end of the barrier layer 145 and the contact structure. Also, since the second air gap 134 is connected to the contact structure 150 via the barrier layer 145, the possibility of the second air gap 134 coming into contact with the contact structure is greatly reduced, improving the yield and reliability of the semiconductor device.

[0063] In the above description, no detailed explanations are given for the technical details such as the composition and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. Additionally, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the various embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0064] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and not for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including: Forming a gate stack structure on a substrate; Forming a plurality of openings penetrating the gate stack structure to form a plurality of word lines separated from each other in the gate stack structure; Forming a slot penetrating the gate stack structure to form a first selection control gate line and a second selection control gate line for controlling adjacent selection transistors in the gate stack structure, the slot isolating the first selection control gate line from the second selection control gate line; Forming a first oxide layer covering sidewalls of the plurality of word lines and sidewalls of the first selection control gate line and the second selection control gate line; Forming a sacrificial layer filling and covering voids between sidewalls of the plurality of word lines and the first oxide layer; Forming a second oxide layer covering the sacrificial layer; Partially removing the sacrificial layer, the first oxide layer, and the second oxide layer in the slot to form an implantation window; Removing the remaining second oxide layer; Successively forming a third oxide layer, a barrier layer, and a fourth oxide layer; Partially removing the sacrificial layer and the barrier layer to form a first air gap between the plurality of word lines; Forming a fifth oxide layer covering the gate stack structure, the openings, and the slot; forming a contact structure in the slot.

2. The manufacturing method according to claim 1, characterized in that, The sacrificial layer and the barrier layer are made of the same material.

3. The manufacturing method according to claim 1, characterized in that, After forming the sacrificial layer, it further includes: Performing ion implantation on the substrate through the implantation window to form a common source-drain region of the adjacent selection transistors.

4. The manufacturing method according to claim 1, characterized in that, After forming the implantation window, the sacrificial layer in the slot is in an "L" shape.

5. The manufacturing method according to claim 1, characterized in that, The first oxide layer, the third oxide layer, the fourth oxide layer, and the fifth oxide layer are collectively referred to as an insulating layer; The contact structure penetrates the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and a part of the barrier layer extends above the sacrificial layer.

6. A semiconductor device, characterized in that, Manufactured by the manufacturing method according to any one of claims 1-5, the semiconductor device includes: A substrate; A gate stack structure on the substrate; A plurality of openings penetrating the gate stack structure to form a plurality of word lines separated from each other in the gate stack structure; A slot penetrating the gate stack structure to form a first selection control gate line and a second selection control gate line for controlling adjacent selection transistors in the gate stack structure, the slot isolating the first selection control gate line from the second selection control gate line; A sacrificial layer, a barrier layer, and a contact structure in the slot; A bit line above the substrate, the bit line being electrically connected to the common source-drain region of the adjacent selection transistors via the contact structure; An insulating layer for forming a first air gap in the plurality of openings and achieving electrical isolation between the barrier layer, the contact structure, and the gate stack structure, Wherein the contact structure penetrates the insulating layer and the barrier layer, the sacrificial layer and the barrier layer are separated by the insulating layer, and a part of the barrier layer extends above the sacrificial layer.

7. The semiconductor device according to claim 6, wherein There is a second air gap at a first end and / or a second end of the barrier layer.

8. The semiconductor device according to claim 7, wherein, The insulating layer includes a first oxide layer, a third oxide layer, a fourth oxide layer, and a fifth oxide layer. The first oxide layer, the sacrificial layer, the third oxide layer, the barrier layer, and the fourth oxide layer are sequentially stacked on the substrate. The fifth oxide layer fills at least the cavity formed by removing the sacrificial layer and the barrier layer on the sidewall of the slotted area, thereby forming the second air gap.

9. The semiconductor device according to claim 6, wherein The sacrificial layer and the barrier layer are made of the same material.

10. The semiconductor device according to claim 6, wherein The thickness of the barrier layer is less than the thickness of the sacrificial layer.

11. The semiconductor device according to claim 6, wherein, The semiconductor device further includes a third air gap above the sacrificial layer.

12. A semiconductor device, characterized in that, Manufactured by the manufacturing method according to any one of claims 1-5, the semiconductor device includes: A substrate; A gate stack structure on the substrate, the gate stack structure including a gate stack of a storage cell and a gate stack of a select transistor; Wherein, between the gate stacks of two adjacent select transistors, there are a sacrificial layer, a barrier layer, an insulating layer, and a contact structure penetrating the barrier layer and the insulating layer. The contact structure connects the common source-drain regions of the two adjacent select transistors. The sacrificial layer and the barrier layer are separated by the insulating layer, and a part of the barrier layer extends above the sacrificial layer.

13. The semiconductor device according to claim 12, wherein The semiconductor device further includes a first air gap between the gate stacks of adjacent storage cells.

14. The semiconductor device according to claim 12, wherein The sacrificial layer and the barrier layer are made of the same material.

15. The semiconductor device according to claim 12, wherein, The thickness of the barrier layer is less than the thickness of the sacrificial layer.

16. The semiconductor device according to claim 12, wherein, The semiconductor device further includes second air gaps on both sides of the barrier layer.

17. The semiconductor device according to any one of claims 12 - 16, characterized in that, The semiconductor device is a NAND flash memory.

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